commit_impl.hh revision 9046:a1104cc13db2 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/the_isa.hh"
51#include "cpu/checker/cpu.hh"
52#include "cpu/o3/commit.hh"
53#include "cpu/o3/thread_state.hh"
54#include "cpu/base.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64#include "sim/full_system.hh"
65
66using namespace std;
67
68template <class Impl>
69DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
70                                          ThreadID _tid)
71    : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
72{
73}
74
75template <class Impl>
76void
77DefaultCommit<Impl>::TrapEvent::process()
78{
79    // This will get reset by commit if it was switched out at the
80    // time of this event processing.
81    commit->trapSquash[tid] = true;
82}
83
84template <class Impl>
85const char *
86DefaultCommit<Impl>::TrapEvent::description() const
87{
88    return "Trap";
89}
90
91template <class Impl>
92DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
93    : cpu(_cpu),
94      squashCounter(0),
95      iewToCommitDelay(params->iewToCommitDelay),
96      commitToIEWDelay(params->commitToIEWDelay),
97      renameToROBDelay(params->renameToROBDelay),
98      fetchToCommitDelay(params->commitToFetchDelay),
99      renameWidth(params->renameWidth),
100      commitWidth(params->commitWidth),
101      numThreads(params->numThreads),
102      drainPending(false),
103      switchedOut(false),
104      trapLatency(params->trapLatency),
105      canHandleInterrupts(true)
106{
107    _status = Active;
108    _nextStatus = Inactive;
109    std::string policy = params->smtCommitPolicy;
110
111    //Convert string to lowercase
112    std::transform(policy.begin(), policy.end(), policy.begin(),
113                   (int(*)(int)) tolower);
114
115    //Assign commit policy
116    if (policy == "aggressive"){
117        commitPolicy = Aggressive;
118
119        DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
120    } else if (policy == "roundrobin"){
121        commitPolicy = RoundRobin;
122
123        //Set-Up Priority List
124        for (ThreadID tid = 0; tid < numThreads; tid++) {
125            priority_list.push_back(tid);
126        }
127
128        DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
129    } else if (policy == "oldestready"){
130        commitPolicy = OldestReady;
131
132        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
133    } else {
134        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
135               "RoundRobin,OldestReady}");
136    }
137
138    for (ThreadID tid = 0; tid < numThreads; tid++) {
139        commitStatus[tid] = Idle;
140        changedROBNumEntries[tid] = false;
141        checkEmptyROB[tid] = false;
142        trapInFlight[tid] = false;
143        committedStores[tid] = false;
144        trapSquash[tid] = false;
145        tcSquash[tid] = false;
146        pc[tid].set(0);
147        lastCommitedSeqNum[tid] = 0;
148    }
149    interrupt = NoFault;
150}
151
152template <class Impl>
153std::string
154DefaultCommit<Impl>::name() const
155{
156    return cpu->name() + ".commit";
157}
158
159template <class Impl>
160void
161DefaultCommit<Impl>::regStats()
162{
163    using namespace Stats;
164    commitCommittedInsts
165        .name(name() + ".commitCommittedInsts")
166        .desc("The number of committed instructions")
167        .prereq(commitCommittedInsts);
168    commitCommittedOps
169        .name(name() + ".commitCommittedOps")
170        .desc("The number of committed instructions")
171        .prereq(commitCommittedInsts);
172    commitSquashedInsts
173        .name(name() + ".commitSquashedInsts")
174        .desc("The number of squashed insts skipped by commit")
175        .prereq(commitSquashedInsts);
176    commitSquashEvents
177        .name(name() + ".commitSquashEvents")
178        .desc("The number of times commit is told to squash")
179        .prereq(commitSquashEvents);
180    commitNonSpecStalls
181        .name(name() + ".commitNonSpecStalls")
182        .desc("The number of times commit has been forced to stall to "
183              "communicate backwards")
184        .prereq(commitNonSpecStalls);
185    branchMispredicts
186        .name(name() + ".branchMispredicts")
187        .desc("The number of times a branch was mispredicted")
188        .prereq(branchMispredicts);
189    numCommittedDist
190        .init(0,commitWidth,1)
191        .name(name() + ".committed_per_cycle")
192        .desc("Number of insts commited each cycle")
193        .flags(Stats::pdf)
194        ;
195
196    instsCommitted
197        .init(cpu->numThreads)
198        .name(name() + ".committedInsts")
199        .desc("Number of instructions committed")
200        .flags(total)
201        ;
202
203    opsCommitted
204        .init(cpu->numThreads)
205        .name(name() + ".committedOps")
206        .desc("Number of ops (including micro ops) committed")
207        .flags(total)
208        ;
209
210    statComSwp
211        .init(cpu->numThreads)
212        .name(name() + ".swp_count")
213        .desc("Number of s/w prefetches committed")
214        .flags(total)
215        ;
216
217    statComRefs
218        .init(cpu->numThreads)
219        .name(name() +  ".refs")
220        .desc("Number of memory references committed")
221        .flags(total)
222        ;
223
224    statComLoads
225        .init(cpu->numThreads)
226        .name(name() +  ".loads")
227        .desc("Number of loads committed")
228        .flags(total)
229        ;
230
231    statComMembars
232        .init(cpu->numThreads)
233        .name(name() +  ".membars")
234        .desc("Number of memory barriers committed")
235        .flags(total)
236        ;
237
238    statComBranches
239        .init(cpu->numThreads)
240        .name(name() + ".branches")
241        .desc("Number of branches committed")
242        .flags(total)
243        ;
244
245    statComFloating
246        .init(cpu->numThreads)
247        .name(name() + ".fp_insts")
248        .desc("Number of committed floating point instructions.")
249        .flags(total)
250        ;
251
252    statComInteger
253        .init(cpu->numThreads)
254        .name(name()+".int_insts")
255        .desc("Number of committed integer instructions.")
256        .flags(total)
257        ;
258
259    statComFunctionCalls
260        .init(cpu->numThreads)
261        .name(name()+".function_calls")
262        .desc("Number of function calls committed.")
263        .flags(total)
264        ;
265
266    commitEligible
267        .init(cpu->numThreads)
268        .name(name() + ".bw_limited")
269        .desc("number of insts not committed due to BW limits")
270        .flags(total)
271        ;
272
273    commitEligibleSamples
274        .name(name() + ".bw_lim_events")
275        .desc("number cycles where commit BW limit reached")
276        ;
277}
278
279template <class Impl>
280void
281DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
282{
283    thread = threads;
284}
285
286template <class Impl>
287void
288DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
289{
290    timeBuffer = tb_ptr;
291
292    // Setup wire to send information back to IEW.
293    toIEW = timeBuffer->getWire(0);
294
295    // Setup wire to read data from IEW (for the ROB).
296    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
297}
298
299template <class Impl>
300void
301DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
302{
303    fetchQueue = fq_ptr;
304
305    // Setup wire to get instructions from rename (for the ROB).
306    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
307}
308
309template <class Impl>
310void
311DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
312{
313    renameQueue = rq_ptr;
314
315    // Setup wire to get instructions from rename (for the ROB).
316    fromRename = renameQueue->getWire(-renameToROBDelay);
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
322{
323    iewQueue = iq_ptr;
324
325    // Setup wire to get instructions from IEW.
326    fromIEW = iewQueue->getWire(-iewToCommitDelay);
327}
328
329template <class Impl>
330void
331DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
332{
333    iewStage = iew_stage;
334}
335
336template<class Impl>
337void
338DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
339{
340    activeThreads = at_ptr;
341}
342
343template <class Impl>
344void
345DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
346{
347    for (ThreadID tid = 0; tid < numThreads; tid++)
348        renameMap[tid] = &rm_ptr[tid];
349}
350
351template <class Impl>
352void
353DefaultCommit<Impl>::setROB(ROB *rob_ptr)
354{
355    rob = rob_ptr;
356}
357
358template <class Impl>
359void
360DefaultCommit<Impl>::initStage()
361{
362    rob->setActiveThreads(activeThreads);
363    rob->resetEntries();
364
365    // Broadcast the number of free entries.
366    for (ThreadID tid = 0; tid < numThreads; tid++) {
367        toIEW->commitInfo[tid].usedROB = true;
368        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
369        toIEW->commitInfo[tid].emptyROB = true;
370    }
371
372    // Commit must broadcast the number of free entries it has at the
373    // start of the simulation, so it starts as active.
374    cpu->activateStage(O3CPU::CommitIdx);
375
376    cpu->activityThisCycle();
377    trapLatency = cpu->ticks(trapLatency);
378}
379
380template <class Impl>
381bool
382DefaultCommit<Impl>::drain()
383{
384    drainPending = true;
385
386    return false;
387}
388
389template <class Impl>
390void
391DefaultCommit<Impl>::switchOut()
392{
393    switchedOut = true;
394    drainPending = false;
395    rob->switchOut();
396}
397
398template <class Impl>
399void
400DefaultCommit<Impl>::resume()
401{
402    drainPending = false;
403}
404
405template <class Impl>
406void
407DefaultCommit<Impl>::takeOverFrom()
408{
409    switchedOut = false;
410    _status = Active;
411    _nextStatus = Inactive;
412    for (ThreadID tid = 0; tid < numThreads; tid++) {
413        commitStatus[tid] = Idle;
414        changedROBNumEntries[tid] = false;
415        trapSquash[tid] = false;
416        tcSquash[tid] = false;
417    }
418    squashCounter = 0;
419    rob->takeOverFrom();
420}
421
422template <class Impl>
423void
424DefaultCommit<Impl>::updateStatus()
425{
426    // reset ROB changed variable
427    list<ThreadID>::iterator threads = activeThreads->begin();
428    list<ThreadID>::iterator end = activeThreads->end();
429
430    while (threads != end) {
431        ThreadID tid = *threads++;
432
433        changedROBNumEntries[tid] = false;
434
435        // Also check if any of the threads has a trap pending
436        if (commitStatus[tid] == TrapPending ||
437            commitStatus[tid] == FetchTrapPending) {
438            _nextStatus = Active;
439        }
440    }
441
442    if (_nextStatus == Inactive && _status == Active) {
443        DPRINTF(Activity, "Deactivating stage.\n");
444        cpu->deactivateStage(O3CPU::CommitIdx);
445    } else if (_nextStatus == Active && _status == Inactive) {
446        DPRINTF(Activity, "Activating stage.\n");
447        cpu->activateStage(O3CPU::CommitIdx);
448    }
449
450    _status = _nextStatus;
451}
452
453template <class Impl>
454void
455DefaultCommit<Impl>::setNextStatus()
456{
457    int squashes = 0;
458
459    list<ThreadID>::iterator threads = activeThreads->begin();
460    list<ThreadID>::iterator end = activeThreads->end();
461
462    while (threads != end) {
463        ThreadID tid = *threads++;
464
465        if (commitStatus[tid] == ROBSquashing) {
466            squashes++;
467        }
468    }
469
470    squashCounter = squashes;
471
472    // If commit is currently squashing, then it will have activity for the
473    // next cycle. Set its next status as active.
474    if (squashCounter) {
475        _nextStatus = Active;
476    }
477}
478
479template <class Impl>
480bool
481DefaultCommit<Impl>::changedROBEntries()
482{
483    list<ThreadID>::iterator threads = activeThreads->begin();
484    list<ThreadID>::iterator end = activeThreads->end();
485
486    while (threads != end) {
487        ThreadID tid = *threads++;
488
489        if (changedROBNumEntries[tid]) {
490            return true;
491        }
492    }
493
494    return false;
495}
496
497template <class Impl>
498size_t
499DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
500{
501    return rob->numFreeEntries(tid);
502}
503
504template <class Impl>
505void
506DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
507{
508    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
509
510    TrapEvent *trap = new TrapEvent(this, tid);
511
512    cpu->schedule(trap, curTick() + trapLatency);
513    trapInFlight[tid] = true;
514    thread[tid]->trapPending = true;
515}
516
517template <class Impl>
518void
519DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
520{
521    assert(!trapInFlight[tid]);
522    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
523
524    tcSquash[tid] = true;
525}
526
527template <class Impl>
528void
529DefaultCommit<Impl>::squashAll(ThreadID tid)
530{
531    // If we want to include the squashing instruction in the squash,
532    // then use one older sequence number.
533    // Hopefully this doesn't mess things up.  Basically I want to squash
534    // all instructions of this thread.
535    InstSeqNum squashed_inst = rob->isEmpty() ?
536        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
537
538    // All younger instructions will be squashed. Set the sequence
539    // number as the youngest instruction in the ROB (0 in this case.
540    // Hopefully nothing breaks.)
541    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
542
543    rob->squash(squashed_inst, tid);
544    changedROBNumEntries[tid] = true;
545
546    // Send back the sequence number of the squashed instruction.
547    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
548
549    // Send back the squash signal to tell stages that they should
550    // squash.
551    toIEW->commitInfo[tid].squash = true;
552
553    // Send back the rob squashing signal so other stages know that
554    // the ROB is in the process of squashing.
555    toIEW->commitInfo[tid].robSquashing = true;
556
557    toIEW->commitInfo[tid].mispredictInst = NULL;
558    toIEW->commitInfo[tid].squashInst = NULL;
559
560    toIEW->commitInfo[tid].pc = pc[tid];
561}
562
563template <class Impl>
564void
565DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
566{
567    squashAll(tid);
568
569    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
570
571    thread[tid]->trapPending = false;
572    thread[tid]->inSyscall = false;
573    trapInFlight[tid] = false;
574
575    trapSquash[tid] = false;
576
577    commitStatus[tid] = ROBSquashing;
578    cpu->activityThisCycle();
579}
580
581template <class Impl>
582void
583DefaultCommit<Impl>::squashFromTC(ThreadID tid)
584{
585    squashAll(tid);
586
587    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
588
589    thread[tid]->inSyscall = false;
590    assert(!thread[tid]->trapPending);
591
592    commitStatus[tid] = ROBSquashing;
593    cpu->activityThisCycle();
594
595    tcSquash[tid] = false;
596}
597
598template <class Impl>
599void
600DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
601        uint64_t squash_after_seq_num)
602{
603    youngestSeqNum[tid] = squash_after_seq_num;
604
605    rob->squash(squash_after_seq_num, tid);
606    changedROBNumEntries[tid] = true;
607
608    // Send back the sequence number of the squashed instruction.
609    toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
610
611    toIEW->commitInfo[tid].squashInst = head_inst;
612    // Send back the squash signal to tell stages that they should squash.
613    toIEW->commitInfo[tid].squash = true;
614
615    // Send back the rob squashing signal so other stages know that
616    // the ROB is in the process of squashing.
617    toIEW->commitInfo[tid].robSquashing = true;
618
619    toIEW->commitInfo[tid].mispredictInst = NULL;
620
621    toIEW->commitInfo[tid].pc = pc[tid];
622    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
623            tid, squash_after_seq_num);
624    commitStatus[tid] = ROBSquashing;
625}
626
627template <class Impl>
628void
629DefaultCommit<Impl>::tick()
630{
631    wroteToTimeBuffer = false;
632    _nextStatus = Inactive;
633
634    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
635        cpu->signalDrained();
636        drainPending = false;
637        return;
638    }
639
640    if (activeThreads->empty())
641        return;
642
643    list<ThreadID>::iterator threads = activeThreads->begin();
644    list<ThreadID>::iterator end = activeThreads->end();
645
646    // Check if any of the threads are done squashing.  Change the
647    // status if they are done.
648    while (threads != end) {
649        ThreadID tid = *threads++;
650
651        // Clear the bit saying if the thread has committed stores
652        // this cycle.
653        committedStores[tid] = false;
654
655        if (commitStatus[tid] == ROBSquashing) {
656
657            if (rob->isDoneSquashing(tid)) {
658                commitStatus[tid] = Running;
659            } else {
660                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
661                        " insts this cycle.\n", tid);
662                rob->doSquash(tid);
663                toIEW->commitInfo[tid].robSquashing = true;
664                wroteToTimeBuffer = true;
665            }
666        }
667    }
668
669    commit();
670
671    markCompletedInsts();
672
673    threads = activeThreads->begin();
674
675    while (threads != end) {
676        ThreadID tid = *threads++;
677
678        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
679            // The ROB has more instructions it can commit. Its next status
680            // will be active.
681            _nextStatus = Active;
682
683            DynInstPtr inst = rob->readHeadInst(tid);
684
685            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
686                    " ROB and ready to commit\n",
687                    tid, inst->seqNum, inst->pcState());
688
689        } else if (!rob->isEmpty(tid)) {
690            DynInstPtr inst = rob->readHeadInst(tid);
691
692            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
693                    "%s is head of ROB and not ready\n",
694                    tid, inst->seqNum, inst->pcState());
695        }
696
697        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
698                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
699    }
700
701
702    if (wroteToTimeBuffer) {
703        DPRINTF(Activity, "Activity This Cycle.\n");
704        cpu->activityThisCycle();
705    }
706
707    updateStatus();
708}
709
710template <class Impl>
711void
712DefaultCommit<Impl>::handleInterrupt()
713{
714    // Verify that we still have an interrupt to handle
715    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
716        DPRINTF(Commit, "Pending interrupt is cleared by master before "
717                "it got handled. Restart fetching from the orig path.\n");
718        toIEW->commitInfo[0].clearInterrupt = true;
719        interrupt = NoFault;
720        return;
721    }
722
723    // Wait until all in flight instructions are finished before enterring
724    // the interrupt.
725    if (canHandleInterrupts && cpu->instList.empty()) {
726        // Squash or record that I need to squash this cycle if
727        // an interrupt needed to be handled.
728        DPRINTF(Commit, "Interrupt detected.\n");
729
730        // Clear the interrupt now that it's going to be handled
731        toIEW->commitInfo[0].clearInterrupt = true;
732
733        assert(!thread[0]->inSyscall);
734        thread[0]->inSyscall = true;
735
736        if (cpu->checker) {
737            cpu->checker->handlePendingInt();
738        }
739
740        // CPU will handle interrupt.
741        cpu->processInterrupts(interrupt);
742
743        thread[0]->inSyscall = false;
744
745        commitStatus[0] = TrapPending;
746
747        // Generate trap squash event.
748        generateTrapEvent(0);
749
750        interrupt = NoFault;
751    } else {
752        DPRINTF(Commit, "Interrupt pending: instruction is %sin "
753                "flight, ROB is %sempty\n",
754                canHandleInterrupts ? "not " : "",
755                cpu->instList.empty() ? "" : "not " );
756    }
757}
758
759template <class Impl>
760void
761DefaultCommit<Impl>::propagateInterrupt()
762{
763    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
764            tcSquash[0])
765        return;
766
767    // Process interrupts if interrupts are enabled, not in PAL
768    // mode, and no other traps or external squashes are currently
769    // pending.
770    // @todo: Allow other threads to handle interrupts.
771
772    // Get any interrupt that happened
773    interrupt = cpu->getInterrupts();
774
775    // Tell fetch that there is an interrupt pending.  This
776    // will make fetch wait until it sees a non PAL-mode PC,
777    // at which point it stops fetching instructions.
778    if (interrupt != NoFault)
779        toIEW->commitInfo[0].interruptPending = true;
780}
781
782template <class Impl>
783void
784DefaultCommit<Impl>::commit()
785{
786    if (FullSystem) {
787        // Check if we have a interrupt and get read to handle it
788        if (cpu->checkInterrupts(cpu->tcBase(0)))
789            propagateInterrupt();
790    }
791
792    ////////////////////////////////////
793    // Check for any possible squashes, handle them first
794    ////////////////////////////////////
795    list<ThreadID>::iterator threads = activeThreads->begin();
796    list<ThreadID>::iterator end = activeThreads->end();
797
798    while (threads != end) {
799        ThreadID tid = *threads++;
800
801        // Not sure which one takes priority.  I think if we have
802        // both, that's a bad sign.
803        if (trapSquash[tid] == true) {
804            assert(!tcSquash[tid]);
805            squashFromTrap(tid);
806        } else if (tcSquash[tid] == true) {
807            assert(commitStatus[tid] != TrapPending);
808            squashFromTC(tid);
809        }
810
811        // Squashed sequence number must be older than youngest valid
812        // instruction in the ROB. This prevents squashes from younger
813        // instructions overriding squashes from older instructions.
814        if (fromIEW->squash[tid] &&
815            commitStatus[tid] != TrapPending &&
816            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
817
818            if (fromIEW->mispredictInst[tid]) {
819                DPRINTF(Commit,
820                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
821                    tid,
822                    fromIEW->mispredictInst[tid]->instAddr(),
823                    fromIEW->squashedSeqNum[tid]);
824            } else {
825                DPRINTF(Commit,
826                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
827                    tid, fromIEW->squashedSeqNum[tid]);
828            }
829
830            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
831                    tid,
832                    fromIEW->pc[tid].nextInstAddr());
833
834            commitStatus[tid] = ROBSquashing;
835
836            // If we want to include the squashing instruction in the squash,
837            // then use one older sequence number.
838            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
839
840            if (fromIEW->includeSquashInst[tid] == true) {
841                squashed_inst--;
842            }
843
844            // All younger instructions will be squashed. Set the sequence
845            // number as the youngest instruction in the ROB.
846            youngestSeqNum[tid] = squashed_inst;
847
848            rob->squash(squashed_inst, tid);
849            changedROBNumEntries[tid] = true;
850
851            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
852
853            toIEW->commitInfo[tid].squash = true;
854
855            // Send back the rob squashing signal so other stages know that
856            // the ROB is in the process of squashing.
857            toIEW->commitInfo[tid].robSquashing = true;
858
859            toIEW->commitInfo[tid].mispredictInst =
860                fromIEW->mispredictInst[tid];
861            toIEW->commitInfo[tid].branchTaken =
862                fromIEW->branchTaken[tid];
863            toIEW->commitInfo[tid].squashInst =
864                                    rob->findInst(tid, squashed_inst);
865            if (toIEW->commitInfo[tid].mispredictInst) {
866                if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
867                     toIEW->commitInfo[tid].branchTaken = true;
868                }
869            }
870
871            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
872
873            if (toIEW->commitInfo[tid].mispredictInst) {
874                ++branchMispredicts;
875            }
876        }
877
878    }
879
880    setNextStatus();
881
882    if (squashCounter != numThreads) {
883        // If we're not currently squashing, then get instructions.
884        getInsts();
885
886        // Try to commit any instructions.
887        commitInsts();
888    }
889
890    //Check for any activity
891    threads = activeThreads->begin();
892
893    while (threads != end) {
894        ThreadID tid = *threads++;
895
896        if (changedROBNumEntries[tid]) {
897            toIEW->commitInfo[tid].usedROB = true;
898            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
899
900            wroteToTimeBuffer = true;
901            changedROBNumEntries[tid] = false;
902            if (rob->isEmpty(tid))
903                checkEmptyROB[tid] = true;
904        }
905
906        // ROB is only considered "empty" for previous stages if: a)
907        // ROB is empty, b) there are no outstanding stores, c) IEW
908        // stage has received any information regarding stores that
909        // committed.
910        // c) is checked by making sure to not consider the ROB empty
911        // on the same cycle as when stores have been committed.
912        // @todo: Make this handle multi-cycle communication between
913        // commit and IEW.
914        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
915            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
916            checkEmptyROB[tid] = false;
917            toIEW->commitInfo[tid].usedROB = true;
918            toIEW->commitInfo[tid].emptyROB = true;
919            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
920            wroteToTimeBuffer = true;
921        }
922
923    }
924}
925
926template <class Impl>
927void
928DefaultCommit<Impl>::commitInsts()
929{
930    ////////////////////////////////////
931    // Handle commit
932    // Note that commit will be handled prior to putting new
933    // instructions in the ROB so that the ROB only tries to commit
934    // instructions it has in this current cycle, and not instructions
935    // it is writing in during this cycle.  Can't commit and squash
936    // things at the same time...
937    ////////////////////////////////////
938
939    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
940
941    unsigned num_committed = 0;
942
943    DynInstPtr head_inst;
944
945    // Commit as many instructions as possible until the commit bandwidth
946    // limit is reached, or it becomes impossible to commit any more.
947    while (num_committed < commitWidth) {
948        // Check for any interrupt that we've already squashed for
949        // and start processing it.
950        if (interrupt != NoFault)
951            handleInterrupt();
952
953        int commit_thread = getCommittingThread();
954
955        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
956            break;
957
958        head_inst = rob->readHeadInst(commit_thread);
959
960        ThreadID tid = head_inst->threadNumber;
961
962        assert(tid == commit_thread);
963
964        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
965                head_inst->seqNum, tid);
966
967        // If the head instruction is squashed, it is ready to retire
968        // (be removed from the ROB) at any time.
969        if (head_inst->isSquashed()) {
970
971            DPRINTF(Commit, "Retiring squashed instruction from "
972                    "ROB.\n");
973
974            rob->retireHead(commit_thread);
975
976            ++commitSquashedInsts;
977
978            // Record that the number of ROB entries has changed.
979            changedROBNumEntries[tid] = true;
980        } else {
981            pc[tid] = head_inst->pcState();
982
983            // Increment the total number of non-speculative instructions
984            // executed.
985            // Hack for now: it really shouldn't happen until after the
986            // commit is deemed to be successful, but this count is needed
987            // for syscalls.
988            thread[tid]->funcExeInst++;
989
990            // Try to commit the head instruction.
991            bool commit_success = commitHead(head_inst, num_committed);
992
993            if (commit_success) {
994                ++num_committed;
995
996                changedROBNumEntries[tid] = true;
997
998                // Set the doneSeqNum to the youngest committed instruction.
999                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1000
1001                if (!head_inst->isMicroop() || head_inst->isLastMicroop())
1002                    ++commitCommittedInsts;
1003                ++commitCommittedOps;
1004
1005                // To match the old model, don't count nops and instruction
1006                // prefetches towards the total commit count.
1007                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
1008                    cpu->instDone(tid, head_inst);
1009                }
1010
1011                if (tid == 0) {
1012                    canHandleInterrupts =  (!head_inst->isDelayedCommit()) &&
1013                                           ((THE_ISA != ALPHA_ISA) ||
1014                                             (!(pc[0].instAddr() & 0x3)));
1015                }
1016
1017                // Updates misc. registers.
1018                head_inst->updateMiscRegs();
1019
1020                cpu->traceFunctions(pc[tid].instAddr());
1021
1022                TheISA::advancePC(pc[tid], head_inst->staticInst);
1023
1024                // Keep track of the last sequence number commited
1025                lastCommitedSeqNum[tid] = head_inst->seqNum;
1026
1027                // If this is an instruction that doesn't play nicely with
1028                // others squash everything and restart fetch
1029                if (head_inst->isSquashAfter())
1030                    squashAfter(tid, head_inst, head_inst->seqNum);
1031
1032                int count = 0;
1033                Addr oldpc;
1034                // Debug statement.  Checks to make sure we're not
1035                // currently updating state while handling PC events.
1036                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1037                do {
1038                    oldpc = pc[tid].instAddr();
1039                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
1040                    count++;
1041                } while (oldpc != pc[tid].instAddr());
1042                if (count > 1) {
1043                    DPRINTF(Commit,
1044                            "PC skip function event, stopping commit\n");
1045                    break;
1046                }
1047            } else {
1048                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1049                        "[tid:%i] [sn:%i].\n",
1050                        head_inst->pcState(), tid ,head_inst->seqNum);
1051                break;
1052            }
1053        }
1054    }
1055
1056    DPRINTF(CommitRate, "%i\n", num_committed);
1057    numCommittedDist.sample(num_committed);
1058
1059    if (num_committed == commitWidth) {
1060        commitEligibleSamples++;
1061    }
1062}
1063
1064template <class Impl>
1065bool
1066DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1067{
1068    assert(head_inst);
1069
1070    ThreadID tid = head_inst->threadNumber;
1071
1072    // If the instruction is not executed yet, then it will need extra
1073    // handling.  Signal backwards that it should be executed.
1074    if (!head_inst->isExecuted()) {
1075        // Keep this number correct.  We have not yet actually executed
1076        // and committed this instruction.
1077        thread[tid]->funcExeInst--;
1078
1079        if (head_inst->isNonSpeculative() ||
1080            head_inst->isStoreConditional() ||
1081            head_inst->isMemBarrier() ||
1082            head_inst->isWriteBarrier()) {
1083
1084            DPRINTF(Commit, "Encountered a barrier or non-speculative "
1085                    "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1086                    head_inst->seqNum, head_inst->pcState());
1087
1088            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1089                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1090                return false;
1091            }
1092
1093            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1094
1095            // Change the instruction so it won't try to commit again until
1096            // it is executed.
1097            head_inst->clearCanCommit();
1098
1099            ++commitNonSpecStalls;
1100
1101            return false;
1102        } else if (head_inst->isLoad()) {
1103            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1104                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1105                return false;
1106            }
1107
1108            assert(head_inst->uncacheable());
1109            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1110                    head_inst->seqNum, head_inst->pcState());
1111
1112            // Send back the non-speculative instruction's sequence
1113            // number.  Tell the lsq to re-execute the load.
1114            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1115            toIEW->commitInfo[tid].uncached = true;
1116            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1117
1118            head_inst->clearCanCommit();
1119
1120            return false;
1121        } else {
1122            panic("Trying to commit un-executed instruction "
1123                  "of unknown type!\n");
1124        }
1125    }
1126
1127    if (head_inst->isThreadSync()) {
1128        // Not handled for now.
1129        panic("Thread sync instructions are not handled yet.\n");
1130    }
1131
1132    // Check if the instruction caused a fault.  If so, trap.
1133    Fault inst_fault = head_inst->getFault();
1134
1135    // Stores mark themselves as completed.
1136    if (!head_inst->isStore() && inst_fault == NoFault) {
1137        head_inst->setCompleted();
1138    }
1139
1140    // Use checker prior to updating anything due to traps or PC
1141    // based events.
1142    if (cpu->checker) {
1143        cpu->checker->verify(head_inst);
1144    }
1145
1146    if (inst_fault != NoFault) {
1147        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1148                head_inst->seqNum, head_inst->pcState());
1149
1150        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1151            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1152            return false;
1153        }
1154
1155        head_inst->setCompleted();
1156
1157        if (cpu->checker) {
1158            // Need to check the instruction before its fault is processed
1159            cpu->checker->verify(head_inst);
1160        }
1161
1162        assert(!thread[tid]->inSyscall);
1163
1164        // Mark that we're in state update mode so that the trap's
1165        // execution doesn't generate extra squashes.
1166        thread[tid]->inSyscall = true;
1167
1168        // Execute the trap.  Although it's slightly unrealistic in
1169        // terms of timing (as it doesn't wait for the full timing of
1170        // the trap event to complete before updating state), it's
1171        // needed to update the state as soon as possible.  This
1172        // prevents external agents from changing any specific state
1173        // that the trap need.
1174        cpu->trap(inst_fault, tid, head_inst->staticInst);
1175
1176        // Exit state update mode to avoid accidental updating.
1177        thread[tid]->inSyscall = false;
1178
1179        commitStatus[tid] = TrapPending;
1180
1181        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1182            head_inst->seqNum);
1183        if (head_inst->traceData) {
1184            if (DTRACE(ExecFaulting)) {
1185                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1186                head_inst->traceData->setCPSeq(thread[tid]->numOp);
1187                head_inst->traceData->dump();
1188            }
1189            delete head_inst->traceData;
1190            head_inst->traceData = NULL;
1191        }
1192
1193        // Generate trap squash event.
1194        generateTrapEvent(tid);
1195        return false;
1196    }
1197
1198    updateComInstStats(head_inst);
1199
1200    if (FullSystem) {
1201        if (thread[tid]->profile) {
1202            thread[tid]->profilePC = head_inst->instAddr();
1203            ProfileNode *node = thread[tid]->profile->consume(
1204                    thread[tid]->getTC(), head_inst->staticInst);
1205
1206            if (node)
1207                thread[tid]->profileNode = node;
1208        }
1209        if (CPA::available()) {
1210            if (head_inst->isControl()) {
1211                ThreadContext *tc = thread[tid]->getTC();
1212                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1213            }
1214        }
1215    }
1216    DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1217            head_inst->seqNum, head_inst->pcState());
1218    if (head_inst->traceData) {
1219        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1220        head_inst->traceData->setCPSeq(thread[tid]->numOp);
1221        head_inst->traceData->dump();
1222        delete head_inst->traceData;
1223        head_inst->traceData = NULL;
1224    }
1225    if (head_inst->isReturn()) {
1226        DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1227                        head_inst->seqNum, head_inst->pcState());
1228    }
1229
1230    // Update the commit rename map
1231    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1232        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1233                                 head_inst->renamedDestRegIdx(i));
1234    }
1235
1236    // Finally clear the head ROB entry.
1237    rob->retireHead(tid);
1238
1239#if TRACING_ON
1240    // Print info needed by the pipeline activity viewer.
1241    DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1242             head_inst->fetchTick,
1243             head_inst->instAddr(),
1244             head_inst->microPC(),
1245             head_inst->seqNum,
1246             head_inst->staticInst->disassemble(head_inst->instAddr()));
1247    DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->fetchTick + head_inst->decodeTick);
1248    DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->fetchTick + head_inst->renameTick);
1249    DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->fetchTick + head_inst->dispatchTick);
1250    DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->fetchTick + head_inst->issueTick);
1251    DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->fetchTick + head_inst->completeTick);
1252    DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1253#endif
1254
1255    // If this was a store, record it for this cycle.
1256    if (head_inst->isStore())
1257        committedStores[tid] = true;
1258
1259    // Return true to indicate that we have committed an instruction.
1260    return true;
1261}
1262
1263template <class Impl>
1264void
1265DefaultCommit<Impl>::getInsts()
1266{
1267    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1268
1269    // Read any renamed instructions and place them into the ROB.
1270    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1271
1272    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1273        DynInstPtr inst;
1274
1275        inst = fromRename->insts[inst_num];
1276        ThreadID tid = inst->threadNumber;
1277
1278        if (!inst->isSquashed() &&
1279            commitStatus[tid] != ROBSquashing &&
1280            commitStatus[tid] != TrapPending) {
1281            changedROBNumEntries[tid] = true;
1282
1283            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1284                    inst->pcState(), inst->seqNum, tid);
1285
1286            rob->insertInst(inst);
1287
1288            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1289
1290            youngestSeqNum[tid] = inst->seqNum;
1291        } else {
1292            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1293                    "squashed, skipping.\n",
1294                    inst->pcState(), inst->seqNum, tid);
1295        }
1296    }
1297}
1298
1299template <class Impl>
1300void
1301DefaultCommit<Impl>::skidInsert()
1302{
1303    DPRINTF(Commit, "Attempting to any instructions from rename into "
1304            "skidBuffer.\n");
1305
1306    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1307        DynInstPtr inst = fromRename->insts[inst_num];
1308
1309        if (!inst->isSquashed()) {
1310            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1311                    "skidBuffer.\n", inst->pcState(), inst->seqNum,
1312                    inst->threadNumber);
1313            skidBuffer.push(inst);
1314        } else {
1315            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1316                    "squashed, skipping.\n",
1317                    inst->pcState(), inst->seqNum, inst->threadNumber);
1318        }
1319    }
1320}
1321
1322template <class Impl>
1323void
1324DefaultCommit<Impl>::markCompletedInsts()
1325{
1326    // Grab completed insts out of the IEW instruction queue, and mark
1327    // instructions completed within the ROB.
1328    for (int inst_num = 0;
1329         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1330         ++inst_num)
1331    {
1332        if (!fromIEW->insts[inst_num]->isSquashed()) {
1333            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1334                    "within ROB.\n",
1335                    fromIEW->insts[inst_num]->threadNumber,
1336                    fromIEW->insts[inst_num]->pcState(),
1337                    fromIEW->insts[inst_num]->seqNum);
1338
1339            // Mark the instruction as ready to commit.
1340            fromIEW->insts[inst_num]->setCanCommit();
1341        }
1342    }
1343}
1344
1345template <class Impl>
1346bool
1347DefaultCommit<Impl>::robDoneSquashing()
1348{
1349    list<ThreadID>::iterator threads = activeThreads->begin();
1350    list<ThreadID>::iterator end = activeThreads->end();
1351
1352    while (threads != end) {
1353        ThreadID tid = *threads++;
1354
1355        if (!rob->isDoneSquashing(tid))
1356            return false;
1357    }
1358
1359    return true;
1360}
1361
1362template <class Impl>
1363void
1364DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1365{
1366    ThreadID tid = inst->threadNumber;
1367
1368    if (!inst->isMicroop() || inst->isLastMicroop())
1369        instsCommitted[tid]++;
1370    opsCommitted[tid]++;
1371
1372    //
1373    //  Control Instructions
1374    //
1375    if (inst->isControl())
1376        statComBranches[tid]++;
1377
1378    //
1379    //  Memory references
1380    //
1381    if (inst->isMemRef()) {
1382        statComRefs[tid]++;
1383
1384        if (inst->isLoad()) {
1385            statComLoads[tid]++;
1386        }
1387    }
1388
1389    if (inst->isMemBarrier()) {
1390        statComMembars[tid]++;
1391    }
1392
1393    // Integer Instruction
1394    if (inst->isInteger())
1395        statComInteger[tid]++;
1396
1397    // Floating Point Instruction
1398    if (inst->isFloating())
1399        statComFloating[tid]++;
1400
1401    // Function Calls
1402    if (inst->isCall())
1403        statComFunctionCalls[tid]++;
1404
1405}
1406
1407////////////////////////////////////////
1408//                                    //
1409//  SMT COMMIT POLICY MAINTAINED HERE //
1410//                                    //
1411////////////////////////////////////////
1412template <class Impl>
1413ThreadID
1414DefaultCommit<Impl>::getCommittingThread()
1415{
1416    if (numThreads > 1) {
1417        switch (commitPolicy) {
1418
1419          case Aggressive:
1420            //If Policy is Aggressive, commit will call
1421            //this function multiple times per
1422            //cycle
1423            return oldestReady();
1424
1425          case RoundRobin:
1426            return roundRobin();
1427
1428          case OldestReady:
1429            return oldestReady();
1430
1431          default:
1432            return InvalidThreadID;
1433        }
1434    } else {
1435        assert(!activeThreads->empty());
1436        ThreadID tid = activeThreads->front();
1437
1438        if (commitStatus[tid] == Running ||
1439            commitStatus[tid] == Idle ||
1440            commitStatus[tid] == FetchTrapPending) {
1441            return tid;
1442        } else {
1443            return InvalidThreadID;
1444        }
1445    }
1446}
1447
1448template<class Impl>
1449ThreadID
1450DefaultCommit<Impl>::roundRobin()
1451{
1452    list<ThreadID>::iterator pri_iter = priority_list.begin();
1453    list<ThreadID>::iterator end      = priority_list.end();
1454
1455    while (pri_iter != end) {
1456        ThreadID tid = *pri_iter;
1457
1458        if (commitStatus[tid] == Running ||
1459            commitStatus[tid] == Idle ||
1460            commitStatus[tid] == FetchTrapPending) {
1461
1462            if (rob->isHeadReady(tid)) {
1463                priority_list.erase(pri_iter);
1464                priority_list.push_back(tid);
1465
1466                return tid;
1467            }
1468        }
1469
1470        pri_iter++;
1471    }
1472
1473    return InvalidThreadID;
1474}
1475
1476template<class Impl>
1477ThreadID
1478DefaultCommit<Impl>::oldestReady()
1479{
1480    unsigned oldest = 0;
1481    bool first = true;
1482
1483    list<ThreadID>::iterator threads = activeThreads->begin();
1484    list<ThreadID>::iterator end = activeThreads->end();
1485
1486    while (threads != end) {
1487        ThreadID tid = *threads++;
1488
1489        if (!rob->isEmpty(tid) &&
1490            (commitStatus[tid] == Running ||
1491             commitStatus[tid] == Idle ||
1492             commitStatus[tid] == FetchTrapPending)) {
1493
1494            if (rob->isHeadReady(tid)) {
1495
1496                DynInstPtr head_inst = rob->readHeadInst(tid);
1497
1498                if (first) {
1499                    oldest = tid;
1500                    first = false;
1501                } else if (head_inst->seqNum < oldest) {
1502                    oldest = tid;
1503                }
1504            }
1505        }
1506    }
1507
1508    if (!first) {
1509        return oldest;
1510    } else {
1511        return InvalidThreadID;
1512    }
1513}
1514