commit_impl.hh revision 8232 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "params/DerivO3CPU.hh"
62#include "sim/faults.hh"
63
64#if USE_CHECKER
65#include "cpu/checker/cpu.hh"
66#endif
67
68using namespace std;
69
70template <class Impl>
71DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
72                                          ThreadID _tid)
73    : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
74{
75    this->setFlags(AutoDelete);
76}
77
78template <class Impl>
79void
80DefaultCommit<Impl>::TrapEvent::process()
81{
82    // This will get reset by commit if it was switched out at the
83    // time of this event processing.
84    commit->trapSquash[tid] = true;
85}
86
87template <class Impl>
88const char *
89DefaultCommit<Impl>::TrapEvent::description() const
90{
91    return "Trap";
92}
93
94template <class Impl>
95DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
96    : cpu(_cpu),
97      squashCounter(0),
98      iewToCommitDelay(params->iewToCommitDelay),
99      commitToIEWDelay(params->commitToIEWDelay),
100      renameToROBDelay(params->renameToROBDelay),
101      fetchToCommitDelay(params->commitToFetchDelay),
102      renameWidth(params->renameWidth),
103      commitWidth(params->commitWidth),
104      numThreads(params->numThreads),
105      drainPending(false),
106      switchedOut(false),
107      trapLatency(params->trapLatency)
108{
109    _status = Active;
110    _nextStatus = Inactive;
111    std::string policy = params->smtCommitPolicy;
112
113    //Convert string to lowercase
114    std::transform(policy.begin(), policy.end(), policy.begin(),
115                   (int(*)(int)) tolower);
116
117    //Assign commit policy
118    if (policy == "aggressive"){
119        commitPolicy = Aggressive;
120
121        DPRINTF(Commit,"Commit Policy set to Aggressive.");
122    } else if (policy == "roundrobin"){
123        commitPolicy = RoundRobin;
124
125        //Set-Up Priority List
126        for (ThreadID tid = 0; tid < numThreads; tid++) {
127            priority_list.push_back(tid);
128        }
129
130        DPRINTF(Commit,"Commit Policy set to Round Robin.");
131    } else if (policy == "oldestready"){
132        commitPolicy = OldestReady;
133
134        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
135    } else {
136        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
137               "RoundRobin,OldestReady}");
138    }
139
140    for (ThreadID tid = 0; tid < numThreads; tid++) {
141        commitStatus[tid] = Idle;
142        changedROBNumEntries[tid] = false;
143        checkEmptyROB[tid] = false;
144        trapInFlight[tid] = false;
145        committedStores[tid] = false;
146        trapSquash[tid] = false;
147        tcSquash[tid] = false;
148        pc[tid].set(0);
149        lastCommitedSeqNum[tid] = 0;
150    }
151#if FULL_SYSTEM
152    interrupt = NoFault;
153#endif
154}
155
156template <class Impl>
157std::string
158DefaultCommit<Impl>::name() const
159{
160    return cpu->name() + ".commit";
161}
162
163template <class Impl>
164void
165DefaultCommit<Impl>::regStats()
166{
167    using namespace Stats;
168    commitCommittedInsts
169        .name(name() + ".commitCommittedInsts")
170        .desc("The number of committed instructions")
171        .prereq(commitCommittedInsts);
172    commitSquashedInsts
173        .name(name() + ".commitSquashedInsts")
174        .desc("The number of squashed insts skipped by commit")
175        .prereq(commitSquashedInsts);
176    commitSquashEvents
177        .name(name() + ".commitSquashEvents")
178        .desc("The number of times commit is told to squash")
179        .prereq(commitSquashEvents);
180    commitNonSpecStalls
181        .name(name() + ".commitNonSpecStalls")
182        .desc("The number of times commit has been forced to stall to "
183              "communicate backwards")
184        .prereq(commitNonSpecStalls);
185    branchMispredicts
186        .name(name() + ".branchMispredicts")
187        .desc("The number of times a branch was mispredicted")
188        .prereq(branchMispredicts);
189    numCommittedDist
190        .init(0,commitWidth,1)
191        .name(name() + ".COM:committed_per_cycle")
192        .desc("Number of insts commited each cycle")
193        .flags(Stats::pdf)
194        ;
195
196    statComInst
197        .init(cpu->numThreads)
198        .name(name() + ".COM:count")
199        .desc("Number of instructions committed")
200        .flags(total)
201        ;
202
203    statComSwp
204        .init(cpu->numThreads)
205        .name(name() + ".COM:swp_count")
206        .desc("Number of s/w prefetches committed")
207        .flags(total)
208        ;
209
210    statComRefs
211        .init(cpu->numThreads)
212        .name(name() +  ".COM:refs")
213        .desc("Number of memory references committed")
214        .flags(total)
215        ;
216
217    statComLoads
218        .init(cpu->numThreads)
219        .name(name() +  ".COM:loads")
220        .desc("Number of loads committed")
221        .flags(total)
222        ;
223
224    statComMembars
225        .init(cpu->numThreads)
226        .name(name() +  ".COM:membars")
227        .desc("Number of memory barriers committed")
228        .flags(total)
229        ;
230
231    statComBranches
232        .init(cpu->numThreads)
233        .name(name() + ".COM:branches")
234        .desc("Number of branches committed")
235        .flags(total)
236        ;
237
238    statComFloating
239        .init(cpu->numThreads)
240        .name(name() + ".COM:fp_insts")
241        .desc("Number of committed floating point instructions.")
242        .flags(total)
243        ;
244
245    statComInteger
246        .init(cpu->numThreads)
247        .name(name()+".COM:int_insts")
248        .desc("Number of committed integer instructions.")
249        .flags(total)
250        ;
251
252    statComFunctionCalls
253        .init(cpu->numThreads)
254        .name(name()+".COM:function_calls")
255        .desc("Number of function calls committed.")
256        .flags(total)
257        ;
258
259    commitEligible
260        .init(cpu->numThreads)
261        .name(name() + ".COM:bw_limited")
262        .desc("number of insts not committed due to BW limits")
263        .flags(total)
264        ;
265
266    commitEligibleSamples
267        .name(name() + ".COM:bw_lim_events")
268        .desc("number cycles where commit BW limit reached")
269        ;
270}
271
272template <class Impl>
273void
274DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
275{
276    thread = threads;
277}
278
279template <class Impl>
280void
281DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
282{
283    timeBuffer = tb_ptr;
284
285    // Setup wire to send information back to IEW.
286    toIEW = timeBuffer->getWire(0);
287
288    // Setup wire to read data from IEW (for the ROB).
289    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
290}
291
292template <class Impl>
293void
294DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
295{
296    fetchQueue = fq_ptr;
297
298    // Setup wire to get instructions from rename (for the ROB).
299    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
300}
301
302template <class Impl>
303void
304DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
305{
306    renameQueue = rq_ptr;
307
308    // Setup wire to get instructions from rename (for the ROB).
309    fromRename = renameQueue->getWire(-renameToROBDelay);
310}
311
312template <class Impl>
313void
314DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
315{
316    iewQueue = iq_ptr;
317
318    // Setup wire to get instructions from IEW.
319    fromIEW = iewQueue->getWire(-iewToCommitDelay);
320}
321
322template <class Impl>
323void
324DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
325{
326    iewStage = iew_stage;
327}
328
329template<class Impl>
330void
331DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
332{
333    activeThreads = at_ptr;
334}
335
336template <class Impl>
337void
338DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
339{
340    for (ThreadID tid = 0; tid < numThreads; tid++)
341        renameMap[tid] = &rm_ptr[tid];
342}
343
344template <class Impl>
345void
346DefaultCommit<Impl>::setROB(ROB *rob_ptr)
347{
348    rob = rob_ptr;
349}
350
351template <class Impl>
352void
353DefaultCommit<Impl>::initStage()
354{
355    rob->setActiveThreads(activeThreads);
356    rob->resetEntries();
357
358    // Broadcast the number of free entries.
359    for (ThreadID tid = 0; tid < numThreads; tid++) {
360        toIEW->commitInfo[tid].usedROB = true;
361        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
362        toIEW->commitInfo[tid].emptyROB = true;
363    }
364
365    // Commit must broadcast the number of free entries it has at the
366    // start of the simulation, so it starts as active.
367    cpu->activateStage(O3CPU::CommitIdx);
368
369    cpu->activityThisCycle();
370    trapLatency = cpu->ticks(trapLatency);
371}
372
373template <class Impl>
374bool
375DefaultCommit<Impl>::drain()
376{
377    drainPending = true;
378
379    return false;
380}
381
382template <class Impl>
383void
384DefaultCommit<Impl>::switchOut()
385{
386    switchedOut = true;
387    drainPending = false;
388    rob->switchOut();
389}
390
391template <class Impl>
392void
393DefaultCommit<Impl>::resume()
394{
395    drainPending = false;
396}
397
398template <class Impl>
399void
400DefaultCommit<Impl>::takeOverFrom()
401{
402    switchedOut = false;
403    _status = Active;
404    _nextStatus = Inactive;
405    for (ThreadID tid = 0; tid < numThreads; tid++) {
406        commitStatus[tid] = Idle;
407        changedROBNumEntries[tid] = false;
408        trapSquash[tid] = false;
409        tcSquash[tid] = false;
410    }
411    squashCounter = 0;
412    rob->takeOverFrom();
413}
414
415template <class Impl>
416void
417DefaultCommit<Impl>::updateStatus()
418{
419    // reset ROB changed variable
420    list<ThreadID>::iterator threads = activeThreads->begin();
421    list<ThreadID>::iterator end = activeThreads->end();
422
423    while (threads != end) {
424        ThreadID tid = *threads++;
425
426        changedROBNumEntries[tid] = false;
427
428        // Also check if any of the threads has a trap pending
429        if (commitStatus[tid] == TrapPending ||
430            commitStatus[tid] == FetchTrapPending) {
431            _nextStatus = Active;
432        }
433    }
434
435    if (_nextStatus == Inactive && _status == Active) {
436        DPRINTF(Activity, "Deactivating stage.\n");
437        cpu->deactivateStage(O3CPU::CommitIdx);
438    } else if (_nextStatus == Active && _status == Inactive) {
439        DPRINTF(Activity, "Activating stage.\n");
440        cpu->activateStage(O3CPU::CommitIdx);
441    }
442
443    _status = _nextStatus;
444}
445
446template <class Impl>
447void
448DefaultCommit<Impl>::setNextStatus()
449{
450    int squashes = 0;
451
452    list<ThreadID>::iterator threads = activeThreads->begin();
453    list<ThreadID>::iterator end = activeThreads->end();
454
455    while (threads != end) {
456        ThreadID tid = *threads++;
457
458        if (commitStatus[tid] == ROBSquashing) {
459            squashes++;
460        }
461    }
462
463    squashCounter = squashes;
464
465    // If commit is currently squashing, then it will have activity for the
466    // next cycle. Set its next status as active.
467    if (squashCounter) {
468        _nextStatus = Active;
469    }
470}
471
472template <class Impl>
473bool
474DefaultCommit<Impl>::changedROBEntries()
475{
476    list<ThreadID>::iterator threads = activeThreads->begin();
477    list<ThreadID>::iterator end = activeThreads->end();
478
479    while (threads != end) {
480        ThreadID tid = *threads++;
481
482        if (changedROBNumEntries[tid]) {
483            return true;
484        }
485    }
486
487    return false;
488}
489
490template <class Impl>
491size_t
492DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
493{
494    return rob->numFreeEntries(tid);
495}
496
497template <class Impl>
498void
499DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
500{
501    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
502
503    TrapEvent *trap = new TrapEvent(this, tid);
504
505    cpu->schedule(trap, curTick() + trapLatency);
506    trapInFlight[tid] = true;
507}
508
509template <class Impl>
510void
511DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
512{
513    assert(!trapInFlight[tid]);
514    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
515
516    tcSquash[tid] = true;
517}
518
519template <class Impl>
520void
521DefaultCommit<Impl>::squashAll(ThreadID tid)
522{
523    // If we want to include the squashing instruction in the squash,
524    // then use one older sequence number.
525    // Hopefully this doesn't mess things up.  Basically I want to squash
526    // all instructions of this thread.
527    InstSeqNum squashed_inst = rob->isEmpty() ?
528        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
529
530    // All younger instructions will be squashed. Set the sequence
531    // number as the youngest instruction in the ROB (0 in this case.
532    // Hopefully nothing breaks.)
533    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
534
535    rob->squash(squashed_inst, tid);
536    changedROBNumEntries[tid] = true;
537
538    // Send back the sequence number of the squashed instruction.
539    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
540
541    // Send back the squash signal to tell stages that they should
542    // squash.
543    toIEW->commitInfo[tid].squash = true;
544
545    // Send back the rob squashing signal so other stages know that
546    // the ROB is in the process of squashing.
547    toIEW->commitInfo[tid].robSquashing = true;
548
549    toIEW->commitInfo[tid].mispredictInst = NULL;
550    toIEW->commitInfo[tid].squashInst = NULL;
551
552    toIEW->commitInfo[tid].pc = pc[tid];
553}
554
555template <class Impl>
556void
557DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
558{
559    squashAll(tid);
560
561    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
562
563    thread[tid]->trapPending = false;
564    thread[tid]->inSyscall = false;
565    trapInFlight[tid] = false;
566
567    trapSquash[tid] = false;
568
569    commitStatus[tid] = ROBSquashing;
570    cpu->activityThisCycle();
571}
572
573template <class Impl>
574void
575DefaultCommit<Impl>::squashFromTC(ThreadID tid)
576{
577    squashAll(tid);
578
579    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
580
581    thread[tid]->inSyscall = false;
582    assert(!thread[tid]->trapPending);
583
584    commitStatus[tid] = ROBSquashing;
585    cpu->activityThisCycle();
586
587    tcSquash[tid] = false;
588}
589
590template <class Impl>
591void
592DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
593        uint64_t squash_after_seq_num)
594{
595    youngestSeqNum[tid] = squash_after_seq_num;
596
597    rob->squash(squash_after_seq_num, tid);
598    changedROBNumEntries[tid] = true;
599
600    // Send back the sequence number of the squashed instruction.
601    toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
602
603    toIEW->commitInfo[tid].squashInst = head_inst;
604    // Send back the squash signal to tell stages that they should squash.
605    toIEW->commitInfo[tid].squash = true;
606
607    // Send back the rob squashing signal so other stages know that
608    // the ROB is in the process of squashing.
609    toIEW->commitInfo[tid].robSquashing = true;
610
611    toIEW->commitInfo[tid].mispredictInst = NULL;
612
613    toIEW->commitInfo[tid].pc = pc[tid];
614    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
615            tid, squash_after_seq_num);
616    commitStatus[tid] = ROBSquashing;
617}
618
619template <class Impl>
620void
621DefaultCommit<Impl>::tick()
622{
623    wroteToTimeBuffer = false;
624    _nextStatus = Inactive;
625
626    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
627        cpu->signalDrained();
628        drainPending = false;
629        return;
630    }
631
632    if (activeThreads->empty())
633        return;
634
635    list<ThreadID>::iterator threads = activeThreads->begin();
636    list<ThreadID>::iterator end = activeThreads->end();
637
638    // Check if any of the threads are done squashing.  Change the
639    // status if they are done.
640    while (threads != end) {
641        ThreadID tid = *threads++;
642
643        // Clear the bit saying if the thread has committed stores
644        // this cycle.
645        committedStores[tid] = false;
646
647        if (commitStatus[tid] == ROBSquashing) {
648
649            if (rob->isDoneSquashing(tid)) {
650                commitStatus[tid] = Running;
651            } else {
652                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
653                        " insts this cycle.\n", tid);
654                rob->doSquash(tid);
655                toIEW->commitInfo[tid].robSquashing = true;
656                wroteToTimeBuffer = true;
657            }
658        }
659    }
660
661    commit();
662
663    markCompletedInsts();
664
665    threads = activeThreads->begin();
666
667    while (threads != end) {
668        ThreadID tid = *threads++;
669
670        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
671            // The ROB has more instructions it can commit. Its next status
672            // will be active.
673            _nextStatus = Active;
674
675            DynInstPtr inst = rob->readHeadInst(tid);
676
677            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
678                    " ROB and ready to commit\n",
679                    tid, inst->seqNum, inst->pcState());
680
681        } else if (!rob->isEmpty(tid)) {
682            DynInstPtr inst = rob->readHeadInst(tid);
683
684            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
685                    "%s is head of ROB and not ready\n",
686                    tid, inst->seqNum, inst->pcState());
687        }
688
689        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
690                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
691    }
692
693
694    if (wroteToTimeBuffer) {
695        DPRINTF(Activity, "Activity This Cycle.\n");
696        cpu->activityThisCycle();
697    }
698
699    updateStatus();
700}
701
702#if FULL_SYSTEM
703template <class Impl>
704void
705DefaultCommit<Impl>::handleInterrupt()
706{
707    // Verify that we still have an interrupt to handle
708    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
709        DPRINTF(Commit, "Pending interrupt is cleared by master before "
710                "it got handled. Restart fetching from the orig path.\n");
711        toIEW->commitInfo[0].clearInterrupt = true;
712        interrupt = NoFault;
713        return;
714    }
715
716    // Wait until the ROB is empty and all stores have drained in
717    // order to enter the interrupt.
718    if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
719        // Squash or record that I need to squash this cycle if
720        // an interrupt needed to be handled.
721        DPRINTF(Commit, "Interrupt detected.\n");
722
723        // Clear the interrupt now that it's going to be handled
724        toIEW->commitInfo[0].clearInterrupt = true;
725
726        assert(!thread[0]->inSyscall);
727        thread[0]->inSyscall = true;
728
729        // CPU will handle interrupt.
730        cpu->processInterrupts(interrupt);
731
732        thread[0]->inSyscall = false;
733
734        commitStatus[0] = TrapPending;
735
736        // Generate trap squash event.
737        generateTrapEvent(0);
738
739        interrupt = NoFault;
740    } else {
741        DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
742    }
743}
744
745template <class Impl>
746void
747DefaultCommit<Impl>::propagateInterrupt()
748{
749    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
750            tcSquash[0])
751        return;
752
753    // Process interrupts if interrupts are enabled, not in PAL
754    // mode, and no other traps or external squashes are currently
755    // pending.
756    // @todo: Allow other threads to handle interrupts.
757
758    // Get any interrupt that happened
759    interrupt = cpu->getInterrupts();
760
761    // Tell fetch that there is an interrupt pending.  This
762    // will make fetch wait until it sees a non PAL-mode PC,
763    // at which point it stops fetching instructions.
764    if (interrupt != NoFault)
765        toIEW->commitInfo[0].interruptPending = true;
766}
767
768#endif // FULL_SYSTEM
769
770template <class Impl>
771void
772DefaultCommit<Impl>::commit()
773{
774
775#if FULL_SYSTEM
776    // Check for any interrupt that we've already squashed for and start processing it.
777    if (interrupt != NoFault)
778        handleInterrupt();
779
780    // Check if we have a interrupt and get read to handle it
781    if (cpu->checkInterrupts(cpu->tcBase(0)))
782        propagateInterrupt();
783#endif // FULL_SYSTEM
784
785    ////////////////////////////////////
786    // Check for any possible squashes, handle them first
787    ////////////////////////////////////
788    list<ThreadID>::iterator threads = activeThreads->begin();
789    list<ThreadID>::iterator end = activeThreads->end();
790
791    while (threads != end) {
792        ThreadID tid = *threads++;
793
794        // Not sure which one takes priority.  I think if we have
795        // both, that's a bad sign.
796        if (trapSquash[tid] == true) {
797            assert(!tcSquash[tid]);
798            squashFromTrap(tid);
799        } else if (tcSquash[tid] == true) {
800            assert(commitStatus[tid] != TrapPending);
801            squashFromTC(tid);
802        }
803
804        // Squashed sequence number must be older than youngest valid
805        // instruction in the ROB. This prevents squashes from younger
806        // instructions overriding squashes from older instructions.
807        if (fromIEW->squash[tid] &&
808            commitStatus[tid] != TrapPending &&
809            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
810
811            if (fromIEW->mispredictInst[tid]) {
812                DPRINTF(Commit,
813                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
814                    tid,
815                    fromIEW->mispredictInst[tid]->instAddr(),
816                    fromIEW->squashedSeqNum[tid]);
817            } else {
818                DPRINTF(Commit,
819                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
820                    tid, fromIEW->squashedSeqNum[tid]);
821            }
822
823            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
824                    tid,
825                    fromIEW->pc[tid].nextInstAddr());
826
827            commitStatus[tid] = ROBSquashing;
828
829            // If we want to include the squashing instruction in the squash,
830            // then use one older sequence number.
831            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
832
833            if (fromIEW->includeSquashInst[tid] == true) {
834                squashed_inst--;
835            }
836
837            // All younger instructions will be squashed. Set the sequence
838            // number as the youngest instruction in the ROB.
839            youngestSeqNum[tid] = squashed_inst;
840
841            rob->squash(squashed_inst, tid);
842            changedROBNumEntries[tid] = true;
843
844            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
845
846            toIEW->commitInfo[tid].squash = true;
847
848            // Send back the rob squashing signal so other stages know that
849            // the ROB is in the process of squashing.
850            toIEW->commitInfo[tid].robSquashing = true;
851
852            toIEW->commitInfo[tid].mispredictInst =
853                fromIEW->mispredictInst[tid];
854            toIEW->commitInfo[tid].branchTaken =
855                fromIEW->branchTaken[tid];
856            toIEW->commitInfo[tid].squashInst = NULL;
857
858            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
859
860            if (toIEW->commitInfo[tid].mispredictInst) {
861                ++branchMispredicts;
862            }
863        }
864
865    }
866
867    setNextStatus();
868
869    if (squashCounter != numThreads) {
870        // If we're not currently squashing, then get instructions.
871        getInsts();
872
873        // Try to commit any instructions.
874        commitInsts();
875    }
876
877    //Check for any activity
878    threads = activeThreads->begin();
879
880    while (threads != end) {
881        ThreadID tid = *threads++;
882
883        if (changedROBNumEntries[tid]) {
884            toIEW->commitInfo[tid].usedROB = true;
885            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
886
887            wroteToTimeBuffer = true;
888            changedROBNumEntries[tid] = false;
889            if (rob->isEmpty(tid))
890                checkEmptyROB[tid] = true;
891        }
892
893        // ROB is only considered "empty" for previous stages if: a)
894        // ROB is empty, b) there are no outstanding stores, c) IEW
895        // stage has received any information regarding stores that
896        // committed.
897        // c) is checked by making sure to not consider the ROB empty
898        // on the same cycle as when stores have been committed.
899        // @todo: Make this handle multi-cycle communication between
900        // commit and IEW.
901        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
902            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
903            checkEmptyROB[tid] = false;
904            toIEW->commitInfo[tid].usedROB = true;
905            toIEW->commitInfo[tid].emptyROB = true;
906            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
907            wroteToTimeBuffer = true;
908        }
909
910    }
911}
912
913template <class Impl>
914void
915DefaultCommit<Impl>::commitInsts()
916{
917    ////////////////////////////////////
918    // Handle commit
919    // Note that commit will be handled prior to putting new
920    // instructions in the ROB so that the ROB only tries to commit
921    // instructions it has in this current cycle, and not instructions
922    // it is writing in during this cycle.  Can't commit and squash
923    // things at the same time...
924    ////////////////////////////////////
925
926    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
927
928    unsigned num_committed = 0;
929
930    DynInstPtr head_inst;
931
932    // Commit as many instructions as possible until the commit bandwidth
933    // limit is reached, or it becomes impossible to commit any more.
934    while (num_committed < commitWidth) {
935        int commit_thread = getCommittingThread();
936
937        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
938            break;
939
940        head_inst = rob->readHeadInst(commit_thread);
941
942        ThreadID tid = head_inst->threadNumber;
943
944        assert(tid == commit_thread);
945
946        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
947                head_inst->seqNum, tid);
948
949        // If the head instruction is squashed, it is ready to retire
950        // (be removed from the ROB) at any time.
951        if (head_inst->isSquashed()) {
952
953            DPRINTF(Commit, "Retiring squashed instruction from "
954                    "ROB.\n");
955
956            rob->retireHead(commit_thread);
957
958            ++commitSquashedInsts;
959
960            // Record that the number of ROB entries has changed.
961            changedROBNumEntries[tid] = true;
962        } else {
963            pc[tid] = head_inst->pcState();
964
965            // Increment the total number of non-speculative instructions
966            // executed.
967            // Hack for now: it really shouldn't happen until after the
968            // commit is deemed to be successful, but this count is needed
969            // for syscalls.
970            thread[tid]->funcExeInst++;
971
972            // Try to commit the head instruction.
973            bool commit_success = commitHead(head_inst, num_committed);
974
975            if (commit_success) {
976                ++num_committed;
977
978                changedROBNumEntries[tid] = true;
979
980                // Set the doneSeqNum to the youngest committed instruction.
981                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
982
983                ++commitCommittedInsts;
984
985                // To match the old model, don't count nops and instruction
986                // prefetches towards the total commit count.
987                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
988                    cpu->instDone(tid);
989                }
990
991                // Updates misc. registers.
992                head_inst->updateMiscRegs();
993
994                TheISA::advancePC(pc[tid], head_inst->staticInst);
995
996                // Keep track of the last sequence number commited
997                lastCommitedSeqNum[tid] = head_inst->seqNum;
998
999                // If this is an instruction that doesn't play nicely with
1000                // others squash everything and restart fetch
1001                if (head_inst->isSquashAfter())
1002                    squashAfter(tid, head_inst, head_inst->seqNum);
1003
1004                int count = 0;
1005                Addr oldpc;
1006                // Debug statement.  Checks to make sure we're not
1007                // currently updating state while handling PC events.
1008                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1009                do {
1010                    oldpc = pc[tid].instAddr();
1011                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
1012                    count++;
1013                } while (oldpc != pc[tid].instAddr());
1014                if (count > 1) {
1015                    DPRINTF(Commit,
1016                            "PC skip function event, stopping commit\n");
1017                    break;
1018                }
1019            } else {
1020                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1021                        "[tid:%i] [sn:%i].\n",
1022                        head_inst->pcState(), tid ,head_inst->seqNum);
1023                break;
1024            }
1025        }
1026    }
1027
1028    DPRINTF(CommitRate, "%i\n", num_committed);
1029    numCommittedDist.sample(num_committed);
1030
1031    if (num_committed == commitWidth) {
1032        commitEligibleSamples++;
1033    }
1034}
1035
1036template <class Impl>
1037bool
1038DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1039{
1040    assert(head_inst);
1041
1042    ThreadID tid = head_inst->threadNumber;
1043
1044    // If the instruction is not executed yet, then it will need extra
1045    // handling.  Signal backwards that it should be executed.
1046    if (!head_inst->isExecuted()) {
1047        // Keep this number correct.  We have not yet actually executed
1048        // and committed this instruction.
1049        thread[tid]->funcExeInst--;
1050
1051        if (head_inst->isNonSpeculative() ||
1052            head_inst->isStoreConditional() ||
1053            head_inst->isMemBarrier() ||
1054            head_inst->isWriteBarrier()) {
1055
1056            DPRINTF(Commit, "Encountered a barrier or non-speculative "
1057                    "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1058                    head_inst->seqNum, head_inst->pcState());
1059
1060            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1061                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1062                return false;
1063            }
1064
1065            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1066
1067            // Change the instruction so it won't try to commit again until
1068            // it is executed.
1069            head_inst->clearCanCommit();
1070
1071            ++commitNonSpecStalls;
1072
1073            return false;
1074        } else if (head_inst->isLoad()) {
1075            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1076                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1077                return false;
1078            }
1079
1080            assert(head_inst->uncacheable());
1081            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1082                    head_inst->seqNum, head_inst->pcState());
1083
1084            // Send back the non-speculative instruction's sequence
1085            // number.  Tell the lsq to re-execute the load.
1086            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1087            toIEW->commitInfo[tid].uncached = true;
1088            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1089
1090            head_inst->clearCanCommit();
1091
1092            return false;
1093        } else {
1094            panic("Trying to commit un-executed instruction "
1095                  "of unknown type!\n");
1096        }
1097    }
1098
1099    if (head_inst->isThreadSync()) {
1100        // Not handled for now.
1101        panic("Thread sync instructions are not handled yet.\n");
1102    }
1103
1104    // Check if the instruction caused a fault.  If so, trap.
1105    Fault inst_fault = head_inst->getFault();
1106
1107    // Stores mark themselves as completed.
1108    if (!head_inst->isStore() && inst_fault == NoFault) {
1109        head_inst->setCompleted();
1110    }
1111
1112#if USE_CHECKER
1113    // Use checker prior to updating anything due to traps or PC
1114    // based events.
1115    if (cpu->checker) {
1116        cpu->checker->verify(head_inst);
1117    }
1118#endif
1119
1120    if (inst_fault != NoFault) {
1121        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1122                head_inst->seqNum, head_inst->pcState());
1123
1124        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1125            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1126            return false;
1127        }
1128
1129        head_inst->setCompleted();
1130
1131#if USE_CHECKER
1132        if (cpu->checker && head_inst->isStore()) {
1133            cpu->checker->verify(head_inst);
1134        }
1135#endif
1136
1137        assert(!thread[tid]->inSyscall);
1138
1139        // Mark that we're in state update mode so that the trap's
1140        // execution doesn't generate extra squashes.
1141        thread[tid]->inSyscall = true;
1142
1143        // Execute the trap.  Although it's slightly unrealistic in
1144        // terms of timing (as it doesn't wait for the full timing of
1145        // the trap event to complete before updating state), it's
1146        // needed to update the state as soon as possible.  This
1147        // prevents external agents from changing any specific state
1148        // that the trap need.
1149        cpu->trap(inst_fault, tid, head_inst->staticInst);
1150
1151        // Exit state update mode to avoid accidental updating.
1152        thread[tid]->inSyscall = false;
1153
1154        commitStatus[tid] = TrapPending;
1155
1156        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1157            head_inst->seqNum);
1158        if (head_inst->traceData) {
1159            if (DTRACE(ExecFaulting)) {
1160                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1161                head_inst->traceData->setCPSeq(thread[tid]->numInst);
1162                head_inst->traceData->dump();
1163            }
1164            delete head_inst->traceData;
1165            head_inst->traceData = NULL;
1166        }
1167
1168        // Generate trap squash event.
1169        generateTrapEvent(tid);
1170        return false;
1171    }
1172
1173    updateComInstStats(head_inst);
1174
1175#if FULL_SYSTEM
1176    if (thread[tid]->profile) {
1177        thread[tid]->profilePC = head_inst->instAddr();
1178        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1179                                                          head_inst->staticInst);
1180
1181        if (node)
1182            thread[tid]->profileNode = node;
1183    }
1184    if (CPA::available()) {
1185        if (head_inst->isControl()) {
1186            ThreadContext *tc = thread[tid]->getTC();
1187            CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1188        }
1189    }
1190#endif
1191    DPRINTF(Commit, "Committing instruction with [sn:%lli]\n",
1192            head_inst->seqNum);
1193    if (head_inst->traceData) {
1194        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1195        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1196        head_inst->traceData->dump();
1197        delete head_inst->traceData;
1198        head_inst->traceData = NULL;
1199    }
1200
1201    // Update the commit rename map
1202    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1203        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1204                                 head_inst->renamedDestRegIdx(i));
1205    }
1206
1207    // Finally clear the head ROB entry.
1208    rob->retireHead(tid);
1209
1210    // If this was a store, record it for this cycle.
1211    if (head_inst->isStore())
1212        committedStores[tid] = true;
1213
1214    // Return true to indicate that we have committed an instruction.
1215    return true;
1216}
1217
1218template <class Impl>
1219void
1220DefaultCommit<Impl>::getInsts()
1221{
1222    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1223
1224    // Read any renamed instructions and place them into the ROB.
1225    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1226
1227    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1228        DynInstPtr inst;
1229
1230        inst = fromRename->insts[inst_num];
1231        ThreadID tid = inst->threadNumber;
1232
1233        if (!inst->isSquashed() &&
1234            commitStatus[tid] != ROBSquashing &&
1235            commitStatus[tid] != TrapPending) {
1236            changedROBNumEntries[tid] = true;
1237
1238            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1239                    inst->pcState(), inst->seqNum, tid);
1240
1241            rob->insertInst(inst);
1242
1243            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1244
1245            youngestSeqNum[tid] = inst->seqNum;
1246        } else {
1247            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1248                    "squashed, skipping.\n",
1249                    inst->pcState(), inst->seqNum, tid);
1250        }
1251    }
1252}
1253
1254template <class Impl>
1255void
1256DefaultCommit<Impl>::skidInsert()
1257{
1258    DPRINTF(Commit, "Attempting to any instructions from rename into "
1259            "skidBuffer.\n");
1260
1261    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1262        DynInstPtr inst = fromRename->insts[inst_num];
1263
1264        if (!inst->isSquashed()) {
1265            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1266                    "skidBuffer.\n", inst->pcState(), inst->seqNum,
1267                    inst->threadNumber);
1268            skidBuffer.push(inst);
1269        } else {
1270            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1271                    "squashed, skipping.\n",
1272                    inst->pcState(), inst->seqNum, inst->threadNumber);
1273        }
1274    }
1275}
1276
1277template <class Impl>
1278void
1279DefaultCommit<Impl>::markCompletedInsts()
1280{
1281    // Grab completed insts out of the IEW instruction queue, and mark
1282    // instructions completed within the ROB.
1283    for (int inst_num = 0;
1284         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1285         ++inst_num)
1286    {
1287        if (!fromIEW->insts[inst_num]->isSquashed()) {
1288            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1289                    "within ROB.\n",
1290                    fromIEW->insts[inst_num]->threadNumber,
1291                    fromIEW->insts[inst_num]->pcState(),
1292                    fromIEW->insts[inst_num]->seqNum);
1293
1294            // Mark the instruction as ready to commit.
1295            fromIEW->insts[inst_num]->setCanCommit();
1296        }
1297    }
1298}
1299
1300template <class Impl>
1301bool
1302DefaultCommit<Impl>::robDoneSquashing()
1303{
1304    list<ThreadID>::iterator threads = activeThreads->begin();
1305    list<ThreadID>::iterator end = activeThreads->end();
1306
1307    while (threads != end) {
1308        ThreadID tid = *threads++;
1309
1310        if (!rob->isDoneSquashing(tid))
1311            return false;
1312    }
1313
1314    return true;
1315}
1316
1317template <class Impl>
1318void
1319DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1320{
1321    ThreadID tid = inst->threadNumber;
1322
1323    //
1324    //  Pick off the software prefetches
1325    //
1326#ifdef TARGET_ALPHA
1327    if (inst->isDataPrefetch()) {
1328        statComSwp[tid]++;
1329    } else {
1330        statComInst[tid]++;
1331    }
1332#else
1333    statComInst[tid]++;
1334#endif
1335
1336    //
1337    //  Control Instructions
1338    //
1339    if (inst->isControl())
1340        statComBranches[tid]++;
1341
1342    //
1343    //  Memory references
1344    //
1345    if (inst->isMemRef()) {
1346        statComRefs[tid]++;
1347
1348        if (inst->isLoad()) {
1349            statComLoads[tid]++;
1350        }
1351    }
1352
1353    if (inst->isMemBarrier()) {
1354        statComMembars[tid]++;
1355    }
1356
1357    // Integer Instruction
1358    if (inst->isInteger())
1359        statComInteger[tid]++;
1360
1361    // Floating Point Instruction
1362    if (inst->isFloating())
1363        statComFloating[tid]++;
1364
1365    // Function Calls
1366    if (inst->isCall())
1367        statComFunctionCalls[tid]++;
1368
1369}
1370
1371////////////////////////////////////////
1372//                                    //
1373//  SMT COMMIT POLICY MAINTAINED HERE //
1374//                                    //
1375////////////////////////////////////////
1376template <class Impl>
1377ThreadID
1378DefaultCommit<Impl>::getCommittingThread()
1379{
1380    if (numThreads > 1) {
1381        switch (commitPolicy) {
1382
1383          case Aggressive:
1384            //If Policy is Aggressive, commit will call
1385            //this function multiple times per
1386            //cycle
1387            return oldestReady();
1388
1389          case RoundRobin:
1390            return roundRobin();
1391
1392          case OldestReady:
1393            return oldestReady();
1394
1395          default:
1396            return InvalidThreadID;
1397        }
1398    } else {
1399        assert(!activeThreads->empty());
1400        ThreadID tid = activeThreads->front();
1401
1402        if (commitStatus[tid] == Running ||
1403            commitStatus[tid] == Idle ||
1404            commitStatus[tid] == FetchTrapPending) {
1405            return tid;
1406        } else {
1407            return InvalidThreadID;
1408        }
1409    }
1410}
1411
1412template<class Impl>
1413ThreadID
1414DefaultCommit<Impl>::roundRobin()
1415{
1416    list<ThreadID>::iterator pri_iter = priority_list.begin();
1417    list<ThreadID>::iterator end      = priority_list.end();
1418
1419    while (pri_iter != end) {
1420        ThreadID tid = *pri_iter;
1421
1422        if (commitStatus[tid] == Running ||
1423            commitStatus[tid] == Idle ||
1424            commitStatus[tid] == FetchTrapPending) {
1425
1426            if (rob->isHeadReady(tid)) {
1427                priority_list.erase(pri_iter);
1428                priority_list.push_back(tid);
1429
1430                return tid;
1431            }
1432        }
1433
1434        pri_iter++;
1435    }
1436
1437    return InvalidThreadID;
1438}
1439
1440template<class Impl>
1441ThreadID
1442DefaultCommit<Impl>::oldestReady()
1443{
1444    unsigned oldest = 0;
1445    bool first = true;
1446
1447    list<ThreadID>::iterator threads = activeThreads->begin();
1448    list<ThreadID>::iterator end = activeThreads->end();
1449
1450    while (threads != end) {
1451        ThreadID tid = *threads++;
1452
1453        if (!rob->isEmpty(tid) &&
1454            (commitStatus[tid] == Running ||
1455             commitStatus[tid] == Idle ||
1456             commitStatus[tid] == FetchTrapPending)) {
1457
1458            if (rob->isHeadReady(tid)) {
1459
1460                DynInstPtr head_inst = rob->readHeadInst(tid);
1461
1462                if (first) {
1463                    oldest = tid;
1464                    first = false;
1465                } else if (head_inst->seqNum < oldest) {
1466                    oldest = tid;
1467                }
1468            }
1469        }
1470    }
1471
1472    if (!first) {
1473        return oldest;
1474    } else {
1475        return InvalidThreadID;
1476    }
1477}
1478