commit_impl.hh revision 7855:c0be563517da 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/cp_annotate.hh"
49#include "base/loader/symtab.hh"
50#include "cpu/timebuf.hh"
51#include "config/full_system.hh"
52#include "config/the_isa.hh"
53#include "config/use_checker.hh"
54#include "cpu/exetrace.hh"
55#include "cpu/o3/commit.hh"
56#include "cpu/o3/thread_state.hh"
57#include "params/DerivO3CPU.hh"
58
59#if USE_CHECKER
60#include "cpu/checker/cpu.hh"
61#endif
62
63using namespace std;
64
65template <class Impl>
66DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
67                                          ThreadID _tid)
68    : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
69{
70    this->setFlags(AutoDelete);
71}
72
73template <class Impl>
74void
75DefaultCommit<Impl>::TrapEvent::process()
76{
77    // This will get reset by commit if it was switched out at the
78    // time of this event processing.
79    commit->trapSquash[tid] = true;
80}
81
82template <class Impl>
83const char *
84DefaultCommit<Impl>::TrapEvent::description() const
85{
86    return "Trap";
87}
88
89template <class Impl>
90DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
91    : cpu(_cpu),
92      squashCounter(0),
93      iewToCommitDelay(params->iewToCommitDelay),
94      commitToIEWDelay(params->commitToIEWDelay),
95      renameToROBDelay(params->renameToROBDelay),
96      fetchToCommitDelay(params->commitToFetchDelay),
97      renameWidth(params->renameWidth),
98      commitWidth(params->commitWidth),
99      numThreads(params->numThreads),
100      drainPending(false),
101      switchedOut(false),
102      trapLatency(params->trapLatency)
103{
104    _status = Active;
105    _nextStatus = Inactive;
106    std::string policy = params->smtCommitPolicy;
107
108    //Convert string to lowercase
109    std::transform(policy.begin(), policy.end(), policy.begin(),
110                   (int(*)(int)) tolower);
111
112    //Assign commit policy
113    if (policy == "aggressive"){
114        commitPolicy = Aggressive;
115
116        DPRINTF(Commit,"Commit Policy set to Aggressive.");
117    } else if (policy == "roundrobin"){
118        commitPolicy = RoundRobin;
119
120        //Set-Up Priority List
121        for (ThreadID tid = 0; tid < numThreads; tid++) {
122            priority_list.push_back(tid);
123        }
124
125        DPRINTF(Commit,"Commit Policy set to Round Robin.");
126    } else if (policy == "oldestready"){
127        commitPolicy = OldestReady;
128
129        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
130    } else {
131        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
132               "RoundRobin,OldestReady}");
133    }
134
135    for (ThreadID tid = 0; tid < numThreads; tid++) {
136        commitStatus[tid] = Idle;
137        changedROBNumEntries[tid] = false;
138        checkEmptyROB[tid] = false;
139        trapInFlight[tid] = false;
140        committedStores[tid] = false;
141        trapSquash[tid] = false;
142        tcSquash[tid] = false;
143        pc[tid].set(0);
144        lastCommitedSeqNum[tid] = 0;
145    }
146#if FULL_SYSTEM
147    interrupt = NoFault;
148#endif
149}
150
151template <class Impl>
152std::string
153DefaultCommit<Impl>::name() const
154{
155    return cpu->name() + ".commit";
156}
157
158template <class Impl>
159void
160DefaultCommit<Impl>::regStats()
161{
162    using namespace Stats;
163    commitCommittedInsts
164        .name(name() + ".commitCommittedInsts")
165        .desc("The number of committed instructions")
166        .prereq(commitCommittedInsts);
167    commitSquashedInsts
168        .name(name() + ".commitSquashedInsts")
169        .desc("The number of squashed insts skipped by commit")
170        .prereq(commitSquashedInsts);
171    commitSquashEvents
172        .name(name() + ".commitSquashEvents")
173        .desc("The number of times commit is told to squash")
174        .prereq(commitSquashEvents);
175    commitNonSpecStalls
176        .name(name() + ".commitNonSpecStalls")
177        .desc("The number of times commit has been forced to stall to "
178              "communicate backwards")
179        .prereq(commitNonSpecStalls);
180    branchMispredicts
181        .name(name() + ".branchMispredicts")
182        .desc("The number of times a branch was mispredicted")
183        .prereq(branchMispredicts);
184    numCommittedDist
185        .init(0,commitWidth,1)
186        .name(name() + ".COM:committed_per_cycle")
187        .desc("Number of insts commited each cycle")
188        .flags(Stats::pdf)
189        ;
190
191    statComInst
192        .init(cpu->numThreads)
193        .name(name() + ".COM:count")
194        .desc("Number of instructions committed")
195        .flags(total)
196        ;
197
198    statComSwp
199        .init(cpu->numThreads)
200        .name(name() + ".COM:swp_count")
201        .desc("Number of s/w prefetches committed")
202        .flags(total)
203        ;
204
205    statComRefs
206        .init(cpu->numThreads)
207        .name(name() +  ".COM:refs")
208        .desc("Number of memory references committed")
209        .flags(total)
210        ;
211
212    statComLoads
213        .init(cpu->numThreads)
214        .name(name() +  ".COM:loads")
215        .desc("Number of loads committed")
216        .flags(total)
217        ;
218
219    statComMembars
220        .init(cpu->numThreads)
221        .name(name() +  ".COM:membars")
222        .desc("Number of memory barriers committed")
223        .flags(total)
224        ;
225
226    statComBranches
227        .init(cpu->numThreads)
228        .name(name() + ".COM:branches")
229        .desc("Number of branches committed")
230        .flags(total)
231        ;
232
233    commitEligible
234        .init(cpu->numThreads)
235        .name(name() + ".COM:bw_limited")
236        .desc("number of insts not committed due to BW limits")
237        .flags(total)
238        ;
239
240    commitEligibleSamples
241        .name(name() + ".COM:bw_lim_events")
242        .desc("number cycles where commit BW limit reached")
243        ;
244}
245
246template <class Impl>
247void
248DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
249{
250    thread = threads;
251}
252
253template <class Impl>
254void
255DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
256{
257    timeBuffer = tb_ptr;
258
259    // Setup wire to send information back to IEW.
260    toIEW = timeBuffer->getWire(0);
261
262    // Setup wire to read data from IEW (for the ROB).
263    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
264}
265
266template <class Impl>
267void
268DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
269{
270    fetchQueue = fq_ptr;
271
272    // Setup wire to get instructions from rename (for the ROB).
273    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
274}
275
276template <class Impl>
277void
278DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
279{
280    renameQueue = rq_ptr;
281
282    // Setup wire to get instructions from rename (for the ROB).
283    fromRename = renameQueue->getWire(-renameToROBDelay);
284}
285
286template <class Impl>
287void
288DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
289{
290    iewQueue = iq_ptr;
291
292    // Setup wire to get instructions from IEW.
293    fromIEW = iewQueue->getWire(-iewToCommitDelay);
294}
295
296template <class Impl>
297void
298DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
299{
300    iewStage = iew_stage;
301}
302
303template<class Impl>
304void
305DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
306{
307    activeThreads = at_ptr;
308}
309
310template <class Impl>
311void
312DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
313{
314    for (ThreadID tid = 0; tid < numThreads; tid++)
315        renameMap[tid] = &rm_ptr[tid];
316}
317
318template <class Impl>
319void
320DefaultCommit<Impl>::setROB(ROB *rob_ptr)
321{
322    rob = rob_ptr;
323}
324
325template <class Impl>
326void
327DefaultCommit<Impl>::initStage()
328{
329    rob->setActiveThreads(activeThreads);
330    rob->resetEntries();
331
332    // Broadcast the number of free entries.
333    for (ThreadID tid = 0; tid < numThreads; tid++) {
334        toIEW->commitInfo[tid].usedROB = true;
335        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
336        toIEW->commitInfo[tid].emptyROB = true;
337    }
338
339    // Commit must broadcast the number of free entries it has at the
340    // start of the simulation, so it starts as active.
341    cpu->activateStage(O3CPU::CommitIdx);
342
343    cpu->activityThisCycle();
344    trapLatency = cpu->ticks(trapLatency);
345}
346
347template <class Impl>
348bool
349DefaultCommit<Impl>::drain()
350{
351    drainPending = true;
352
353    return false;
354}
355
356template <class Impl>
357void
358DefaultCommit<Impl>::switchOut()
359{
360    switchedOut = true;
361    drainPending = false;
362    rob->switchOut();
363}
364
365template <class Impl>
366void
367DefaultCommit<Impl>::resume()
368{
369    drainPending = false;
370}
371
372template <class Impl>
373void
374DefaultCommit<Impl>::takeOverFrom()
375{
376    switchedOut = false;
377    _status = Active;
378    _nextStatus = Inactive;
379    for (ThreadID tid = 0; tid < numThreads; tid++) {
380        commitStatus[tid] = Idle;
381        changedROBNumEntries[tid] = false;
382        trapSquash[tid] = false;
383        tcSquash[tid] = false;
384    }
385    squashCounter = 0;
386    rob->takeOverFrom();
387}
388
389template <class Impl>
390void
391DefaultCommit<Impl>::updateStatus()
392{
393    // reset ROB changed variable
394    list<ThreadID>::iterator threads = activeThreads->begin();
395    list<ThreadID>::iterator end = activeThreads->end();
396
397    while (threads != end) {
398        ThreadID tid = *threads++;
399
400        changedROBNumEntries[tid] = false;
401
402        // Also check if any of the threads has a trap pending
403        if (commitStatus[tid] == TrapPending ||
404            commitStatus[tid] == FetchTrapPending) {
405            _nextStatus = Active;
406        }
407    }
408
409    if (_nextStatus == Inactive && _status == Active) {
410        DPRINTF(Activity, "Deactivating stage.\n");
411        cpu->deactivateStage(O3CPU::CommitIdx);
412    } else if (_nextStatus == Active && _status == Inactive) {
413        DPRINTF(Activity, "Activating stage.\n");
414        cpu->activateStage(O3CPU::CommitIdx);
415    }
416
417    _status = _nextStatus;
418}
419
420template <class Impl>
421void
422DefaultCommit<Impl>::setNextStatus()
423{
424    int squashes = 0;
425
426    list<ThreadID>::iterator threads = activeThreads->begin();
427    list<ThreadID>::iterator end = activeThreads->end();
428
429    while (threads != end) {
430        ThreadID tid = *threads++;
431
432        if (commitStatus[tid] == ROBSquashing) {
433            squashes++;
434        }
435    }
436
437    squashCounter = squashes;
438
439    // If commit is currently squashing, then it will have activity for the
440    // next cycle. Set its next status as active.
441    if (squashCounter) {
442        _nextStatus = Active;
443    }
444}
445
446template <class Impl>
447bool
448DefaultCommit<Impl>::changedROBEntries()
449{
450    list<ThreadID>::iterator threads = activeThreads->begin();
451    list<ThreadID>::iterator end = activeThreads->end();
452
453    while (threads != end) {
454        ThreadID tid = *threads++;
455
456        if (changedROBNumEntries[tid]) {
457            return true;
458        }
459    }
460
461    return false;
462}
463
464template <class Impl>
465size_t
466DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
467{
468    return rob->numFreeEntries(tid);
469}
470
471template <class Impl>
472void
473DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
474{
475    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
476
477    TrapEvent *trap = new TrapEvent(this, tid);
478
479    cpu->schedule(trap, curTick() + trapLatency);
480    trapInFlight[tid] = true;
481}
482
483template <class Impl>
484void
485DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
486{
487    assert(!trapInFlight[tid]);
488    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
489
490    tcSquash[tid] = true;
491}
492
493template <class Impl>
494void
495DefaultCommit<Impl>::squashAll(ThreadID tid)
496{
497    // If we want to include the squashing instruction in the squash,
498    // then use one older sequence number.
499    // Hopefully this doesn't mess things up.  Basically I want to squash
500    // all instructions of this thread.
501    InstSeqNum squashed_inst = rob->isEmpty() ?
502        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
503
504    // All younger instructions will be squashed. Set the sequence
505    // number as the youngest instruction in the ROB (0 in this case.
506    // Hopefully nothing breaks.)
507    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
508
509    rob->squash(squashed_inst, tid);
510    changedROBNumEntries[tid] = true;
511
512    // Send back the sequence number of the squashed instruction.
513    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
514
515    // Send back the squash signal to tell stages that they should
516    // squash.
517    toIEW->commitInfo[tid].squash = true;
518
519    // Send back the rob squashing signal so other stages know that
520    // the ROB is in the process of squashing.
521    toIEW->commitInfo[tid].robSquashing = true;
522
523    toIEW->commitInfo[tid].branchMispredict = false;
524    toIEW->commitInfo[tid].mispredictInst = NULL;
525
526    toIEW->commitInfo[tid].pc = pc[tid];
527}
528
529template <class Impl>
530void
531DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
532{
533    squashAll(tid);
534
535    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
536
537    thread[tid]->trapPending = false;
538    thread[tid]->inSyscall = false;
539    trapInFlight[tid] = false;
540
541    trapSquash[tid] = false;
542
543    commitStatus[tid] = ROBSquashing;
544    cpu->activityThisCycle();
545}
546
547template <class Impl>
548void
549DefaultCommit<Impl>::squashFromTC(ThreadID tid)
550{
551    squashAll(tid);
552
553    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
554
555    thread[tid]->inSyscall = false;
556    assert(!thread[tid]->trapPending);
557
558    commitStatus[tid] = ROBSquashing;
559    cpu->activityThisCycle();
560
561    tcSquash[tid] = false;
562}
563
564template <class Impl>
565void
566DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
567{
568    youngestSeqNum[tid] = squash_after_seq_num;
569
570    rob->squash(squash_after_seq_num, tid);
571    changedROBNumEntries[tid] = true;
572
573    // Send back the sequence number of the squashed instruction.
574    toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
575
576    // Send back the squash signal to tell stages that they should squash.
577    toIEW->commitInfo[tid].squash = true;
578
579    // Send back the rob squashing signal so other stages know that
580    // the ROB is in the process of squashing.
581    toIEW->commitInfo[tid].robSquashing = true;
582
583    toIEW->commitInfo[tid].branchMispredict = false;
584
585    toIEW->commitInfo[tid].pc = pc[tid];
586    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
587            tid, squash_after_seq_num);
588    commitStatus[tid] = ROBSquashing;
589}
590
591template <class Impl>
592void
593DefaultCommit<Impl>::tick()
594{
595    wroteToTimeBuffer = false;
596    _nextStatus = Inactive;
597
598    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
599        cpu->signalDrained();
600        drainPending = false;
601        return;
602    }
603
604    if (activeThreads->empty())
605        return;
606
607    list<ThreadID>::iterator threads = activeThreads->begin();
608    list<ThreadID>::iterator end = activeThreads->end();
609
610    // Check if any of the threads are done squashing.  Change the
611    // status if they are done.
612    while (threads != end) {
613        ThreadID tid = *threads++;
614
615        // Clear the bit saying if the thread has committed stores
616        // this cycle.
617        committedStores[tid] = false;
618
619        if (commitStatus[tid] == ROBSquashing) {
620
621            if (rob->isDoneSquashing(tid)) {
622                commitStatus[tid] = Running;
623            } else {
624                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
625                        " insts this cycle.\n", tid);
626                rob->doSquash(tid);
627                toIEW->commitInfo[tid].robSquashing = true;
628                wroteToTimeBuffer = true;
629            }
630        }
631    }
632
633    commit();
634
635    markCompletedInsts();
636
637    threads = activeThreads->begin();
638
639    while (threads != end) {
640        ThreadID tid = *threads++;
641
642        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
643            // The ROB has more instructions it can commit. Its next status
644            // will be active.
645            _nextStatus = Active;
646
647            DynInstPtr inst = rob->readHeadInst(tid);
648
649            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
650                    " ROB and ready to commit\n",
651                    tid, inst->seqNum, inst->pcState());
652
653        } else if (!rob->isEmpty(tid)) {
654            DynInstPtr inst = rob->readHeadInst(tid);
655
656            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
657                    "%s is head of ROB and not ready\n",
658                    tid, inst->seqNum, inst->pcState());
659        }
660
661        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
662                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
663    }
664
665
666    if (wroteToTimeBuffer) {
667        DPRINTF(Activity, "Activity This Cycle.\n");
668        cpu->activityThisCycle();
669    }
670
671    updateStatus();
672}
673
674#if FULL_SYSTEM
675template <class Impl>
676void
677DefaultCommit<Impl>::handleInterrupt()
678{
679    // Verify that we still have an interrupt to handle
680    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
681        DPRINTF(Commit, "Pending interrupt is cleared by master before "
682                "it got handled. Restart fetching from the orig path.\n");
683        toIEW->commitInfo[0].clearInterrupt = true;
684        interrupt = NoFault;
685        return;
686    }
687
688    // Wait until the ROB is empty and all stores have drained in
689    // order to enter the interrupt.
690    if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
691        // Squash or record that I need to squash this cycle if
692        // an interrupt needed to be handled.
693        DPRINTF(Commit, "Interrupt detected.\n");
694
695        // Clear the interrupt now that it's going to be handled
696        toIEW->commitInfo[0].clearInterrupt = true;
697
698        assert(!thread[0]->inSyscall);
699        thread[0]->inSyscall = true;
700
701        // CPU will handle interrupt.
702        cpu->processInterrupts(interrupt);
703
704        thread[0]->inSyscall = false;
705
706        commitStatus[0] = TrapPending;
707
708        // Generate trap squash event.
709        generateTrapEvent(0);
710
711        interrupt = NoFault;
712    } else {
713        DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
714    }
715}
716
717template <class Impl>
718void
719DefaultCommit<Impl>::propagateInterrupt()
720{
721    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
722            tcSquash[0])
723        return;
724
725    // Process interrupts if interrupts are enabled, not in PAL
726    // mode, and no other traps or external squashes are currently
727    // pending.
728    // @todo: Allow other threads to handle interrupts.
729
730    // Get any interrupt that happened
731    interrupt = cpu->getInterrupts();
732
733    // Tell fetch that there is an interrupt pending.  This
734    // will make fetch wait until it sees a non PAL-mode PC,
735    // at which point it stops fetching instructions.
736    if (interrupt != NoFault)
737        toIEW->commitInfo[0].interruptPending = true;
738}
739
740#endif // FULL_SYSTEM
741
742template <class Impl>
743void
744DefaultCommit<Impl>::commit()
745{
746
747#if FULL_SYSTEM
748    // Check for any interrupt that we've already squashed for and start processing it.
749    if (interrupt != NoFault)
750        handleInterrupt();
751
752    // Check if we have a interrupt and get read to handle it
753    if (cpu->checkInterrupts(cpu->tcBase(0)))
754        propagateInterrupt();
755#endif // FULL_SYSTEM
756
757    ////////////////////////////////////
758    // Check for any possible squashes, handle them first
759    ////////////////////////////////////
760    list<ThreadID>::iterator threads = activeThreads->begin();
761    list<ThreadID>::iterator end = activeThreads->end();
762
763    while (threads != end) {
764        ThreadID tid = *threads++;
765
766        // Not sure which one takes priority.  I think if we have
767        // both, that's a bad sign.
768        if (trapSquash[tid] == true) {
769            assert(!tcSquash[tid]);
770            squashFromTrap(tid);
771        } else if (tcSquash[tid] == true) {
772            assert(commitStatus[tid] != TrapPending);
773            squashFromTC(tid);
774        }
775
776        // Squashed sequence number must be older than youngest valid
777        // instruction in the ROB. This prevents squashes from younger
778        // instructions overriding squashes from older instructions.
779        if (fromIEW->squash[tid] &&
780            commitStatus[tid] != TrapPending &&
781            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
782
783            DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
784                    tid,
785                    fromIEW->mispredPC[tid],
786                    fromIEW->squashedSeqNum[tid]);
787
788            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
789                    tid,
790                    fromIEW->pc[tid].nextInstAddr());
791
792            commitStatus[tid] = ROBSquashing;
793
794            // If we want to include the squashing instruction in the squash,
795            // then use one older sequence number.
796            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
797
798            if (fromIEW->includeSquashInst[tid] == true) {
799                squashed_inst--;
800            }
801
802            // All younger instructions will be squashed. Set the sequence
803            // number as the youngest instruction in the ROB.
804            youngestSeqNum[tid] = squashed_inst;
805
806            rob->squash(squashed_inst, tid);
807            changedROBNumEntries[tid] = true;
808
809            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
810
811            toIEW->commitInfo[tid].squash = true;
812
813            // Send back the rob squashing signal so other stages know that
814            // the ROB is in the process of squashing.
815            toIEW->commitInfo[tid].robSquashing = true;
816
817            toIEW->commitInfo[tid].branchMispredict =
818                fromIEW->branchMispredict[tid];
819            toIEW->commitInfo[tid].mispredictInst =
820                fromIEW->mispredictInst[tid];
821            toIEW->commitInfo[tid].branchTaken =
822                fromIEW->branchTaken[tid];
823
824            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
825
826            toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
827
828            if (toIEW->commitInfo[tid].branchMispredict) {
829                ++branchMispredicts;
830            }
831        }
832
833    }
834
835    setNextStatus();
836
837    if (squashCounter != numThreads) {
838        // If we're not currently squashing, then get instructions.
839        getInsts();
840
841        // Try to commit any instructions.
842        commitInsts();
843    }
844
845    //Check for any activity
846    threads = activeThreads->begin();
847
848    while (threads != end) {
849        ThreadID tid = *threads++;
850
851        if (changedROBNumEntries[tid]) {
852            toIEW->commitInfo[tid].usedROB = true;
853            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
854
855            wroteToTimeBuffer = true;
856            changedROBNumEntries[tid] = false;
857            if (rob->isEmpty(tid))
858                checkEmptyROB[tid] = true;
859        }
860
861        // ROB is only considered "empty" for previous stages if: a)
862        // ROB is empty, b) there are no outstanding stores, c) IEW
863        // stage has received any information regarding stores that
864        // committed.
865        // c) is checked by making sure to not consider the ROB empty
866        // on the same cycle as when stores have been committed.
867        // @todo: Make this handle multi-cycle communication between
868        // commit and IEW.
869        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
870            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
871            checkEmptyROB[tid] = false;
872            toIEW->commitInfo[tid].usedROB = true;
873            toIEW->commitInfo[tid].emptyROB = true;
874            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
875            wroteToTimeBuffer = true;
876        }
877
878    }
879}
880
881template <class Impl>
882void
883DefaultCommit<Impl>::commitInsts()
884{
885    ////////////////////////////////////
886    // Handle commit
887    // Note that commit will be handled prior to putting new
888    // instructions in the ROB so that the ROB only tries to commit
889    // instructions it has in this current cycle, and not instructions
890    // it is writing in during this cycle.  Can't commit and squash
891    // things at the same time...
892    ////////////////////////////////////
893
894    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
895
896    unsigned num_committed = 0;
897
898    DynInstPtr head_inst;
899
900    // Commit as many instructions as possible until the commit bandwidth
901    // limit is reached, or it becomes impossible to commit any more.
902    while (num_committed < commitWidth) {
903        int commit_thread = getCommittingThread();
904
905        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
906            break;
907
908        head_inst = rob->readHeadInst(commit_thread);
909
910        ThreadID tid = head_inst->threadNumber;
911
912        assert(tid == commit_thread);
913
914        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
915                head_inst->seqNum, tid);
916
917        // If the head instruction is squashed, it is ready to retire
918        // (be removed from the ROB) at any time.
919        if (head_inst->isSquashed()) {
920
921            DPRINTF(Commit, "Retiring squashed instruction from "
922                    "ROB.\n");
923
924            rob->retireHead(commit_thread);
925
926            ++commitSquashedInsts;
927
928            // Record that the number of ROB entries has changed.
929            changedROBNumEntries[tid] = true;
930        } else {
931            pc[tid] = head_inst->pcState();
932
933            // Increment the total number of non-speculative instructions
934            // executed.
935            // Hack for now: it really shouldn't happen until after the
936            // commit is deemed to be successful, but this count is needed
937            // for syscalls.
938            thread[tid]->funcExeInst++;
939
940            // Try to commit the head instruction.
941            bool commit_success = commitHead(head_inst, num_committed);
942
943            if (commit_success) {
944                ++num_committed;
945
946                changedROBNumEntries[tid] = true;
947
948                // Set the doneSeqNum to the youngest committed instruction.
949                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
950
951                ++commitCommittedInsts;
952
953                // To match the old model, don't count nops and instruction
954                // prefetches towards the total commit count.
955                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
956                    cpu->instDone(tid);
957                }
958
959                // Updates misc. registers.
960                head_inst->updateMiscRegs();
961
962                TheISA::advancePC(pc[tid], head_inst->staticInst);
963
964                // Keep track of the last sequence number commited
965                lastCommitedSeqNum[tid] = head_inst->seqNum;
966
967                // If this is an instruction that doesn't play nicely with
968                // others squash everything and restart fetch
969                if (head_inst->isSquashAfter())
970                    squashAfter(tid, head_inst->seqNum);
971
972                int count = 0;
973                Addr oldpc;
974                // Debug statement.  Checks to make sure we're not
975                // currently updating state while handling PC events.
976                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
977                do {
978                    oldpc = pc[tid].instAddr();
979                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
980                    count++;
981                } while (oldpc != pc[tid].instAddr());
982                if (count > 1) {
983                    DPRINTF(Commit,
984                            "PC skip function event, stopping commit\n");
985                    break;
986                }
987            } else {
988                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
989                        "[tid:%i] [sn:%i].\n",
990                        head_inst->pcState(), tid ,head_inst->seqNum);
991                break;
992            }
993        }
994    }
995
996    DPRINTF(CommitRate, "%i\n", num_committed);
997    numCommittedDist.sample(num_committed);
998
999    if (num_committed == commitWidth) {
1000        commitEligibleSamples++;
1001    }
1002}
1003
1004template <class Impl>
1005bool
1006DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1007{
1008    assert(head_inst);
1009
1010    ThreadID tid = head_inst->threadNumber;
1011
1012    // If the instruction is not executed yet, then it will need extra
1013    // handling.  Signal backwards that it should be executed.
1014    if (!head_inst->isExecuted()) {
1015        // Keep this number correct.  We have not yet actually executed
1016        // and committed this instruction.
1017        thread[tid]->funcExeInst--;
1018
1019        if (head_inst->isNonSpeculative() ||
1020            head_inst->isStoreConditional() ||
1021            head_inst->isMemBarrier() ||
1022            head_inst->isWriteBarrier()) {
1023
1024            DPRINTF(Commit, "Encountered a barrier or non-speculative "
1025                    "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1026                    head_inst->seqNum, head_inst->pcState());
1027
1028            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1029                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1030                return false;
1031            }
1032
1033            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1034
1035            // Change the instruction so it won't try to commit again until
1036            // it is executed.
1037            head_inst->clearCanCommit();
1038
1039            ++commitNonSpecStalls;
1040
1041            return false;
1042        } else if (head_inst->isLoad()) {
1043            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1044                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1045                return false;
1046            }
1047
1048            assert(head_inst->uncacheable());
1049            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1050                    head_inst->seqNum, head_inst->pcState());
1051
1052            // Send back the non-speculative instruction's sequence
1053            // number.  Tell the lsq to re-execute the load.
1054            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1055            toIEW->commitInfo[tid].uncached = true;
1056            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1057
1058            head_inst->clearCanCommit();
1059
1060            return false;
1061        } else {
1062            panic("Trying to commit un-executed instruction "
1063                  "of unknown type!\n");
1064        }
1065    }
1066
1067    if (head_inst->isThreadSync()) {
1068        // Not handled for now.
1069        panic("Thread sync instructions are not handled yet.\n");
1070    }
1071
1072    // Check if the instruction caused a fault.  If so, trap.
1073    Fault inst_fault = head_inst->getFault();
1074
1075    // Stores mark themselves as completed.
1076    if (!head_inst->isStore() && inst_fault == NoFault) {
1077        head_inst->setCompleted();
1078    }
1079
1080#if USE_CHECKER
1081    // Use checker prior to updating anything due to traps or PC
1082    // based events.
1083    if (cpu->checker) {
1084        cpu->checker->verify(head_inst);
1085    }
1086#endif
1087
1088    if (inst_fault != NoFault) {
1089        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1090                head_inst->seqNum, head_inst->pcState());
1091
1092        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1093            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1094            return false;
1095        }
1096
1097        head_inst->setCompleted();
1098
1099#if USE_CHECKER
1100        if (cpu->checker && head_inst->isStore()) {
1101            cpu->checker->verify(head_inst);
1102        }
1103#endif
1104
1105        assert(!thread[tid]->inSyscall);
1106
1107        // Mark that we're in state update mode so that the trap's
1108        // execution doesn't generate extra squashes.
1109        thread[tid]->inSyscall = true;
1110
1111        // Execute the trap.  Although it's slightly unrealistic in
1112        // terms of timing (as it doesn't wait for the full timing of
1113        // the trap event to complete before updating state), it's
1114        // needed to update the state as soon as possible.  This
1115        // prevents external agents from changing any specific state
1116        // that the trap need.
1117        cpu->trap(inst_fault, tid, head_inst->staticInst);
1118
1119        // Exit state update mode to avoid accidental updating.
1120        thread[tid]->inSyscall = false;
1121
1122        commitStatus[tid] = TrapPending;
1123
1124        if (head_inst->traceData) {
1125            if (DTRACE(ExecFaulting)) {
1126                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1127                head_inst->traceData->setCPSeq(thread[tid]->numInst);
1128                head_inst->traceData->dump();
1129            }
1130            delete head_inst->traceData;
1131            head_inst->traceData = NULL;
1132        }
1133
1134        // Generate trap squash event.
1135        generateTrapEvent(tid);
1136        return false;
1137    }
1138
1139    updateComInstStats(head_inst);
1140
1141#if FULL_SYSTEM
1142    if (thread[tid]->profile) {
1143        thread[tid]->profilePC = head_inst->instAddr();
1144        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1145                                                          head_inst->staticInst);
1146
1147        if (node)
1148            thread[tid]->profileNode = node;
1149    }
1150    if (CPA::available()) {
1151        if (head_inst->isControl()) {
1152            ThreadContext *tc = thread[tid]->getTC();
1153            CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1154        }
1155    }
1156#endif
1157
1158    if (head_inst->traceData) {
1159        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1160        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1161        head_inst->traceData->dump();
1162        delete head_inst->traceData;
1163        head_inst->traceData = NULL;
1164    }
1165
1166    // Update the commit rename map
1167    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1168        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1169                                 head_inst->renamedDestRegIdx(i));
1170    }
1171
1172    if (head_inst->isCopy())
1173        panic("Should not commit any copy instructions!");
1174
1175    // Finally clear the head ROB entry.
1176    rob->retireHead(tid);
1177
1178    // If this was a store, record it for this cycle.
1179    if (head_inst->isStore())
1180        committedStores[tid] = true;
1181
1182    // Return true to indicate that we have committed an instruction.
1183    return true;
1184}
1185
1186template <class Impl>
1187void
1188DefaultCommit<Impl>::getInsts()
1189{
1190    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1191
1192    // Read any renamed instructions and place them into the ROB.
1193    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1194
1195    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1196        DynInstPtr inst;
1197
1198        inst = fromRename->insts[inst_num];
1199        ThreadID tid = inst->threadNumber;
1200
1201        if (!inst->isSquashed() &&
1202            commitStatus[tid] != ROBSquashing &&
1203            commitStatus[tid] != TrapPending) {
1204            changedROBNumEntries[tid] = true;
1205
1206            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1207                    inst->pcState(), inst->seqNum, tid);
1208
1209            rob->insertInst(inst);
1210
1211            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1212
1213            youngestSeqNum[tid] = inst->seqNum;
1214        } else {
1215            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1216                    "squashed, skipping.\n",
1217                    inst->pcState(), inst->seqNum, tid);
1218        }
1219    }
1220}
1221
1222template <class Impl>
1223void
1224DefaultCommit<Impl>::skidInsert()
1225{
1226    DPRINTF(Commit, "Attempting to any instructions from rename into "
1227            "skidBuffer.\n");
1228
1229    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1230        DynInstPtr inst = fromRename->insts[inst_num];
1231
1232        if (!inst->isSquashed()) {
1233            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1234                    "skidBuffer.\n", inst->pcState(), inst->seqNum,
1235                    inst->threadNumber);
1236            skidBuffer.push(inst);
1237        } else {
1238            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1239                    "squashed, skipping.\n",
1240                    inst->pcState(), inst->seqNum, inst->threadNumber);
1241        }
1242    }
1243}
1244
1245template <class Impl>
1246void
1247DefaultCommit<Impl>::markCompletedInsts()
1248{
1249    // Grab completed insts out of the IEW instruction queue, and mark
1250    // instructions completed within the ROB.
1251    for (int inst_num = 0;
1252         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1253         ++inst_num)
1254    {
1255        if (!fromIEW->insts[inst_num]->isSquashed()) {
1256            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1257                    "within ROB.\n",
1258                    fromIEW->insts[inst_num]->threadNumber,
1259                    fromIEW->insts[inst_num]->pcState(),
1260                    fromIEW->insts[inst_num]->seqNum);
1261
1262            // Mark the instruction as ready to commit.
1263            fromIEW->insts[inst_num]->setCanCommit();
1264        }
1265    }
1266}
1267
1268template <class Impl>
1269bool
1270DefaultCommit<Impl>::robDoneSquashing()
1271{
1272    list<ThreadID>::iterator threads = activeThreads->begin();
1273    list<ThreadID>::iterator end = activeThreads->end();
1274
1275    while (threads != end) {
1276        ThreadID tid = *threads++;
1277
1278        if (!rob->isDoneSquashing(tid))
1279            return false;
1280    }
1281
1282    return true;
1283}
1284
1285template <class Impl>
1286void
1287DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1288{
1289    ThreadID tid = inst->threadNumber;
1290
1291    //
1292    //  Pick off the software prefetches
1293    //
1294#ifdef TARGET_ALPHA
1295    if (inst->isDataPrefetch()) {
1296        statComSwp[tid]++;
1297    } else {
1298        statComInst[tid]++;
1299    }
1300#else
1301    statComInst[tid]++;
1302#endif
1303
1304    //
1305    //  Control Instructions
1306    //
1307    if (inst->isControl())
1308        statComBranches[tid]++;
1309
1310    //
1311    //  Memory references
1312    //
1313    if (inst->isMemRef()) {
1314        statComRefs[tid]++;
1315
1316        if (inst->isLoad()) {
1317            statComLoads[tid]++;
1318        }
1319    }
1320
1321    if (inst->isMemBarrier()) {
1322        statComMembars[tid]++;
1323    }
1324}
1325
1326////////////////////////////////////////
1327//                                    //
1328//  SMT COMMIT POLICY MAINTAINED HERE //
1329//                                    //
1330////////////////////////////////////////
1331template <class Impl>
1332ThreadID
1333DefaultCommit<Impl>::getCommittingThread()
1334{
1335    if (numThreads > 1) {
1336        switch (commitPolicy) {
1337
1338          case Aggressive:
1339            //If Policy is Aggressive, commit will call
1340            //this function multiple times per
1341            //cycle
1342            return oldestReady();
1343
1344          case RoundRobin:
1345            return roundRobin();
1346
1347          case OldestReady:
1348            return oldestReady();
1349
1350          default:
1351            return InvalidThreadID;
1352        }
1353    } else {
1354        assert(!activeThreads->empty());
1355        ThreadID tid = activeThreads->front();
1356
1357        if (commitStatus[tid] == Running ||
1358            commitStatus[tid] == Idle ||
1359            commitStatus[tid] == FetchTrapPending) {
1360            return tid;
1361        } else {
1362            return InvalidThreadID;
1363        }
1364    }
1365}
1366
1367template<class Impl>
1368ThreadID
1369DefaultCommit<Impl>::roundRobin()
1370{
1371    list<ThreadID>::iterator pri_iter = priority_list.begin();
1372    list<ThreadID>::iterator end      = priority_list.end();
1373
1374    while (pri_iter != end) {
1375        ThreadID tid = *pri_iter;
1376
1377        if (commitStatus[tid] == Running ||
1378            commitStatus[tid] == Idle ||
1379            commitStatus[tid] == FetchTrapPending) {
1380
1381            if (rob->isHeadReady(tid)) {
1382                priority_list.erase(pri_iter);
1383                priority_list.push_back(tid);
1384
1385                return tid;
1386            }
1387        }
1388
1389        pri_iter++;
1390    }
1391
1392    return InvalidThreadID;
1393}
1394
1395template<class Impl>
1396ThreadID
1397DefaultCommit<Impl>::oldestReady()
1398{
1399    unsigned oldest = 0;
1400    bool first = true;
1401
1402    list<ThreadID>::iterator threads = activeThreads->begin();
1403    list<ThreadID>::iterator end = activeThreads->end();
1404
1405    while (threads != end) {
1406        ThreadID tid = *threads++;
1407
1408        if (!rob->isEmpty(tid) &&
1409            (commitStatus[tid] == Running ||
1410             commitStatus[tid] == Idle ||
1411             commitStatus[tid] == FetchTrapPending)) {
1412
1413            if (rob->isHeadReady(tid)) {
1414
1415                DynInstPtr head_inst = rob->readHeadInst(tid);
1416
1417                if (first) {
1418                    oldest = tid;
1419                    first = false;
1420                } else if (head_inst->seqNum < oldest) {
1421                    oldest = tid;
1422                }
1423            }
1424        }
1425    }
1426
1427    if (!first) {
1428        return oldest;
1429    } else {
1430        return InvalidThreadID;
1431    }
1432}
1433