commit_impl.hh revision 5529:9ae69b9cd7fd 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49#include "params/DerivO3CPU.hh"
50
51template <class Impl>
52DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
53                                          unsigned _tid)
54    : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
55{
56    this->setFlags(Event::AutoDelete);
57}
58
59template <class Impl>
60void
61DefaultCommit<Impl>::TrapEvent::process()
62{
63    // This will get reset by commit if it was switched out at the
64    // time of this event processing.
65    commit->trapSquash[tid] = true;
66}
67
68template <class Impl>
69const char *
70DefaultCommit<Impl>::TrapEvent::description() const
71{
72    return "Trap";
73}
74
75template <class Impl>
76DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
77    : cpu(_cpu),
78      squashCounter(0),
79      iewToCommitDelay(params->iewToCommitDelay),
80      commitToIEWDelay(params->commitToIEWDelay),
81      renameToROBDelay(params->renameToROBDelay),
82      fetchToCommitDelay(params->commitToFetchDelay),
83      renameWidth(params->renameWidth),
84      commitWidth(params->commitWidth),
85      numThreads(params->numThreads),
86      drainPending(false),
87      switchedOut(false),
88      trapLatency(params->trapLatency)
89{
90    _status = Active;
91    _nextStatus = Inactive;
92    std::string policy = params->smtCommitPolicy;
93
94    //Convert string to lowercase
95    std::transform(policy.begin(), policy.end(), policy.begin(),
96                   (int(*)(int)) tolower);
97
98    //Assign commit policy
99    if (policy == "aggressive"){
100        commitPolicy = Aggressive;
101
102        DPRINTF(Commit,"Commit Policy set to Aggressive.");
103    } else if (policy == "roundrobin"){
104        commitPolicy = RoundRobin;
105
106        //Set-Up Priority List
107        for (int tid=0; tid < numThreads; tid++) {
108            priority_list.push_back(tid);
109        }
110
111        DPRINTF(Commit,"Commit Policy set to Round Robin.");
112    } else if (policy == "oldestready"){
113        commitPolicy = OldestReady;
114
115        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
116    } else {
117        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
118               "RoundRobin,OldestReady}");
119    }
120
121    for (int i=0; i < numThreads; i++) {
122        commitStatus[i] = Idle;
123        changedROBNumEntries[i] = false;
124        checkEmptyROB[i] = false;
125        trapInFlight[i] = false;
126        committedStores[i] = false;
127        trapSquash[i] = false;
128        tcSquash[i] = false;
129        microPC[i] = nextMicroPC[i] = PC[i] = nextPC[i] = nextNPC[i] = 0;
130    }
131#if FULL_SYSTEM
132    interrupt = NoFault;
133#endif
134}
135
136template <class Impl>
137std::string
138DefaultCommit<Impl>::name() const
139{
140    return cpu->name() + ".commit";
141}
142
143template <class Impl>
144void
145DefaultCommit<Impl>::regStats()
146{
147    using namespace Stats;
148    commitCommittedInsts
149        .name(name() + ".commitCommittedInsts")
150        .desc("The number of committed instructions")
151        .prereq(commitCommittedInsts);
152    commitSquashedInsts
153        .name(name() + ".commitSquashedInsts")
154        .desc("The number of squashed insts skipped by commit")
155        .prereq(commitSquashedInsts);
156    commitSquashEvents
157        .name(name() + ".commitSquashEvents")
158        .desc("The number of times commit is told to squash")
159        .prereq(commitSquashEvents);
160    commitNonSpecStalls
161        .name(name() + ".commitNonSpecStalls")
162        .desc("The number of times commit has been forced to stall to "
163              "communicate backwards")
164        .prereq(commitNonSpecStalls);
165    branchMispredicts
166        .name(name() + ".branchMispredicts")
167        .desc("The number of times a branch was mispredicted")
168        .prereq(branchMispredicts);
169    numCommittedDist
170        .init(0,commitWidth,1)
171        .name(name() + ".COM:committed_per_cycle")
172        .desc("Number of insts commited each cycle")
173        .flags(Stats::pdf)
174        ;
175
176    statComInst
177        .init(cpu->number_of_threads)
178        .name(name() + ".COM:count")
179        .desc("Number of instructions committed")
180        .flags(total)
181        ;
182
183    statComSwp
184        .init(cpu->number_of_threads)
185        .name(name() + ".COM:swp_count")
186        .desc("Number of s/w prefetches committed")
187        .flags(total)
188        ;
189
190    statComRefs
191        .init(cpu->number_of_threads)
192        .name(name() +  ".COM:refs")
193        .desc("Number of memory references committed")
194        .flags(total)
195        ;
196
197    statComLoads
198        .init(cpu->number_of_threads)
199        .name(name() +  ".COM:loads")
200        .desc("Number of loads committed")
201        .flags(total)
202        ;
203
204    statComMembars
205        .init(cpu->number_of_threads)
206        .name(name() +  ".COM:membars")
207        .desc("Number of memory barriers committed")
208        .flags(total)
209        ;
210
211    statComBranches
212        .init(cpu->number_of_threads)
213        .name(name() + ".COM:branches")
214        .desc("Number of branches committed")
215        .flags(total)
216        ;
217
218    commitEligible
219        .init(cpu->number_of_threads)
220        .name(name() + ".COM:bw_limited")
221        .desc("number of insts not committed due to BW limits")
222        .flags(total)
223        ;
224
225    commitEligibleSamples
226        .name(name() + ".COM:bw_lim_events")
227        .desc("number cycles where commit BW limit reached")
228        ;
229}
230
231template <class Impl>
232void
233DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
234{
235    thread = threads;
236}
237
238template <class Impl>
239void
240DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
241{
242    timeBuffer = tb_ptr;
243
244    // Setup wire to send information back to IEW.
245    toIEW = timeBuffer->getWire(0);
246
247    // Setup wire to read data from IEW (for the ROB).
248    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
249}
250
251template <class Impl>
252void
253DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
254{
255    fetchQueue = fq_ptr;
256
257    // Setup wire to get instructions from rename (for the ROB).
258    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
259}
260
261template <class Impl>
262void
263DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
264{
265    renameQueue = rq_ptr;
266
267    // Setup wire to get instructions from rename (for the ROB).
268    fromRename = renameQueue->getWire(-renameToROBDelay);
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
274{
275    iewQueue = iq_ptr;
276
277    // Setup wire to get instructions from IEW.
278    fromIEW = iewQueue->getWire(-iewToCommitDelay);
279}
280
281template <class Impl>
282void
283DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
284{
285    iewStage = iew_stage;
286}
287
288template<class Impl>
289void
290DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
291{
292    activeThreads = at_ptr;
293}
294
295template <class Impl>
296void
297DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
298{
299    for (int i=0; i < numThreads; i++) {
300        renameMap[i] = &rm_ptr[i];
301    }
302}
303
304template <class Impl>
305void
306DefaultCommit<Impl>::setROB(ROB *rob_ptr)
307{
308    rob = rob_ptr;
309}
310
311template <class Impl>
312void
313DefaultCommit<Impl>::initStage()
314{
315    rob->setActiveThreads(activeThreads);
316    rob->resetEntries();
317
318    // Broadcast the number of free entries.
319    for (int i=0; i < numThreads; i++) {
320        toIEW->commitInfo[i].usedROB = true;
321        toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
322        toIEW->commitInfo[i].emptyROB = true;
323    }
324
325    // Commit must broadcast the number of free entries it has at the
326    // start of the simulation, so it starts as active.
327    cpu->activateStage(O3CPU::CommitIdx);
328
329    cpu->activityThisCycle();
330    trapLatency = cpu->ticks(trapLatency);
331}
332
333template <class Impl>
334bool
335DefaultCommit<Impl>::drain()
336{
337    drainPending = true;
338
339    return false;
340}
341
342template <class Impl>
343void
344DefaultCommit<Impl>::switchOut()
345{
346    switchedOut = true;
347    drainPending = false;
348    rob->switchOut();
349}
350
351template <class Impl>
352void
353DefaultCommit<Impl>::resume()
354{
355    drainPending = false;
356}
357
358template <class Impl>
359void
360DefaultCommit<Impl>::takeOverFrom()
361{
362    switchedOut = false;
363    _status = Active;
364    _nextStatus = Inactive;
365    for (int i=0; i < numThreads; i++) {
366        commitStatus[i] = Idle;
367        changedROBNumEntries[i] = false;
368        trapSquash[i] = false;
369        tcSquash[i] = false;
370    }
371    squashCounter = 0;
372    rob->takeOverFrom();
373}
374
375template <class Impl>
376void
377DefaultCommit<Impl>::updateStatus()
378{
379    // reset ROB changed variable
380    std::list<unsigned>::iterator threads = activeThreads->begin();
381    std::list<unsigned>::iterator end = activeThreads->end();
382
383    while (threads != end) {
384        unsigned tid = *threads++;
385
386        changedROBNumEntries[tid] = false;
387
388        // Also check if any of the threads has a trap pending
389        if (commitStatus[tid] == TrapPending ||
390            commitStatus[tid] == FetchTrapPending) {
391            _nextStatus = Active;
392        }
393    }
394
395    if (_nextStatus == Inactive && _status == Active) {
396        DPRINTF(Activity, "Deactivating stage.\n");
397        cpu->deactivateStage(O3CPU::CommitIdx);
398    } else if (_nextStatus == Active && _status == Inactive) {
399        DPRINTF(Activity, "Activating stage.\n");
400        cpu->activateStage(O3CPU::CommitIdx);
401    }
402
403    _status = _nextStatus;
404}
405
406template <class Impl>
407void
408DefaultCommit<Impl>::setNextStatus()
409{
410    int squashes = 0;
411
412    std::list<unsigned>::iterator threads = activeThreads->begin();
413    std::list<unsigned>::iterator end = activeThreads->end();
414
415    while (threads != end) {
416        unsigned tid = *threads++;
417
418        if (commitStatus[tid] == ROBSquashing) {
419            squashes++;
420        }
421    }
422
423    squashCounter = squashes;
424
425    // If commit is currently squashing, then it will have activity for the
426    // next cycle. Set its next status as active.
427    if (squashCounter) {
428        _nextStatus = Active;
429    }
430}
431
432template <class Impl>
433bool
434DefaultCommit<Impl>::changedROBEntries()
435{
436    std::list<unsigned>::iterator threads = activeThreads->begin();
437    std::list<unsigned>::iterator end = activeThreads->end();
438
439    while (threads != end) {
440        unsigned tid = *threads++;
441
442        if (changedROBNumEntries[tid]) {
443            return true;
444        }
445    }
446
447    return false;
448}
449
450template <class Impl>
451unsigned
452DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
453{
454    return rob->numFreeEntries(tid);
455}
456
457template <class Impl>
458void
459DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
460{
461    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
462
463    TrapEvent *trap = new TrapEvent(this, tid);
464
465    trap->schedule(curTick + trapLatency);
466    trapInFlight[tid] = true;
467}
468
469template <class Impl>
470void
471DefaultCommit<Impl>::generateTCEvent(unsigned tid)
472{
473    assert(!trapInFlight[tid]);
474    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
475
476    tcSquash[tid] = true;
477}
478
479template <class Impl>
480void
481DefaultCommit<Impl>::squashAll(unsigned tid)
482{
483    // If we want to include the squashing instruction in the squash,
484    // then use one older sequence number.
485    // Hopefully this doesn't mess things up.  Basically I want to squash
486    // all instructions of this thread.
487    InstSeqNum squashed_inst = rob->isEmpty() ?
488        0 : rob->readHeadInst(tid)->seqNum - 1;
489
490    // All younger instructions will be squashed. Set the sequence
491    // number as the youngest instruction in the ROB (0 in this case.
492    // Hopefully nothing breaks.)
493    youngestSeqNum[tid] = 0;
494
495    rob->squash(squashed_inst, tid);
496    changedROBNumEntries[tid] = true;
497
498    // Send back the sequence number of the squashed instruction.
499    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
500
501    // Send back the squash signal to tell stages that they should
502    // squash.
503    toIEW->commitInfo[tid].squash = true;
504
505    // Send back the rob squashing signal so other stages know that
506    // the ROB is in the process of squashing.
507    toIEW->commitInfo[tid].robSquashing = true;
508
509    toIEW->commitInfo[tid].branchMispredict = false;
510
511    toIEW->commitInfo[tid].nextPC = PC[tid];
512    toIEW->commitInfo[tid].nextNPC = nextPC[tid];
513    toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid];
514}
515
516template <class Impl>
517void
518DefaultCommit<Impl>::squashFromTrap(unsigned tid)
519{
520    squashAll(tid);
521
522    DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
523
524    thread[tid]->trapPending = false;
525    thread[tid]->inSyscall = false;
526    trapInFlight[tid] = false;
527
528    trapSquash[tid] = false;
529
530    commitStatus[tid] = ROBSquashing;
531    cpu->activityThisCycle();
532}
533
534template <class Impl>
535void
536DefaultCommit<Impl>::squashFromTC(unsigned tid)
537{
538    squashAll(tid);
539
540    DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
541
542    thread[tid]->inSyscall = false;
543    assert(!thread[tid]->trapPending);
544
545    commitStatus[tid] = ROBSquashing;
546    cpu->activityThisCycle();
547
548    tcSquash[tid] = false;
549}
550
551template <class Impl>
552void
553DefaultCommit<Impl>::tick()
554{
555    wroteToTimeBuffer = false;
556    _nextStatus = Inactive;
557
558    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
559        cpu->signalDrained();
560        drainPending = false;
561        return;
562    }
563
564    if (activeThreads->empty())
565        return;
566
567    std::list<unsigned>::iterator threads = activeThreads->begin();
568    std::list<unsigned>::iterator end = activeThreads->end();
569
570    // Check if any of the threads are done squashing.  Change the
571    // status if they are done.
572    while (threads != end) {
573        unsigned tid = *threads++;
574
575        // Clear the bit saying if the thread has committed stores
576        // this cycle.
577        committedStores[tid] = false;
578
579        if (commitStatus[tid] == ROBSquashing) {
580
581            if (rob->isDoneSquashing(tid)) {
582                commitStatus[tid] = Running;
583            } else {
584                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
585                        " insts this cycle.\n", tid);
586                rob->doSquash(tid);
587                toIEW->commitInfo[tid].robSquashing = true;
588                wroteToTimeBuffer = true;
589            }
590        }
591    }
592
593    commit();
594
595    markCompletedInsts();
596
597    threads = activeThreads->begin();
598
599    while (threads != end) {
600        unsigned tid = *threads++;
601
602        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
603            // The ROB has more instructions it can commit. Its next status
604            // will be active.
605            _nextStatus = Active;
606
607            DynInstPtr inst = rob->readHeadInst(tid);
608
609            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
610                    " ROB and ready to commit\n",
611                    tid, inst->seqNum, inst->readPC());
612
613        } else if (!rob->isEmpty(tid)) {
614            DynInstPtr inst = rob->readHeadInst(tid);
615
616            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
617                    "%#x is head of ROB and not ready\n",
618                    tid, inst->seqNum, inst->readPC());
619        }
620
621        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
622                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
623    }
624
625
626    if (wroteToTimeBuffer) {
627        DPRINTF(Activity, "Activity This Cycle.\n");
628        cpu->activityThisCycle();
629    }
630
631    updateStatus();
632}
633
634#if FULL_SYSTEM
635template <class Impl>
636void
637DefaultCommit<Impl>::handleInterrupt()
638{
639    if (interrupt != NoFault) {
640        // Wait until the ROB is empty and all stores have drained in
641        // order to enter the interrupt.
642        if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
643            // Squash or record that I need to squash this cycle if
644            // an interrupt needed to be handled.
645            DPRINTF(Commit, "Interrupt detected.\n");
646
647            // Clear the interrupt now that it's going to be handled
648            toIEW->commitInfo[0].clearInterrupt = true;
649
650            assert(!thread[0]->inSyscall);
651            thread[0]->inSyscall = true;
652
653            // CPU will handle interrupt.
654            cpu->processInterrupts(interrupt);
655
656            thread[0]->inSyscall = false;
657
658            commitStatus[0] = TrapPending;
659
660            // Generate trap squash event.
661            generateTrapEvent(0);
662
663            interrupt = NoFault;
664        } else {
665            DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
666        }
667    } else if (commitStatus[0] != TrapPending &&
668               cpu->check_interrupts(cpu->tcBase(0)) &&
669               !trapSquash[0] &&
670               !tcSquash[0]) {
671        // Process interrupts if interrupts are enabled, not in PAL
672        // mode, and no other traps or external squashes are currently
673        // pending.
674        // @todo: Allow other threads to handle interrupts.
675
676        // Get any interrupt that happened
677        interrupt = cpu->getInterrupts();
678
679        if (interrupt != NoFault) {
680            // Tell fetch that there is an interrupt pending.  This
681            // will make fetch wait until it sees a non PAL-mode PC,
682            // at which point it stops fetching instructions.
683            toIEW->commitInfo[0].interruptPending = true;
684        }
685    }
686}
687#endif // FULL_SYSTEM
688
689template <class Impl>
690void
691DefaultCommit<Impl>::commit()
692{
693
694#if FULL_SYSTEM
695    // Check for any interrupt, and start processing it.  Or if we
696    // have an outstanding interrupt and are at a point when it is
697    // valid to take an interrupt, process it.
698    if (cpu->check_interrupts(cpu->tcBase(0))) {
699        handleInterrupt();
700    }
701#endif // FULL_SYSTEM
702
703    ////////////////////////////////////
704    // Check for any possible squashes, handle them first
705    ////////////////////////////////////
706    std::list<unsigned>::iterator threads = activeThreads->begin();
707    std::list<unsigned>::iterator end = activeThreads->end();
708
709    while (threads != end) {
710        unsigned tid = *threads++;
711
712        // Not sure which one takes priority.  I think if we have
713        // both, that's a bad sign.
714        if (trapSquash[tid] == true) {
715            assert(!tcSquash[tid]);
716            squashFromTrap(tid);
717        } else if (tcSquash[tid] == true) {
718            assert(commitStatus[tid] != TrapPending);
719            squashFromTC(tid);
720        }
721
722        // Squashed sequence number must be older than youngest valid
723        // instruction in the ROB. This prevents squashes from younger
724        // instructions overriding squashes from older instructions.
725        if (fromIEW->squash[tid] &&
726            commitStatus[tid] != TrapPending &&
727            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
728
729            DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
730                    tid,
731                    fromIEW->mispredPC[tid],
732                    fromIEW->squashedSeqNum[tid]);
733
734            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
735                    tid,
736                    fromIEW->nextPC[tid]);
737
738            commitStatus[tid] = ROBSquashing;
739
740            // If we want to include the squashing instruction in the squash,
741            // then use one older sequence number.
742            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
743
744            if (fromIEW->includeSquashInst[tid] == true) {
745                squashed_inst--;
746            }
747
748            // All younger instructions will be squashed. Set the sequence
749            // number as the youngest instruction in the ROB.
750            youngestSeqNum[tid] = squashed_inst;
751
752            rob->squash(squashed_inst, tid);
753            changedROBNumEntries[tid] = true;
754
755            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
756
757            toIEW->commitInfo[tid].squash = true;
758
759            // Send back the rob squashing signal so other stages know that
760            // the ROB is in the process of squashing.
761            toIEW->commitInfo[tid].robSquashing = true;
762
763            toIEW->commitInfo[tid].branchMispredict =
764                fromIEW->branchMispredict[tid];
765
766            toIEW->commitInfo[tid].branchTaken =
767                fromIEW->branchTaken[tid];
768
769            toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
770            toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
771            toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid];
772
773            toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
774
775            if (toIEW->commitInfo[tid].branchMispredict) {
776                ++branchMispredicts;
777            }
778        }
779
780    }
781
782    setNextStatus();
783
784    if (squashCounter != numThreads) {
785        // If we're not currently squashing, then get instructions.
786        getInsts();
787
788        // Try to commit any instructions.
789        commitInsts();
790    }
791
792    //Check for any activity
793    threads = activeThreads->begin();
794
795    while (threads != end) {
796        unsigned tid = *threads++;
797
798        if (changedROBNumEntries[tid]) {
799            toIEW->commitInfo[tid].usedROB = true;
800            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
801
802            wroteToTimeBuffer = true;
803            changedROBNumEntries[tid] = false;
804            if (rob->isEmpty(tid))
805                checkEmptyROB[tid] = true;
806        }
807
808        // ROB is only considered "empty" for previous stages if: a)
809        // ROB is empty, b) there are no outstanding stores, c) IEW
810        // stage has received any information regarding stores that
811        // committed.
812        // c) is checked by making sure to not consider the ROB empty
813        // on the same cycle as when stores have been committed.
814        // @todo: Make this handle multi-cycle communication between
815        // commit and IEW.
816        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
817            !iewStage->hasStoresToWB() && !committedStores[tid]) {
818            checkEmptyROB[tid] = false;
819            toIEW->commitInfo[tid].usedROB = true;
820            toIEW->commitInfo[tid].emptyROB = true;
821            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
822            wroteToTimeBuffer = true;
823        }
824
825    }
826}
827
828template <class Impl>
829void
830DefaultCommit<Impl>::commitInsts()
831{
832    ////////////////////////////////////
833    // Handle commit
834    // Note that commit will be handled prior to putting new
835    // instructions in the ROB so that the ROB only tries to commit
836    // instructions it has in this current cycle, and not instructions
837    // it is writing in during this cycle.  Can't commit and squash
838    // things at the same time...
839    ////////////////////////////////////
840
841    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
842
843    unsigned num_committed = 0;
844
845    DynInstPtr head_inst;
846
847    // Commit as many instructions as possible until the commit bandwidth
848    // limit is reached, or it becomes impossible to commit any more.
849    while (num_committed < commitWidth) {
850        int commit_thread = getCommittingThread();
851
852        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
853            break;
854
855        head_inst = rob->readHeadInst(commit_thread);
856
857        int tid = head_inst->threadNumber;
858
859        assert(tid == commit_thread);
860
861        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
862                head_inst->seqNum, tid);
863
864        // If the head instruction is squashed, it is ready to retire
865        // (be removed from the ROB) at any time.
866        if (head_inst->isSquashed()) {
867
868            DPRINTF(Commit, "Retiring squashed instruction from "
869                    "ROB.\n");
870
871            rob->retireHead(commit_thread);
872
873            ++commitSquashedInsts;
874
875            // Record that the number of ROB entries has changed.
876            changedROBNumEntries[tid] = true;
877        } else {
878            PC[tid] = head_inst->readPC();
879            nextPC[tid] = head_inst->readNextPC();
880            nextNPC[tid] = head_inst->readNextNPC();
881            nextMicroPC[tid] = head_inst->readNextMicroPC();
882
883            // Increment the total number of non-speculative instructions
884            // executed.
885            // Hack for now: it really shouldn't happen until after the
886            // commit is deemed to be successful, but this count is needed
887            // for syscalls.
888            thread[tid]->funcExeInst++;
889
890            // Try to commit the head instruction.
891            bool commit_success = commitHead(head_inst, num_committed);
892
893            if (commit_success) {
894                ++num_committed;
895
896                changedROBNumEntries[tid] = true;
897
898                // Set the doneSeqNum to the youngest committed instruction.
899                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
900
901                ++commitCommittedInsts;
902
903                // To match the old model, don't count nops and instruction
904                // prefetches towards the total commit count.
905                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
906                    cpu->instDone(tid);
907                }
908
909                PC[tid] = nextPC[tid];
910                nextPC[tid] = nextNPC[tid];
911                nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
912                microPC[tid] = nextMicroPC[tid];
913                nextMicroPC[tid] = microPC[tid] + 1;
914
915                int count = 0;
916                Addr oldpc;
917                // Debug statement.  Checks to make sure we're not
918                // currently updating state while handling PC events.
919                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
920                do {
921                    oldpc = PC[tid];
922                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
923                    count++;
924                } while (oldpc != PC[tid]);
925                if (count > 1) {
926                    DPRINTF(Commit,
927                            "PC skip function event, stopping commit\n");
928                    break;
929                }
930            } else {
931                DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
932                        "[tid:%i] [sn:%i].\n",
933                        head_inst->readPC(), tid ,head_inst->seqNum);
934                break;
935            }
936        }
937    }
938
939    DPRINTF(CommitRate, "%i\n", num_committed);
940    numCommittedDist.sample(num_committed);
941
942    if (num_committed == commitWidth) {
943        commitEligibleSamples++;
944    }
945}
946
947template <class Impl>
948bool
949DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
950{
951    assert(head_inst);
952
953    int tid = head_inst->threadNumber;
954
955    // If the instruction is not executed yet, then it will need extra
956    // handling.  Signal backwards that it should be executed.
957    if (!head_inst->isExecuted()) {
958        // Keep this number correct.  We have not yet actually executed
959        // and committed this instruction.
960        thread[tid]->funcExeInst--;
961
962        if (head_inst->isNonSpeculative() ||
963            head_inst->isStoreConditional() ||
964            head_inst->isMemBarrier() ||
965            head_inst->isWriteBarrier()) {
966
967            DPRINTF(Commit, "Encountered a barrier or non-speculative "
968                    "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
969                    head_inst->seqNum, head_inst->readPC());
970
971            if (inst_num > 0 || iewStage->hasStoresToWB()) {
972                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
973                return false;
974            }
975
976            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
977
978            // Change the instruction so it won't try to commit again until
979            // it is executed.
980            head_inst->clearCanCommit();
981
982            ++commitNonSpecStalls;
983
984            return false;
985        } else if (head_inst->isLoad()) {
986            if (inst_num > 0 || iewStage->hasStoresToWB()) {
987                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
988                return false;
989            }
990
991            assert(head_inst->uncacheable());
992            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
993                    head_inst->seqNum, head_inst->readPC());
994
995            // Send back the non-speculative instruction's sequence
996            // number.  Tell the lsq to re-execute the load.
997            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
998            toIEW->commitInfo[tid].uncached = true;
999            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1000
1001            head_inst->clearCanCommit();
1002
1003            return false;
1004        } else {
1005            panic("Trying to commit un-executed instruction "
1006                  "of unknown type!\n");
1007        }
1008    }
1009
1010    if (head_inst->isThreadSync()) {
1011        // Not handled for now.
1012        panic("Thread sync instructions are not handled yet.\n");
1013    }
1014
1015    // Check if the instruction caused a fault.  If so, trap.
1016    Fault inst_fault = head_inst->getFault();
1017
1018    // Stores mark themselves as completed.
1019    if (!head_inst->isStore() && inst_fault == NoFault) {
1020        head_inst->setCompleted();
1021    }
1022
1023#if USE_CHECKER
1024    // Use checker prior to updating anything due to traps or PC
1025    // based events.
1026    if (cpu->checker) {
1027        cpu->checker->verify(head_inst);
1028    }
1029#endif
1030
1031    // DTB will sometimes need the machine instruction for when
1032    // faults happen.  So we will set it here, prior to the DTB
1033    // possibly needing it for its fault.
1034    thread[tid]->setInst(
1035        static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1036
1037    if (inst_fault != NoFault) {
1038        DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1039                head_inst->seqNum, head_inst->readPC());
1040
1041        if (iewStage->hasStoresToWB() || inst_num > 0) {
1042            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1043            return false;
1044        }
1045
1046        head_inst->setCompleted();
1047
1048#if USE_CHECKER
1049        if (cpu->checker && head_inst->isStore()) {
1050            cpu->checker->verify(head_inst);
1051        }
1052#endif
1053
1054        assert(!thread[tid]->inSyscall);
1055
1056        // Mark that we're in state update mode so that the trap's
1057        // execution doesn't generate extra squashes.
1058        thread[tid]->inSyscall = true;
1059
1060        // Execute the trap.  Although it's slightly unrealistic in
1061        // terms of timing (as it doesn't wait for the full timing of
1062        // the trap event to complete before updating state), it's
1063        // needed to update the state as soon as possible.  This
1064        // prevents external agents from changing any specific state
1065        // that the trap need.
1066        cpu->trap(inst_fault, tid);
1067
1068        // Exit state update mode to avoid accidental updating.
1069        thread[tid]->inSyscall = false;
1070
1071        commitStatus[tid] = TrapPending;
1072
1073        if (head_inst->traceData) {
1074            head_inst->traceData->setFetchSeq(head_inst->seqNum);
1075            head_inst->traceData->setCPSeq(thread[tid]->numInst);
1076            head_inst->traceData->dump();
1077            delete head_inst->traceData;
1078            head_inst->traceData = NULL;
1079        }
1080
1081        // Generate trap squash event.
1082        generateTrapEvent(tid);
1083//        warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1084        return false;
1085    }
1086
1087    updateComInstStats(head_inst);
1088
1089#if FULL_SYSTEM
1090    if (thread[tid]->profile) {
1091//        bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1092//        thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1093        thread[tid]->profilePC = head_inst->readPC();
1094        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1095                                                          head_inst->staticInst);
1096
1097        if (node)
1098            thread[tid]->profileNode = node;
1099    }
1100#endif
1101
1102    if (head_inst->traceData) {
1103        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1104        head_inst->traceData->setCPSeq(thread[tid]->numInst);
1105        head_inst->traceData->dump();
1106        delete head_inst->traceData;
1107        head_inst->traceData = NULL;
1108    }
1109
1110    // Update the commit rename map
1111    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1112        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1113                                 head_inst->renamedDestRegIdx(i));
1114    }
1115
1116    if (head_inst->isCopy())
1117        panic("Should not commit any copy instructions!");
1118
1119    // Finally clear the head ROB entry.
1120    rob->retireHead(tid);
1121
1122    // If this was a store, record it for this cycle.
1123    if (head_inst->isStore())
1124        committedStores[tid] = true;
1125
1126    // Return true to indicate that we have committed an instruction.
1127    return true;
1128}
1129
1130template <class Impl>
1131void
1132DefaultCommit<Impl>::getInsts()
1133{
1134    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1135
1136    // Read any renamed instructions and place them into the ROB.
1137    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1138
1139    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1140        DynInstPtr inst;
1141
1142        inst = fromRename->insts[inst_num];
1143        int tid = inst->threadNumber;
1144
1145        if (!inst->isSquashed() &&
1146            commitStatus[tid] != ROBSquashing &&
1147            commitStatus[tid] != TrapPending) {
1148            changedROBNumEntries[tid] = true;
1149
1150            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1151                    inst->readPC(), inst->seqNum, tid);
1152
1153            rob->insertInst(inst);
1154
1155            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1156
1157            youngestSeqNum[tid] = inst->seqNum;
1158        } else {
1159            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1160                    "squashed, skipping.\n",
1161                    inst->readPC(), inst->seqNum, tid);
1162        }
1163    }
1164}
1165
1166template <class Impl>
1167void
1168DefaultCommit<Impl>::skidInsert()
1169{
1170    DPRINTF(Commit, "Attempting to any instructions from rename into "
1171            "skidBuffer.\n");
1172
1173    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1174        DynInstPtr inst = fromRename->insts[inst_num];
1175
1176        if (!inst->isSquashed()) {
1177            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1178                    "skidBuffer.\n", inst->readPC(), inst->seqNum,
1179                    inst->threadNumber);
1180            skidBuffer.push(inst);
1181        } else {
1182            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1183                    "squashed, skipping.\n",
1184                    inst->readPC(), inst->seqNum, inst->threadNumber);
1185        }
1186    }
1187}
1188
1189template <class Impl>
1190void
1191DefaultCommit<Impl>::markCompletedInsts()
1192{
1193    // Grab completed insts out of the IEW instruction queue, and mark
1194    // instructions completed within the ROB.
1195    for (int inst_num = 0;
1196         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1197         ++inst_num)
1198    {
1199        if (!fromIEW->insts[inst_num]->isSquashed()) {
1200            DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1201                    "within ROB.\n",
1202                    fromIEW->insts[inst_num]->threadNumber,
1203                    fromIEW->insts[inst_num]->readPC(),
1204                    fromIEW->insts[inst_num]->seqNum);
1205
1206            // Mark the instruction as ready to commit.
1207            fromIEW->insts[inst_num]->setCanCommit();
1208        }
1209    }
1210}
1211
1212template <class Impl>
1213bool
1214DefaultCommit<Impl>::robDoneSquashing()
1215{
1216    std::list<unsigned>::iterator threads = activeThreads->begin();
1217    std::list<unsigned>::iterator end = activeThreads->end();
1218
1219    while (threads != end) {
1220        unsigned tid = *threads++;
1221
1222        if (!rob->isDoneSquashing(tid))
1223            return false;
1224    }
1225
1226    return true;
1227}
1228
1229template <class Impl>
1230void
1231DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1232{
1233    unsigned thread = inst->threadNumber;
1234
1235    //
1236    //  Pick off the software prefetches
1237    //
1238#ifdef TARGET_ALPHA
1239    if (inst->isDataPrefetch()) {
1240        statComSwp[thread]++;
1241    } else {
1242        statComInst[thread]++;
1243    }
1244#else
1245    statComInst[thread]++;
1246#endif
1247
1248    //
1249    //  Control Instructions
1250    //
1251    if (inst->isControl())
1252        statComBranches[thread]++;
1253
1254    //
1255    //  Memory references
1256    //
1257    if (inst->isMemRef()) {
1258        statComRefs[thread]++;
1259
1260        if (inst->isLoad()) {
1261            statComLoads[thread]++;
1262        }
1263    }
1264
1265    if (inst->isMemBarrier()) {
1266        statComMembars[thread]++;
1267    }
1268}
1269
1270////////////////////////////////////////
1271//                                    //
1272//  SMT COMMIT POLICY MAINTAINED HERE //
1273//                                    //
1274////////////////////////////////////////
1275template <class Impl>
1276int
1277DefaultCommit<Impl>::getCommittingThread()
1278{
1279    if (numThreads > 1) {
1280        switch (commitPolicy) {
1281
1282          case Aggressive:
1283            //If Policy is Aggressive, commit will call
1284            //this function multiple times per
1285            //cycle
1286            return oldestReady();
1287
1288          case RoundRobin:
1289            return roundRobin();
1290
1291          case OldestReady:
1292            return oldestReady();
1293
1294          default:
1295            return -1;
1296        }
1297    } else {
1298        assert(!activeThreads->empty());
1299        int tid = activeThreads->front();
1300
1301        if (commitStatus[tid] == Running ||
1302            commitStatus[tid] == Idle ||
1303            commitStatus[tid] == FetchTrapPending) {
1304            return tid;
1305        } else {
1306            return -1;
1307        }
1308    }
1309}
1310
1311template<class Impl>
1312int
1313DefaultCommit<Impl>::roundRobin()
1314{
1315    std::list<unsigned>::iterator pri_iter = priority_list.begin();
1316    std::list<unsigned>::iterator end      = priority_list.end();
1317
1318    while (pri_iter != end) {
1319        unsigned tid = *pri_iter;
1320
1321        if (commitStatus[tid] == Running ||
1322            commitStatus[tid] == Idle ||
1323            commitStatus[tid] == FetchTrapPending) {
1324
1325            if (rob->isHeadReady(tid)) {
1326                priority_list.erase(pri_iter);
1327                priority_list.push_back(tid);
1328
1329                return tid;
1330            }
1331        }
1332
1333        pri_iter++;
1334    }
1335
1336    return -1;
1337}
1338
1339template<class Impl>
1340int
1341DefaultCommit<Impl>::oldestReady()
1342{
1343    unsigned oldest = 0;
1344    bool first = true;
1345
1346    std::list<unsigned>::iterator threads = activeThreads->begin();
1347    std::list<unsigned>::iterator end = activeThreads->end();
1348
1349    while (threads != end) {
1350        unsigned tid = *threads++;
1351
1352        if (!rob->isEmpty(tid) &&
1353            (commitStatus[tid] == Running ||
1354             commitStatus[tid] == Idle ||
1355             commitStatus[tid] == FetchTrapPending)) {
1356
1357            if (rob->isHeadReady(tid)) {
1358
1359                DynInstPtr head_inst = rob->readHeadInst(tid);
1360
1361                if (first) {
1362                    oldest = tid;
1363                    first = false;
1364                } else if (head_inst->seqNum < oldest) {
1365                    oldest = tid;
1366                }
1367            }
1368        }
1369    }
1370
1371    if (!first) {
1372        return oldest;
1373    } else {
1374        return -1;
1375    }
1376}
1377