commit_impl.hh revision 4405:57af43e114b5
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 2004-2006 The Regents of The University of Michigan 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org * 286145Snate@binkert.org * Authors: Kevin Lim 2911793Sbrandon.potter@amd.com * Korey Sewell 3011793Sbrandon.potter@amd.com */ 317002Snate@binkert.org 327002Snate@binkert.org#include "config/full_system.hh" 337002Snate@binkert.org#include "config/use_checker.hh" 347039Snate@binkert.org 356145Snate@binkert.org#include <algorithm> 367002Snate@binkert.org#include <string> 377002Snate@binkert.org 389497Snilay@cs.wisc.edu#include "arch/utility.hh" 396145Snate@binkert.org#include "base/loader/symtab.hh" 407039Snate@binkert.org#include "base/timebuf.hh" 419497Snilay@cs.wisc.edu#include "cpu/exetrace.hh" 426145Snate@binkert.org#include "cpu/o3/commit.hh" 436145Snate@binkert.org#include "cpu/o3/thread_state.hh" 446145Snate@binkert.org 456145Snate@binkert.org#if USE_CHECKER 466145Snate@binkert.org#include "cpu/checker/cpu.hh" 476145Snate@binkert.org#endif 487039Snate@binkert.org 499497Snilay@cs.wisc.edutemplate <class Impl> 506145Snate@binkert.orgDefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 517039Snate@binkert.org unsigned _tid) 527039Snate@binkert.org : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 536145Snate@binkert.org{ 546145Snate@binkert.org this->setFlags(Event::AutoDelete); 557039Snate@binkert.org} 569497Snilay@cs.wisc.edu 576145Snate@binkert.orgtemplate <class Impl> 587039Snate@binkert.orgvoid 597039Snate@binkert.orgDefaultCommit<Impl>::TrapEvent::process() 609497Snilay@cs.wisc.edu{ 619497Snilay@cs.wisc.edu // This will get reset by commit if it was switched out at the 627039Snate@binkert.org // time of this event processing. 637039Snate@binkert.org commit->trapSquash[tid] = true; 649497Snilay@cs.wisc.edu} 657039Snate@binkert.org 667039Snate@binkert.orgtemplate <class Impl> 677039Snate@binkert.orgconst char * 687039Snate@binkert.orgDefaultCommit<Impl>::TrapEvent::description() 696145Snate@binkert.org{ 706145Snate@binkert.org return "Trap event"; 719497Snilay@cs.wisc.edu} 729497Snilay@cs.wisc.edu 739497Snilay@cs.wisc.edutemplate <class Impl> 749497Snilay@cs.wisc.eduDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params) 759497Snilay@cs.wisc.edu : cpu(_cpu), 769497Snilay@cs.wisc.edu squashCounter(0), 779497Snilay@cs.wisc.edu iewToCommitDelay(params->iewToCommitDelay), 789497Snilay@cs.wisc.edu commitToIEWDelay(params->commitToIEWDelay), 799497Snilay@cs.wisc.edu renameToROBDelay(params->renameToROBDelay), 809497Snilay@cs.wisc.edu fetchToCommitDelay(params->commitToFetchDelay), 819497Snilay@cs.wisc.edu renameWidth(params->renameWidth), 829497Snilay@cs.wisc.edu commitWidth(params->commitWidth), 839497Snilay@cs.wisc.edu numThreads(params->numberOfThreads), 849497Snilay@cs.wisc.edu drainPending(false), 859497Snilay@cs.wisc.edu switchedOut(false), 866145Snate@binkert.org trapLatency(params->trapLatency) 877039Snate@binkert.org{ 8811061Snilay@cs.wisc.edu _status = Active; 896145Snate@binkert.org _nextStatus = Inactive; 907039Snate@binkert.org std::string policy = params->smtCommitPolicy; 917039Snate@binkert.org 927039Snate@binkert.org //Convert string to lowercase 936145Snate@binkert.org std::transform(policy.begin(), policy.end(), policy.begin(), 947039Snate@binkert.org (int(*)(int)) tolower); 957039Snate@binkert.org 966145Snate@binkert.org //Assign commit policy 979497Snilay@cs.wisc.edu if (policy == "aggressive"){ 989497Snilay@cs.wisc.edu commitPolicy = Aggressive; 997039Snate@binkert.org 1007039Snate@binkert.org DPRINTF(Commit,"Commit Policy set to Aggressive."); 1017039Snate@binkert.org } else if (policy == "roundrobin"){ 1027039Snate@binkert.org commitPolicy = RoundRobin; 1037039Snate@binkert.org 1047039Snate@binkert.org //Set-Up Priority List 1057039Snate@binkert.org for (int tid=0; tid < numThreads; tid++) { 1067039Snate@binkert.org priority_list.push_back(tid); 1077039Snate@binkert.org } 1087039Snate@binkert.org 1096145Snate@binkert.org DPRINTF(Commit,"Commit Policy set to Round Robin."); 1107039Snate@binkert.org } else if (policy == "oldestready"){ 1119497Snilay@cs.wisc.edu commitPolicy = OldestReady; 1129497Snilay@cs.wisc.edu 1139497Snilay@cs.wisc.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1147039Snate@binkert.org } else { 1156145Snate@binkert.org assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1169497Snilay@cs.wisc.edu "RoundRobin,OldestReady}"); 1179497Snilay@cs.wisc.edu } 1187039Snate@binkert.org 1197039Snate@binkert.org for (int i=0; i < numThreads; i++) { 1206145Snate@binkert.org commitStatus[i] = Idle; 1216145Snate@binkert.org changedROBNumEntries[i] = false; 1227039Snate@binkert.org checkEmptyROB[i] = false; 1239497Snilay@cs.wisc.edu trapInFlight[i] = false; 1246145Snate@binkert.org committedStores[i] = false; 1259497Snilay@cs.wisc.edu trapSquash[i] = false; 1266145Snate@binkert.org tcSquash[i] = false; 1279497Snilay@cs.wisc.edu PC[i] = nextPC[i] = nextNPC[i] = 0; 1289773Snilay@cs.wisc.edu } 1299773Snilay@cs.wisc.edu#if FULL_SYSTEM 1309773Snilay@cs.wisc.edu interrupt = NoFault; 1319773Snilay@cs.wisc.edu#endif 1329773Snilay@cs.wisc.edu} 1339773Snilay@cs.wisc.edu 1347039Snate@binkert.orgtemplate <class Impl> 1356145Snate@binkert.orgstd::string 1369497Snilay@cs.wisc.eduDefaultCommit<Impl>::name() const 1379497Snilay@cs.wisc.edu{ 1389497Snilay@cs.wisc.edu return cpu->name() + ".commit"; 1399497Snilay@cs.wisc.edu} 1409497Snilay@cs.wisc.edu 1419497Snilay@cs.wisc.edutemplate <class Impl> 1429497Snilay@cs.wisc.eduvoid 1439497Snilay@cs.wisc.eduDefaultCommit<Impl>::regStats() 1449497Snilay@cs.wisc.edu{ 1457039Snate@binkert.org using namespace Stats; 1469497Snilay@cs.wisc.edu commitCommittedInsts 1479497Snilay@cs.wisc.edu .name(name() + ".commitCommittedInsts") 1489497Snilay@cs.wisc.edu .desc("The number of committed instructions") 1499497Snilay@cs.wisc.edu .prereq(commitCommittedInsts); 1509497Snilay@cs.wisc.edu commitSquashedInsts 1519497Snilay@cs.wisc.edu .name(name() + ".commitSquashedInsts") 1529497Snilay@cs.wisc.edu .desc("The number of squashed insts skipped by commit") 1539497Snilay@cs.wisc.edu .prereq(commitSquashedInsts); 1549497Snilay@cs.wisc.edu commitSquashEvents 1559497Snilay@cs.wisc.edu .name(name() + ".commitSquashEvents") 1569497Snilay@cs.wisc.edu .desc("The number of times commit is told to squash") 1579497Snilay@cs.wisc.edu .prereq(commitSquashEvents); 1589497Snilay@cs.wisc.edu commitNonSpecStalls 1599497Snilay@cs.wisc.edu .name(name() + ".commitNonSpecStalls") 1609497Snilay@cs.wisc.edu .desc("The number of times commit has been forced to stall to " 1619497Snilay@cs.wisc.edu "communicate backwards") 1629497Snilay@cs.wisc.edu .prereq(commitNonSpecStalls); 1639497Snilay@cs.wisc.edu branchMispredicts 1649497Snilay@cs.wisc.edu .name(name() + ".branchMispredicts") 1659497Snilay@cs.wisc.edu .desc("The number of times a branch was mispredicted") 1669497Snilay@cs.wisc.edu .prereq(branchMispredicts); 1679497Snilay@cs.wisc.edu numCommittedDist 1689497Snilay@cs.wisc.edu .init(0,commitWidth,1) 1696145Snate@binkert.org .name(name() + ".COM:committed_per_cycle") 1706145Snate@binkert.org .desc("Number of insts commited each cycle") 1716145Snate@binkert.org .flags(Stats::pdf) 1726145Snate@binkert.org ; 1736145Snate@binkert.org 1746145Snate@binkert.org statComInst 1757039Snate@binkert.org .init(cpu->number_of_threads) 1767039Snate@binkert.org .name(name() + ".COM:count") 1776145Snate@binkert.org .desc("Number of instructions committed") 1787039Snate@binkert.org .flags(total) 1797039Snate@binkert.org ; 1807039Snate@binkert.org 1817039Snate@binkert.org statComSwp 1827039Snate@binkert.org .init(cpu->number_of_threads) 1837039Snate@binkert.org .name(name() + ".COM:swp_count") 1847039Snate@binkert.org .desc("Number of s/w prefetches committed") 1856145Snate@binkert.org .flags(total) 1866145Snate@binkert.org ; 1877039Snate@binkert.org 1887039Snate@binkert.org statComRefs 1896145Snate@binkert.org .init(cpu->number_of_threads) 1907039Snate@binkert.org .name(name() + ".COM:refs") 1916145Snate@binkert.org .desc("Number of memory references committed") 1926145Snate@binkert.org .flags(total) 1937039Snate@binkert.org ; 1947039Snate@binkert.org 1956145Snate@binkert.org statComLoads 1967039Snate@binkert.org .init(cpu->number_of_threads) 1977039Snate@binkert.org .name(name() + ".COM:loads") 1987039Snate@binkert.org .desc("Number of loads committed") 1997039Snate@binkert.org .flags(total) 2007039Snate@binkert.org ; 2016145Snate@binkert.org 2026145Snate@binkert.org statComMembars 2037039Snate@binkert.org .init(cpu->number_of_threads) 2047039Snate@binkert.org .name(name() + ".COM:membars") 2056145Snate@binkert.org .desc("Number of memory barriers committed") 2067039Snate@binkert.org .flags(total) 2077039Snate@binkert.org ; 2086145Snate@binkert.org 2097039Snate@binkert.org statComBranches 2106145Snate@binkert.org .init(cpu->number_of_threads) 2117039Snate@binkert.org .name(name() + ".COM:branches") 2127039Snate@binkert.org .desc("Number of branches committed") 2137039Snate@binkert.org .flags(total) 2147039Snate@binkert.org ; 2157039Snate@binkert.org 2167039Snate@binkert.org commitEligible 2177039Snate@binkert.org .init(cpu->number_of_threads) 2187039Snate@binkert.org .name(name() + ".COM:bw_limited") 2197039Snate@binkert.org .desc("number of insts not committed due to BW limits") 2207039Snate@binkert.org .flags(total) 2217039Snate@binkert.org ; 2229497Snilay@cs.wisc.edu 2239497Snilay@cs.wisc.edu commitEligibleSamples 2247039Snate@binkert.org .name(name() + ".COM:bw_lim_events") 2257039Snate@binkert.org .desc("number cycles where commit BW limit reached") 2267039Snate@binkert.org ; 2277039Snate@binkert.org} 2287039Snate@binkert.org 2297039Snate@binkert.orgtemplate <class Impl> 2307039Snate@binkert.orgvoid 2316145Snate@binkert.orgDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2326145Snate@binkert.org{ 2337039Snate@binkert.org thread = threads; 2347039Snate@binkert.org} 2356145Snate@binkert.org 2367039Snate@binkert.orgtemplate <class Impl> 2376145Snate@binkert.orgvoid 238DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 239{ 240 timeBuffer = tb_ptr; 241 242 // Setup wire to send information back to IEW. 243 toIEW = timeBuffer->getWire(0); 244 245 // Setup wire to read data from IEW (for the ROB). 246 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 247} 248 249template <class Impl> 250void 251DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 252{ 253 fetchQueue = fq_ptr; 254 255 // Setup wire to get instructions from rename (for the ROB). 256 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 257} 258 259template <class Impl> 260void 261DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 262{ 263 renameQueue = rq_ptr; 264 265 // Setup wire to get instructions from rename (for the ROB). 266 fromRename = renameQueue->getWire(-renameToROBDelay); 267} 268 269template <class Impl> 270void 271DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 272{ 273 iewQueue = iq_ptr; 274 275 // Setup wire to get instructions from IEW. 276 fromIEW = iewQueue->getWire(-iewToCommitDelay); 277} 278 279template <class Impl> 280void 281DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 282{ 283 iewStage = iew_stage; 284} 285 286template<class Impl> 287void 288DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 289{ 290 activeThreads = at_ptr; 291} 292 293template <class Impl> 294void 295DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 296{ 297 for (int i=0; i < numThreads; i++) { 298 renameMap[i] = &rm_ptr[i]; 299 } 300} 301 302template <class Impl> 303void 304DefaultCommit<Impl>::setROB(ROB *rob_ptr) 305{ 306 rob = rob_ptr; 307} 308 309template <class Impl> 310void 311DefaultCommit<Impl>::initStage() 312{ 313 rob->setActiveThreads(activeThreads); 314 rob->resetEntries(); 315 316 // Broadcast the number of free entries. 317 for (int i=0; i < numThreads; i++) { 318 toIEW->commitInfo[i].usedROB = true; 319 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 320 toIEW->commitInfo[i].emptyROB = true; 321 } 322 323 // Commit must broadcast the number of free entries it has at the 324 // start of the simulation, so it starts as active. 325 cpu->activateStage(O3CPU::CommitIdx); 326 327 cpu->activityThisCycle(); 328 trapLatency = cpu->cycles(trapLatency); 329} 330 331template <class Impl> 332bool 333DefaultCommit<Impl>::drain() 334{ 335 drainPending = true; 336 337 return false; 338} 339 340template <class Impl> 341void 342DefaultCommit<Impl>::switchOut() 343{ 344 switchedOut = true; 345 drainPending = false; 346 rob->switchOut(); 347} 348 349template <class Impl> 350void 351DefaultCommit<Impl>::resume() 352{ 353 drainPending = false; 354} 355 356template <class Impl> 357void 358DefaultCommit<Impl>::takeOverFrom() 359{ 360 switchedOut = false; 361 _status = Active; 362 _nextStatus = Inactive; 363 for (int i=0; i < numThreads; i++) { 364 commitStatus[i] = Idle; 365 changedROBNumEntries[i] = false; 366 trapSquash[i] = false; 367 tcSquash[i] = false; 368 } 369 squashCounter = 0; 370 rob->takeOverFrom(); 371} 372 373template <class Impl> 374void 375DefaultCommit<Impl>::updateStatus() 376{ 377 // reset ROB changed variable 378 std::list<unsigned>::iterator threads = activeThreads->begin(); 379 std::list<unsigned>::iterator end = activeThreads->end(); 380 381 while (threads != end) { 382 unsigned tid = *threads++; 383 384 changedROBNumEntries[tid] = false; 385 386 // Also check if any of the threads has a trap pending 387 if (commitStatus[tid] == TrapPending || 388 commitStatus[tid] == FetchTrapPending) { 389 _nextStatus = Active; 390 } 391 } 392 393 if (_nextStatus == Inactive && _status == Active) { 394 DPRINTF(Activity, "Deactivating stage.\n"); 395 cpu->deactivateStage(O3CPU::CommitIdx); 396 } else if (_nextStatus == Active && _status == Inactive) { 397 DPRINTF(Activity, "Activating stage.\n"); 398 cpu->activateStage(O3CPU::CommitIdx); 399 } 400 401 _status = _nextStatus; 402} 403 404template <class Impl> 405void 406DefaultCommit<Impl>::setNextStatus() 407{ 408 int squashes = 0; 409 410 std::list<unsigned>::iterator threads = activeThreads->begin(); 411 std::list<unsigned>::iterator end = activeThreads->end(); 412 413 while (threads != end) { 414 unsigned tid = *threads++; 415 416 if (commitStatus[tid] == ROBSquashing) { 417 squashes++; 418 } 419 } 420 421 squashCounter = squashes; 422 423 // If commit is currently squashing, then it will have activity for the 424 // next cycle. Set its next status as active. 425 if (squashCounter) { 426 _nextStatus = Active; 427 } 428} 429 430template <class Impl> 431bool 432DefaultCommit<Impl>::changedROBEntries() 433{ 434 std::list<unsigned>::iterator threads = activeThreads->begin(); 435 std::list<unsigned>::iterator end = activeThreads->end(); 436 437 while (threads != end) { 438 unsigned tid = *threads++; 439 440 if (changedROBNumEntries[tid]) { 441 return true; 442 } 443 } 444 445 return false; 446} 447 448template <class Impl> 449unsigned 450DefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 451{ 452 return rob->numFreeEntries(tid); 453} 454 455template <class Impl> 456void 457DefaultCommit<Impl>::generateTrapEvent(unsigned tid) 458{ 459 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 460 461 TrapEvent *trap = new TrapEvent(this, tid); 462 463 trap->schedule(curTick + trapLatency); 464 trapInFlight[tid] = true; 465} 466 467template <class Impl> 468void 469DefaultCommit<Impl>::generateTCEvent(unsigned tid) 470{ 471 assert(!trapInFlight[tid]); 472 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 473 474 tcSquash[tid] = true; 475} 476 477template <class Impl> 478void 479DefaultCommit<Impl>::squashAll(unsigned tid) 480{ 481 // If we want to include the squashing instruction in the squash, 482 // then use one older sequence number. 483 // Hopefully this doesn't mess things up. Basically I want to squash 484 // all instructions of this thread. 485 InstSeqNum squashed_inst = rob->isEmpty() ? 486 0 : rob->readHeadInst(tid)->seqNum - 1; 487 488 // All younger instructions will be squashed. Set the sequence 489 // number as the youngest instruction in the ROB (0 in this case. 490 // Hopefully nothing breaks.) 491 youngestSeqNum[tid] = 0; 492 493 rob->squash(squashed_inst, tid); 494 changedROBNumEntries[tid] = true; 495 496 // Send back the sequence number of the squashed instruction. 497 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 498 499 // Send back the squash signal to tell stages that they should 500 // squash. 501 toIEW->commitInfo[tid].squash = true; 502 503 // Send back the rob squashing signal so other stages know that 504 // the ROB is in the process of squashing. 505 toIEW->commitInfo[tid].robSquashing = true; 506 507 toIEW->commitInfo[tid].branchMispredict = false; 508 509 toIEW->commitInfo[tid].nextPC = PC[tid]; 510 toIEW->commitInfo[tid].nextNPC = nextPC[tid]; 511} 512 513template <class Impl> 514void 515DefaultCommit<Impl>::squashFromTrap(unsigned tid) 516{ 517 squashAll(tid); 518 519 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 520 521 thread[tid]->trapPending = false; 522 thread[tid]->inSyscall = false; 523 trapInFlight[tid] = false; 524 525 trapSquash[tid] = false; 526 527 commitStatus[tid] = ROBSquashing; 528 cpu->activityThisCycle(); 529} 530 531template <class Impl> 532void 533DefaultCommit<Impl>::squashFromTC(unsigned tid) 534{ 535 squashAll(tid); 536 537 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 538 539 thread[tid]->inSyscall = false; 540 assert(!thread[tid]->trapPending); 541 542 commitStatus[tid] = ROBSquashing; 543 cpu->activityThisCycle(); 544 545 tcSquash[tid] = false; 546} 547 548template <class Impl> 549void 550DefaultCommit<Impl>::tick() 551{ 552 wroteToTimeBuffer = false; 553 _nextStatus = Inactive; 554 555 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 556 cpu->signalDrained(); 557 drainPending = false; 558 return; 559 } 560 561 if (activeThreads->empty()) 562 return; 563 564 std::list<unsigned>::iterator threads = activeThreads->begin(); 565 std::list<unsigned>::iterator end = activeThreads->end(); 566 567 // Check if any of the threads are done squashing. Change the 568 // status if they are done. 569 while (threads != end) { 570 unsigned tid = *threads++; 571 572 // Clear the bit saying if the thread has committed stores 573 // this cycle. 574 committedStores[tid] = false; 575 576 if (commitStatus[tid] == ROBSquashing) { 577 578 if (rob->isDoneSquashing(tid)) { 579 commitStatus[tid] = Running; 580 } else { 581 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 582 " insts this cycle.\n", tid); 583 rob->doSquash(tid); 584 toIEW->commitInfo[tid].robSquashing = true; 585 wroteToTimeBuffer = true; 586 } 587 } 588 } 589 590 commit(); 591 592 markCompletedInsts(); 593 594 threads = activeThreads->begin(); 595 596 while (threads != end) { 597 unsigned tid = *threads++; 598 599 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 600 // The ROB has more instructions it can commit. Its next status 601 // will be active. 602 _nextStatus = Active; 603 604 DynInstPtr inst = rob->readHeadInst(tid); 605 606 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 607 " ROB and ready to commit\n", 608 tid, inst->seqNum, inst->readPC()); 609 610 } else if (!rob->isEmpty(tid)) { 611 DynInstPtr inst = rob->readHeadInst(tid); 612 613 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 614 "%#x is head of ROB and not ready\n", 615 tid, inst->seqNum, inst->readPC()); 616 } 617 618 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 619 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 620 } 621 622 623 if (wroteToTimeBuffer) { 624 DPRINTF(Activity, "Activity This Cycle.\n"); 625 cpu->activityThisCycle(); 626 } 627 628 updateStatus(); 629} 630 631#if FULL_SYSTEM 632template <class Impl> 633void 634DefaultCommit<Impl>::handleInterrupt() 635{ 636 if (interrupt != NoFault) { 637 // Wait until the ROB is empty and all stores have drained in 638 // order to enter the interrupt. 639 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 640 // Squash or record that I need to squash this cycle if 641 // an interrupt needed to be handled. 642 DPRINTF(Commit, "Interrupt detected.\n"); 643 644 // Clear the interrupt now that it's going to be handled 645 toIEW->commitInfo[0].clearInterrupt = true; 646 647 assert(!thread[0]->inSyscall); 648 thread[0]->inSyscall = true; 649 650 // CPU will handle interrupt. 651 cpu->processInterrupts(interrupt); 652 653 thread[0]->inSyscall = false; 654 655 commitStatus[0] = TrapPending; 656 657 // Generate trap squash event. 658 generateTrapEvent(0); 659 660 interrupt = NoFault; 661 } else { 662 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 663 } 664 } else if (commitStatus[0] != TrapPending && 665 cpu->check_interrupts(cpu->tcBase(0)) && 666 !trapSquash[0] && 667 !tcSquash[0]) { 668 // Process interrupts if interrupts are enabled, not in PAL 669 // mode, and no other traps or external squashes are currently 670 // pending. 671 // @todo: Allow other threads to handle interrupts. 672 673 // Get any interrupt that happened 674 interrupt = cpu->getInterrupts(); 675 676 if (interrupt != NoFault) { 677 // Tell fetch that there is an interrupt pending. This 678 // will make fetch wait until it sees a non PAL-mode PC, 679 // at which point it stops fetching instructions. 680 toIEW->commitInfo[0].interruptPending = true; 681 } 682 } 683} 684#endif // FULL_SYSTEM 685 686template <class Impl> 687void 688DefaultCommit<Impl>::commit() 689{ 690 691#if FULL_SYSTEM 692 // Check for any interrupt, and start processing it. Or if we 693 // have an outstanding interrupt and are at a point when it is 694 // valid to take an interrupt, process it. 695 if (cpu->check_interrupts(cpu->tcBase(0))) { 696 handleInterrupt(); 697 } 698#endif // FULL_SYSTEM 699 700 //////////////////////////////////// 701 // Check for any possible squashes, handle them first 702 //////////////////////////////////// 703 std::list<unsigned>::iterator threads = activeThreads->begin(); 704 std::list<unsigned>::iterator end = activeThreads->end(); 705 706 while (threads != end) { 707 unsigned tid = *threads++; 708 709 // Not sure which one takes priority. I think if we have 710 // both, that's a bad sign. 711 if (trapSquash[tid] == true) { 712 assert(!tcSquash[tid]); 713 squashFromTrap(tid); 714 } else if (tcSquash[tid] == true) { 715 assert(commitStatus[tid] != TrapPending); 716 squashFromTC(tid); 717 } 718 719 // Squashed sequence number must be older than youngest valid 720 // instruction in the ROB. This prevents squashes from younger 721 // instructions overriding squashes from older instructions. 722 if (fromIEW->squash[tid] && 723 commitStatus[tid] != TrapPending && 724 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 725 726 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 727 tid, 728 fromIEW->mispredPC[tid], 729 fromIEW->squashedSeqNum[tid]); 730 731 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 732 tid, 733 fromIEW->nextPC[tid]); 734 735 commitStatus[tid] = ROBSquashing; 736 737 // If we want to include the squashing instruction in the squash, 738 // then use one older sequence number. 739 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 740 741#if ISA_HAS_DELAY_SLOT 742 InstSeqNum bdelay_done_seq_num = squashed_inst; 743 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid]; 744 bool branchMispredict = fromIEW->branchMispredict[tid]; 745 746 // Squashing/not squashing the branch delay slot only makes 747 // sense when you're squashing from a branch, ie from a branch 748 // mispredict. 749 if (branchMispredict && !squash_bdelay_slot) { 750 bdelay_done_seq_num++; 751 } 752#endif 753 754 if (fromIEW->includeSquashInst[tid] == true) { 755 squashed_inst--; 756#if ISA_HAS_DELAY_SLOT 757 bdelay_done_seq_num--; 758#endif 759 } 760 761 // All younger instructions will be squashed. Set the sequence 762 // number as the youngest instruction in the ROB. 763 youngestSeqNum[tid] = squashed_inst; 764 765#if ISA_HAS_DELAY_SLOT 766 rob->squash(bdelay_done_seq_num, tid); 767 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 768 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 769#else 770 rob->squash(squashed_inst, tid); 771 toIEW->commitInfo[tid].squashDelaySlot = true; 772#endif 773 changedROBNumEntries[tid] = true; 774 775 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 776 777 toIEW->commitInfo[tid].squash = true; 778 779 // Send back the rob squashing signal so other stages know that 780 // the ROB is in the process of squashing. 781 toIEW->commitInfo[tid].robSquashing = true; 782 783 toIEW->commitInfo[tid].branchMispredict = 784 fromIEW->branchMispredict[tid]; 785 786 toIEW->commitInfo[tid].branchTaken = 787 fromIEW->branchTaken[tid]; 788 789 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 790 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid]; 791 792 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 793 794 if (toIEW->commitInfo[tid].branchMispredict) { 795 ++branchMispredicts; 796 } 797 } 798 799 } 800 801 setNextStatus(); 802 803 if (squashCounter != numThreads) { 804 // If we're not currently squashing, then get instructions. 805 getInsts(); 806 807 // Try to commit any instructions. 808 commitInsts(); 809 } else { 810#if ISA_HAS_DELAY_SLOT 811 skidInsert(); 812#endif 813 } 814 815 //Check for any activity 816 threads = activeThreads->begin(); 817 818 while (threads != end) { 819 unsigned tid = *threads++; 820 821 if (changedROBNumEntries[tid]) { 822 toIEW->commitInfo[tid].usedROB = true; 823 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 824 825 wroteToTimeBuffer = true; 826 changedROBNumEntries[tid] = false; 827 if (rob->isEmpty(tid)) 828 checkEmptyROB[tid] = true; 829 } 830 831 // ROB is only considered "empty" for previous stages if: a) 832 // ROB is empty, b) there are no outstanding stores, c) IEW 833 // stage has received any information regarding stores that 834 // committed. 835 // c) is checked by making sure to not consider the ROB empty 836 // on the same cycle as when stores have been committed. 837 // @todo: Make this handle multi-cycle communication between 838 // commit and IEW. 839 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 840 !iewStage->hasStoresToWB() && !committedStores[tid]) { 841 checkEmptyROB[tid] = false; 842 toIEW->commitInfo[tid].usedROB = true; 843 toIEW->commitInfo[tid].emptyROB = true; 844 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 845 wroteToTimeBuffer = true; 846 } 847 848 } 849} 850 851template <class Impl> 852void 853DefaultCommit<Impl>::commitInsts() 854{ 855 //////////////////////////////////// 856 // Handle commit 857 // Note that commit will be handled prior to putting new 858 // instructions in the ROB so that the ROB only tries to commit 859 // instructions it has in this current cycle, and not instructions 860 // it is writing in during this cycle. Can't commit and squash 861 // things at the same time... 862 //////////////////////////////////// 863 864 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 865 866 unsigned num_committed = 0; 867 868 DynInstPtr head_inst; 869 870 // Commit as many instructions as possible until the commit bandwidth 871 // limit is reached, or it becomes impossible to commit any more. 872 while (num_committed < commitWidth) { 873 int commit_thread = getCommittingThread(); 874 875 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 876 break; 877 878 head_inst = rob->readHeadInst(commit_thread); 879 880 int tid = head_inst->threadNumber; 881 882 assert(tid == commit_thread); 883 884 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 885 head_inst->seqNum, tid); 886 887 // If the head instruction is squashed, it is ready to retire 888 // (be removed from the ROB) at any time. 889 if (head_inst->isSquashed()) { 890 891 DPRINTF(Commit, "Retiring squashed instruction from " 892 "ROB.\n"); 893 894 rob->retireHead(commit_thread); 895 896 ++commitSquashedInsts; 897 898 // Record that the number of ROB entries has changed. 899 changedROBNumEntries[tid] = true; 900 } else { 901 PC[tid] = head_inst->readPC(); 902 nextPC[tid] = head_inst->readNextPC(); 903 nextNPC[tid] = head_inst->readNextNPC(); 904 905 // Increment the total number of non-speculative instructions 906 // executed. 907 // Hack for now: it really shouldn't happen until after the 908 // commit is deemed to be successful, but this count is needed 909 // for syscalls. 910 thread[tid]->funcExeInst++; 911 912 // Try to commit the head instruction. 913 bool commit_success = commitHead(head_inst, num_committed); 914 915 if (commit_success) { 916 ++num_committed; 917 918 changedROBNumEntries[tid] = true; 919 920 // Set the doneSeqNum to the youngest committed instruction. 921 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 922 923 ++commitCommittedInsts; 924 925 // To match the old model, don't count nops and instruction 926 // prefetches towards the total commit count. 927 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 928 cpu->instDone(tid); 929 } 930 931 PC[tid] = nextPC[tid]; 932#if ISA_HAS_DELAY_SLOT 933 nextPC[tid] = nextNPC[tid]; 934 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 935#else 936 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 937#endif 938 939#if FULL_SYSTEM 940 int count = 0; 941 Addr oldpc; 942 do { 943 // Debug statement. Checks to make sure we're not 944 // currently updating state while handling PC events. 945 if (count == 0) 946 assert(!thread[tid]->inSyscall && 947 !thread[tid]->trapPending); 948 oldpc = PC[tid]; 949 cpu->system->pcEventQueue.service( 950 thread[tid]->getTC()); 951 count++; 952 } while (oldpc != PC[tid]); 953 if (count > 1) { 954 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 955 break; 956 } 957#endif 958 } else { 959 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 960 "[tid:%i] [sn:%i].\n", 961 head_inst->readPC(), tid ,head_inst->seqNum); 962 break; 963 } 964 } 965 } 966 967 DPRINTF(CommitRate, "%i\n", num_committed); 968 numCommittedDist.sample(num_committed); 969 970 if (num_committed == commitWidth) { 971 commitEligibleSamples++; 972 } 973} 974 975template <class Impl> 976bool 977DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 978{ 979 assert(head_inst); 980 981 int tid = head_inst->threadNumber; 982 983 // If the instruction is not executed yet, then it will need extra 984 // handling. Signal backwards that it should be executed. 985 if (!head_inst->isExecuted()) { 986 // Keep this number correct. We have not yet actually executed 987 // and committed this instruction. 988 thread[tid]->funcExeInst--; 989 990 if (head_inst->isNonSpeculative() || 991 head_inst->isStoreConditional() || 992 head_inst->isMemBarrier() || 993 head_inst->isWriteBarrier()) { 994 995 DPRINTF(Commit, "Encountered a barrier or non-speculative " 996 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 997 head_inst->seqNum, head_inst->readPC()); 998 999 if (inst_num > 0 || iewStage->hasStoresToWB()) { 1000 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1001 return false; 1002 } 1003 1004 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1005 1006 // Change the instruction so it won't try to commit again until 1007 // it is executed. 1008 head_inst->clearCanCommit(); 1009 1010 ++commitNonSpecStalls; 1011 1012 return false; 1013 } else if (head_inst->isLoad()) { 1014 if (inst_num > 0 || iewStage->hasStoresToWB()) { 1015 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1016 return false; 1017 } 1018 1019 assert(head_inst->uncacheable()); 1020 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 1021 head_inst->seqNum, head_inst->readPC()); 1022 1023 // Send back the non-speculative instruction's sequence 1024 // number. Tell the lsq to re-execute the load. 1025 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1026 toIEW->commitInfo[tid].uncached = true; 1027 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1028 1029 head_inst->clearCanCommit(); 1030 1031 return false; 1032 } else { 1033 panic("Trying to commit un-executed instruction " 1034 "of unknown type!\n"); 1035 } 1036 } 1037 1038 if (head_inst->isThreadSync()) { 1039 // Not handled for now. 1040 panic("Thread sync instructions are not handled yet.\n"); 1041 } 1042 1043 // Check if the instruction caused a fault. If so, trap. 1044 Fault inst_fault = head_inst->getFault(); 1045 1046 // Stores mark themselves as completed. 1047 if (!head_inst->isStore() && inst_fault == NoFault) { 1048 head_inst->setCompleted(); 1049 } 1050 1051#if USE_CHECKER 1052 // Use checker prior to updating anything due to traps or PC 1053 // based events. 1054 if (cpu->checker) { 1055 cpu->checker->verify(head_inst); 1056 } 1057#endif 1058 1059 // DTB will sometimes need the machine instruction for when 1060 // faults happen. So we will set it here, prior to the DTB 1061 // possibly needing it for its fault. 1062 thread[tid]->setInst( 1063 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1064 1065 if (inst_fault != NoFault) { 1066 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1067 head_inst->seqNum, head_inst->readPC()); 1068 1069 if (iewStage->hasStoresToWB() || inst_num > 0) { 1070 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1071 return false; 1072 } 1073 1074 head_inst->setCompleted(); 1075 1076#if USE_CHECKER 1077 if (cpu->checker && head_inst->isStore()) { 1078 cpu->checker->verify(head_inst); 1079 } 1080#endif 1081 1082 assert(!thread[tid]->inSyscall); 1083 1084 // Mark that we're in state update mode so that the trap's 1085 // execution doesn't generate extra squashes. 1086 thread[tid]->inSyscall = true; 1087 1088 // Execute the trap. Although it's slightly unrealistic in 1089 // terms of timing (as it doesn't wait for the full timing of 1090 // the trap event to complete before updating state), it's 1091 // needed to update the state as soon as possible. This 1092 // prevents external agents from changing any specific state 1093 // that the trap need. 1094 cpu->trap(inst_fault, tid); 1095 1096 // Exit state update mode to avoid accidental updating. 1097 thread[tid]->inSyscall = false; 1098 1099 commitStatus[tid] = TrapPending; 1100 1101 if (head_inst->traceData) { 1102 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1103 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1104 head_inst->traceData->dump(); 1105 delete head_inst->traceData; 1106 head_inst->traceData = NULL; 1107 } 1108 1109 // Generate trap squash event. 1110 generateTrapEvent(tid); 1111// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 1112 return false; 1113 } 1114 1115 updateComInstStats(head_inst); 1116 1117#if FULL_SYSTEM 1118 if (thread[tid]->profile) { 1119// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 1120// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 1121 thread[tid]->profilePC = head_inst->readPC(); 1122 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1123 head_inst->staticInst); 1124 1125 if (node) 1126 thread[tid]->profileNode = node; 1127 } 1128#endif 1129 1130 if (head_inst->traceData) { 1131 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1132 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1133 head_inst->traceData->dump(); 1134 delete head_inst->traceData; 1135 head_inst->traceData = NULL; 1136 } 1137 1138 // Update the commit rename map 1139 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1140 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1141 head_inst->renamedDestRegIdx(i)); 1142 } 1143 1144 if (head_inst->isCopy()) 1145 panic("Should not commit any copy instructions!"); 1146 1147 // Finally clear the head ROB entry. 1148 rob->retireHead(tid); 1149 1150 // If this was a store, record it for this cycle. 1151 if (head_inst->isStore()) 1152 committedStores[tid] = true; 1153 1154 // Return true to indicate that we have committed an instruction. 1155 return true; 1156} 1157 1158template <class Impl> 1159void 1160DefaultCommit<Impl>::getInsts() 1161{ 1162 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1163 1164#if ISA_HAS_DELAY_SLOT 1165 // Read any renamed instructions and place them into the ROB. 1166 int insts_to_process = std::min((int)renameWidth, 1167 (int)(fromRename->size + skidBuffer.size())); 1168 int rename_idx = 0; 1169 1170 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 1171 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 1172 skidBuffer.size()); 1173#else 1174 // Read any renamed instructions and place them into the ROB. 1175 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1176#endif 1177 1178 1179 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1180 DynInstPtr inst; 1181 1182#if ISA_HAS_DELAY_SLOT 1183 // Get insts from skidBuffer or from Rename 1184 if (skidBuffer.size() > 0) { 1185 DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 1186 inst = skidBuffer.front(); 1187 skidBuffer.pop(); 1188 } else { 1189 DPRINTF(Commit, "Grabbing rename inst.\n"); 1190 inst = fromRename->insts[rename_idx++]; 1191 } 1192#else 1193 inst = fromRename->insts[inst_num]; 1194#endif 1195 int tid = inst->threadNumber; 1196 1197 if (!inst->isSquashed() && 1198 commitStatus[tid] != ROBSquashing && 1199 commitStatus[tid] != TrapPending) { 1200 changedROBNumEntries[tid] = true; 1201 1202 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1203 inst->readPC(), inst->seqNum, tid); 1204 1205 rob->insertInst(inst); 1206 1207 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1208 1209 youngestSeqNum[tid] = inst->seqNum; 1210 } else { 1211 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1212 "squashed, skipping.\n", 1213 inst->readPC(), inst->seqNum, tid); 1214 } 1215 } 1216 1217#if ISA_HAS_DELAY_SLOT 1218 if (rename_idx < fromRename->size) { 1219 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 1220 1221 for (; 1222 rename_idx < fromRename->size; 1223 rename_idx++) { 1224 DynInstPtr inst = fromRename->insts[rename_idx]; 1225 1226 if (!inst->isSquashed()) { 1227 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1228 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1229 inst->threadNumber); 1230 skidBuffer.push(inst); 1231 } else { 1232 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1233 "squashed, skipping.\n", 1234 inst->readPC(), inst->seqNum, inst->threadNumber); 1235 } 1236 } 1237 } 1238#endif 1239 1240} 1241 1242template <class Impl> 1243void 1244DefaultCommit<Impl>::skidInsert() 1245{ 1246 DPRINTF(Commit, "Attempting to any instructions from rename into " 1247 "skidBuffer.\n"); 1248 1249 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1250 DynInstPtr inst = fromRename->insts[inst_num]; 1251 1252 if (!inst->isSquashed()) { 1253 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1254 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1255 inst->threadNumber); 1256 skidBuffer.push(inst); 1257 } else { 1258 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1259 "squashed, skipping.\n", 1260 inst->readPC(), inst->seqNum, inst->threadNumber); 1261 } 1262 } 1263} 1264 1265template <class Impl> 1266void 1267DefaultCommit<Impl>::markCompletedInsts() 1268{ 1269 // Grab completed insts out of the IEW instruction queue, and mark 1270 // instructions completed within the ROB. 1271 for (int inst_num = 0; 1272 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1273 ++inst_num) 1274 { 1275 if (!fromIEW->insts[inst_num]->isSquashed()) { 1276 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1277 "within ROB.\n", 1278 fromIEW->insts[inst_num]->threadNumber, 1279 fromIEW->insts[inst_num]->readPC(), 1280 fromIEW->insts[inst_num]->seqNum); 1281 1282 // Mark the instruction as ready to commit. 1283 fromIEW->insts[inst_num]->setCanCommit(); 1284 } 1285 } 1286} 1287 1288template <class Impl> 1289bool 1290DefaultCommit<Impl>::robDoneSquashing() 1291{ 1292 std::list<unsigned>::iterator threads = activeThreads->begin(); 1293 std::list<unsigned>::iterator end = activeThreads->end(); 1294 1295 while (threads != end) { 1296 unsigned tid = *threads++; 1297 1298 if (!rob->isDoneSquashing(tid)) 1299 return false; 1300 } 1301 1302 return true; 1303} 1304 1305template <class Impl> 1306void 1307DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1308{ 1309 unsigned thread = inst->threadNumber; 1310 1311 // 1312 // Pick off the software prefetches 1313 // 1314#ifdef TARGET_ALPHA 1315 if (inst->isDataPrefetch()) { 1316 statComSwp[thread]++; 1317 } else { 1318 statComInst[thread]++; 1319 } 1320#else 1321 statComInst[thread]++; 1322#endif 1323 1324 // 1325 // Control Instructions 1326 // 1327 if (inst->isControl()) 1328 statComBranches[thread]++; 1329 1330 // 1331 // Memory references 1332 // 1333 if (inst->isMemRef()) { 1334 statComRefs[thread]++; 1335 1336 if (inst->isLoad()) { 1337 statComLoads[thread]++; 1338 } 1339 } 1340 1341 if (inst->isMemBarrier()) { 1342 statComMembars[thread]++; 1343 } 1344} 1345 1346//////////////////////////////////////// 1347// // 1348// SMT COMMIT POLICY MAINTAINED HERE // 1349// // 1350//////////////////////////////////////// 1351template <class Impl> 1352int 1353DefaultCommit<Impl>::getCommittingThread() 1354{ 1355 if (numThreads > 1) { 1356 switch (commitPolicy) { 1357 1358 case Aggressive: 1359 //If Policy is Aggressive, commit will call 1360 //this function multiple times per 1361 //cycle 1362 return oldestReady(); 1363 1364 case RoundRobin: 1365 return roundRobin(); 1366 1367 case OldestReady: 1368 return oldestReady(); 1369 1370 default: 1371 return -1; 1372 } 1373 } else { 1374 assert(!activeThreads->empty()); 1375 int tid = activeThreads->front(); 1376 1377 if (commitStatus[tid] == Running || 1378 commitStatus[tid] == Idle || 1379 commitStatus[tid] == FetchTrapPending) { 1380 return tid; 1381 } else { 1382 return -1; 1383 } 1384 } 1385} 1386 1387template<class Impl> 1388int 1389DefaultCommit<Impl>::roundRobin() 1390{ 1391 std::list<unsigned>::iterator pri_iter = priority_list.begin(); 1392 std::list<unsigned>::iterator end = priority_list.end(); 1393 1394 while (pri_iter != end) { 1395 unsigned tid = *pri_iter; 1396 1397 if (commitStatus[tid] == Running || 1398 commitStatus[tid] == Idle || 1399 commitStatus[tid] == FetchTrapPending) { 1400 1401 if (rob->isHeadReady(tid)) { 1402 priority_list.erase(pri_iter); 1403 priority_list.push_back(tid); 1404 1405 return tid; 1406 } 1407 } 1408 1409 pri_iter++; 1410 } 1411 1412 return -1; 1413} 1414 1415template<class Impl> 1416int 1417DefaultCommit<Impl>::oldestReady() 1418{ 1419 unsigned oldest = 0; 1420 bool first = true; 1421 1422 std::list<unsigned>::iterator threads = activeThreads->begin(); 1423 std::list<unsigned>::iterator end = activeThreads->end(); 1424 1425 while (threads != end) { 1426 unsigned tid = *threads++; 1427 1428 if (!rob->isEmpty(tid) && 1429 (commitStatus[tid] == Running || 1430 commitStatus[tid] == Idle || 1431 commitStatus[tid] == FetchTrapPending)) { 1432 1433 if (rob->isHeadReady(tid)) { 1434 1435 DynInstPtr head_inst = rob->readHeadInst(tid); 1436 1437 if (first) { 1438 oldest = tid; 1439 first = false; 1440 } else if (head_inst->seqNum < oldest) { 1441 oldest = tid; 1442 } 1443 } 1444 } 1445 } 1446 1447 if (!first) { 1448 return oldest; 1449 } else { 1450 return -1; 1451 } 1452} 1453