commit_impl.hh revision 3980:9bcb2a2e9bb8
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/full_system.hh" 33#include "config/use_checker.hh" 34 35#include <algorithm> 36#include <string> 37 38#include "arch/utility.hh" 39#include "base/loader/symtab.hh" 40#include "base/timebuf.hh" 41#include "cpu/exetrace.hh" 42#include "cpu/o3/commit.hh" 43#include "cpu/o3/thread_state.hh" 44 45#if USE_CHECKER 46#include "cpu/checker/cpu.hh" 47#endif 48 49template <class Impl> 50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 51 unsigned _tid) 52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 53{ 54 this->setFlags(Event::AutoDelete); 55} 56 57template <class Impl> 58void 59DefaultCommit<Impl>::TrapEvent::process() 60{ 61 // This will get reset by commit if it was switched out at the 62 // time of this event processing. 63 commit->trapSquash[tid] = true; 64} 65 66template <class Impl> 67const char * 68DefaultCommit<Impl>::TrapEvent::description() 69{ 70 return "Trap event"; 71} 72 73template <class Impl> 74DefaultCommit<Impl>::DefaultCommit(Params *params) 75 : squashCounter(0), 76 iewToCommitDelay(params->iewToCommitDelay), 77 commitToIEWDelay(params->commitToIEWDelay), 78 renameToROBDelay(params->renameToROBDelay), 79 fetchToCommitDelay(params->commitToFetchDelay), 80 renameWidth(params->renameWidth), 81 commitWidth(params->commitWidth), 82 numThreads(params->numberOfThreads), 83 drainPending(false), 84 switchedOut(false), 85 trapLatency(params->trapLatency) 86{ 87 _status = Active; 88 _nextStatus = Inactive; 89 std::string policy = params->smtCommitPolicy; 90 91 //Convert string to lowercase 92 std::transform(policy.begin(), policy.end(), policy.begin(), 93 (int(*)(int)) tolower); 94 95 //Assign commit policy 96 if (policy == "aggressive"){ 97 commitPolicy = Aggressive; 98 99 DPRINTF(Commit,"Commit Policy set to Aggressive."); 100 } else if (policy == "roundrobin"){ 101 commitPolicy = RoundRobin; 102 103 //Set-Up Priority List 104 for (int tid=0; tid < numThreads; tid++) { 105 priority_list.push_back(tid); 106 } 107 108 DPRINTF(Commit,"Commit Policy set to Round Robin."); 109 } else if (policy == "oldestready"){ 110 commitPolicy = OldestReady; 111 112 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 113 } else { 114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 115 "RoundRobin,OldestReady}"); 116 } 117 118 for (int i=0; i < numThreads; i++) { 119 commitStatus[i] = Idle; 120 changedROBNumEntries[i] = false; 121 trapSquash[i] = false; 122 tcSquash[i] = false; 123 PC[i] = nextPC[i] = nextNPC[i] = 0; 124 } 125#if FULL_SYSTEM 126 interrupt = NoFault; 127#endif 128} 129 130template <class Impl> 131std::string 132DefaultCommit<Impl>::name() const 133{ 134 return cpu->name() + ".commit"; 135} 136 137template <class Impl> 138void 139DefaultCommit<Impl>::regStats() 140{ 141 using namespace Stats; 142 commitCommittedInsts 143 .name(name() + ".commitCommittedInsts") 144 .desc("The number of committed instructions") 145 .prereq(commitCommittedInsts); 146 commitSquashedInsts 147 .name(name() + ".commitSquashedInsts") 148 .desc("The number of squashed insts skipped by commit") 149 .prereq(commitSquashedInsts); 150 commitSquashEvents 151 .name(name() + ".commitSquashEvents") 152 .desc("The number of times commit is told to squash") 153 .prereq(commitSquashEvents); 154 commitNonSpecStalls 155 .name(name() + ".commitNonSpecStalls") 156 .desc("The number of times commit has been forced to stall to " 157 "communicate backwards") 158 .prereq(commitNonSpecStalls); 159 branchMispredicts 160 .name(name() + ".branchMispredicts") 161 .desc("The number of times a branch was mispredicted") 162 .prereq(branchMispredicts); 163 numCommittedDist 164 .init(0,commitWidth,1) 165 .name(name() + ".COM:committed_per_cycle") 166 .desc("Number of insts commited each cycle") 167 .flags(Stats::pdf) 168 ; 169 170 statComInst 171 .init(cpu->number_of_threads) 172 .name(name() + ".COM:count") 173 .desc("Number of instructions committed") 174 .flags(total) 175 ; 176 177 statComSwp 178 .init(cpu->number_of_threads) 179 .name(name() + ".COM:swp_count") 180 .desc("Number of s/w prefetches committed") 181 .flags(total) 182 ; 183 184 statComRefs 185 .init(cpu->number_of_threads) 186 .name(name() + ".COM:refs") 187 .desc("Number of memory references committed") 188 .flags(total) 189 ; 190 191 statComLoads 192 .init(cpu->number_of_threads) 193 .name(name() + ".COM:loads") 194 .desc("Number of loads committed") 195 .flags(total) 196 ; 197 198 statComMembars 199 .init(cpu->number_of_threads) 200 .name(name() + ".COM:membars") 201 .desc("Number of memory barriers committed") 202 .flags(total) 203 ; 204 205 statComBranches 206 .init(cpu->number_of_threads) 207 .name(name() + ".COM:branches") 208 .desc("Number of branches committed") 209 .flags(total) 210 ; 211 212 commitEligible 213 .init(cpu->number_of_threads) 214 .name(name() + ".COM:bw_limited") 215 .desc("number of insts not committed due to BW limits") 216 .flags(total) 217 ; 218 219 commitEligibleSamples 220 .name(name() + ".COM:bw_lim_events") 221 .desc("number cycles where commit BW limit reached") 222 ; 223} 224 225template <class Impl> 226void 227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 228{ 229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 230 cpu = cpu_ptr; 231 232 // Commit must broadcast the number of free entries it has at the start of 233 // the simulation, so it starts as active. 234 cpu->activateStage(O3CPU::CommitIdx); 235 236 trapLatency = cpu->cycles(trapLatency); 237} 238 239template <class Impl> 240void 241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 242{ 243 thread = threads; 244} 245 246template <class Impl> 247void 248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 249{ 250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 251 timeBuffer = tb_ptr; 252 253 // Setup wire to send information back to IEW. 254 toIEW = timeBuffer->getWire(0); 255 256 // Setup wire to read data from IEW (for the ROB). 257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 258} 259 260template <class Impl> 261void 262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 263{ 264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 265 fetchQueue = fq_ptr; 266 267 // Setup wire to get instructions from rename (for the ROB). 268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 269} 270 271template <class Impl> 272void 273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 274{ 275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 276 renameQueue = rq_ptr; 277 278 // Setup wire to get instructions from rename (for the ROB). 279 fromRename = renameQueue->getWire(-renameToROBDelay); 280} 281 282template <class Impl> 283void 284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 285{ 286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 287 iewQueue = iq_ptr; 288 289 // Setup wire to get instructions from IEW. 290 fromIEW = iewQueue->getWire(-iewToCommitDelay); 291} 292 293template <class Impl> 294void 295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 296{ 297 iewStage = iew_stage; 298} 299 300template<class Impl> 301void 302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 303{ 304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 305 activeThreads = at_ptr; 306} 307 308template <class Impl> 309void 310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 311{ 312 DPRINTF(Commit, "Setting rename map pointers.\n"); 313 314 for (int i=0; i < numThreads; i++) { 315 renameMap[i] = &rm_ptr[i]; 316 } 317} 318 319template <class Impl> 320void 321DefaultCommit<Impl>::setROB(ROB *rob_ptr) 322{ 323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 324 rob = rob_ptr; 325} 326 327template <class Impl> 328void 329DefaultCommit<Impl>::initStage() 330{ 331 rob->setActiveThreads(activeThreads); 332 rob->resetEntries(); 333 334 // Broadcast the number of free entries. 335 for (int i=0; i < numThreads; i++) { 336 toIEW->commitInfo[i].usedROB = true; 337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 338 } 339 340 cpu->activityThisCycle(); 341} 342 343template <class Impl> 344bool 345DefaultCommit<Impl>::drain() 346{ 347 drainPending = true; 348 349 return false; 350} 351 352template <class Impl> 353void 354DefaultCommit<Impl>::switchOut() 355{ 356 switchedOut = true; 357 drainPending = false; 358 rob->switchOut(); 359} 360 361template <class Impl> 362void 363DefaultCommit<Impl>::resume() 364{ 365 drainPending = false; 366} 367 368template <class Impl> 369void 370DefaultCommit<Impl>::takeOverFrom() 371{ 372 switchedOut = false; 373 _status = Active; 374 _nextStatus = Inactive; 375 for (int i=0; i < numThreads; i++) { 376 commitStatus[i] = Idle; 377 changedROBNumEntries[i] = false; 378 trapSquash[i] = false; 379 tcSquash[i] = false; 380 } 381 squashCounter = 0; 382 rob->takeOverFrom(); 383} 384 385template <class Impl> 386void 387DefaultCommit<Impl>::updateStatus() 388{ 389 // reset ROB changed variable 390 std::list<unsigned>::iterator threads = activeThreads->begin(); 391 std::list<unsigned>::iterator end = activeThreads->end(); 392 393 while (threads != end) { 394 unsigned tid = *threads++; 395 396 changedROBNumEntries[tid] = false; 397 398 // Also check if any of the threads has a trap pending 399 if (commitStatus[tid] == TrapPending || 400 commitStatus[tid] == FetchTrapPending) { 401 _nextStatus = Active; 402 } 403 } 404 405 if (_nextStatus == Inactive && _status == Active) { 406 DPRINTF(Activity, "Deactivating stage.\n"); 407 cpu->deactivateStage(O3CPU::CommitIdx); 408 } else if (_nextStatus == Active && _status == Inactive) { 409 DPRINTF(Activity, "Activating stage.\n"); 410 cpu->activateStage(O3CPU::CommitIdx); 411 } 412 413 _status = _nextStatus; 414} 415 416template <class Impl> 417void 418DefaultCommit<Impl>::setNextStatus() 419{ 420 int squashes = 0; 421 422 std::list<unsigned>::iterator threads = activeThreads->begin(); 423 std::list<unsigned>::iterator end = activeThreads->end(); 424 425 while (threads != end) { 426 unsigned tid = *threads++; 427 428 if (commitStatus[tid] == ROBSquashing) { 429 squashes++; 430 } 431 } 432 433 squashCounter = squashes; 434 435 // If commit is currently squashing, then it will have activity for the 436 // next cycle. Set its next status as active. 437 if (squashCounter) { 438 _nextStatus = Active; 439 } 440} 441 442template <class Impl> 443bool 444DefaultCommit<Impl>::changedROBEntries() 445{ 446 std::list<unsigned>::iterator threads = activeThreads->begin(); 447 std::list<unsigned>::iterator end = activeThreads->end(); 448 449 while (threads != end) { 450 unsigned tid = *threads++; 451 452 if (changedROBNumEntries[tid]) { 453 return true; 454 } 455 } 456 457 return false; 458} 459 460template <class Impl> 461unsigned 462DefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 463{ 464 return rob->numFreeEntries(tid); 465} 466 467template <class Impl> 468void 469DefaultCommit<Impl>::generateTrapEvent(unsigned tid) 470{ 471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 472 473 TrapEvent *trap = new TrapEvent(this, tid); 474 475 trap->schedule(curTick + trapLatency); 476 477 thread[tid]->trapPending = true; 478} 479 480template <class Impl> 481void 482DefaultCommit<Impl>::generateTCEvent(unsigned tid) 483{ 484 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 485 486 tcSquash[tid] = true; 487} 488 489template <class Impl> 490void 491DefaultCommit<Impl>::squashAll(unsigned tid) 492{ 493 // If we want to include the squashing instruction in the squash, 494 // then use one older sequence number. 495 // Hopefully this doesn't mess things up. Basically I want to squash 496 // all instructions of this thread. 497 InstSeqNum squashed_inst = rob->isEmpty() ? 498 0 : rob->readHeadInst(tid)->seqNum - 1;; 499 500 // All younger instructions will be squashed. Set the sequence 501 // number as the youngest instruction in the ROB (0 in this case. 502 // Hopefully nothing breaks.) 503 youngestSeqNum[tid] = 0; 504 505 rob->squash(squashed_inst, tid); 506 changedROBNumEntries[tid] = true; 507 508 // Send back the sequence number of the squashed instruction. 509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 510 511 // Send back the squash signal to tell stages that they should 512 // squash. 513 toIEW->commitInfo[tid].squash = true; 514 515 // Send back the rob squashing signal so other stages know that 516 // the ROB is in the process of squashing. 517 toIEW->commitInfo[tid].robSquashing = true; 518 519 toIEW->commitInfo[tid].branchMispredict = false; 520 521 toIEW->commitInfo[tid].nextPC = PC[tid]; 522 toIEW->commitInfo[tid].nextNPC = nextPC[tid]; 523} 524 525template <class Impl> 526void 527DefaultCommit<Impl>::squashFromTrap(unsigned tid) 528{ 529 squashAll(tid); 530 531 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 532 533 thread[tid]->trapPending = false; 534 thread[tid]->inSyscall = false; 535 536 trapSquash[tid] = false; 537 538 commitStatus[tid] = ROBSquashing; 539 cpu->activityThisCycle(); 540} 541 542template <class Impl> 543void 544DefaultCommit<Impl>::squashFromTC(unsigned tid) 545{ 546 squashAll(tid); 547 548 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 549 550 thread[tid]->inSyscall = false; 551 assert(!thread[tid]->trapPending); 552 553 commitStatus[tid] = ROBSquashing; 554 cpu->activityThisCycle(); 555 556 tcSquash[tid] = false; 557} 558 559template <class Impl> 560void 561DefaultCommit<Impl>::tick() 562{ 563 wroteToTimeBuffer = false; 564 _nextStatus = Inactive; 565 566 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 567 cpu->signalDrained(); 568 drainPending = false; 569 return; 570 } 571 572 if (activeThreads->empty()) 573 return; 574 575 std::list<unsigned>::iterator threads = activeThreads->begin(); 576 std::list<unsigned>::iterator end = activeThreads->end(); 577 578 // Check if any of the threads are done squashing. Change the 579 // status if they are done. 580 while (threads != end) { 581 unsigned tid = *threads++; 582 583 if (commitStatus[tid] == ROBSquashing) { 584 585 if (rob->isDoneSquashing(tid)) { 586 commitStatus[tid] = Running; 587 } else { 588 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 589 " insts this cycle.\n", tid); 590 rob->doSquash(tid); 591 toIEW->commitInfo[tid].robSquashing = true; 592 wroteToTimeBuffer = true; 593 } 594 } 595 } 596 597 commit(); 598 599 markCompletedInsts(); 600 601 threads = activeThreads->begin(); 602 603 while (threads != end) { 604 unsigned tid = *threads++; 605 606 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 607 // The ROB has more instructions it can commit. Its next status 608 // will be active. 609 _nextStatus = Active; 610 611 DynInstPtr inst = rob->readHeadInst(tid); 612 613 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 614 " ROB and ready to commit\n", 615 tid, inst->seqNum, inst->readPC()); 616 617 } else if (!rob->isEmpty(tid)) { 618 DynInstPtr inst = rob->readHeadInst(tid); 619 620 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 621 "%#x is head of ROB and not ready\n", 622 tid, inst->seqNum, inst->readPC()); 623 } 624 625 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 626 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 627 } 628 629 630 if (wroteToTimeBuffer) { 631 DPRINTF(Activity, "Activity This Cycle.\n"); 632 cpu->activityThisCycle(); 633 } 634 635 updateStatus(); 636} 637 638template <class Impl> 639void 640DefaultCommit<Impl>::commit() 641{ 642 643 ////////////////////////////////////// 644 // Check for interrupts 645 ////////////////////////////////////// 646 647#if FULL_SYSTEM 648 if (interrupt != NoFault) { 649 // Wait until the ROB is empty and all stores have drained in 650 // order to enter the interrupt. 651 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 652 // Squash or record that I need to squash this cycle if 653 // an interrupt needed to be handled. 654 DPRINTF(Commit, "Interrupt detected.\n"); 655 656 assert(!thread[0]->inSyscall); 657 thread[0]->inSyscall = true; 658 659 // CPU will handle interrupt. 660 cpu->processInterrupts(interrupt); 661 662 thread[0]->inSyscall = false; 663 664 commitStatus[0] = TrapPending; 665 666 // Generate trap squash event. 667 generateTrapEvent(0); 668 669 // Clear the interrupt now that it's been handled 670 toIEW->commitInfo[0].clearInterrupt = true; 671 interrupt = NoFault; 672 } else { 673 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 674 } 675 } else if (cpu->check_interrupts(cpu->tcBase(0)) && 676 commitStatus[0] != TrapPending && 677 !trapSquash[0] && 678 !tcSquash[0]) { 679 // Process interrupts if interrupts are enabled, not in PAL 680 // mode, and no other traps or external squashes are currently 681 // pending. 682 // @todo: Allow other threads to handle interrupts. 683 684 // Get any interrupt that happened 685 interrupt = cpu->getInterrupts(); 686 687 if (interrupt != NoFault) { 688 // Tell fetch that there is an interrupt pending. This 689 // will make fetch wait until it sees a non PAL-mode PC, 690 // at which point it stops fetching instructions. 691 toIEW->commitInfo[0].interruptPending = true; 692 } 693 } 694 695#endif // FULL_SYSTEM 696 697 //////////////////////////////////// 698 // Check for any possible squashes, handle them first 699 //////////////////////////////////// 700 std::list<unsigned>::iterator threads = activeThreads->begin(); 701 std::list<unsigned>::iterator end = activeThreads->end(); 702 703 while (threads != end) { 704 unsigned tid = *threads++; 705 706 // Not sure which one takes priority. I think if we have 707 // both, that's a bad sign. 708 if (trapSquash[tid] == true) { 709 assert(!tcSquash[tid]); 710 squashFromTrap(tid); 711 } else if (tcSquash[tid] == true) { 712 squashFromTC(tid); 713 } 714 715 // Squashed sequence number must be older than youngest valid 716 // instruction in the ROB. This prevents squashes from younger 717 // instructions overriding squashes from older instructions. 718 if (fromIEW->squash[tid] && 719 commitStatus[tid] != TrapPending && 720 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 721 722 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 723 tid, 724 fromIEW->mispredPC[tid], 725 fromIEW->squashedSeqNum[tid]); 726 727 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 728 tid, 729 fromIEW->nextPC[tid]); 730 731 commitStatus[tid] = ROBSquashing; 732 733 // If we want to include the squashing instruction in the squash, 734 // then use one older sequence number. 735 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 736 737#if ISA_HAS_DELAY_SLOT 738 InstSeqNum bdelay_done_seq_num = squashed_inst; 739 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid]; 740 bool branchMispredict = fromIEW->branchMispredict[tid]; 741 742 // Squashing/not squashing the branch delay slot only makes 743 // sense when you're squashing from a branch, ie from a branch 744 // mispredict. 745 if (branchMispredict && !squash_bdelay_slot) { 746 bdelay_done_seq_num++; 747 } 748#endif 749 750 if (fromIEW->includeSquashInst[tid] == true) { 751 squashed_inst--; 752#if ISA_HAS_DELAY_SLOT 753 bdelay_done_seq_num--; 754#endif 755 } 756 // All younger instructions will be squashed. Set the sequence 757 // number as the youngest instruction in the ROB. 758 youngestSeqNum[tid] = squashed_inst; 759 760#if ISA_HAS_DELAY_SLOT 761 rob->squash(bdelay_done_seq_num, tid); 762 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 763 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 764#else 765 rob->squash(squashed_inst, tid); 766 toIEW->commitInfo[tid].squashDelaySlot = true; 767#endif 768 changedROBNumEntries[tid] = true; 769 770 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 771 772 toIEW->commitInfo[tid].squash = true; 773 774 // Send back the rob squashing signal so other stages know that 775 // the ROB is in the process of squashing. 776 toIEW->commitInfo[tid].robSquashing = true; 777 778 toIEW->commitInfo[tid].branchMispredict = 779 fromIEW->branchMispredict[tid]; 780 781 toIEW->commitInfo[tid].branchTaken = 782 fromIEW->branchTaken[tid]; 783 784 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 785 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid]; 786 787 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 788 789 if (toIEW->commitInfo[tid].branchMispredict) { 790 ++branchMispredicts; 791 } 792 } 793 794 } 795 796 setNextStatus(); 797 798 if (squashCounter != numThreads) { 799 // If we're not currently squashing, then get instructions. 800 getInsts(); 801 802 // Try to commit any instructions. 803 commitInsts(); 804 } else { 805#if ISA_HAS_DELAY_SLOT 806 skidInsert(); 807#endif 808 } 809 810 //Check for any activity 811 threads = activeThreads->begin(); 812 813 while (threads != end) { 814 unsigned tid = *threads++; 815 816 if (changedROBNumEntries[tid]) { 817 toIEW->commitInfo[tid].usedROB = true; 818 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 819 820 if (rob->isEmpty(tid)) { 821 toIEW->commitInfo[tid].emptyROB = true; 822 } 823 824 wroteToTimeBuffer = true; 825 changedROBNumEntries[tid] = false; 826 } 827 } 828} 829 830template <class Impl> 831void 832DefaultCommit<Impl>::commitInsts() 833{ 834 //////////////////////////////////// 835 // Handle commit 836 // Note that commit will be handled prior to putting new 837 // instructions in the ROB so that the ROB only tries to commit 838 // instructions it has in this current cycle, and not instructions 839 // it is writing in during this cycle. Can't commit and squash 840 // things at the same time... 841 //////////////////////////////////// 842 843 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 844 845 unsigned num_committed = 0; 846 847 DynInstPtr head_inst; 848 849 // Commit as many instructions as possible until the commit bandwidth 850 // limit is reached, or it becomes impossible to commit any more. 851 while (num_committed < commitWidth) { 852 int commit_thread = getCommittingThread(); 853 854 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 855 break; 856 857 head_inst = rob->readHeadInst(commit_thread); 858 859 int tid = head_inst->threadNumber; 860 861 assert(tid == commit_thread); 862 863 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 864 head_inst->seqNum, tid); 865 866 // If the head instruction is squashed, it is ready to retire 867 // (be removed from the ROB) at any time. 868 if (head_inst->isSquashed()) { 869 870 DPRINTF(Commit, "Retiring squashed instruction from " 871 "ROB.\n"); 872 873 rob->retireHead(commit_thread); 874 875 ++commitSquashedInsts; 876 877 // Record that the number of ROB entries has changed. 878 changedROBNumEntries[tid] = true; 879 } else { 880 PC[tid] = head_inst->readPC(); 881 nextPC[tid] = head_inst->readNextPC(); 882 nextNPC[tid] = head_inst->readNextNPC(); 883 884 // Increment the total number of non-speculative instructions 885 // executed. 886 // Hack for now: it really shouldn't happen until after the 887 // commit is deemed to be successful, but this count is needed 888 // for syscalls. 889 thread[tid]->funcExeInst++; 890 891 // Try to commit the head instruction. 892 bool commit_success = commitHead(head_inst, num_committed); 893 894 if (commit_success) { 895 ++num_committed; 896 897 changedROBNumEntries[tid] = true; 898 899 // Set the doneSeqNum to the youngest committed instruction. 900 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 901 902 ++commitCommittedInsts; 903 904 // To match the old model, don't count nops and instruction 905 // prefetches towards the total commit count. 906 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 907 cpu->instDone(tid); 908 } 909 910 PC[tid] = nextPC[tid]; 911#if ISA_HAS_DELAY_SLOT 912 nextPC[tid] = nextNPC[tid]; 913 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 914#else 915 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 916#endif 917 918#if FULL_SYSTEM 919 int count = 0; 920 Addr oldpc; 921 do { 922 // Debug statement. Checks to make sure we're not 923 // currently updating state while handling PC events. 924 if (count == 0) 925 assert(!thread[tid]->inSyscall && 926 !thread[tid]->trapPending); 927 oldpc = PC[tid]; 928 cpu->system->pcEventQueue.service( 929 thread[tid]->getTC()); 930 count++; 931 } while (oldpc != PC[tid]); 932 if (count > 1) { 933 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 934 break; 935 } 936#endif 937 } else { 938 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 939 "[tid:%i] [sn:%i].\n", 940 head_inst->readPC(), tid ,head_inst->seqNum); 941 break; 942 } 943 } 944 } 945 946 DPRINTF(CommitRate, "%i\n", num_committed); 947 numCommittedDist.sample(num_committed); 948 949 if (num_committed == commitWidth) { 950 commitEligibleSamples++; 951 } 952} 953 954template <class Impl> 955bool 956DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 957{ 958 assert(head_inst); 959 960 int tid = head_inst->threadNumber; 961 962 // If the instruction is not executed yet, then it will need extra 963 // handling. Signal backwards that it should be executed. 964 if (!head_inst->isExecuted()) { 965 // Keep this number correct. We have not yet actually executed 966 // and committed this instruction. 967 thread[tid]->funcExeInst--; 968 969 head_inst->setAtCommit(); 970 971 if (head_inst->isNonSpeculative() || 972 head_inst->isStoreConditional() || 973 head_inst->isMemBarrier() || 974 head_inst->isWriteBarrier()) { 975 976 DPRINTF(Commit, "Encountered a barrier or non-speculative " 977 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 978 head_inst->seqNum, head_inst->readPC()); 979 980 // Hack to make sure syscalls/memory barriers/quiesces 981 // aren't executed until all stores write back their data. 982 // This direct communication shouldn't be used for 983 // anything other than this. 984 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 985 head_inst->isQuiesce()) && 986 iewStage->hasStoresToWB()) 987 { 988 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 989 return false; 990 } else if (inst_num > 0 || iewStage->hasStoresToWB()) { 991 DPRINTF(Commit, "Waiting to become head of commit.\n"); 992 return false; 993 } 994 995 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 996 997 // Change the instruction so it won't try to commit again until 998 // it is executed. 999 head_inst->clearCanCommit(); 1000 1001 ++commitNonSpecStalls; 1002 1003 return false; 1004 } else if (head_inst->isLoad()) { 1005 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 1006 head_inst->seqNum, head_inst->readPC()); 1007 1008 // Send back the non-speculative instruction's sequence 1009 // number. Tell the lsq to re-execute the load. 1010 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1011 toIEW->commitInfo[tid].uncached = true; 1012 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1013 1014 head_inst->clearCanCommit(); 1015 1016 return false; 1017 } else { 1018 panic("Trying to commit un-executed instruction " 1019 "of unknown type!\n"); 1020 } 1021 } 1022 1023 if (head_inst->isThreadSync()) { 1024 // Not handled for now. 1025 panic("Thread sync instructions are not handled yet.\n"); 1026 } 1027 1028 // Stores mark themselves as completed. 1029 if (!head_inst->isStore()) { 1030 head_inst->setCompleted(); 1031 } 1032 1033#if USE_CHECKER 1034 // Use checker prior to updating anything due to traps or PC 1035 // based events. 1036 if (cpu->checker) { 1037 cpu->checker->verify(head_inst); 1038 } 1039#endif 1040 1041 // Check if the instruction caused a fault. If so, trap. 1042 Fault inst_fault = head_inst->getFault(); 1043 1044 // DTB will sometimes need the machine instruction for when 1045 // faults happen. So we will set it here, prior to the DTB 1046 // possibly needing it for its fault. 1047 thread[tid]->setInst( 1048 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1049 1050 if (inst_fault != NoFault) { 1051 head_inst->setCompleted(); 1052 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1053 head_inst->seqNum, head_inst->readPC()); 1054 1055 if (iewStage->hasStoresToWB() || inst_num > 0) { 1056 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1057 return false; 1058 } 1059 1060#if USE_CHECKER 1061 if (cpu->checker && head_inst->isStore()) { 1062 cpu->checker->verify(head_inst); 1063 } 1064#endif 1065 1066 assert(!thread[tid]->inSyscall); 1067 1068 // Mark that we're in state update mode so that the trap's 1069 // execution doesn't generate extra squashes. 1070 thread[tid]->inSyscall = true; 1071 1072 // Execute the trap. Although it's slightly unrealistic in 1073 // terms of timing (as it doesn't wait for the full timing of 1074 // the trap event to complete before updating state), it's 1075 // needed to update the state as soon as possible. This 1076 // prevents external agents from changing any specific state 1077 // that the trap need. 1078 cpu->trap(inst_fault, tid); 1079 1080 // Exit state update mode to avoid accidental updating. 1081 thread[tid]->inSyscall = false; 1082 1083 commitStatus[tid] = TrapPending; 1084 1085 // Generate trap squash event. 1086 generateTrapEvent(tid); 1087// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 1088 return false; 1089 } 1090 1091 updateComInstStats(head_inst); 1092 1093#if FULL_SYSTEM 1094 if (thread[tid]->profile) { 1095// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 1096// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 1097 thread[tid]->profilePC = head_inst->readPC(); 1098 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1099 head_inst->staticInst); 1100 1101 if (node) 1102 thread[tid]->profileNode = node; 1103 } 1104#endif 1105 1106 if (head_inst->traceData) { 1107 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1108 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1109 head_inst->traceData->finalize(); 1110 head_inst->traceData = NULL; 1111 } 1112 1113 // Update the commit rename map 1114 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1115 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1116 head_inst->renamedDestRegIdx(i)); 1117 } 1118 1119 if (head_inst->isCopy()) 1120 panic("Should not commit any copy instructions!"); 1121 1122 // Finally clear the head ROB entry. 1123 rob->retireHead(tid); 1124 1125 // Return true to indicate that we have committed an instruction. 1126 return true; 1127} 1128 1129template <class Impl> 1130void 1131DefaultCommit<Impl>::getInsts() 1132{ 1133 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1134 1135#if ISA_HAS_DELAY_SLOT 1136 // Read any renamed instructions and place them into the ROB. 1137 int insts_to_process = std::min((int)renameWidth, 1138 (int)(fromRename->size + skidBuffer.size())); 1139 int rename_idx = 0; 1140 1141 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 1142 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 1143 skidBuffer.size()); 1144#else 1145 // Read any renamed instructions and place them into the ROB. 1146 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1147#endif 1148 1149 1150 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1151 DynInstPtr inst; 1152 1153#if ISA_HAS_DELAY_SLOT 1154 // Get insts from skidBuffer or from Rename 1155 if (skidBuffer.size() > 0) { 1156 DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 1157 inst = skidBuffer.front(); 1158 skidBuffer.pop(); 1159 } else { 1160 DPRINTF(Commit, "Grabbing rename inst.\n"); 1161 inst = fromRename->insts[rename_idx++]; 1162 } 1163#else 1164 inst = fromRename->insts[inst_num]; 1165#endif 1166 int tid = inst->threadNumber; 1167 1168 if (!inst->isSquashed() && 1169 commitStatus[tid] != ROBSquashing) { 1170 changedROBNumEntries[tid] = true; 1171 1172 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1173 inst->readPC(), inst->seqNum, tid); 1174 1175 rob->insertInst(inst); 1176 1177 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1178 1179 youngestSeqNum[tid] = inst->seqNum; 1180 } else { 1181 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1182 "squashed, skipping.\n", 1183 inst->readPC(), inst->seqNum, tid); 1184 } 1185 } 1186 1187#if ISA_HAS_DELAY_SLOT 1188 if (rename_idx < fromRename->size) { 1189 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 1190 1191 for (; 1192 rename_idx < fromRename->size; 1193 rename_idx++) { 1194 DynInstPtr inst = fromRename->insts[rename_idx]; 1195 1196 if (!inst->isSquashed()) { 1197 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1198 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1199 inst->threadNumber); 1200 skidBuffer.push(inst); 1201 } else { 1202 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1203 "squashed, skipping.\n", 1204 inst->readPC(), inst->seqNum, inst->threadNumber); 1205 } 1206 } 1207 } 1208#endif 1209 1210} 1211 1212template <class Impl> 1213void 1214DefaultCommit<Impl>::skidInsert() 1215{ 1216 DPRINTF(Commit, "Attempting to any instructions from rename into " 1217 "skidBuffer.\n"); 1218 1219 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1220 DynInstPtr inst = fromRename->insts[inst_num]; 1221 1222 if (!inst->isSquashed()) { 1223 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1224 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1225 inst->threadNumber); 1226 skidBuffer.push(inst); 1227 } else { 1228 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1229 "squashed, skipping.\n", 1230 inst->readPC(), inst->seqNum, inst->threadNumber); 1231 } 1232 } 1233} 1234 1235template <class Impl> 1236void 1237DefaultCommit<Impl>::markCompletedInsts() 1238{ 1239 // Grab completed insts out of the IEW instruction queue, and mark 1240 // instructions completed within the ROB. 1241 for (int inst_num = 0; 1242 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1243 ++inst_num) 1244 { 1245 if (!fromIEW->insts[inst_num]->isSquashed()) { 1246 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1247 "within ROB.\n", 1248 fromIEW->insts[inst_num]->threadNumber, 1249 fromIEW->insts[inst_num]->readPC(), 1250 fromIEW->insts[inst_num]->seqNum); 1251 1252 // Mark the instruction as ready to commit. 1253 fromIEW->insts[inst_num]->setCanCommit(); 1254 } 1255 } 1256} 1257 1258template <class Impl> 1259bool 1260DefaultCommit<Impl>::robDoneSquashing() 1261{ 1262 std::list<unsigned>::iterator threads = activeThreads->begin(); 1263 std::list<unsigned>::iterator end = activeThreads->end(); 1264 1265 while (threads != end) { 1266 unsigned tid = *threads++; 1267 1268 if (!rob->isDoneSquashing(tid)) 1269 return false; 1270 } 1271 1272 return true; 1273} 1274 1275template <class Impl> 1276void 1277DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1278{ 1279 unsigned thread = inst->threadNumber; 1280 1281 // 1282 // Pick off the software prefetches 1283 // 1284#ifdef TARGET_ALPHA 1285 if (inst->isDataPrefetch()) { 1286 statComSwp[thread]++; 1287 } else { 1288 statComInst[thread]++; 1289 } 1290#else 1291 statComInst[thread]++; 1292#endif 1293 1294 // 1295 // Control Instructions 1296 // 1297 if (inst->isControl()) 1298 statComBranches[thread]++; 1299 1300 // 1301 // Memory references 1302 // 1303 if (inst->isMemRef()) { 1304 statComRefs[thread]++; 1305 1306 if (inst->isLoad()) { 1307 statComLoads[thread]++; 1308 } 1309 } 1310 1311 if (inst->isMemBarrier()) { 1312 statComMembars[thread]++; 1313 } 1314} 1315 1316//////////////////////////////////////// 1317// // 1318// SMT COMMIT POLICY MAINTAINED HERE // 1319// // 1320//////////////////////////////////////// 1321template <class Impl> 1322int 1323DefaultCommit<Impl>::getCommittingThread() 1324{ 1325 if (numThreads > 1) { 1326 switch (commitPolicy) { 1327 1328 case Aggressive: 1329 //If Policy is Aggressive, commit will call 1330 //this function multiple times per 1331 //cycle 1332 return oldestReady(); 1333 1334 case RoundRobin: 1335 return roundRobin(); 1336 1337 case OldestReady: 1338 return oldestReady(); 1339 1340 default: 1341 return -1; 1342 } 1343 } else { 1344 assert(!activeThreads->empty()); 1345 int tid = activeThreads->front(); 1346 1347 if (commitStatus[tid] == Running || 1348 commitStatus[tid] == Idle || 1349 commitStatus[tid] == FetchTrapPending) { 1350 return tid; 1351 } else { 1352 return -1; 1353 } 1354 } 1355} 1356 1357template<class Impl> 1358int 1359DefaultCommit<Impl>::roundRobin() 1360{ 1361 std::list<unsigned>::iterator pri_iter = priority_list.begin(); 1362 std::list<unsigned>::iterator end = priority_list.end(); 1363 1364 while (pri_iter != end) { 1365 unsigned tid = *pri_iter; 1366 1367 if (commitStatus[tid] == Running || 1368 commitStatus[tid] == Idle || 1369 commitStatus[tid] == FetchTrapPending) { 1370 1371 if (rob->isHeadReady(tid)) { 1372 priority_list.erase(pri_iter); 1373 priority_list.push_back(tid); 1374 1375 return tid; 1376 } 1377 } 1378 1379 pri_iter++; 1380 } 1381 1382 return -1; 1383} 1384 1385template<class Impl> 1386int 1387DefaultCommit<Impl>::oldestReady() 1388{ 1389 unsigned oldest = 0; 1390 bool first = true; 1391 1392 std::list<unsigned>::iterator threads = activeThreads->begin(); 1393 std::list<unsigned>::iterator end = activeThreads->end(); 1394 1395 while (threads != end) { 1396 unsigned tid = *threads++; 1397 1398 if (!rob->isEmpty(tid) && 1399 (commitStatus[tid] == Running || 1400 commitStatus[tid] == Idle || 1401 commitStatus[tid] == FetchTrapPending)) { 1402 1403 if (rob->isHeadReady(tid)) { 1404 1405 DynInstPtr head_inst = rob->readHeadInst(tid); 1406 1407 if (first) { 1408 oldest = tid; 1409 first = false; 1410 } else if (head_inst->seqNum < oldest) { 1411 oldest = tid; 1412 } 1413 } 1414 } 1415 } 1416 1417 if (!first) { 1418 return oldest; 1419 } else { 1420 return -1; 1421 } 1422} 1423