commit_impl.hh revision 3634:7e9abbddf9da
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/full_system.hh" 33#include "config/use_checker.hh" 34 35#include <algorithm> 36#include <string> 37 38#include "arch/utility.hh" 39#include "base/loader/symtab.hh" 40#include "base/timebuf.hh" 41#include "cpu/exetrace.hh" 42#include "cpu/o3/commit.hh" 43#include "cpu/o3/thread_state.hh" 44 45#if USE_CHECKER 46#include "cpu/checker/cpu.hh" 47#endif 48 49template <class Impl> 50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 51 unsigned _tid) 52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 53{ 54 this->setFlags(Event::AutoDelete); 55} 56 57template <class Impl> 58void 59DefaultCommit<Impl>::TrapEvent::process() 60{ 61 // This will get reset by commit if it was switched out at the 62 // time of this event processing. 63 commit->trapSquash[tid] = true; 64} 65 66template <class Impl> 67const char * 68DefaultCommit<Impl>::TrapEvent::description() 69{ 70 return "Trap event"; 71} 72 73template <class Impl> 74DefaultCommit<Impl>::DefaultCommit(Params *params) 75 : squashCounter(0), 76 iewToCommitDelay(params->iewToCommitDelay), 77 commitToIEWDelay(params->commitToIEWDelay), 78 renameToROBDelay(params->renameToROBDelay), 79 fetchToCommitDelay(params->commitToFetchDelay), 80 renameWidth(params->renameWidth), 81 commitWidth(params->commitWidth), 82 numThreads(params->numberOfThreads), 83 drainPending(false), 84 switchedOut(false), 85 trapLatency(params->trapLatency) 86{ 87 _status = Active; 88 _nextStatus = Inactive; 89 std::string policy = params->smtCommitPolicy; 90 91 //Convert string to lowercase 92 std::transform(policy.begin(), policy.end(), policy.begin(), 93 (int(*)(int)) tolower); 94 95 //Assign commit policy 96 if (policy == "aggressive"){ 97 commitPolicy = Aggressive; 98 99 DPRINTF(Commit,"Commit Policy set to Aggressive."); 100 } else if (policy == "roundrobin"){ 101 commitPolicy = RoundRobin; 102 103 //Set-Up Priority List 104 for (int tid=0; tid < numThreads; tid++) { 105 priority_list.push_back(tid); 106 } 107 108 DPRINTF(Commit,"Commit Policy set to Round Robin."); 109 } else if (policy == "oldestready"){ 110 commitPolicy = OldestReady; 111 112 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 113 } else { 114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 115 "RoundRobin,OldestReady}"); 116 } 117 118 for (int i=0; i < numThreads; i++) { 119 commitStatus[i] = Idle; 120 changedROBNumEntries[i] = false; 121 trapSquash[i] = false; 122 tcSquash[i] = false; 123 PC[i] = nextPC[i] = nextNPC[i] = 0; 124 } 125} 126 127template <class Impl> 128std::string 129DefaultCommit<Impl>::name() const 130{ 131 return cpu->name() + ".commit"; 132} 133 134template <class Impl> 135void 136DefaultCommit<Impl>::regStats() 137{ 138 using namespace Stats; 139 commitCommittedInsts 140 .name(name() + ".commitCommittedInsts") 141 .desc("The number of committed instructions") 142 .prereq(commitCommittedInsts); 143 commitSquashedInsts 144 .name(name() + ".commitSquashedInsts") 145 .desc("The number of squashed insts skipped by commit") 146 .prereq(commitSquashedInsts); 147 commitSquashEvents 148 .name(name() + ".commitSquashEvents") 149 .desc("The number of times commit is told to squash") 150 .prereq(commitSquashEvents); 151 commitNonSpecStalls 152 .name(name() + ".commitNonSpecStalls") 153 .desc("The number of times commit has been forced to stall to " 154 "communicate backwards") 155 .prereq(commitNonSpecStalls); 156 branchMispredicts 157 .name(name() + ".branchMispredicts") 158 .desc("The number of times a branch was mispredicted") 159 .prereq(branchMispredicts); 160 numCommittedDist 161 .init(0,commitWidth,1) 162 .name(name() + ".COM:committed_per_cycle") 163 .desc("Number of insts commited each cycle") 164 .flags(Stats::pdf) 165 ; 166 167 statComInst 168 .init(cpu->number_of_threads) 169 .name(name() + ".COM:count") 170 .desc("Number of instructions committed") 171 .flags(total) 172 ; 173 174 statComSwp 175 .init(cpu->number_of_threads) 176 .name(name() + ".COM:swp_count") 177 .desc("Number of s/w prefetches committed") 178 .flags(total) 179 ; 180 181 statComRefs 182 .init(cpu->number_of_threads) 183 .name(name() + ".COM:refs") 184 .desc("Number of memory references committed") 185 .flags(total) 186 ; 187 188 statComLoads 189 .init(cpu->number_of_threads) 190 .name(name() + ".COM:loads") 191 .desc("Number of loads committed") 192 .flags(total) 193 ; 194 195 statComMembars 196 .init(cpu->number_of_threads) 197 .name(name() + ".COM:membars") 198 .desc("Number of memory barriers committed") 199 .flags(total) 200 ; 201 202 statComBranches 203 .init(cpu->number_of_threads) 204 .name(name() + ".COM:branches") 205 .desc("Number of branches committed") 206 .flags(total) 207 ; 208 209 commitEligible 210 .init(cpu->number_of_threads) 211 .name(name() + ".COM:bw_limited") 212 .desc("number of insts not committed due to BW limits") 213 .flags(total) 214 ; 215 216 commitEligibleSamples 217 .name(name() + ".COM:bw_lim_events") 218 .desc("number cycles where commit BW limit reached") 219 ; 220} 221 222template <class Impl> 223void 224DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 225{ 226 DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 227 cpu = cpu_ptr; 228 229 // Commit must broadcast the number of free entries it has at the start of 230 // the simulation, so it starts as active. 231 cpu->activateStage(O3CPU::CommitIdx); 232 233 trapLatency = cpu->cycles(trapLatency); 234} 235 236template <class Impl> 237void 238DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 239{ 240 thread = threads; 241} 242 243template <class Impl> 244void 245DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 246{ 247 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 248 timeBuffer = tb_ptr; 249 250 // Setup wire to send information back to IEW. 251 toIEW = timeBuffer->getWire(0); 252 253 // Setup wire to read data from IEW (for the ROB). 254 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 255} 256 257template <class Impl> 258void 259DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 260{ 261 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 262 fetchQueue = fq_ptr; 263 264 // Setup wire to get instructions from rename (for the ROB). 265 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 266} 267 268template <class Impl> 269void 270DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 271{ 272 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 273 renameQueue = rq_ptr; 274 275 // Setup wire to get instructions from rename (for the ROB). 276 fromRename = renameQueue->getWire(-renameToROBDelay); 277} 278 279template <class Impl> 280void 281DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 282{ 283 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 284 iewQueue = iq_ptr; 285 286 // Setup wire to get instructions from IEW. 287 fromIEW = iewQueue->getWire(-iewToCommitDelay); 288} 289 290template <class Impl> 291void 292DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 293{ 294 iewStage = iew_stage; 295} 296 297template<class Impl> 298void 299DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 300{ 301 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 302 activeThreads = at_ptr; 303} 304 305template <class Impl> 306void 307DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 308{ 309 DPRINTF(Commit, "Setting rename map pointers.\n"); 310 311 for (int i=0; i < numThreads; i++) { 312 renameMap[i] = &rm_ptr[i]; 313 } 314} 315 316template <class Impl> 317void 318DefaultCommit<Impl>::setROB(ROB *rob_ptr) 319{ 320 DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 321 rob = rob_ptr; 322} 323 324template <class Impl> 325void 326DefaultCommit<Impl>::initStage() 327{ 328 rob->setActiveThreads(activeThreads); 329 rob->resetEntries(); 330 331 // Broadcast the number of free entries. 332 for (int i=0; i < numThreads; i++) { 333 toIEW->commitInfo[i].usedROB = true; 334 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 335 } 336 337 cpu->activityThisCycle(); 338} 339 340template <class Impl> 341bool 342DefaultCommit<Impl>::drain() 343{ 344 drainPending = true; 345 346 return false; 347} 348 349template <class Impl> 350void 351DefaultCommit<Impl>::switchOut() 352{ 353 switchedOut = true; 354 drainPending = false; 355 rob->switchOut(); 356} 357 358template <class Impl> 359void 360DefaultCommit<Impl>::resume() 361{ 362 drainPending = false; 363} 364 365template <class Impl> 366void 367DefaultCommit<Impl>::takeOverFrom() 368{ 369 switchedOut = false; 370 _status = Active; 371 _nextStatus = Inactive; 372 for (int i=0; i < numThreads; i++) { 373 commitStatus[i] = Idle; 374 changedROBNumEntries[i] = false; 375 trapSquash[i] = false; 376 tcSquash[i] = false; 377 } 378 squashCounter = 0; 379 rob->takeOverFrom(); 380} 381 382template <class Impl> 383void 384DefaultCommit<Impl>::updateStatus() 385{ 386 // reset ROB changed variable 387 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 388 while (threads != (*activeThreads).end()) { 389 unsigned tid = *threads++; 390 changedROBNumEntries[tid] = false; 391 392 // Also check if any of the threads has a trap pending 393 if (commitStatus[tid] == TrapPending || 394 commitStatus[tid] == FetchTrapPending) { 395 _nextStatus = Active; 396 } 397 } 398 399 if (_nextStatus == Inactive && _status == Active) { 400 DPRINTF(Activity, "Deactivating stage.\n"); 401 cpu->deactivateStage(O3CPU::CommitIdx); 402 } else if (_nextStatus == Active && _status == Inactive) { 403 DPRINTF(Activity, "Activating stage.\n"); 404 cpu->activateStage(O3CPU::CommitIdx); 405 } 406 407 _status = _nextStatus; 408} 409 410template <class Impl> 411void 412DefaultCommit<Impl>::setNextStatus() 413{ 414 int squashes = 0; 415 416 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 417 418 while (threads != (*activeThreads).end()) { 419 unsigned tid = *threads++; 420 421 if (commitStatus[tid] == ROBSquashing) { 422 squashes++; 423 } 424 } 425 426 squashCounter = squashes; 427 428 // If commit is currently squashing, then it will have activity for the 429 // next cycle. Set its next status as active. 430 if (squashCounter) { 431 _nextStatus = Active; 432 } 433} 434 435template <class Impl> 436bool 437DefaultCommit<Impl>::changedROBEntries() 438{ 439 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 440 441 while (threads != (*activeThreads).end()) { 442 unsigned tid = *threads++; 443 444 if (changedROBNumEntries[tid]) { 445 return true; 446 } 447 } 448 449 return false; 450} 451 452template <class Impl> 453unsigned 454DefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 455{ 456 return rob->numFreeEntries(tid); 457} 458 459template <class Impl> 460void 461DefaultCommit<Impl>::generateTrapEvent(unsigned tid) 462{ 463 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 464 465 TrapEvent *trap = new TrapEvent(this, tid); 466 467 trap->schedule(curTick + trapLatency); 468 469 thread[tid]->trapPending = true; 470} 471 472template <class Impl> 473void 474DefaultCommit<Impl>::generateTCEvent(unsigned tid) 475{ 476 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 477 478 tcSquash[tid] = true; 479} 480 481template <class Impl> 482void 483DefaultCommit<Impl>::squashAll(unsigned tid) 484{ 485 // If we want to include the squashing instruction in the squash, 486 // then use one older sequence number. 487 // Hopefully this doesn't mess things up. Basically I want to squash 488 // all instructions of this thread. 489 InstSeqNum squashed_inst = rob->isEmpty() ? 490 0 : rob->readHeadInst(tid)->seqNum - 1;; 491 492 // All younger instructions will be squashed. Set the sequence 493 // number as the youngest instruction in the ROB (0 in this case. 494 // Hopefully nothing breaks.) 495 youngestSeqNum[tid] = 0; 496 497 rob->squash(squashed_inst, tid); 498 changedROBNumEntries[tid] = true; 499 500 // Send back the sequence number of the squashed instruction. 501 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 502 503 // Send back the squash signal to tell stages that they should 504 // squash. 505 toIEW->commitInfo[tid].squash = true; 506 507 // Send back the rob squashing signal so other stages know that 508 // the ROB is in the process of squashing. 509 toIEW->commitInfo[tid].robSquashing = true; 510 511 toIEW->commitInfo[tid].branchMispredict = false; 512 513 toIEW->commitInfo[tid].nextPC = PC[tid]; 514} 515 516template <class Impl> 517void 518DefaultCommit<Impl>::squashFromTrap(unsigned tid) 519{ 520 squashAll(tid); 521 522 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 523 524 thread[tid]->trapPending = false; 525 thread[tid]->inSyscall = false; 526 527 trapSquash[tid] = false; 528 529 commitStatus[tid] = ROBSquashing; 530 cpu->activityThisCycle(); 531} 532 533template <class Impl> 534void 535DefaultCommit<Impl>::squashFromTC(unsigned tid) 536{ 537 squashAll(tid); 538 539 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 540 541 thread[tid]->inSyscall = false; 542 assert(!thread[tid]->trapPending); 543 544 commitStatus[tid] = ROBSquashing; 545 cpu->activityThisCycle(); 546 547 tcSquash[tid] = false; 548} 549 550template <class Impl> 551void 552DefaultCommit<Impl>::tick() 553{ 554 wroteToTimeBuffer = false; 555 _nextStatus = Inactive; 556 557 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 558 cpu->signalDrained(); 559 drainPending = false; 560 return; 561 } 562 563 if ((*activeThreads).size() <= 0) 564 return; 565 566 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 567 568 // Check if any of the threads are done squashing. Change the 569 // status if they are done. 570 while (threads != (*activeThreads).end()) { 571 unsigned tid = *threads++; 572 573 if (commitStatus[tid] == ROBSquashing) { 574 575 if (rob->isDoneSquashing(tid)) { 576 commitStatus[tid] = Running; 577 } else { 578 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 579 " insts this cycle.\n", tid); 580 rob->doSquash(tid); 581 toIEW->commitInfo[tid].robSquashing = true; 582 wroteToTimeBuffer = true; 583 } 584 } 585 } 586 587 commit(); 588 589 markCompletedInsts(); 590 591 threads = (*activeThreads).begin(); 592 593 while (threads != (*activeThreads).end()) { 594 unsigned tid = *threads++; 595 596 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 597 // The ROB has more instructions it can commit. Its next status 598 // will be active. 599 _nextStatus = Active; 600 601 DynInstPtr inst = rob->readHeadInst(tid); 602 603 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 604 " ROB and ready to commit\n", 605 tid, inst->seqNum, inst->readPC()); 606 607 } else if (!rob->isEmpty(tid)) { 608 DynInstPtr inst = rob->readHeadInst(tid); 609 610 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 611 "%#x is head of ROB and not ready\n", 612 tid, inst->seqNum, inst->readPC()); 613 } 614 615 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 616 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 617 } 618 619 620 if (wroteToTimeBuffer) { 621 DPRINTF(Activity, "Activity This Cycle.\n"); 622 cpu->activityThisCycle(); 623 } 624 625 updateStatus(); 626} 627 628template <class Impl> 629void 630DefaultCommit<Impl>::commit() 631{ 632 633 ////////////////////////////////////// 634 // Check for interrupts 635 ////////////////////////////////////// 636 637#if FULL_SYSTEM 638 // Process interrupts if interrupts are enabled, not in PAL mode, 639 // and no other traps or external squashes are currently pending. 640 // @todo: Allow other threads to handle interrupts. 641 if (cpu->checkInterrupts && 642 cpu->check_interrupts(cpu->tcBase(0)) && 643 commitStatus[0] != TrapPending && 644 !trapSquash[0] && 645 !tcSquash[0]) { 646 647 // Get any interrupt that happened 648 Fault intr = cpu->getInterrupts(); 649 650 // Exit this if block if there's no fault. 651 if (intr == NoFault) { 652 goto commit_insts; 653 } 654 655 // Tell fetch that there is an interrupt pending. This will 656 // make fetch wait until it sees a non PAL-mode PC, at which 657 // point it stops fetching instructions. 658 toIEW->commitInfo[0].interruptPending = true; 659 660 // Wait until the ROB is empty and all stores have drained in 661 // order to enter the interrupt. 662 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 663 // Squash or record that I need to squash this cycle if 664 // an interrupt needed to be handled. 665 DPRINTF(Commit, "Interrupt detected.\n"); 666 667 assert(!thread[0]->inSyscall); 668 thread[0]->inSyscall = true; 669 670 // CPU will handle interrupt. 671 cpu->processInterrupts(intr); 672 673 thread[0]->inSyscall = false; 674 675 commitStatus[0] = TrapPending; 676 677 // Generate trap squash event. 678 generateTrapEvent(0); 679 680 toIEW->commitInfo[0].clearInterrupt = true; 681 } else { 682 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 683 } 684 } 685 686 // Label for goto. Not pretty but more readable than really big 687 // if statement above. 688 commit_insts: 689#endif // FULL_SYSTEM 690 691 //////////////////////////////////// 692 // Check for any possible squashes, handle them first 693 //////////////////////////////////// 694 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 695 696 while (threads != (*activeThreads).end()) { 697 unsigned tid = *threads++; 698 699 // Not sure which one takes priority. I think if we have 700 // both, that's a bad sign. 701 if (trapSquash[tid] == true) { 702 assert(!tcSquash[tid]); 703 squashFromTrap(tid); 704 } else if (tcSquash[tid] == true) { 705 squashFromTC(tid); 706 } 707 708 // Squashed sequence number must be older than youngest valid 709 // instruction in the ROB. This prevents squashes from younger 710 // instructions overriding squashes from older instructions. 711 if (fromIEW->squash[tid] && 712 commitStatus[tid] != TrapPending && 713 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 714 715 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 716 tid, 717 fromIEW->mispredPC[tid], 718 fromIEW->squashedSeqNum[tid]); 719 720 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 721 tid, 722 fromIEW->nextPC[tid]); 723 724 commitStatus[tid] = ROBSquashing; 725 726 // If we want to include the squashing instruction in the squash, 727 // then use one older sequence number. 728 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 729 730#if ISA_HAS_DELAY_SLOT 731 InstSeqNum bdelay_done_seq_num; 732 bool squash_bdelay_slot; 733 734 if (fromIEW->branchMispredict[tid]) { 735 if (fromIEW->branchTaken[tid] && 736 fromIEW->condDelaySlotBranch[tid]) { 737 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch" 738 "mispredicted as taken. Squashing after previous " 739 "inst, [sn:%i]\n", 740 tid, squashed_inst); 741 bdelay_done_seq_num = squashed_inst; 742 squash_bdelay_slot = true; 743 } else { 744 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing " 745 "after delay slot [sn:%i]\n", tid, squashed_inst+1); 746 bdelay_done_seq_num = squashed_inst + 1; 747 squash_bdelay_slot = false; 748 } 749 } else { 750 bdelay_done_seq_num = squashed_inst; 751 } 752#endif 753 754 if (fromIEW->includeSquashInst[tid] == true) { 755 squashed_inst--; 756#if ISA_HAS_DELAY_SLOT 757 bdelay_done_seq_num--; 758#endif 759 } 760 // All younger instructions will be squashed. Set the sequence 761 // number as the youngest instruction in the ROB. 762 youngestSeqNum[tid] = squashed_inst; 763 764#if ISA_HAS_DELAY_SLOT 765 rob->squash(bdelay_done_seq_num, tid); 766 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 767 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 768#else 769 rob->squash(squashed_inst, tid); 770 toIEW->commitInfo[tid].squashDelaySlot = true; 771#endif 772 changedROBNumEntries[tid] = true; 773 774 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 775 776 toIEW->commitInfo[tid].squash = true; 777 778 // Send back the rob squashing signal so other stages know that 779 // the ROB is in the process of squashing. 780 toIEW->commitInfo[tid].robSquashing = true; 781 782 toIEW->commitInfo[tid].branchMispredict = 783 fromIEW->branchMispredict[tid]; 784 785 toIEW->commitInfo[tid].branchTaken = 786 fromIEW->branchTaken[tid]; 787 788 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 789 790 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 791 792 if (toIEW->commitInfo[tid].branchMispredict) { 793 ++branchMispredicts; 794 } 795 } 796 797 } 798 799 setNextStatus(); 800 801 if (squashCounter != numThreads) { 802 // If we're not currently squashing, then get instructions. 803 getInsts(); 804 805 // Try to commit any instructions. 806 commitInsts(); 807 } else { 808#if ISA_HAS_DELAY_SLOT 809 skidInsert(); 810#endif 811 } 812 813 //Check for any activity 814 threads = (*activeThreads).begin(); 815 816 while (threads != (*activeThreads).end()) { 817 unsigned tid = *threads++; 818 819 if (changedROBNumEntries[tid]) { 820 toIEW->commitInfo[tid].usedROB = true; 821 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 822 823 if (rob->isEmpty(tid)) { 824 toIEW->commitInfo[tid].emptyROB = true; 825 } 826 827 wroteToTimeBuffer = true; 828 changedROBNumEntries[tid] = false; 829 } 830 } 831} 832 833template <class Impl> 834void 835DefaultCommit<Impl>::commitInsts() 836{ 837 //////////////////////////////////// 838 // Handle commit 839 // Note that commit will be handled prior to putting new 840 // instructions in the ROB so that the ROB only tries to commit 841 // instructions it has in this current cycle, and not instructions 842 // it is writing in during this cycle. Can't commit and squash 843 // things at the same time... 844 //////////////////////////////////// 845 846 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 847 848 unsigned num_committed = 0; 849 850 DynInstPtr head_inst; 851 852 // Commit as many instructions as possible until the commit bandwidth 853 // limit is reached, or it becomes impossible to commit any more. 854 while (num_committed < commitWidth) { 855 int commit_thread = getCommittingThread(); 856 857 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 858 break; 859 860 head_inst = rob->readHeadInst(commit_thread); 861 862 int tid = head_inst->threadNumber; 863 864 assert(tid == commit_thread); 865 866 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 867 head_inst->seqNum, tid); 868 869 // If the head instruction is squashed, it is ready to retire 870 // (be removed from the ROB) at any time. 871 if (head_inst->isSquashed()) { 872 873 DPRINTF(Commit, "Retiring squashed instruction from " 874 "ROB.\n"); 875 876 rob->retireHead(commit_thread); 877 878 ++commitSquashedInsts; 879 880 // Record that the number of ROB entries has changed. 881 changedROBNumEntries[tid] = true; 882 } else { 883 PC[tid] = head_inst->readPC(); 884 nextPC[tid] = head_inst->readNextPC(); 885 nextNPC[tid] = head_inst->readNextNPC(); 886 887 // Increment the total number of non-speculative instructions 888 // executed. 889 // Hack for now: it really shouldn't happen until after the 890 // commit is deemed to be successful, but this count is needed 891 // for syscalls. 892 thread[tid]->funcExeInst++; 893 894 // Try to commit the head instruction. 895 bool commit_success = commitHead(head_inst, num_committed); 896 897 if (commit_success) { 898 ++num_committed; 899 900 changedROBNumEntries[tid] = true; 901 902 // Set the doneSeqNum to the youngest committed instruction. 903 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 904 905 ++commitCommittedInsts; 906 907 // To match the old model, don't count nops and instruction 908 // prefetches towards the total commit count. 909 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 910 cpu->instDone(tid); 911 } 912 913 PC[tid] = nextPC[tid]; 914#if ISA_HAS_DELAY_SLOT 915 nextPC[tid] = nextNPC[tid]; 916 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 917#else 918 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 919#endif 920 921#if FULL_SYSTEM 922 int count = 0; 923 Addr oldpc; 924 do { 925 // Debug statement. Checks to make sure we're not 926 // currently updating state while handling PC events. 927 if (count == 0) 928 assert(!thread[tid]->inSyscall && 929 !thread[tid]->trapPending); 930 oldpc = PC[tid]; 931 cpu->system->pcEventQueue.service( 932 thread[tid]->getTC()); 933 count++; 934 } while (oldpc != PC[tid]); 935 if (count > 1) { 936 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 937 break; 938 } 939#endif 940 } else { 941 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 942 "[tid:%i] [sn:%i].\n", 943 head_inst->readPC(), tid ,head_inst->seqNum); 944 break; 945 } 946 } 947 } 948 949 DPRINTF(CommitRate, "%i\n", num_committed); 950 numCommittedDist.sample(num_committed); 951 952 if (num_committed == commitWidth) { 953 commitEligibleSamples++; 954 } 955} 956 957template <class Impl> 958bool 959DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 960{ 961 assert(head_inst); 962 963 int tid = head_inst->threadNumber; 964 965 // If the instruction is not executed yet, then it will need extra 966 // handling. Signal backwards that it should be executed. 967 if (!head_inst->isExecuted()) { 968 // Keep this number correct. We have not yet actually executed 969 // and committed this instruction. 970 thread[tid]->funcExeInst--; 971 972 head_inst->setAtCommit(); 973 974 if (head_inst->isNonSpeculative() || 975 head_inst->isStoreConditional() || 976 head_inst->isMemBarrier() || 977 head_inst->isWriteBarrier()) { 978 979 DPRINTF(Commit, "Encountered a barrier or non-speculative " 980 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 981 head_inst->seqNum, head_inst->readPC()); 982 983#if !FULL_SYSTEM 984 // Hack to make sure syscalls/memory barriers/quiesces 985 // aren't executed until all stores write back their data. 986 // This direct communication shouldn't be used for 987 // anything other than this. 988 if (inst_num > 0 || iewStage->hasStoresToWB()) 989#else 990 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 991 head_inst->isQuiesce()) && 992 iewStage->hasStoresToWB()) 993#endif 994 { 995 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 996 return false; 997 } 998 999 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1000 1001 // Change the instruction so it won't try to commit again until 1002 // it is executed. 1003 head_inst->clearCanCommit(); 1004 1005 ++commitNonSpecStalls; 1006 1007 return false; 1008 } else if (head_inst->isLoad()) { 1009 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 1010 head_inst->seqNum, head_inst->readPC()); 1011 1012 // Send back the non-speculative instruction's sequence 1013 // number. Tell the lsq to re-execute the load. 1014 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1015 toIEW->commitInfo[tid].uncached = true; 1016 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1017 1018 head_inst->clearCanCommit(); 1019 1020 return false; 1021 } else { 1022 panic("Trying to commit un-executed instruction " 1023 "of unknown type!\n"); 1024 } 1025 } 1026 1027 if (head_inst->isThreadSync()) { 1028 // Not handled for now. 1029 panic("Thread sync instructions are not handled yet.\n"); 1030 } 1031 1032 // Stores mark themselves as completed. 1033 if (!head_inst->isStore()) { 1034 head_inst->setCompleted(); 1035 } 1036 1037#if USE_CHECKER 1038 // Use checker prior to updating anything due to traps or PC 1039 // based events. 1040 if (cpu->checker) { 1041 cpu->checker->verify(head_inst); 1042 } 1043#endif 1044 1045 // Check if the instruction caused a fault. If so, trap. 1046 Fault inst_fault = head_inst->getFault(); 1047 1048 // DTB will sometimes need the machine instruction for when 1049 // faults happen. So we will set it here, prior to the DTB 1050 // possibly needing it for its fault. 1051 thread[tid]->setInst( 1052 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1053 1054 if (inst_fault != NoFault) { 1055 head_inst->setCompleted(); 1056 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1057 head_inst->seqNum, head_inst->readPC()); 1058 1059 if (iewStage->hasStoresToWB() || inst_num > 0) { 1060 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1061 return false; 1062 } 1063 1064#if USE_CHECKER 1065 if (cpu->checker && head_inst->isStore()) { 1066 cpu->checker->verify(head_inst); 1067 } 1068#endif 1069 1070 assert(!thread[tid]->inSyscall); 1071 1072 // Mark that we're in state update mode so that the trap's 1073 // execution doesn't generate extra squashes. 1074 thread[tid]->inSyscall = true; 1075 1076 // Execute the trap. Although it's slightly unrealistic in 1077 // terms of timing (as it doesn't wait for the full timing of 1078 // the trap event to complete before updating state), it's 1079 // needed to update the state as soon as possible. This 1080 // prevents external agents from changing any specific state 1081 // that the trap need. 1082 cpu->trap(inst_fault, tid); 1083 1084 // Exit state update mode to avoid accidental updating. 1085 thread[tid]->inSyscall = false; 1086 1087 commitStatus[tid] = TrapPending; 1088 1089 // Generate trap squash event. 1090 generateTrapEvent(tid); 1091// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 1092 return false; 1093 } 1094 1095 updateComInstStats(head_inst); 1096 1097#if FULL_SYSTEM 1098 if (thread[tid]->profile) { 1099// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 1100// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 1101 thread[tid]->profilePC = head_inst->readPC(); 1102 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1103 head_inst->staticInst); 1104 1105 if (node) 1106 thread[tid]->profileNode = node; 1107 } 1108#endif 1109 1110 if (head_inst->traceData) { 1111 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1112 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1113 head_inst->traceData->finalize(); 1114 head_inst->traceData = NULL; 1115 } 1116 1117 // Update the commit rename map 1118 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1119 renameMap[tid]->setEntry(head_inst->destRegIdx(i), 1120 head_inst->renamedDestRegIdx(i)); 1121 } 1122 1123 if (head_inst->isCopy()) 1124 panic("Should not commit any copy instructions!"); 1125 1126 // Finally clear the head ROB entry. 1127 rob->retireHead(tid); 1128 1129 // Return true to indicate that we have committed an instruction. 1130 return true; 1131} 1132 1133template <class Impl> 1134void 1135DefaultCommit<Impl>::getInsts() 1136{ 1137 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1138 1139#if ISA_HAS_DELAY_SLOT 1140 // Read any renamed instructions and place them into the ROB. 1141 int insts_to_process = std::min((int)renameWidth, 1142 (int)(fromRename->size + skidBuffer.size())); 1143 int rename_idx = 0; 1144 1145 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 1146 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 1147 skidBuffer.size()); 1148#else 1149 // Read any renamed instructions and place them into the ROB. 1150 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1151#endif 1152 1153 1154 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1155 DynInstPtr inst; 1156 1157#if ISA_HAS_DELAY_SLOT 1158 // Get insts from skidBuffer or from Rename 1159 if (skidBuffer.size() > 0) { 1160 DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 1161 inst = skidBuffer.front(); 1162 skidBuffer.pop(); 1163 } else { 1164 DPRINTF(Commit, "Grabbing rename inst.\n"); 1165 inst = fromRename->insts[rename_idx++]; 1166 } 1167#else 1168 inst = fromRename->insts[inst_num]; 1169#endif 1170 int tid = inst->threadNumber; 1171 1172 if (!inst->isSquashed() && 1173 commitStatus[tid] != ROBSquashing) { 1174 changedROBNumEntries[tid] = true; 1175 1176 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1177 inst->readPC(), inst->seqNum, tid); 1178 1179 rob->insertInst(inst); 1180 1181 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1182 1183 youngestSeqNum[tid] = inst->seqNum; 1184 } else { 1185 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1186 "squashed, skipping.\n", 1187 inst->readPC(), inst->seqNum, tid); 1188 } 1189 } 1190 1191#if ISA_HAS_DELAY_SLOT 1192 if (rename_idx < fromRename->size) { 1193 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 1194 1195 for (; 1196 rename_idx < fromRename->size; 1197 rename_idx++) { 1198 DynInstPtr inst = fromRename->insts[rename_idx]; 1199 int tid = inst->threadNumber; 1200 1201 if (!inst->isSquashed()) { 1202 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1203 "skidBuffer.\n", inst->readPC(), inst->seqNum, tid); 1204 skidBuffer.push(inst); 1205 } else { 1206 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1207 "squashed, skipping.\n", 1208 inst->readPC(), inst->seqNum, tid); 1209 } 1210 } 1211 } 1212#endif 1213 1214} 1215 1216template <class Impl> 1217void 1218DefaultCommit<Impl>::skidInsert() 1219{ 1220 DPRINTF(Commit, "Attempting to any instructions from rename into " 1221 "skidBuffer.\n"); 1222 1223 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1224 DynInstPtr inst = fromRename->insts[inst_num]; 1225 1226 if (!inst->isSquashed()) { 1227 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1228 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1229 inst->threadNumber); 1230 skidBuffer.push(inst); 1231 } else { 1232 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1233 "squashed, skipping.\n", 1234 inst->readPC(), inst->seqNum, inst->threadNumber); 1235 } 1236 } 1237} 1238 1239template <class Impl> 1240void 1241DefaultCommit<Impl>::markCompletedInsts() 1242{ 1243 // Grab completed insts out of the IEW instruction queue, and mark 1244 // instructions completed within the ROB. 1245 for (int inst_num = 0; 1246 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1247 ++inst_num) 1248 { 1249 if (!fromIEW->insts[inst_num]->isSquashed()) { 1250 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1251 "within ROB.\n", 1252 fromIEW->insts[inst_num]->threadNumber, 1253 fromIEW->insts[inst_num]->readPC(), 1254 fromIEW->insts[inst_num]->seqNum); 1255 1256 // Mark the instruction as ready to commit. 1257 fromIEW->insts[inst_num]->setCanCommit(); 1258 } 1259 } 1260} 1261 1262template <class Impl> 1263bool 1264DefaultCommit<Impl>::robDoneSquashing() 1265{ 1266 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1267 1268 while (threads != (*activeThreads).end()) { 1269 unsigned tid = *threads++; 1270 1271 if (!rob->isDoneSquashing(tid)) 1272 return false; 1273 } 1274 1275 return true; 1276} 1277 1278template <class Impl> 1279void 1280DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1281{ 1282 unsigned thread = inst->threadNumber; 1283 1284 // 1285 // Pick off the software prefetches 1286 // 1287#ifdef TARGET_ALPHA 1288 if (inst->isDataPrefetch()) { 1289 statComSwp[thread]++; 1290 } else { 1291 statComInst[thread]++; 1292 } 1293#else 1294 statComInst[thread]++; 1295#endif 1296 1297 // 1298 // Control Instructions 1299 // 1300 if (inst->isControl()) 1301 statComBranches[thread]++; 1302 1303 // 1304 // Memory references 1305 // 1306 if (inst->isMemRef()) { 1307 statComRefs[thread]++; 1308 1309 if (inst->isLoad()) { 1310 statComLoads[thread]++; 1311 } 1312 } 1313 1314 if (inst->isMemBarrier()) { 1315 statComMembars[thread]++; 1316 } 1317} 1318 1319//////////////////////////////////////// 1320// // 1321// SMT COMMIT POLICY MAINTAINED HERE // 1322// // 1323//////////////////////////////////////// 1324template <class Impl> 1325int 1326DefaultCommit<Impl>::getCommittingThread() 1327{ 1328 if (numThreads > 1) { 1329 switch (commitPolicy) { 1330 1331 case Aggressive: 1332 //If Policy is Aggressive, commit will call 1333 //this function multiple times per 1334 //cycle 1335 return oldestReady(); 1336 1337 case RoundRobin: 1338 return roundRobin(); 1339 1340 case OldestReady: 1341 return oldestReady(); 1342 1343 default: 1344 return -1; 1345 } 1346 } else { 1347 int tid = (*activeThreads).front(); 1348 1349 if (commitStatus[tid] == Running || 1350 commitStatus[tid] == Idle || 1351 commitStatus[tid] == FetchTrapPending) { 1352 return tid; 1353 } else { 1354 return -1; 1355 } 1356 } 1357} 1358 1359template<class Impl> 1360int 1361DefaultCommit<Impl>::roundRobin() 1362{ 1363 std::list<unsigned>::iterator pri_iter = priority_list.begin(); 1364 std::list<unsigned>::iterator end = priority_list.end(); 1365 1366 while (pri_iter != end) { 1367 unsigned tid = *pri_iter; 1368 1369 if (commitStatus[tid] == Running || 1370 commitStatus[tid] == Idle || 1371 commitStatus[tid] == FetchTrapPending) { 1372 1373 if (rob->isHeadReady(tid)) { 1374 priority_list.erase(pri_iter); 1375 priority_list.push_back(tid); 1376 1377 return tid; 1378 } 1379 } 1380 1381 pri_iter++; 1382 } 1383 1384 return -1; 1385} 1386 1387template<class Impl> 1388int 1389DefaultCommit<Impl>::oldestReady() 1390{ 1391 unsigned oldest = 0; 1392 bool first = true; 1393 1394 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1395 1396 while (threads != (*activeThreads).end()) { 1397 unsigned tid = *threads++; 1398 1399 if (!rob->isEmpty(tid) && 1400 (commitStatus[tid] == Running || 1401 commitStatus[tid] == Idle || 1402 commitStatus[tid] == FetchTrapPending)) { 1403 1404 if (rob->isHeadReady(tid)) { 1405 1406 DynInstPtr head_inst = rob->readHeadInst(tid); 1407 1408 if (first) { 1409 oldest = tid; 1410 first = false; 1411 } else if (head_inst->seqNum < oldest) { 1412 oldest = tid; 1413 } 1414 } 1415 } 1416 } 1417 1418 if (!first) { 1419 return oldest; 1420 } else { 1421 return -1; 1422 } 1423} 1424