commit_impl.hh revision 13449:2f7efa89c58b 
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44#ifndef __CPU_O3_COMMIT_IMPL_HH__
45#define __CPU_O3_COMMIT_IMPL_HH__
46
47#include <algorithm>
48#include <set>
49#include <string>
50
51#include "arch/utility.hh"
52#include "base/cp_annotate.hh"
53#include "base/loader/symtab.hh"
54#include "base/logging.hh"
55#include "config/the_isa.hh"
56#include "cpu/checker/cpu.hh"
57#include "cpu/o3/commit.hh"
58#include "cpu/o3/thread_state.hh"
59#include "cpu/base.hh"
60#include "cpu/exetrace.hh"
61#include "cpu/timebuf.hh"
62#include "debug/Activity.hh"
63#include "debug/Commit.hh"
64#include "debug/CommitRate.hh"
65#include "debug/Drain.hh"
66#include "debug/ExecFaulting.hh"
67#include "debug/O3PipeView.hh"
68#include "params/DerivO3CPU.hh"
69#include "sim/faults.hh"
70#include "sim/full_system.hh"
71
72using namespace std;
73
74template <class Impl>
75void
76DefaultCommit<Impl>::processTrapEvent(ThreadID tid)
77{
78    // This will get reset by commit if it was switched out at the
79    // time of this event processing.
80    trapSquash[tid] = true;
81}
82
83template <class Impl>
84DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
85    : cpu(_cpu),
86      iewToCommitDelay(params->iewToCommitDelay),
87      commitToIEWDelay(params->commitToIEWDelay),
88      renameToROBDelay(params->renameToROBDelay),
89      fetchToCommitDelay(params->commitToFetchDelay),
90      renameWidth(params->renameWidth),
91      commitWidth(params->commitWidth),
92      numThreads(params->numThreads),
93      drainPending(false),
94      drainImminent(false),
95      trapLatency(params->trapLatency),
96      canHandleInterrupts(true),
97      avoidQuiesceLiveLock(false)
98{
99    if (commitWidth > Impl::MaxWidth)
100        fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
101             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
102             commitWidth, static_cast<int>(Impl::MaxWidth));
103
104    _status = Active;
105    _nextStatus = Inactive;
106    std::string policy = params->smtCommitPolicy;
107
108    //Convert string to lowercase
109    std::transform(policy.begin(), policy.end(), policy.begin(),
110                   (int(*)(int)) tolower);
111
112    //Assign commit policy
113    if (policy == "aggressive"){
114        commitPolicy = Aggressive;
115
116        DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
117    } else if (policy == "roundrobin"){
118        commitPolicy = RoundRobin;
119
120        //Set-Up Priority List
121        for (ThreadID tid = 0; tid < numThreads; tid++) {
122            priority_list.push_back(tid);
123        }
124
125        DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
126    } else if (policy == "oldestready"){
127        commitPolicy = OldestReady;
128
129        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
130    } else {
131        panic("Invalid SMT commit policy. Options are: Aggressive, "
132               "RoundRobin, OldestReady");
133    }
134
135    for (ThreadID tid = 0; tid < numThreads; tid++) {
136        commitStatus[tid] = Idle;
137        changedROBNumEntries[tid] = false;
138        checkEmptyROB[tid] = false;
139        trapInFlight[tid] = false;
140        committedStores[tid] = false;
141        trapSquash[tid] = false;
142        tcSquash[tid] = false;
143        pc[tid].set(0);
144        lastCommitedSeqNum[tid] = 0;
145        squashAfterInst[tid] = NULL;
146    }
147    interrupt = NoFault;
148}
149
150template <class Impl>
151std::string
152DefaultCommit<Impl>::name() const
153{
154    return cpu->name() + ".commit";
155}
156
157template <class Impl>
158void
159DefaultCommit<Impl>::regProbePoints()
160{
161    ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
162    ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
163    ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
164}
165
166template <class Impl>
167void
168DefaultCommit<Impl>::regStats()
169{
170    using namespace Stats;
171    commitSquashedInsts
172        .name(name() + ".commitSquashedInsts")
173        .desc("The number of squashed insts skipped by commit")
174        .prereq(commitSquashedInsts);
175
176    commitNonSpecStalls
177        .name(name() + ".commitNonSpecStalls")
178        .desc("The number of times commit has been forced to stall to "
179              "communicate backwards")
180        .prereq(commitNonSpecStalls);
181
182    branchMispredicts
183        .name(name() + ".branchMispredicts")
184        .desc("The number of times a branch was mispredicted")
185        .prereq(branchMispredicts);
186
187    numCommittedDist
188        .init(0,commitWidth,1)
189        .name(name() + ".committed_per_cycle")
190        .desc("Number of insts commited each cycle")
191        .flags(Stats::pdf)
192        ;
193
194    instsCommitted
195        .init(cpu->numThreads)
196        .name(name() + ".committedInsts")
197        .desc("Number of instructions committed")
198        .flags(total)
199        ;
200
201    opsCommitted
202        .init(cpu->numThreads)
203        .name(name() + ".committedOps")
204        .desc("Number of ops (including micro ops) committed")
205        .flags(total)
206        ;
207
208    statComSwp
209        .init(cpu->numThreads)
210        .name(name() + ".swp_count")
211        .desc("Number of s/w prefetches committed")
212        .flags(total)
213        ;
214
215    statComRefs
216        .init(cpu->numThreads)
217        .name(name() +  ".refs")
218        .desc("Number of memory references committed")
219        .flags(total)
220        ;
221
222    statComLoads
223        .init(cpu->numThreads)
224        .name(name() +  ".loads")
225        .desc("Number of loads committed")
226        .flags(total)
227        ;
228
229    statComMembars
230        .init(cpu->numThreads)
231        .name(name() +  ".membars")
232        .desc("Number of memory barriers committed")
233        .flags(total)
234        ;
235
236    statComBranches
237        .init(cpu->numThreads)
238        .name(name() + ".branches")
239        .desc("Number of branches committed")
240        .flags(total)
241        ;
242
243    statComFloating
244        .init(cpu->numThreads)
245        .name(name() + ".fp_insts")
246        .desc("Number of committed floating point instructions.")
247        .flags(total)
248        ;
249
250    statComVector
251        .init(cpu->numThreads)
252        .name(name() + ".vec_insts")
253        .desc("Number of committed Vector instructions.")
254        .flags(total)
255        ;
256
257    statComInteger
258        .init(cpu->numThreads)
259        .name(name()+".int_insts")
260        .desc("Number of committed integer instructions.")
261        .flags(total)
262        ;
263
264    statComFunctionCalls
265        .init(cpu->numThreads)
266        .name(name()+".function_calls")
267        .desc("Number of function calls committed.")
268        .flags(total)
269        ;
270
271    statCommittedInstType
272        .init(numThreads,Enums::Num_OpClass)
273        .name(name() + ".op_class")
274        .desc("Class of committed instruction")
275        .flags(total | pdf | dist)
276        ;
277    statCommittedInstType.ysubnames(Enums::OpClassStrings);
278
279    commitEligibleSamples
280        .name(name() + ".bw_lim_events")
281        .desc("number cycles where commit BW limit reached")
282        ;
283}
284
285template <class Impl>
286void
287DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
288{
289    thread = threads;
290}
291
292template <class Impl>
293void
294DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
295{
296    timeBuffer = tb_ptr;
297
298    // Setup wire to send information back to IEW.
299    toIEW = timeBuffer->getWire(0);
300
301    // Setup wire to read data from IEW (for the ROB).
302    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
303}
304
305template <class Impl>
306void
307DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
308{
309    fetchQueue = fq_ptr;
310
311    // Setup wire to get instructions from rename (for the ROB).
312    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
313}
314
315template <class Impl>
316void
317DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
318{
319    renameQueue = rq_ptr;
320
321    // Setup wire to get instructions from rename (for the ROB).
322    fromRename = renameQueue->getWire(-renameToROBDelay);
323}
324
325template <class Impl>
326void
327DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
328{
329    iewQueue = iq_ptr;
330
331    // Setup wire to get instructions from IEW.
332    fromIEW = iewQueue->getWire(-iewToCommitDelay);
333}
334
335template <class Impl>
336void
337DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
338{
339    iewStage = iew_stage;
340}
341
342template<class Impl>
343void
344DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
345{
346    activeThreads = at_ptr;
347}
348
349template <class Impl>
350void
351DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
352{
353    for (ThreadID tid = 0; tid < numThreads; tid++)
354        renameMap[tid] = &rm_ptr[tid];
355}
356
357template <class Impl>
358void
359DefaultCommit<Impl>::setROB(ROB *rob_ptr)
360{
361    rob = rob_ptr;
362}
363
364template <class Impl>
365void
366DefaultCommit<Impl>::startupStage()
367{
368    rob->setActiveThreads(activeThreads);
369    rob->resetEntries();
370
371    // Broadcast the number of free entries.
372    for (ThreadID tid = 0; tid < numThreads; tid++) {
373        toIEW->commitInfo[tid].usedROB = true;
374        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
375        toIEW->commitInfo[tid].emptyROB = true;
376    }
377
378    // Commit must broadcast the number of free entries it has at the
379    // start of the simulation, so it starts as active.
380    cpu->activateStage(O3CPU::CommitIdx);
381
382    cpu->activityThisCycle();
383}
384
385template <class Impl>
386void
387DefaultCommit<Impl>::drain()
388{
389    drainPending = true;
390}
391
392template <class Impl>
393void
394DefaultCommit<Impl>::drainResume()
395{
396    drainPending = false;
397    drainImminent = false;
398}
399
400template <class Impl>
401void
402DefaultCommit<Impl>::drainSanityCheck() const
403{
404    assert(isDrained());
405    rob->drainSanityCheck();
406}
407
408template <class Impl>
409bool
410DefaultCommit<Impl>::isDrained() const
411{
412    /* Make sure no one is executing microcode. There are two reasons
413     * for this:
414     * - Hardware virtualized CPUs can't switch into the middle of a
415     *   microcode sequence.
416     * - The current fetch implementation will most likely get very
417     *   confused if it tries to start fetching an instruction that
418     *   is executing in the middle of a ucode sequence that changes
419     *   address mappings. This can happen on for example x86.
420     */
421    for (ThreadID tid = 0; tid < numThreads; tid++) {
422        if (pc[tid].microPC() != 0)
423            return false;
424    }
425
426    /* Make sure that all instructions have finished committing before
427     * declaring the system as drained. We want the pipeline to be
428     * completely empty when we declare the CPU to be drained. This
429     * makes debugging easier since CPU handover and restoring from a
430     * checkpoint with a different CPU should have the same timing.
431     */
432    return rob->isEmpty() &&
433        interrupt == NoFault;
434}
435
436template <class Impl>
437void
438DefaultCommit<Impl>::takeOverFrom()
439{
440    _status = Active;
441    _nextStatus = Inactive;
442    for (ThreadID tid = 0; tid < numThreads; tid++) {
443        commitStatus[tid] = Idle;
444        changedROBNumEntries[tid] = false;
445        trapSquash[tid] = false;
446        tcSquash[tid] = false;
447        squashAfterInst[tid] = NULL;
448    }
449    rob->takeOverFrom();
450}
451
452template <class Impl>
453void
454DefaultCommit<Impl>::deactivateThread(ThreadID tid)
455{
456    list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
457            priority_list.end(), tid);
458
459    if (thread_it != priority_list.end()) {
460        priority_list.erase(thread_it);
461    }
462}
463
464
465template <class Impl>
466void
467DefaultCommit<Impl>::updateStatus()
468{
469    // reset ROB changed variable
470    list<ThreadID>::iterator threads = activeThreads->begin();
471    list<ThreadID>::iterator end = activeThreads->end();
472
473    while (threads != end) {
474        ThreadID tid = *threads++;
475
476        changedROBNumEntries[tid] = false;
477
478        // Also check if any of the threads has a trap pending
479        if (commitStatus[tid] == TrapPending ||
480            commitStatus[tid] == FetchTrapPending) {
481            _nextStatus = Active;
482        }
483    }
484
485    if (_nextStatus == Inactive && _status == Active) {
486        DPRINTF(Activity, "Deactivating stage.\n");
487        cpu->deactivateStage(O3CPU::CommitIdx);
488    } else if (_nextStatus == Active && _status == Inactive) {
489        DPRINTF(Activity, "Activating stage.\n");
490        cpu->activateStage(O3CPU::CommitIdx);
491    }
492
493    _status = _nextStatus;
494}
495
496template <class Impl>
497bool
498DefaultCommit<Impl>::changedROBEntries()
499{
500    list<ThreadID>::iterator threads = activeThreads->begin();
501    list<ThreadID>::iterator end = activeThreads->end();
502
503    while (threads != end) {
504        ThreadID tid = *threads++;
505
506        if (changedROBNumEntries[tid]) {
507            return true;
508        }
509    }
510
511    return false;
512}
513
514template <class Impl>
515size_t
516DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
517{
518    return rob->numFreeEntries(tid);
519}
520
521template <class Impl>
522void
523DefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault)
524{
525    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
526
527    EventFunctionWrapper *trap = new EventFunctionWrapper(
528        [this, tid]{ processTrapEvent(tid); },
529        "Trap", true, Event::CPU_Tick_Pri);
530
531    Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
532                     cpu->syscallRetryLatency : trapLatency;
533
534    cpu->schedule(trap, cpu->clockEdge(latency));
535    trapInFlight[tid] = true;
536    thread[tid]->trapPending = true;
537}
538
539template <class Impl>
540void
541DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
542{
543    assert(!trapInFlight[tid]);
544    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
545
546    tcSquash[tid] = true;
547}
548
549template <class Impl>
550void
551DefaultCommit<Impl>::squashAll(ThreadID tid)
552{
553    // If we want to include the squashing instruction in the squash,
554    // then use one older sequence number.
555    // Hopefully this doesn't mess things up.  Basically I want to squash
556    // all instructions of this thread.
557    InstSeqNum squashed_inst = rob->isEmpty(tid) ?
558        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
559
560    // All younger instructions will be squashed. Set the sequence
561    // number as the youngest instruction in the ROB (0 in this case.
562    // Hopefully nothing breaks.)
563    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
564
565    rob->squash(squashed_inst, tid);
566    changedROBNumEntries[tid] = true;
567
568    // Send back the sequence number of the squashed instruction.
569    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
570
571    // Send back the squash signal to tell stages that they should
572    // squash.
573    toIEW->commitInfo[tid].squash = true;
574
575    // Send back the rob squashing signal so other stages know that
576    // the ROB is in the process of squashing.
577    toIEW->commitInfo[tid].robSquashing = true;
578
579    toIEW->commitInfo[tid].mispredictInst = NULL;
580    toIEW->commitInfo[tid].squashInst = NULL;
581
582    toIEW->commitInfo[tid].pc = pc[tid];
583}
584
585template <class Impl>
586void
587DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
588{
589    squashAll(tid);
590
591    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
592
593    thread[tid]->trapPending = false;
594    thread[tid]->noSquashFromTC = false;
595    trapInFlight[tid] = false;
596
597    trapSquash[tid] = false;
598
599    commitStatus[tid] = ROBSquashing;
600    cpu->activityThisCycle();
601}
602
603template <class Impl>
604void
605DefaultCommit<Impl>::squashFromTC(ThreadID tid)
606{
607    squashAll(tid);
608
609    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
610
611    thread[tid]->noSquashFromTC = false;
612    assert(!thread[tid]->trapPending);
613
614    commitStatus[tid] = ROBSquashing;
615    cpu->activityThisCycle();
616
617    tcSquash[tid] = false;
618}
619
620template <class Impl>
621void
622DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
623{
624    DPRINTF(Commit, "Squashing after squash after request, "
625            "restarting at PC %s\n", pc[tid]);
626
627    squashAll(tid);
628    // Make sure to inform the fetch stage of which instruction caused
629    // the squash. It'll try to re-fetch an instruction executing in
630    // microcode unless this is set.
631    toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
632    squashAfterInst[tid] = NULL;
633
634    commitStatus[tid] = ROBSquashing;
635    cpu->activityThisCycle();
636}
637
638template <class Impl>
639void
640DefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst)
641{
642    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
643            tid, head_inst->seqNum);
644
645    assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
646    commitStatus[tid] = SquashAfterPending;
647    squashAfterInst[tid] = head_inst;
648}
649
650template <class Impl>
651void
652DefaultCommit<Impl>::tick()
653{
654    wroteToTimeBuffer = false;
655    _nextStatus = Inactive;
656
657    if (activeThreads->empty())
658        return;
659
660    list<ThreadID>::iterator threads = activeThreads->begin();
661    list<ThreadID>::iterator end = activeThreads->end();
662
663    // Check if any of the threads are done squashing.  Change the
664    // status if they are done.
665    while (threads != end) {
666        ThreadID tid = *threads++;
667
668        // Clear the bit saying if the thread has committed stores
669        // this cycle.
670        committedStores[tid] = false;
671
672        if (commitStatus[tid] == ROBSquashing) {
673
674            if (rob->isDoneSquashing(tid)) {
675                commitStatus[tid] = Running;
676            } else {
677                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
678                        " insts this cycle.\n", tid);
679                rob->doSquash(tid);
680                toIEW->commitInfo[tid].robSquashing = true;
681                wroteToTimeBuffer = true;
682            }
683        }
684    }
685
686    commit();
687
688    markCompletedInsts();
689
690    threads = activeThreads->begin();
691
692    while (threads != end) {
693        ThreadID tid = *threads++;
694
695        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
696            // The ROB has more instructions it can commit. Its next status
697            // will be active.
698            _nextStatus = Active;
699
700            const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
701
702            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
703                    " ROB and ready to commit\n",
704                    tid, inst->seqNum, inst->pcState());
705
706        } else if (!rob->isEmpty(tid)) {
707            const DynInstPtr &inst = rob->readHeadInst(tid);
708
709            ppCommitStall->notify(inst);
710
711            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
712                    "%s is head of ROB and not ready\n",
713                    tid, inst->seqNum, inst->pcState());
714        }
715
716        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
717                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
718    }
719
720
721    if (wroteToTimeBuffer) {
722        DPRINTF(Activity, "Activity This Cycle.\n");
723        cpu->activityThisCycle();
724    }
725
726    updateStatus();
727}
728
729template <class Impl>
730void
731DefaultCommit<Impl>::handleInterrupt()
732{
733    // Verify that we still have an interrupt to handle
734    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
735        DPRINTF(Commit, "Pending interrupt is cleared by master before "
736                "it got handled. Restart fetching from the orig path.\n");
737        toIEW->commitInfo[0].clearInterrupt = true;
738        interrupt = NoFault;
739        avoidQuiesceLiveLock = true;
740        return;
741    }
742
743    // Wait until all in flight instructions are finished before enterring
744    // the interrupt.
745    if (canHandleInterrupts && cpu->instList.empty()) {
746        // Squash or record that I need to squash this cycle if
747        // an interrupt needed to be handled.
748        DPRINTF(Commit, "Interrupt detected.\n");
749
750        // Clear the interrupt now that it's going to be handled
751        toIEW->commitInfo[0].clearInterrupt = true;
752
753        assert(!thread[0]->noSquashFromTC);
754        thread[0]->noSquashFromTC = true;
755
756        if (cpu->checker) {
757            cpu->checker->handlePendingInt();
758        }
759
760        // CPU will handle interrupt. Note that we ignore the local copy of
761        // interrupt. This is because the local copy may no longer be the
762        // interrupt that the interrupt controller thinks is being handled.
763        cpu->processInterrupts(cpu->getInterrupts());
764
765        thread[0]->noSquashFromTC = false;
766
767        commitStatus[0] = TrapPending;
768
769        interrupt = NoFault;
770
771        // Generate trap squash event.
772        generateTrapEvent(0, interrupt);
773
774        avoidQuiesceLiveLock = false;
775    } else {
776        DPRINTF(Commit, "Interrupt pending: instruction is %sin "
777                "flight, ROB is %sempty\n",
778                canHandleInterrupts ? "not " : "",
779                cpu->instList.empty() ? "" : "not " );
780    }
781}
782
783template <class Impl>
784void
785DefaultCommit<Impl>::propagateInterrupt()
786{
787    // Don't propagate intterupts if we are currently handling a trap or
788    // in draining and the last observable instruction has been committed.
789    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
790            tcSquash[0] || drainImminent)
791        return;
792
793    // Process interrupts if interrupts are enabled, not in PAL
794    // mode, and no other traps or external squashes are currently
795    // pending.
796    // @todo: Allow other threads to handle interrupts.
797
798    // Get any interrupt that happened
799    interrupt = cpu->getInterrupts();
800
801    // Tell fetch that there is an interrupt pending.  This
802    // will make fetch wait until it sees a non PAL-mode PC,
803    // at which point it stops fetching instructions.
804    if (interrupt != NoFault)
805        toIEW->commitInfo[0].interruptPending = true;
806}
807
808template <class Impl>
809void
810DefaultCommit<Impl>::commit()
811{
812    if (FullSystem) {
813        // Check if we have a interrupt and get read to handle it
814        if (cpu->checkInterrupts(cpu->tcBase(0)))
815            propagateInterrupt();
816    }
817
818    ////////////////////////////////////
819    // Check for any possible squashes, handle them first
820    ////////////////////////////////////
821    list<ThreadID>::iterator threads = activeThreads->begin();
822    list<ThreadID>::iterator end = activeThreads->end();
823
824    int num_squashing_threads = 0;
825
826    while (threads != end) {
827        ThreadID tid = *threads++;
828
829        // Not sure which one takes priority.  I think if we have
830        // both, that's a bad sign.
831        if (trapSquash[tid]) {
832            assert(!tcSquash[tid]);
833            squashFromTrap(tid);
834        } else if (tcSquash[tid]) {
835            assert(commitStatus[tid] != TrapPending);
836            squashFromTC(tid);
837        } else if (commitStatus[tid] == SquashAfterPending) {
838            // A squash from the previous cycle of the commit stage (i.e.,
839            // commitInsts() called squashAfter) is pending. Squash the
840            // thread now.
841            squashFromSquashAfter(tid);
842        }
843
844        // Squashed sequence number must be older than youngest valid
845        // instruction in the ROB. This prevents squashes from younger
846        // instructions overriding squashes from older instructions.
847        if (fromIEW->squash[tid] &&
848            commitStatus[tid] != TrapPending &&
849            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
850
851            if (fromIEW->mispredictInst[tid]) {
852                DPRINTF(Commit,
853                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
854                    tid,
855                    fromIEW->mispredictInst[tid]->instAddr(),
856                    fromIEW->squashedSeqNum[tid]);
857            } else {
858                DPRINTF(Commit,
859                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
860                    tid, fromIEW->squashedSeqNum[tid]);
861            }
862
863            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
864                    tid,
865                    fromIEW->pc[tid].nextInstAddr());
866
867            commitStatus[tid] = ROBSquashing;
868
869            // If we want to include the squashing instruction in the squash,
870            // then use one older sequence number.
871            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
872
873            if (fromIEW->includeSquashInst[tid]) {
874                squashed_inst--;
875            }
876
877            // All younger instructions will be squashed. Set the sequence
878            // number as the youngest instruction in the ROB.
879            youngestSeqNum[tid] = squashed_inst;
880
881            rob->squash(squashed_inst, tid);
882            changedROBNumEntries[tid] = true;
883
884            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
885
886            toIEW->commitInfo[tid].squash = true;
887
888            // Send back the rob squashing signal so other stages know that
889            // the ROB is in the process of squashing.
890            toIEW->commitInfo[tid].robSquashing = true;
891
892            toIEW->commitInfo[tid].mispredictInst =
893                fromIEW->mispredictInst[tid];
894            toIEW->commitInfo[tid].branchTaken =
895                fromIEW->branchTaken[tid];
896            toIEW->commitInfo[tid].squashInst =
897                                    rob->findInst(tid, squashed_inst);
898            if (toIEW->commitInfo[tid].mispredictInst) {
899                if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
900                     toIEW->commitInfo[tid].branchTaken = true;
901                }
902                ++branchMispredicts;
903            }
904
905            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
906        }
907
908        if (commitStatus[tid] == ROBSquashing) {
909            num_squashing_threads++;
910        }
911    }
912
913    // If commit is currently squashing, then it will have activity for the
914    // next cycle. Set its next status as active.
915    if (num_squashing_threads) {
916        _nextStatus = Active;
917    }
918
919    if (num_squashing_threads != numThreads) {
920        // If we're not currently squashing, then get instructions.
921        getInsts();
922
923        // Try to commit any instructions.
924        commitInsts();
925    }
926
927    //Check for any activity
928    threads = activeThreads->begin();
929
930    while (threads != end) {
931        ThreadID tid = *threads++;
932
933        if (changedROBNumEntries[tid]) {
934            toIEW->commitInfo[tid].usedROB = true;
935            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
936
937            wroteToTimeBuffer = true;
938            changedROBNumEntries[tid] = false;
939            if (rob->isEmpty(tid))
940                checkEmptyROB[tid] = true;
941        }
942
943        // ROB is only considered "empty" for previous stages if: a)
944        // ROB is empty, b) there are no outstanding stores, c) IEW
945        // stage has received any information regarding stores that
946        // committed.
947        // c) is checked by making sure to not consider the ROB empty
948        // on the same cycle as when stores have been committed.
949        // @todo: Make this handle multi-cycle communication between
950        // commit and IEW.
951        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
952            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
953            checkEmptyROB[tid] = false;
954            toIEW->commitInfo[tid].usedROB = true;
955            toIEW->commitInfo[tid].emptyROB = true;
956            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
957            wroteToTimeBuffer = true;
958        }
959
960    }
961}
962
963template <class Impl>
964void
965DefaultCommit<Impl>::commitInsts()
966{
967    ////////////////////////////////////
968    // Handle commit
969    // Note that commit will be handled prior to putting new
970    // instructions in the ROB so that the ROB only tries to commit
971    // instructions it has in this current cycle, and not instructions
972    // it is writing in during this cycle.  Can't commit and squash
973    // things at the same time...
974    ////////////////////////////////////
975
976    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
977
978    unsigned num_committed = 0;
979
980    DynInstPtr head_inst;
981
982    // Commit as many instructions as possible until the commit bandwidth
983    // limit is reached, or it becomes impossible to commit any more.
984    while (num_committed < commitWidth) {
985        // Check for any interrupt that we've already squashed for
986        // and start processing it.
987        if (interrupt != NoFault)
988            handleInterrupt();
989
990        ThreadID commit_thread = getCommittingThread();
991
992        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
993            break;
994
995        head_inst = rob->readHeadInst(commit_thread);
996
997        ThreadID tid = head_inst->threadNumber;
998
999        assert(tid == commit_thread);
1000
1001        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1002                head_inst->seqNum, tid);
1003
1004        // If the head instruction is squashed, it is ready to retire
1005        // (be removed from the ROB) at any time.
1006        if (head_inst->isSquashed()) {
1007
1008            DPRINTF(Commit, "Retiring squashed instruction from "
1009                    "ROB.\n");
1010
1011            rob->retireHead(commit_thread);
1012
1013            ++commitSquashedInsts;
1014            // Notify potential listeners that this instruction is squashed
1015            ppSquash->notify(head_inst);
1016
1017            // Record that the number of ROB entries has changed.
1018            changedROBNumEntries[tid] = true;
1019        } else {
1020            pc[tid] = head_inst->pcState();
1021
1022            // Increment the total number of non-speculative instructions
1023            // executed.
1024            // Hack for now: it really shouldn't happen until after the
1025            // commit is deemed to be successful, but this count is needed
1026            // for syscalls.
1027            thread[tid]->funcExeInst++;
1028
1029            // Try to commit the head instruction.
1030            bool commit_success = commitHead(head_inst, num_committed);
1031
1032            if (commit_success) {
1033                ++num_committed;
1034                statCommittedInstType[tid][head_inst->opClass()]++;
1035                ppCommit->notify(head_inst);
1036
1037                changedROBNumEntries[tid] = true;
1038
1039                // Set the doneSeqNum to the youngest committed instruction.
1040                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1041
1042                if (tid == 0) {
1043                    canHandleInterrupts =  (!head_inst->isDelayedCommit()) &&
1044                                           ((THE_ISA != ALPHA_ISA) ||
1045                                             (!(pc[0].instAddr() & 0x3)));
1046                }
1047
1048                // at this point store conditionals should either have
1049                // been completed or predicated false
1050                assert(!head_inst->isStoreConditional() ||
1051                       head_inst->isCompleted() ||
1052                       !head_inst->readPredicate());
1053
1054                // Updates misc. registers.
1055                head_inst->updateMiscRegs();
1056
1057                // Check instruction execution if it successfully commits and
1058                // is not carrying a fault.
1059                if (cpu->checker) {
1060                    cpu->checker->verify(head_inst);
1061                }
1062
1063                cpu->traceFunctions(pc[tid].instAddr());
1064
1065                TheISA::advancePC(pc[tid], head_inst->staticInst);
1066
1067                // Keep track of the last sequence number commited
1068                lastCommitedSeqNum[tid] = head_inst->seqNum;
1069
1070                // If this is an instruction that doesn't play nicely with
1071                // others squash everything and restart fetch
1072                if (head_inst->isSquashAfter())
1073                    squashAfter(tid, head_inst);
1074
1075                if (drainPending) {
1076                    if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1077                        !thread[tid]->trapPending) {
1078                        // Last architectually committed instruction.
1079                        // Squash the pipeline, stall fetch, and use
1080                        // drainImminent to disable interrupts
1081                        DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1082                        squashAfter(tid, head_inst);
1083                        cpu->commitDrained(tid);
1084                        drainImminent = true;
1085                    }
1086                }
1087
1088                bool onInstBoundary = !head_inst->isMicroop() ||
1089                                      head_inst->isLastMicroop() ||
1090                                      !head_inst->isDelayedCommit();
1091
1092                if (onInstBoundary) {
1093                    int count = 0;
1094                    Addr oldpc;
1095                    // Make sure we're not currently updating state while
1096                    // handling PC events.
1097                    assert(!thread[tid]->noSquashFromTC &&
1098                           !thread[tid]->trapPending);
1099                    do {
1100                        oldpc = pc[tid].instAddr();
1101                        cpu->system->pcEventQueue.service(thread[tid]->getTC());
1102                        count++;
1103                    } while (oldpc != pc[tid].instAddr());
1104                    if (count > 1) {
1105                        DPRINTF(Commit,
1106                                "PC skip function event, stopping commit\n");
1107                        break;
1108                    }
1109                }
1110
1111                // Check if an instruction just enabled interrupts and we've
1112                // previously had an interrupt pending that was not handled
1113                // because interrupts were subsequently disabled before the
1114                // pipeline reached a place to handle the interrupt. In that
1115                // case squash now to make sure the interrupt is handled.
1116                //
1117                // If we don't do this, we might end up in a live lock situation
1118                if (!interrupt && avoidQuiesceLiveLock &&
1119                    onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1120                    squashAfter(tid, head_inst);
1121            } else {
1122                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1123                        "[tid:%i] [sn:%i].\n",
1124                        head_inst->pcState(), tid ,head_inst->seqNum);
1125                break;
1126            }
1127        }
1128    }
1129
1130    DPRINTF(CommitRate, "%i\n", num_committed);
1131    numCommittedDist.sample(num_committed);
1132
1133    if (num_committed == commitWidth) {
1134        commitEligibleSamples++;
1135    }
1136}
1137
1138template <class Impl>
1139bool
1140DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
1141{
1142    assert(head_inst);
1143
1144    ThreadID tid = head_inst->threadNumber;
1145
1146    // If the instruction is not executed yet, then it will need extra
1147    // handling.  Signal backwards that it should be executed.
1148    if (!head_inst->isExecuted()) {
1149        // Keep this number correct.  We have not yet actually executed
1150        // and committed this instruction.
1151        thread[tid]->funcExeInst--;
1152
1153        // Make sure we are only trying to commit un-executed instructions we
1154        // think are possible.
1155        assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1156               || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1157               (head_inst->isLoad() && head_inst->strictlyOrdered()));
1158
1159        DPRINTF(Commit, "Encountered a barrier or non-speculative "
1160                "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1161                head_inst->seqNum, head_inst->pcState());
1162
1163        if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1164            DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1165            return false;
1166        }
1167
1168        toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1169
1170        // Change the instruction so it won't try to commit again until
1171        // it is executed.
1172        head_inst->clearCanCommit();
1173
1174        if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1175            DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n",
1176                    head_inst->seqNum, head_inst->pcState());
1177            toIEW->commitInfo[tid].strictlyOrdered = true;
1178            toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1179        } else {
1180            ++commitNonSpecStalls;
1181        }
1182
1183        return false;
1184    }
1185
1186    if (head_inst->isThreadSync()) {
1187        // Not handled for now.
1188        panic("Thread sync instructions are not handled yet.\n");
1189    }
1190
1191    // Check if the instruction caused a fault.  If so, trap.
1192    Fault inst_fault = head_inst->getFault();
1193
1194    // Stores mark themselves as completed.
1195    if (!head_inst->isStore() && inst_fault == NoFault) {
1196        head_inst->setCompleted();
1197    }
1198
1199    if (inst_fault != NoFault) {
1200        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1201                head_inst->seqNum, head_inst->pcState());
1202
1203        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1204            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1205            return false;
1206        }
1207
1208        head_inst->setCompleted();
1209
1210        // If instruction has faulted, let the checker execute it and
1211        // check if it sees the same fault and control flow.
1212        if (cpu->checker) {
1213            // Need to check the instruction before its fault is processed
1214            cpu->checker->verify(head_inst);
1215        }
1216
1217        assert(!thread[tid]->noSquashFromTC);
1218
1219        // Mark that we're in state update mode so that the trap's
1220        // execution doesn't generate extra squashes.
1221        thread[tid]->noSquashFromTC = true;
1222
1223        // Execute the trap.  Although it's slightly unrealistic in
1224        // terms of timing (as it doesn't wait for the full timing of
1225        // the trap event to complete before updating state), it's
1226        // needed to update the state as soon as possible.  This
1227        // prevents external agents from changing any specific state
1228        // that the trap need.
1229        cpu->trap(inst_fault, tid,
1230                  head_inst->notAnInst() ?
1231                      StaticInst::nullStaticInstPtr :
1232                      head_inst->staticInst);
1233
1234        // Exit state update mode to avoid accidental updating.
1235        thread[tid]->noSquashFromTC = false;
1236
1237        commitStatus[tid] = TrapPending;
1238
1239        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1240            head_inst->seqNum);
1241        if (head_inst->traceData) {
1242            if (DTRACE(ExecFaulting)) {
1243                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1244                head_inst->traceData->setCPSeq(thread[tid]->numOp);
1245                head_inst->traceData->dump();
1246            }
1247            delete head_inst->traceData;
1248            head_inst->traceData = NULL;
1249        }
1250
1251        // Generate trap squash event.
1252        generateTrapEvent(tid, inst_fault);
1253        return false;
1254    }
1255
1256    updateComInstStats(head_inst);
1257
1258    if (FullSystem) {
1259        if (thread[tid]->profile) {
1260            thread[tid]->profilePC = head_inst->instAddr();
1261            ProfileNode *node = thread[tid]->profile->consume(
1262                    thread[tid]->getTC(), head_inst->staticInst);
1263
1264            if (node)
1265                thread[tid]->profileNode = node;
1266        }
1267        if (CPA::available()) {
1268            if (head_inst->isControl()) {
1269                ThreadContext *tc = thread[tid]->getTC();
1270                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1271            }
1272        }
1273    }
1274    DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1275            head_inst->seqNum, head_inst->pcState());
1276    if (head_inst->traceData) {
1277        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1278        head_inst->traceData->setCPSeq(thread[tid]->numOp);
1279        head_inst->traceData->dump();
1280        delete head_inst->traceData;
1281        head_inst->traceData = NULL;
1282    }
1283    if (head_inst->isReturn()) {
1284        DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1285                        head_inst->seqNum, head_inst->pcState());
1286    }
1287
1288    // Update the commit rename map
1289    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1290        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1291                                 head_inst->renamedDestRegIdx(i));
1292    }
1293
1294    // Finally clear the head ROB entry.
1295    rob->retireHead(tid);
1296
1297#if TRACING_ON
1298    if (DTRACE(O3PipeView)) {
1299        head_inst->commitTick = curTick() - head_inst->fetchTick;
1300    }
1301#endif
1302
1303    // If this was a store, record it for this cycle.
1304    if (head_inst->isStore())
1305        committedStores[tid] = true;
1306
1307    // Return true to indicate that we have committed an instruction.
1308    return true;
1309}
1310
1311template <class Impl>
1312void
1313DefaultCommit<Impl>::getInsts()
1314{
1315    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1316
1317    // Read any renamed instructions and place them into the ROB.
1318    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1319
1320    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1321        const DynInstPtr &inst = fromRename->insts[inst_num];
1322        ThreadID tid = inst->threadNumber;
1323
1324        if (!inst->isSquashed() &&
1325            commitStatus[tid] != ROBSquashing &&
1326            commitStatus[tid] != TrapPending) {
1327            changedROBNumEntries[tid] = true;
1328
1329            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1330                    inst->pcState(), inst->seqNum, tid);
1331
1332            rob->insertInst(inst);
1333
1334            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1335
1336            youngestSeqNum[tid] = inst->seqNum;
1337        } else {
1338            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1339                    "squashed, skipping.\n",
1340                    inst->pcState(), inst->seqNum, tid);
1341        }
1342    }
1343}
1344
1345template <class Impl>
1346void
1347DefaultCommit<Impl>::markCompletedInsts()
1348{
1349    // Grab completed insts out of the IEW instruction queue, and mark
1350    // instructions completed within the ROB.
1351    for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1352        assert(fromIEW->insts[inst_num]);
1353        if (!fromIEW->insts[inst_num]->isSquashed()) {
1354            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1355                    "within ROB.\n",
1356                    fromIEW->insts[inst_num]->threadNumber,
1357                    fromIEW->insts[inst_num]->pcState(),
1358                    fromIEW->insts[inst_num]->seqNum);
1359
1360            // Mark the instruction as ready to commit.
1361            fromIEW->insts[inst_num]->setCanCommit();
1362        }
1363    }
1364}
1365
1366template <class Impl>
1367void
1368DefaultCommit<Impl>::updateComInstStats(const DynInstPtr &inst)
1369{
1370    ThreadID tid = inst->threadNumber;
1371
1372    if (!inst->isMicroop() || inst->isLastMicroop())
1373        instsCommitted[tid]++;
1374    opsCommitted[tid]++;
1375
1376    // To match the old model, don't count nops and instruction
1377    // prefetches towards the total commit count.
1378    if (!inst->isNop() && !inst->isInstPrefetch()) {
1379        cpu->instDone(tid, inst);
1380    }
1381
1382    //
1383    //  Control Instructions
1384    //
1385    if (inst->isControl())
1386        statComBranches[tid]++;
1387
1388    //
1389    //  Memory references
1390    //
1391    if (inst->isMemRef()) {
1392        statComRefs[tid]++;
1393
1394        if (inst->isLoad()) {
1395            statComLoads[tid]++;
1396        }
1397    }
1398
1399    if (inst->isMemBarrier()) {
1400        statComMembars[tid]++;
1401    }
1402
1403    // Integer Instruction
1404    if (inst->isInteger())
1405        statComInteger[tid]++;
1406
1407    // Floating Point Instruction
1408    if (inst->isFloating())
1409        statComFloating[tid]++;
1410    // Vector Instruction
1411    if (inst->isVector())
1412        statComVector[tid]++;
1413
1414    // Function Calls
1415    if (inst->isCall())
1416        statComFunctionCalls[tid]++;
1417
1418}
1419
1420////////////////////////////////////////
1421//                                    //
1422//  SMT COMMIT POLICY MAINTAINED HERE //
1423//                                    //
1424////////////////////////////////////////
1425template <class Impl>
1426ThreadID
1427DefaultCommit<Impl>::getCommittingThread()
1428{
1429    if (numThreads > 1) {
1430        switch (commitPolicy) {
1431
1432          case Aggressive:
1433            //If Policy is Aggressive, commit will call
1434            //this function multiple times per
1435            //cycle
1436            return oldestReady();
1437
1438          case RoundRobin:
1439            return roundRobin();
1440
1441          case OldestReady:
1442            return oldestReady();
1443
1444          default:
1445            return InvalidThreadID;
1446        }
1447    } else {
1448        assert(!activeThreads->empty());
1449        ThreadID tid = activeThreads->front();
1450
1451        if (commitStatus[tid] == Running ||
1452            commitStatus[tid] == Idle ||
1453            commitStatus[tid] == FetchTrapPending) {
1454            return tid;
1455        } else {
1456            return InvalidThreadID;
1457        }
1458    }
1459}
1460
1461template<class Impl>
1462ThreadID
1463DefaultCommit<Impl>::roundRobin()
1464{
1465    list<ThreadID>::iterator pri_iter = priority_list.begin();
1466    list<ThreadID>::iterator end      = priority_list.end();
1467
1468    while (pri_iter != end) {
1469        ThreadID tid = *pri_iter;
1470
1471        if (commitStatus[tid] == Running ||
1472            commitStatus[tid] == Idle ||
1473            commitStatus[tid] == FetchTrapPending) {
1474
1475            if (rob->isHeadReady(tid)) {
1476                priority_list.erase(pri_iter);
1477                priority_list.push_back(tid);
1478
1479                return tid;
1480            }
1481        }
1482
1483        pri_iter++;
1484    }
1485
1486    return InvalidThreadID;
1487}
1488
1489template<class Impl>
1490ThreadID
1491DefaultCommit<Impl>::oldestReady()
1492{
1493    unsigned oldest = 0;
1494    bool first = true;
1495
1496    list<ThreadID>::iterator threads = activeThreads->begin();
1497    list<ThreadID>::iterator end = activeThreads->end();
1498
1499    while (threads != end) {
1500        ThreadID tid = *threads++;
1501
1502        if (!rob->isEmpty(tid) &&
1503            (commitStatus[tid] == Running ||
1504             commitStatus[tid] == Idle ||
1505             commitStatus[tid] == FetchTrapPending)) {
1506
1507            if (rob->isHeadReady(tid)) {
1508
1509                const DynInstPtr &head_inst = rob->readHeadInst(tid);
1510
1511                if (first) {
1512                    oldest = tid;
1513                    first = false;
1514                } else if (head_inst->seqNum < oldest) {
1515                    oldest = tid;
1516                }
1517            }
1518        }
1519    }
1520
1521    if (!first) {
1522        return oldest;
1523    } else {
1524        return InvalidThreadID;
1525    }
1526}
1527
1528#endif//__CPU_O3_COMMIT_IMPL_HH__
1529