commit_impl.hh revision 10328:867b536a68be
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43#ifndef __CPU_O3_COMMIT_IMPL_HH__ 44#define __CPU_O3_COMMIT_IMPL_HH__ 45 46#include <algorithm> 47#include <set> 48#include <string> 49 50#include "arch/utility.hh" 51#include "base/loader/symtab.hh" 52#include "base/cp_annotate.hh" 53#include "config/the_isa.hh" 54#include "cpu/checker/cpu.hh" 55#include "cpu/o3/commit.hh" 56#include "cpu/o3/thread_state.hh" 57#include "cpu/base.hh" 58#include "cpu/exetrace.hh" 59#include "cpu/timebuf.hh" 60#include "debug/Activity.hh" 61#include "debug/Commit.hh" 62#include "debug/CommitRate.hh" 63#include "debug/Drain.hh" 64#include "debug/ExecFaulting.hh" 65#include "debug/O3PipeView.hh" 66#include "params/DerivO3CPU.hh" 67#include "sim/faults.hh" 68#include "sim/full_system.hh" 69 70using namespace std; 71 72template <class Impl> 73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 74 ThreadID _tid) 75 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 76{ 77} 78 79template <class Impl> 80void 81DefaultCommit<Impl>::TrapEvent::process() 82{ 83 // This will get reset by commit if it was switched out at the 84 // time of this event processing. 85 commit->trapSquash[tid] = true; 86} 87 88template <class Impl> 89const char * 90DefaultCommit<Impl>::TrapEvent::description() const 91{ 92 return "Trap"; 93} 94 95template <class Impl> 96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 97 : cpu(_cpu), 98 squashCounter(0), 99 iewToCommitDelay(params->iewToCommitDelay), 100 commitToIEWDelay(params->commitToIEWDelay), 101 renameToROBDelay(params->renameToROBDelay), 102 fetchToCommitDelay(params->commitToFetchDelay), 103 renameWidth(params->renameWidth), 104 commitWidth(params->commitWidth), 105 numThreads(params->numThreads), 106 drainPending(false), 107 trapLatency(params->trapLatency), 108 canHandleInterrupts(true), 109 avoidQuiesceLiveLock(false) 110{ 111 if (commitWidth > Impl::MaxWidth) 112 fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 113 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 114 commitWidth, static_cast<int>(Impl::MaxWidth)); 115 116 _status = Active; 117 _nextStatus = Inactive; 118 std::string policy = params->smtCommitPolicy; 119 120 //Convert string to lowercase 121 std::transform(policy.begin(), policy.end(), policy.begin(), 122 (int(*)(int)) tolower); 123 124 //Assign commit policy 125 if (policy == "aggressive"){ 126 commitPolicy = Aggressive; 127 128 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 129 } else if (policy == "roundrobin"){ 130 commitPolicy = RoundRobin; 131 132 //Set-Up Priority List 133 for (ThreadID tid = 0; tid < numThreads; tid++) { 134 priority_list.push_back(tid); 135 } 136 137 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 138 } else if (policy == "oldestready"){ 139 commitPolicy = OldestReady; 140 141 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 142 } else { 143 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 144 "RoundRobin,OldestReady}"); 145 } 146 147 for (ThreadID tid = 0; tid < numThreads; tid++) { 148 commitStatus[tid] = Idle; 149 changedROBNumEntries[tid] = false; 150 checkEmptyROB[tid] = false; 151 trapInFlight[tid] = false; 152 committedStores[tid] = false; 153 trapSquash[tid] = false; 154 tcSquash[tid] = false; 155 pc[tid].set(0); 156 lastCommitedSeqNum[tid] = 0; 157 squashAfterInst[tid] = NULL; 158 } 159 interrupt = NoFault; 160} 161 162template <class Impl> 163std::string 164DefaultCommit<Impl>::name() const 165{ 166 return cpu->name() + ".commit"; 167} 168 169template <class Impl> 170void 171DefaultCommit<Impl>::regProbePoints() 172{ 173 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 174 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 175} 176 177template <class Impl> 178void 179DefaultCommit<Impl>::regStats() 180{ 181 using namespace Stats; 182 commitSquashedInsts 183 .name(name() + ".commitSquashedInsts") 184 .desc("The number of squashed insts skipped by commit") 185 .prereq(commitSquashedInsts); 186 commitSquashEvents 187 .name(name() + ".commitSquashEvents") 188 .desc("The number of times commit is told to squash") 189 .prereq(commitSquashEvents); 190 commitNonSpecStalls 191 .name(name() + ".commitNonSpecStalls") 192 .desc("The number of times commit has been forced to stall to " 193 "communicate backwards") 194 .prereq(commitNonSpecStalls); 195 branchMispredicts 196 .name(name() + ".branchMispredicts") 197 .desc("The number of times a branch was mispredicted") 198 .prereq(branchMispredicts); 199 numCommittedDist 200 .init(0,commitWidth,1) 201 .name(name() + ".committed_per_cycle") 202 .desc("Number of insts commited each cycle") 203 .flags(Stats::pdf) 204 ; 205 206 instsCommitted 207 .init(cpu->numThreads) 208 .name(name() + ".committedInsts") 209 .desc("Number of instructions committed") 210 .flags(total) 211 ; 212 213 opsCommitted 214 .init(cpu->numThreads) 215 .name(name() + ".committedOps") 216 .desc("Number of ops (including micro ops) committed") 217 .flags(total) 218 ; 219 220 statComSwp 221 .init(cpu->numThreads) 222 .name(name() + ".swp_count") 223 .desc("Number of s/w prefetches committed") 224 .flags(total) 225 ; 226 227 statComRefs 228 .init(cpu->numThreads) 229 .name(name() + ".refs") 230 .desc("Number of memory references committed") 231 .flags(total) 232 ; 233 234 statComLoads 235 .init(cpu->numThreads) 236 .name(name() + ".loads") 237 .desc("Number of loads committed") 238 .flags(total) 239 ; 240 241 statComMembars 242 .init(cpu->numThreads) 243 .name(name() + ".membars") 244 .desc("Number of memory barriers committed") 245 .flags(total) 246 ; 247 248 statComBranches 249 .init(cpu->numThreads) 250 .name(name() + ".branches") 251 .desc("Number of branches committed") 252 .flags(total) 253 ; 254 255 statComFloating 256 .init(cpu->numThreads) 257 .name(name() + ".fp_insts") 258 .desc("Number of committed floating point instructions.") 259 .flags(total) 260 ; 261 262 statComInteger 263 .init(cpu->numThreads) 264 .name(name()+".int_insts") 265 .desc("Number of committed integer instructions.") 266 .flags(total) 267 ; 268 269 statComFunctionCalls 270 .init(cpu->numThreads) 271 .name(name()+".function_calls") 272 .desc("Number of function calls committed.") 273 .flags(total) 274 ; 275 276 statCommittedInstType 277 .init(numThreads,Enums::Num_OpClass) 278 .name(name() + ".op_class") 279 .desc("Class of committed instruction") 280 .flags(total | pdf | dist) 281 ; 282 statCommittedInstType.ysubnames(Enums::OpClassStrings); 283 284 commitEligible 285 .init(cpu->numThreads) 286 .name(name() + ".bw_limited") 287 .desc("number of insts not committed due to BW limits") 288 .flags(total) 289 ; 290 291 commitEligibleSamples 292 .name(name() + ".bw_lim_events") 293 .desc("number cycles where commit BW limit reached") 294 ; 295} 296 297template <class Impl> 298void 299DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 300{ 301 thread = threads; 302} 303 304template <class Impl> 305void 306DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 307{ 308 timeBuffer = tb_ptr; 309 310 // Setup wire to send information back to IEW. 311 toIEW = timeBuffer->getWire(0); 312 313 // Setup wire to read data from IEW (for the ROB). 314 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 315} 316 317template <class Impl> 318void 319DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 320{ 321 fetchQueue = fq_ptr; 322 323 // Setup wire to get instructions from rename (for the ROB). 324 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 325} 326 327template <class Impl> 328void 329DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 330{ 331 renameQueue = rq_ptr; 332 333 // Setup wire to get instructions from rename (for the ROB). 334 fromRename = renameQueue->getWire(-renameToROBDelay); 335} 336 337template <class Impl> 338void 339DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 340{ 341 iewQueue = iq_ptr; 342 343 // Setup wire to get instructions from IEW. 344 fromIEW = iewQueue->getWire(-iewToCommitDelay); 345} 346 347template <class Impl> 348void 349DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 350{ 351 iewStage = iew_stage; 352} 353 354template<class Impl> 355void 356DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 357{ 358 activeThreads = at_ptr; 359} 360 361template <class Impl> 362void 363DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 364{ 365 for (ThreadID tid = 0; tid < numThreads; tid++) 366 renameMap[tid] = &rm_ptr[tid]; 367} 368 369template <class Impl> 370void 371DefaultCommit<Impl>::setROB(ROB *rob_ptr) 372{ 373 rob = rob_ptr; 374} 375 376template <class Impl> 377void 378DefaultCommit<Impl>::startupStage() 379{ 380 rob->setActiveThreads(activeThreads); 381 rob->resetEntries(); 382 383 // Broadcast the number of free entries. 384 for (ThreadID tid = 0; tid < numThreads; tid++) { 385 toIEW->commitInfo[tid].usedROB = true; 386 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 387 toIEW->commitInfo[tid].emptyROB = true; 388 } 389 390 // Commit must broadcast the number of free entries it has at the 391 // start of the simulation, so it starts as active. 392 cpu->activateStage(O3CPU::CommitIdx); 393 394 cpu->activityThisCycle(); 395} 396 397template <class Impl> 398void 399DefaultCommit<Impl>::drain() 400{ 401 drainPending = true; 402} 403 404template <class Impl> 405void 406DefaultCommit<Impl>::drainResume() 407{ 408 drainPending = false; 409} 410 411template <class Impl> 412void 413DefaultCommit<Impl>::drainSanityCheck() const 414{ 415 assert(isDrained()); 416 rob->drainSanityCheck(); 417} 418 419template <class Impl> 420bool 421DefaultCommit<Impl>::isDrained() const 422{ 423 /* Make sure no one is executing microcode. There are two reasons 424 * for this: 425 * - Hardware virtualized CPUs can't switch into the middle of a 426 * microcode sequence. 427 * - The current fetch implementation will most likely get very 428 * confused if it tries to start fetching an instruction that 429 * is executing in the middle of a ucode sequence that changes 430 * address mappings. This can happen on for example x86. 431 */ 432 for (ThreadID tid = 0; tid < numThreads; tid++) { 433 if (pc[tid].microPC() != 0) 434 return false; 435 } 436 437 /* Make sure that all instructions have finished committing before 438 * declaring the system as drained. We want the pipeline to be 439 * completely empty when we declare the CPU to be drained. This 440 * makes debugging easier since CPU handover and restoring from a 441 * checkpoint with a different CPU should have the same timing. 442 */ 443 return rob->isEmpty() && 444 interrupt == NoFault; 445} 446 447template <class Impl> 448void 449DefaultCommit<Impl>::takeOverFrom() 450{ 451 _status = Active; 452 _nextStatus = Inactive; 453 for (ThreadID tid = 0; tid < numThreads; tid++) { 454 commitStatus[tid] = Idle; 455 changedROBNumEntries[tid] = false; 456 trapSquash[tid] = false; 457 tcSquash[tid] = false; 458 squashAfterInst[tid] = NULL; 459 } 460 squashCounter = 0; 461 rob->takeOverFrom(); 462} 463 464template <class Impl> 465void 466DefaultCommit<Impl>::updateStatus() 467{ 468 // reset ROB changed variable 469 list<ThreadID>::iterator threads = activeThreads->begin(); 470 list<ThreadID>::iterator end = activeThreads->end(); 471 472 while (threads != end) { 473 ThreadID tid = *threads++; 474 475 changedROBNumEntries[tid] = false; 476 477 // Also check if any of the threads has a trap pending 478 if (commitStatus[tid] == TrapPending || 479 commitStatus[tid] == FetchTrapPending) { 480 _nextStatus = Active; 481 } 482 } 483 484 if (_nextStatus == Inactive && _status == Active) { 485 DPRINTF(Activity, "Deactivating stage.\n"); 486 cpu->deactivateStage(O3CPU::CommitIdx); 487 } else if (_nextStatus == Active && _status == Inactive) { 488 DPRINTF(Activity, "Activating stage.\n"); 489 cpu->activateStage(O3CPU::CommitIdx); 490 } 491 492 _status = _nextStatus; 493} 494 495template <class Impl> 496void 497DefaultCommit<Impl>::setNextStatus() 498{ 499 int squashes = 0; 500 501 list<ThreadID>::iterator threads = activeThreads->begin(); 502 list<ThreadID>::iterator end = activeThreads->end(); 503 504 while (threads != end) { 505 ThreadID tid = *threads++; 506 507 if (commitStatus[tid] == ROBSquashing) { 508 squashes++; 509 } 510 } 511 512 squashCounter = squashes; 513 514 // If commit is currently squashing, then it will have activity for the 515 // next cycle. Set its next status as active. 516 if (squashCounter) { 517 _nextStatus = Active; 518 } 519} 520 521template <class Impl> 522bool 523DefaultCommit<Impl>::changedROBEntries() 524{ 525 list<ThreadID>::iterator threads = activeThreads->begin(); 526 list<ThreadID>::iterator end = activeThreads->end(); 527 528 while (threads != end) { 529 ThreadID tid = *threads++; 530 531 if (changedROBNumEntries[tid]) { 532 return true; 533 } 534 } 535 536 return false; 537} 538 539template <class Impl> 540size_t 541DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 542{ 543 return rob->numFreeEntries(tid); 544} 545 546template <class Impl> 547void 548DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 549{ 550 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 551 552 TrapEvent *trap = new TrapEvent(this, tid); 553 554 cpu->schedule(trap, cpu->clockEdge(trapLatency)); 555 trapInFlight[tid] = true; 556 thread[tid]->trapPending = true; 557} 558 559template <class Impl> 560void 561DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 562{ 563 assert(!trapInFlight[tid]); 564 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 565 566 tcSquash[tid] = true; 567} 568 569template <class Impl> 570void 571DefaultCommit<Impl>::squashAll(ThreadID tid) 572{ 573 // If we want to include the squashing instruction in the squash, 574 // then use one older sequence number. 575 // Hopefully this doesn't mess things up. Basically I want to squash 576 // all instructions of this thread. 577 InstSeqNum squashed_inst = rob->isEmpty(tid) ? 578 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 579 580 // All younger instructions will be squashed. Set the sequence 581 // number as the youngest instruction in the ROB (0 in this case. 582 // Hopefully nothing breaks.) 583 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 584 585 rob->squash(squashed_inst, tid); 586 changedROBNumEntries[tid] = true; 587 588 // Send back the sequence number of the squashed instruction. 589 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 590 591 // Send back the squash signal to tell stages that they should 592 // squash. 593 toIEW->commitInfo[tid].squash = true; 594 595 // Send back the rob squashing signal so other stages know that 596 // the ROB is in the process of squashing. 597 toIEW->commitInfo[tid].robSquashing = true; 598 599 toIEW->commitInfo[tid].mispredictInst = NULL; 600 toIEW->commitInfo[tid].squashInst = NULL; 601 602 toIEW->commitInfo[tid].pc = pc[tid]; 603} 604 605template <class Impl> 606void 607DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 608{ 609 squashAll(tid); 610 611 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 612 613 thread[tid]->trapPending = false; 614 thread[tid]->noSquashFromTC = false; 615 trapInFlight[tid] = false; 616 617 trapSquash[tid] = false; 618 619 commitStatus[tid] = ROBSquashing; 620 cpu->activityThisCycle(); 621} 622 623template <class Impl> 624void 625DefaultCommit<Impl>::squashFromTC(ThreadID tid) 626{ 627 squashAll(tid); 628 629 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 630 631 thread[tid]->noSquashFromTC = false; 632 assert(!thread[tid]->trapPending); 633 634 commitStatus[tid] = ROBSquashing; 635 cpu->activityThisCycle(); 636 637 tcSquash[tid] = false; 638} 639 640template <class Impl> 641void 642DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 643{ 644 DPRINTF(Commit, "Squashing after squash after request, " 645 "restarting at PC %s\n", pc[tid]); 646 647 squashAll(tid); 648 // Make sure to inform the fetch stage of which instruction caused 649 // the squash. It'll try to re-fetch an instruction executing in 650 // microcode unless this is set. 651 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 652 squashAfterInst[tid] = NULL; 653 654 commitStatus[tid] = ROBSquashing; 655 cpu->activityThisCycle(); 656} 657 658template <class Impl> 659void 660DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst) 661{ 662 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 663 tid, head_inst->seqNum); 664 665 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 666 commitStatus[tid] = SquashAfterPending; 667 squashAfterInst[tid] = head_inst; 668} 669 670template <class Impl> 671void 672DefaultCommit<Impl>::tick() 673{ 674 wroteToTimeBuffer = false; 675 _nextStatus = Inactive; 676 677 if (activeThreads->empty()) 678 return; 679 680 list<ThreadID>::iterator threads = activeThreads->begin(); 681 list<ThreadID>::iterator end = activeThreads->end(); 682 683 // Check if any of the threads are done squashing. Change the 684 // status if they are done. 685 while (threads != end) { 686 ThreadID tid = *threads++; 687 688 // Clear the bit saying if the thread has committed stores 689 // this cycle. 690 committedStores[tid] = false; 691 692 if (commitStatus[tid] == ROBSquashing) { 693 694 if (rob->isDoneSquashing(tid)) { 695 commitStatus[tid] = Running; 696 } else { 697 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 698 " insts this cycle.\n", tid); 699 rob->doSquash(tid); 700 toIEW->commitInfo[tid].robSquashing = true; 701 wroteToTimeBuffer = true; 702 } 703 } 704 } 705 706 commit(); 707 708 markCompletedInsts(); 709 710 threads = activeThreads->begin(); 711 712 while (threads != end) { 713 ThreadID tid = *threads++; 714 715 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 716 // The ROB has more instructions it can commit. Its next status 717 // will be active. 718 _nextStatus = Active; 719 720 DynInstPtr inst = rob->readHeadInst(tid); 721 722 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 723 " ROB and ready to commit\n", 724 tid, inst->seqNum, inst->pcState()); 725 726 } else if (!rob->isEmpty(tid)) { 727 DynInstPtr inst = rob->readHeadInst(tid); 728 729 ppCommitStall->notify(inst); 730 731 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 732 "%s is head of ROB and not ready\n", 733 tid, inst->seqNum, inst->pcState()); 734 } 735 736 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 737 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 738 } 739 740 741 if (wroteToTimeBuffer) { 742 DPRINTF(Activity, "Activity This Cycle.\n"); 743 cpu->activityThisCycle(); 744 } 745 746 updateStatus(); 747} 748 749template <class Impl> 750void 751DefaultCommit<Impl>::handleInterrupt() 752{ 753 // Verify that we still have an interrupt to handle 754 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 755 DPRINTF(Commit, "Pending interrupt is cleared by master before " 756 "it got handled. Restart fetching from the orig path.\n"); 757 toIEW->commitInfo[0].clearInterrupt = true; 758 interrupt = NoFault; 759 avoidQuiesceLiveLock = true; 760 return; 761 } 762 763 // Wait until all in flight instructions are finished before enterring 764 // the interrupt. 765 if (canHandleInterrupts && cpu->instList.empty()) { 766 // Squash or record that I need to squash this cycle if 767 // an interrupt needed to be handled. 768 DPRINTF(Commit, "Interrupt detected.\n"); 769 770 // Clear the interrupt now that it's going to be handled 771 toIEW->commitInfo[0].clearInterrupt = true; 772 773 assert(!thread[0]->noSquashFromTC); 774 thread[0]->noSquashFromTC = true; 775 776 if (cpu->checker) { 777 cpu->checker->handlePendingInt(); 778 } 779 780 // CPU will handle interrupt. Note that we ignore the local copy of 781 // interrupt. This is because the local copy may no longer be the 782 // interrupt that the interrupt controller thinks is being handled. 783 cpu->processInterrupts(cpu->getInterrupts()); 784 785 thread[0]->noSquashFromTC = false; 786 787 commitStatus[0] = TrapPending; 788 789 // Generate trap squash event. 790 generateTrapEvent(0); 791 792 interrupt = NoFault; 793 avoidQuiesceLiveLock = false; 794 } else { 795 DPRINTF(Commit, "Interrupt pending: instruction is %sin " 796 "flight, ROB is %sempty\n", 797 canHandleInterrupts ? "not " : "", 798 cpu->instList.empty() ? "" : "not " ); 799 } 800} 801 802template <class Impl> 803void 804DefaultCommit<Impl>::propagateInterrupt() 805{ 806 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 807 tcSquash[0]) 808 return; 809 810 // Process interrupts if interrupts are enabled, not in PAL 811 // mode, and no other traps or external squashes are currently 812 // pending. 813 // @todo: Allow other threads to handle interrupts. 814 815 // Get any interrupt that happened 816 interrupt = cpu->getInterrupts(); 817 818 // Tell fetch that there is an interrupt pending. This 819 // will make fetch wait until it sees a non PAL-mode PC, 820 // at which point it stops fetching instructions. 821 if (interrupt != NoFault) 822 toIEW->commitInfo[0].interruptPending = true; 823} 824 825template <class Impl> 826void 827DefaultCommit<Impl>::commit() 828{ 829 if (FullSystem) { 830 // Check if we have a interrupt and get read to handle it 831 if (cpu->checkInterrupts(cpu->tcBase(0))) 832 propagateInterrupt(); 833 } 834 835 //////////////////////////////////// 836 // Check for any possible squashes, handle them first 837 //////////////////////////////////// 838 list<ThreadID>::iterator threads = activeThreads->begin(); 839 list<ThreadID>::iterator end = activeThreads->end(); 840 841 while (threads != end) { 842 ThreadID tid = *threads++; 843 844 // Not sure which one takes priority. I think if we have 845 // both, that's a bad sign. 846 if (trapSquash[tid]) { 847 assert(!tcSquash[tid]); 848 squashFromTrap(tid); 849 } else if (tcSquash[tid]) { 850 assert(commitStatus[tid] != TrapPending); 851 squashFromTC(tid); 852 } else if (commitStatus[tid] == SquashAfterPending) { 853 // A squash from the previous cycle of the commit stage (i.e., 854 // commitInsts() called squashAfter) is pending. Squash the 855 // thread now. 856 squashFromSquashAfter(tid); 857 } 858 859 // Squashed sequence number must be older than youngest valid 860 // instruction in the ROB. This prevents squashes from younger 861 // instructions overriding squashes from older instructions. 862 if (fromIEW->squash[tid] && 863 commitStatus[tid] != TrapPending && 864 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 865 866 if (fromIEW->mispredictInst[tid]) { 867 DPRINTF(Commit, 868 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 869 tid, 870 fromIEW->mispredictInst[tid]->instAddr(), 871 fromIEW->squashedSeqNum[tid]); 872 } else { 873 DPRINTF(Commit, 874 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 875 tid, fromIEW->squashedSeqNum[tid]); 876 } 877 878 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 879 tid, 880 fromIEW->pc[tid].nextInstAddr()); 881 882 commitStatus[tid] = ROBSquashing; 883 884 // If we want to include the squashing instruction in the squash, 885 // then use one older sequence number. 886 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 887 888 if (fromIEW->includeSquashInst[tid]) { 889 squashed_inst--; 890 } 891 892 // All younger instructions will be squashed. Set the sequence 893 // number as the youngest instruction in the ROB. 894 youngestSeqNum[tid] = squashed_inst; 895 896 rob->squash(squashed_inst, tid); 897 changedROBNumEntries[tid] = true; 898 899 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 900 901 toIEW->commitInfo[tid].squash = true; 902 903 // Send back the rob squashing signal so other stages know that 904 // the ROB is in the process of squashing. 905 toIEW->commitInfo[tid].robSquashing = true; 906 907 toIEW->commitInfo[tid].mispredictInst = 908 fromIEW->mispredictInst[tid]; 909 toIEW->commitInfo[tid].branchTaken = 910 fromIEW->branchTaken[tid]; 911 toIEW->commitInfo[tid].squashInst = 912 rob->findInst(tid, squashed_inst); 913 if (toIEW->commitInfo[tid].mispredictInst) { 914 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 915 toIEW->commitInfo[tid].branchTaken = true; 916 } 917 } 918 919 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 920 921 if (toIEW->commitInfo[tid].mispredictInst) { 922 ++branchMispredicts; 923 } 924 } 925 926 } 927 928 setNextStatus(); 929 930 if (squashCounter != numThreads) { 931 // If we're not currently squashing, then get instructions. 932 getInsts(); 933 934 // Try to commit any instructions. 935 commitInsts(); 936 } 937 938 //Check for any activity 939 threads = activeThreads->begin(); 940 941 while (threads != end) { 942 ThreadID tid = *threads++; 943 944 if (changedROBNumEntries[tid]) { 945 toIEW->commitInfo[tid].usedROB = true; 946 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 947 948 wroteToTimeBuffer = true; 949 changedROBNumEntries[tid] = false; 950 if (rob->isEmpty(tid)) 951 checkEmptyROB[tid] = true; 952 } 953 954 // ROB is only considered "empty" for previous stages if: a) 955 // ROB is empty, b) there are no outstanding stores, c) IEW 956 // stage has received any information regarding stores that 957 // committed. 958 // c) is checked by making sure to not consider the ROB empty 959 // on the same cycle as when stores have been committed. 960 // @todo: Make this handle multi-cycle communication between 961 // commit and IEW. 962 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 963 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 964 checkEmptyROB[tid] = false; 965 toIEW->commitInfo[tid].usedROB = true; 966 toIEW->commitInfo[tid].emptyROB = true; 967 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 968 wroteToTimeBuffer = true; 969 } 970 971 } 972} 973 974template <class Impl> 975void 976DefaultCommit<Impl>::commitInsts() 977{ 978 //////////////////////////////////// 979 // Handle commit 980 // Note that commit will be handled prior to putting new 981 // instructions in the ROB so that the ROB only tries to commit 982 // instructions it has in this current cycle, and not instructions 983 // it is writing in during this cycle. Can't commit and squash 984 // things at the same time... 985 //////////////////////////////////// 986 987 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 988 989 unsigned num_committed = 0; 990 991 DynInstPtr head_inst; 992 993 // Commit as many instructions as possible until the commit bandwidth 994 // limit is reached, or it becomes impossible to commit any more. 995 while (num_committed < commitWidth) { 996 // Check for any interrupt that we've already squashed for 997 // and start processing it. 998 if (interrupt != NoFault) 999 handleInterrupt(); 1000 1001 int commit_thread = getCommittingThread(); 1002 1003 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 1004 break; 1005 1006 head_inst = rob->readHeadInst(commit_thread); 1007 1008 ThreadID tid = head_inst->threadNumber; 1009 1010 assert(tid == commit_thread); 1011 1012 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 1013 head_inst->seqNum, tid); 1014 1015 // If the head instruction is squashed, it is ready to retire 1016 // (be removed from the ROB) at any time. 1017 if (head_inst->isSquashed()) { 1018 1019 DPRINTF(Commit, "Retiring squashed instruction from " 1020 "ROB.\n"); 1021 1022 rob->retireHead(commit_thread); 1023 1024 ++commitSquashedInsts; 1025 1026 // Record that the number of ROB entries has changed. 1027 changedROBNumEntries[tid] = true; 1028 } else { 1029 pc[tid] = head_inst->pcState(); 1030 1031 // Increment the total number of non-speculative instructions 1032 // executed. 1033 // Hack for now: it really shouldn't happen until after the 1034 // commit is deemed to be successful, but this count is needed 1035 // for syscalls. 1036 thread[tid]->funcExeInst++; 1037 1038 // Try to commit the head instruction. 1039 bool commit_success = commitHead(head_inst, num_committed); 1040 1041 if (commit_success) { 1042 ++num_committed; 1043 statCommittedInstType[tid][head_inst->opClass()]++; 1044 ppCommit->notify(head_inst); 1045 1046 changedROBNumEntries[tid] = true; 1047 1048 // Set the doneSeqNum to the youngest committed instruction. 1049 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 1050 1051 if (tid == 0) { 1052 canHandleInterrupts = (!head_inst->isDelayedCommit()) && 1053 ((THE_ISA != ALPHA_ISA) || 1054 (!(pc[0].instAddr() & 0x3))); 1055 } 1056 1057 // Updates misc. registers. 1058 head_inst->updateMiscRegs(); 1059 1060 // Check instruction execution if it successfully commits and 1061 // is not carrying a fault. 1062 if (cpu->checker) { 1063 cpu->checker->verify(head_inst); 1064 } 1065 1066 cpu->traceFunctions(pc[tid].instAddr()); 1067 1068 TheISA::advancePC(pc[tid], head_inst->staticInst); 1069 1070 // Keep track of the last sequence number commited 1071 lastCommitedSeqNum[tid] = head_inst->seqNum; 1072 1073 // If this is an instruction that doesn't play nicely with 1074 // others squash everything and restart fetch 1075 if (head_inst->isSquashAfter()) 1076 squashAfter(tid, head_inst); 1077 1078 if (drainPending) { 1079 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 1080 if (pc[tid].microPC() == 0 && interrupt == NoFault) { 1081 squashAfter(tid, head_inst); 1082 cpu->commitDrained(tid); 1083 } 1084 } 1085 1086 int count = 0; 1087 Addr oldpc; 1088 // Debug statement. Checks to make sure we're not 1089 // currently updating state while handling PC events. 1090 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending); 1091 do { 1092 oldpc = pc[tid].instAddr(); 1093 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1094 count++; 1095 } while (oldpc != pc[tid].instAddr()); 1096 if (count > 1) { 1097 DPRINTF(Commit, 1098 "PC skip function event, stopping commit\n"); 1099 break; 1100 } 1101 1102 // Check if an instruction just enabled interrupts and we've 1103 // previously had an interrupt pending that was not handled 1104 // because interrupts were subsequently disabled before the 1105 // pipeline reached a place to handle the interrupt. In that 1106 // case squash now to make sure the interrupt is handled. 1107 // 1108 // If we don't do this, we might end up in a live lock situation 1109 if (!interrupt && avoidQuiesceLiveLock && 1110 (!head_inst->isMicroop() || head_inst->isLastMicroop()) && 1111 cpu->checkInterrupts(cpu->tcBase(0))) 1112 squashAfter(tid, head_inst); 1113 } else { 1114 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1115 "[tid:%i] [sn:%i].\n", 1116 head_inst->pcState(), tid ,head_inst->seqNum); 1117 break; 1118 } 1119 } 1120 } 1121 1122 DPRINTF(CommitRate, "%i\n", num_committed); 1123 numCommittedDist.sample(num_committed); 1124 1125 if (num_committed == commitWidth) { 1126 commitEligibleSamples++; 1127 } 1128} 1129 1130template <class Impl> 1131bool 1132DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1133{ 1134 assert(head_inst); 1135 1136 ThreadID tid = head_inst->threadNumber; 1137 1138 // If the instruction is not executed yet, then it will need extra 1139 // handling. Signal backwards that it should be executed. 1140 if (!head_inst->isExecuted()) { 1141 // Keep this number correct. We have not yet actually executed 1142 // and committed this instruction. 1143 thread[tid]->funcExeInst--; 1144 1145 // Make sure we are only trying to commit un-executed instructions we 1146 // think are possible. 1147 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 1148 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 1149 (head_inst->isLoad() && head_inst->uncacheable())); 1150 1151 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1152 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1153 head_inst->seqNum, head_inst->pcState()); 1154 1155 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1156 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1157 return false; 1158 } 1159 1160 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1161 1162 // Change the instruction so it won't try to commit again until 1163 // it is executed. 1164 head_inst->clearCanCommit(); 1165 1166 if (head_inst->isLoad() && head_inst->uncacheable()) { 1167 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1168 head_inst->seqNum, head_inst->pcState()); 1169 toIEW->commitInfo[tid].uncached = true; 1170 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1171 } else { 1172 ++commitNonSpecStalls; 1173 } 1174 1175 return false; 1176 } 1177 1178 if (head_inst->isThreadSync()) { 1179 // Not handled for now. 1180 panic("Thread sync instructions are not handled yet.\n"); 1181 } 1182 1183 // Check if the instruction caused a fault. If so, trap. 1184 Fault inst_fault = head_inst->getFault(); 1185 1186 // Stores mark themselves as completed. 1187 if (!head_inst->isStore() && inst_fault == NoFault) { 1188 head_inst->setCompleted(); 1189 } 1190 1191 if (inst_fault != NoFault) { 1192 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1193 head_inst->seqNum, head_inst->pcState()); 1194 1195 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1196 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1197 return false; 1198 } 1199 1200 head_inst->setCompleted(); 1201 1202 // If instruction has faulted, let the checker execute it and 1203 // check if it sees the same fault and control flow. 1204 if (cpu->checker) { 1205 // Need to check the instruction before its fault is processed 1206 cpu->checker->verify(head_inst); 1207 } 1208 1209 assert(!thread[tid]->noSquashFromTC); 1210 1211 // Mark that we're in state update mode so that the trap's 1212 // execution doesn't generate extra squashes. 1213 thread[tid]->noSquashFromTC = true; 1214 1215 // Execute the trap. Although it's slightly unrealistic in 1216 // terms of timing (as it doesn't wait for the full timing of 1217 // the trap event to complete before updating state), it's 1218 // needed to update the state as soon as possible. This 1219 // prevents external agents from changing any specific state 1220 // that the trap need. 1221 cpu->trap(inst_fault, tid, head_inst->staticInst); 1222 1223 // Exit state update mode to avoid accidental updating. 1224 thread[tid]->noSquashFromTC = false; 1225 1226 commitStatus[tid] = TrapPending; 1227 1228 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1229 head_inst->seqNum); 1230 if (head_inst->traceData) { 1231 if (DTRACE(ExecFaulting)) { 1232 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1233 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1234 head_inst->traceData->dump(); 1235 } 1236 delete head_inst->traceData; 1237 head_inst->traceData = NULL; 1238 } 1239 1240 // Generate trap squash event. 1241 generateTrapEvent(tid); 1242 return false; 1243 } 1244 1245 updateComInstStats(head_inst); 1246 1247 if (FullSystem) { 1248 if (thread[tid]->profile) { 1249 thread[tid]->profilePC = head_inst->instAddr(); 1250 ProfileNode *node = thread[tid]->profile->consume( 1251 thread[tid]->getTC(), head_inst->staticInst); 1252 1253 if (node) 1254 thread[tid]->profileNode = node; 1255 } 1256 if (CPA::available()) { 1257 if (head_inst->isControl()) { 1258 ThreadContext *tc = thread[tid]->getTC(); 1259 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1260 } 1261 } 1262 } 1263 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1264 head_inst->seqNum, head_inst->pcState()); 1265 if (head_inst->traceData) { 1266 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1267 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1268 head_inst->traceData->dump(); 1269 delete head_inst->traceData; 1270 head_inst->traceData = NULL; 1271 } 1272 if (head_inst->isReturn()) { 1273 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 1274 head_inst->seqNum, head_inst->pcState()); 1275 } 1276 1277 // Update the commit rename map 1278 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1279 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1280 head_inst->renamedDestRegIdx(i)); 1281 } 1282 1283 // Finally clear the head ROB entry. 1284 rob->retireHead(tid); 1285 1286#if TRACING_ON 1287 if (DTRACE(O3PipeView)) { 1288 head_inst->commitTick = curTick() - head_inst->fetchTick; 1289 } 1290#endif 1291 1292 // If this was a store, record it for this cycle. 1293 if (head_inst->isStore()) 1294 committedStores[tid] = true; 1295 1296 // Return true to indicate that we have committed an instruction. 1297 return true; 1298} 1299 1300template <class Impl> 1301void 1302DefaultCommit<Impl>::getInsts() 1303{ 1304 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1305 1306 // Read any renamed instructions and place them into the ROB. 1307 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1308 1309 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1310 DynInstPtr inst; 1311 1312 inst = fromRename->insts[inst_num]; 1313 ThreadID tid = inst->threadNumber; 1314 1315 if (!inst->isSquashed() && 1316 commitStatus[tid] != ROBSquashing && 1317 commitStatus[tid] != TrapPending) { 1318 changedROBNumEntries[tid] = true; 1319 1320 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1321 inst->pcState(), inst->seqNum, tid); 1322 1323 rob->insertInst(inst); 1324 1325 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1326 1327 youngestSeqNum[tid] = inst->seqNum; 1328 } else { 1329 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1330 "squashed, skipping.\n", 1331 inst->pcState(), inst->seqNum, tid); 1332 } 1333 } 1334} 1335 1336template <class Impl> 1337void 1338DefaultCommit<Impl>::markCompletedInsts() 1339{ 1340 // Grab completed insts out of the IEW instruction queue, and mark 1341 // instructions completed within the ROB. 1342 for (int inst_num = 0; 1343 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1344 ++inst_num) 1345 { 1346 if (!fromIEW->insts[inst_num]->isSquashed()) { 1347 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1348 "within ROB.\n", 1349 fromIEW->insts[inst_num]->threadNumber, 1350 fromIEW->insts[inst_num]->pcState(), 1351 fromIEW->insts[inst_num]->seqNum); 1352 1353 // Mark the instruction as ready to commit. 1354 fromIEW->insts[inst_num]->setCanCommit(); 1355 } 1356 } 1357} 1358 1359template <class Impl> 1360void 1361DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1362{ 1363 ThreadID tid = inst->threadNumber; 1364 1365 if (!inst->isMicroop() || inst->isLastMicroop()) 1366 instsCommitted[tid]++; 1367 opsCommitted[tid]++; 1368 1369 // To match the old model, don't count nops and instruction 1370 // prefetches towards the total commit count. 1371 if (!inst->isNop() && !inst->isInstPrefetch()) { 1372 cpu->instDone(tid, inst); 1373 } 1374 1375 // 1376 // Control Instructions 1377 // 1378 if (inst->isControl()) 1379 statComBranches[tid]++; 1380 1381 // 1382 // Memory references 1383 // 1384 if (inst->isMemRef()) { 1385 statComRefs[tid]++; 1386 1387 if (inst->isLoad()) { 1388 statComLoads[tid]++; 1389 } 1390 } 1391 1392 if (inst->isMemBarrier()) { 1393 statComMembars[tid]++; 1394 } 1395 1396 // Integer Instruction 1397 if (inst->isInteger()) 1398 statComInteger[tid]++; 1399 1400 // Floating Point Instruction 1401 if (inst->isFloating()) 1402 statComFloating[tid]++; 1403 1404 // Function Calls 1405 if (inst->isCall()) 1406 statComFunctionCalls[tid]++; 1407 1408} 1409 1410//////////////////////////////////////// 1411// // 1412// SMT COMMIT POLICY MAINTAINED HERE // 1413// // 1414//////////////////////////////////////// 1415template <class Impl> 1416ThreadID 1417DefaultCommit<Impl>::getCommittingThread() 1418{ 1419 if (numThreads > 1) { 1420 switch (commitPolicy) { 1421 1422 case Aggressive: 1423 //If Policy is Aggressive, commit will call 1424 //this function multiple times per 1425 //cycle 1426 return oldestReady(); 1427 1428 case RoundRobin: 1429 return roundRobin(); 1430 1431 case OldestReady: 1432 return oldestReady(); 1433 1434 default: 1435 return InvalidThreadID; 1436 } 1437 } else { 1438 assert(!activeThreads->empty()); 1439 ThreadID tid = activeThreads->front(); 1440 1441 if (commitStatus[tid] == Running || 1442 commitStatus[tid] == Idle || 1443 commitStatus[tid] == FetchTrapPending) { 1444 return tid; 1445 } else { 1446 return InvalidThreadID; 1447 } 1448 } 1449} 1450 1451template<class Impl> 1452ThreadID 1453DefaultCommit<Impl>::roundRobin() 1454{ 1455 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1456 list<ThreadID>::iterator end = priority_list.end(); 1457 1458 while (pri_iter != end) { 1459 ThreadID tid = *pri_iter; 1460 1461 if (commitStatus[tid] == Running || 1462 commitStatus[tid] == Idle || 1463 commitStatus[tid] == FetchTrapPending) { 1464 1465 if (rob->isHeadReady(tid)) { 1466 priority_list.erase(pri_iter); 1467 priority_list.push_back(tid); 1468 1469 return tid; 1470 } 1471 } 1472 1473 pri_iter++; 1474 } 1475 1476 return InvalidThreadID; 1477} 1478 1479template<class Impl> 1480ThreadID 1481DefaultCommit<Impl>::oldestReady() 1482{ 1483 unsigned oldest = 0; 1484 bool first = true; 1485 1486 list<ThreadID>::iterator threads = activeThreads->begin(); 1487 list<ThreadID>::iterator end = activeThreads->end(); 1488 1489 while (threads != end) { 1490 ThreadID tid = *threads++; 1491 1492 if (!rob->isEmpty(tid) && 1493 (commitStatus[tid] == Running || 1494 commitStatus[tid] == Idle || 1495 commitStatus[tid] == FetchTrapPending)) { 1496 1497 if (rob->isHeadReady(tid)) { 1498 1499 DynInstPtr head_inst = rob->readHeadInst(tid); 1500 1501 if (first) { 1502 oldest = tid; 1503 first = false; 1504 } else if (head_inst->seqNum < oldest) { 1505 oldest = tid; 1506 } 1507 } 1508 } 1509 } 1510 1511 if (!first) { 1512 return oldest; 1513 } else { 1514 return InvalidThreadID; 1515 } 1516} 1517 1518#endif//__CPU_O3_COMMIT_IMPL_HH__ 1519