commit_impl.hh revision 10164:2d2c60bda8b2
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43#ifndef __CPU_O3_COMMIT_IMPL_HH__ 44#define __CPU_O3_COMMIT_IMPL_HH__ 45 46#include <algorithm> 47#include <set> 48#include <string> 49 50#include "arch/utility.hh" 51#include "base/loader/symtab.hh" 52#include "base/cp_annotate.hh" 53#include "config/the_isa.hh" 54#include "cpu/checker/cpu.hh" 55#include "cpu/o3/commit.hh" 56#include "cpu/o3/thread_state.hh" 57#include "cpu/base.hh" 58#include "cpu/exetrace.hh" 59#include "cpu/timebuf.hh" 60#include "debug/Activity.hh" 61#include "debug/Commit.hh" 62#include "debug/CommitRate.hh" 63#include "debug/Drain.hh" 64#include "debug/ExecFaulting.hh" 65#include "debug/O3PipeView.hh" 66#include "params/DerivO3CPU.hh" 67#include "sim/faults.hh" 68#include "sim/full_system.hh" 69 70using namespace std; 71 72template <class Impl> 73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 74 ThreadID _tid) 75 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 76{ 77} 78 79template <class Impl> 80void 81DefaultCommit<Impl>::TrapEvent::process() 82{ 83 // This will get reset by commit if it was switched out at the 84 // time of this event processing. 85 commit->trapSquash[tid] = true; 86} 87 88template <class Impl> 89const char * 90DefaultCommit<Impl>::TrapEvent::description() const 91{ 92 return "Trap"; 93} 94 95template <class Impl> 96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 97 : cpu(_cpu), 98 squashCounter(0), 99 iewToCommitDelay(params->iewToCommitDelay), 100 commitToIEWDelay(params->commitToIEWDelay), 101 renameToROBDelay(params->renameToROBDelay), 102 fetchToCommitDelay(params->commitToFetchDelay), 103 renameWidth(params->renameWidth), 104 commitWidth(params->commitWidth), 105 numThreads(params->numThreads), 106 drainPending(false), 107 trapLatency(params->trapLatency), 108 canHandleInterrupts(true), 109 avoidQuiesceLiveLock(false) 110{ 111 _status = Active; 112 _nextStatus = Inactive; 113 std::string policy = params->smtCommitPolicy; 114 115 //Convert string to lowercase 116 std::transform(policy.begin(), policy.end(), policy.begin(), 117 (int(*)(int)) tolower); 118 119 //Assign commit policy 120 if (policy == "aggressive"){ 121 commitPolicy = Aggressive; 122 123 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 124 } else if (policy == "roundrobin"){ 125 commitPolicy = RoundRobin; 126 127 //Set-Up Priority List 128 for (ThreadID tid = 0; tid < numThreads; tid++) { 129 priority_list.push_back(tid); 130 } 131 132 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 133 } else if (policy == "oldestready"){ 134 commitPolicy = OldestReady; 135 136 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 137 } else { 138 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 139 "RoundRobin,OldestReady}"); 140 } 141 142 for (ThreadID tid = 0; tid < numThreads; tid++) { 143 commitStatus[tid] = Idle; 144 changedROBNumEntries[tid] = false; 145 checkEmptyROB[tid] = false; 146 trapInFlight[tid] = false; 147 committedStores[tid] = false; 148 trapSquash[tid] = false; 149 tcSquash[tid] = false; 150 pc[tid].set(0); 151 lastCommitedSeqNum[tid] = 0; 152 squashAfterInst[tid] = NULL; 153 } 154 interrupt = NoFault; 155} 156 157template <class Impl> 158std::string 159DefaultCommit<Impl>::name() const 160{ 161 return cpu->name() + ".commit"; 162} 163 164template <class Impl> 165void 166DefaultCommit<Impl>::regProbePoints() 167{ 168 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 169 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 170} 171 172template <class Impl> 173void 174DefaultCommit<Impl>::regStats() 175{ 176 using namespace Stats; 177 commitSquashedInsts 178 .name(name() + ".commitSquashedInsts") 179 .desc("The number of squashed insts skipped by commit") 180 .prereq(commitSquashedInsts); 181 commitSquashEvents 182 .name(name() + ".commitSquashEvents") 183 .desc("The number of times commit is told to squash") 184 .prereq(commitSquashEvents); 185 commitNonSpecStalls 186 .name(name() + ".commitNonSpecStalls") 187 .desc("The number of times commit has been forced to stall to " 188 "communicate backwards") 189 .prereq(commitNonSpecStalls); 190 branchMispredicts 191 .name(name() + ".branchMispredicts") 192 .desc("The number of times a branch was mispredicted") 193 .prereq(branchMispredicts); 194 numCommittedDist 195 .init(0,commitWidth,1) 196 .name(name() + ".committed_per_cycle") 197 .desc("Number of insts commited each cycle") 198 .flags(Stats::pdf) 199 ; 200 201 instsCommitted 202 .init(cpu->numThreads) 203 .name(name() + ".committedInsts") 204 .desc("Number of instructions committed") 205 .flags(total) 206 ; 207 208 opsCommitted 209 .init(cpu->numThreads) 210 .name(name() + ".committedOps") 211 .desc("Number of ops (including micro ops) committed") 212 .flags(total) 213 ; 214 215 statComSwp 216 .init(cpu->numThreads) 217 .name(name() + ".swp_count") 218 .desc("Number of s/w prefetches committed") 219 .flags(total) 220 ; 221 222 statComRefs 223 .init(cpu->numThreads) 224 .name(name() + ".refs") 225 .desc("Number of memory references committed") 226 .flags(total) 227 ; 228 229 statComLoads 230 .init(cpu->numThreads) 231 .name(name() + ".loads") 232 .desc("Number of loads committed") 233 .flags(total) 234 ; 235 236 statComMembars 237 .init(cpu->numThreads) 238 .name(name() + ".membars") 239 .desc("Number of memory barriers committed") 240 .flags(total) 241 ; 242 243 statComBranches 244 .init(cpu->numThreads) 245 .name(name() + ".branches") 246 .desc("Number of branches committed") 247 .flags(total) 248 ; 249 250 statComFloating 251 .init(cpu->numThreads) 252 .name(name() + ".fp_insts") 253 .desc("Number of committed floating point instructions.") 254 .flags(total) 255 ; 256 257 statComInteger 258 .init(cpu->numThreads) 259 .name(name()+".int_insts") 260 .desc("Number of committed integer instructions.") 261 .flags(total) 262 ; 263 264 statComFunctionCalls 265 .init(cpu->numThreads) 266 .name(name()+".function_calls") 267 .desc("Number of function calls committed.") 268 .flags(total) 269 ; 270 271 commitEligible 272 .init(cpu->numThreads) 273 .name(name() + ".bw_limited") 274 .desc("number of insts not committed due to BW limits") 275 .flags(total) 276 ; 277 278 commitEligibleSamples 279 .name(name() + ".bw_lim_events") 280 .desc("number cycles where commit BW limit reached") 281 ; 282} 283 284template <class Impl> 285void 286DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 287{ 288 thread = threads; 289} 290 291template <class Impl> 292void 293DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 294{ 295 timeBuffer = tb_ptr; 296 297 // Setup wire to send information back to IEW. 298 toIEW = timeBuffer->getWire(0); 299 300 // Setup wire to read data from IEW (for the ROB). 301 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 302} 303 304template <class Impl> 305void 306DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 307{ 308 fetchQueue = fq_ptr; 309 310 // Setup wire to get instructions from rename (for the ROB). 311 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 312} 313 314template <class Impl> 315void 316DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 317{ 318 renameQueue = rq_ptr; 319 320 // Setup wire to get instructions from rename (for the ROB). 321 fromRename = renameQueue->getWire(-renameToROBDelay); 322} 323 324template <class Impl> 325void 326DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 327{ 328 iewQueue = iq_ptr; 329 330 // Setup wire to get instructions from IEW. 331 fromIEW = iewQueue->getWire(-iewToCommitDelay); 332} 333 334template <class Impl> 335void 336DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 337{ 338 iewStage = iew_stage; 339} 340 341template<class Impl> 342void 343DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 344{ 345 activeThreads = at_ptr; 346} 347 348template <class Impl> 349void 350DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 351{ 352 for (ThreadID tid = 0; tid < numThreads; tid++) 353 renameMap[tid] = &rm_ptr[tid]; 354} 355 356template <class Impl> 357void 358DefaultCommit<Impl>::setROB(ROB *rob_ptr) 359{ 360 rob = rob_ptr; 361} 362 363template <class Impl> 364void 365DefaultCommit<Impl>::startupStage() 366{ 367 rob->setActiveThreads(activeThreads); 368 rob->resetEntries(); 369 370 // Broadcast the number of free entries. 371 for (ThreadID tid = 0; tid < numThreads; tid++) { 372 toIEW->commitInfo[tid].usedROB = true; 373 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 374 toIEW->commitInfo[tid].emptyROB = true; 375 } 376 377 // Commit must broadcast the number of free entries it has at the 378 // start of the simulation, so it starts as active. 379 cpu->activateStage(O3CPU::CommitIdx); 380 381 cpu->activityThisCycle(); 382} 383 384template <class Impl> 385void 386DefaultCommit<Impl>::drain() 387{ 388 drainPending = true; 389} 390 391template <class Impl> 392void 393DefaultCommit<Impl>::drainResume() 394{ 395 drainPending = false; 396} 397 398template <class Impl> 399void 400DefaultCommit<Impl>::drainSanityCheck() const 401{ 402 assert(isDrained()); 403 rob->drainSanityCheck(); 404} 405 406template <class Impl> 407bool 408DefaultCommit<Impl>::isDrained() const 409{ 410 /* Make sure no one is executing microcode. There are two reasons 411 * for this: 412 * - Hardware virtualized CPUs can't switch into the middle of a 413 * microcode sequence. 414 * - The current fetch implementation will most likely get very 415 * confused if it tries to start fetching an instruction that 416 * is executing in the middle of a ucode sequence that changes 417 * address mappings. This can happen on for example x86. 418 */ 419 for (ThreadID tid = 0; tid < numThreads; tid++) { 420 if (pc[tid].microPC() != 0) 421 return false; 422 } 423 424 /* Make sure that all instructions have finished committing before 425 * declaring the system as drained. We want the pipeline to be 426 * completely empty when we declare the CPU to be drained. This 427 * makes debugging easier since CPU handover and restoring from a 428 * checkpoint with a different CPU should have the same timing. 429 */ 430 return rob->isEmpty() && 431 interrupt == NoFault; 432} 433 434template <class Impl> 435void 436DefaultCommit<Impl>::takeOverFrom() 437{ 438 _status = Active; 439 _nextStatus = Inactive; 440 for (ThreadID tid = 0; tid < numThreads; tid++) { 441 commitStatus[tid] = Idle; 442 changedROBNumEntries[tid] = false; 443 trapSquash[tid] = false; 444 tcSquash[tid] = false; 445 squashAfterInst[tid] = NULL; 446 } 447 squashCounter = 0; 448 rob->takeOverFrom(); 449} 450 451template <class Impl> 452void 453DefaultCommit<Impl>::updateStatus() 454{ 455 // reset ROB changed variable 456 list<ThreadID>::iterator threads = activeThreads->begin(); 457 list<ThreadID>::iterator end = activeThreads->end(); 458 459 while (threads != end) { 460 ThreadID tid = *threads++; 461 462 changedROBNumEntries[tid] = false; 463 464 // Also check if any of the threads has a trap pending 465 if (commitStatus[tid] == TrapPending || 466 commitStatus[tid] == FetchTrapPending) { 467 _nextStatus = Active; 468 } 469 } 470 471 if (_nextStatus == Inactive && _status == Active) { 472 DPRINTF(Activity, "Deactivating stage.\n"); 473 cpu->deactivateStage(O3CPU::CommitIdx); 474 } else if (_nextStatus == Active && _status == Inactive) { 475 DPRINTF(Activity, "Activating stage.\n"); 476 cpu->activateStage(O3CPU::CommitIdx); 477 } 478 479 _status = _nextStatus; 480} 481 482template <class Impl> 483void 484DefaultCommit<Impl>::setNextStatus() 485{ 486 int squashes = 0; 487 488 list<ThreadID>::iterator threads = activeThreads->begin(); 489 list<ThreadID>::iterator end = activeThreads->end(); 490 491 while (threads != end) { 492 ThreadID tid = *threads++; 493 494 if (commitStatus[tid] == ROBSquashing) { 495 squashes++; 496 } 497 } 498 499 squashCounter = squashes; 500 501 // If commit is currently squashing, then it will have activity for the 502 // next cycle. Set its next status as active. 503 if (squashCounter) { 504 _nextStatus = Active; 505 } 506} 507 508template <class Impl> 509bool 510DefaultCommit<Impl>::changedROBEntries() 511{ 512 list<ThreadID>::iterator threads = activeThreads->begin(); 513 list<ThreadID>::iterator end = activeThreads->end(); 514 515 while (threads != end) { 516 ThreadID tid = *threads++; 517 518 if (changedROBNumEntries[tid]) { 519 return true; 520 } 521 } 522 523 return false; 524} 525 526template <class Impl> 527size_t 528DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 529{ 530 return rob->numFreeEntries(tid); 531} 532 533template <class Impl> 534void 535DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 536{ 537 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 538 539 TrapEvent *trap = new TrapEvent(this, tid); 540 541 cpu->schedule(trap, cpu->clockEdge(trapLatency)); 542 trapInFlight[tid] = true; 543 thread[tid]->trapPending = true; 544} 545 546template <class Impl> 547void 548DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 549{ 550 assert(!trapInFlight[tid]); 551 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 552 553 tcSquash[tid] = true; 554} 555 556template <class Impl> 557void 558DefaultCommit<Impl>::squashAll(ThreadID tid) 559{ 560 // If we want to include the squashing instruction in the squash, 561 // then use one older sequence number. 562 // Hopefully this doesn't mess things up. Basically I want to squash 563 // all instructions of this thread. 564 InstSeqNum squashed_inst = rob->isEmpty(tid) ? 565 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 566 567 // All younger instructions will be squashed. Set the sequence 568 // number as the youngest instruction in the ROB (0 in this case. 569 // Hopefully nothing breaks.) 570 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 571 572 rob->squash(squashed_inst, tid); 573 changedROBNumEntries[tid] = true; 574 575 // Send back the sequence number of the squashed instruction. 576 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 577 578 // Send back the squash signal to tell stages that they should 579 // squash. 580 toIEW->commitInfo[tid].squash = true; 581 582 // Send back the rob squashing signal so other stages know that 583 // the ROB is in the process of squashing. 584 toIEW->commitInfo[tid].robSquashing = true; 585 586 toIEW->commitInfo[tid].mispredictInst = NULL; 587 toIEW->commitInfo[tid].squashInst = NULL; 588 589 toIEW->commitInfo[tid].pc = pc[tid]; 590} 591 592template <class Impl> 593void 594DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 595{ 596 squashAll(tid); 597 598 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 599 600 thread[tid]->trapPending = false; 601 thread[tid]->noSquashFromTC = false; 602 trapInFlight[tid] = false; 603 604 trapSquash[tid] = false; 605 606 commitStatus[tid] = ROBSquashing; 607 cpu->activityThisCycle(); 608} 609 610template <class Impl> 611void 612DefaultCommit<Impl>::squashFromTC(ThreadID tid) 613{ 614 squashAll(tid); 615 616 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 617 618 thread[tid]->noSquashFromTC = false; 619 assert(!thread[tid]->trapPending); 620 621 commitStatus[tid] = ROBSquashing; 622 cpu->activityThisCycle(); 623 624 tcSquash[tid] = false; 625} 626 627template <class Impl> 628void 629DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 630{ 631 DPRINTF(Commit, "Squashing after squash after request, " 632 "restarting at PC %s\n", pc[tid]); 633 634 squashAll(tid); 635 // Make sure to inform the fetch stage of which instruction caused 636 // the squash. It'll try to re-fetch an instruction executing in 637 // microcode unless this is set. 638 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 639 squashAfterInst[tid] = NULL; 640 641 commitStatus[tid] = ROBSquashing; 642 cpu->activityThisCycle(); 643} 644 645template <class Impl> 646void 647DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst) 648{ 649 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 650 tid, head_inst->seqNum); 651 652 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 653 commitStatus[tid] = SquashAfterPending; 654 squashAfterInst[tid] = head_inst; 655} 656 657template <class Impl> 658void 659DefaultCommit<Impl>::tick() 660{ 661 wroteToTimeBuffer = false; 662 _nextStatus = Inactive; 663 664 if (activeThreads->empty()) 665 return; 666 667 list<ThreadID>::iterator threads = activeThreads->begin(); 668 list<ThreadID>::iterator end = activeThreads->end(); 669 670 // Check if any of the threads are done squashing. Change the 671 // status if they are done. 672 while (threads != end) { 673 ThreadID tid = *threads++; 674 675 // Clear the bit saying if the thread has committed stores 676 // this cycle. 677 committedStores[tid] = false; 678 679 if (commitStatus[tid] == ROBSquashing) { 680 681 if (rob->isDoneSquashing(tid)) { 682 commitStatus[tid] = Running; 683 } else { 684 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 685 " insts this cycle.\n", tid); 686 rob->doSquash(tid); 687 toIEW->commitInfo[tid].robSquashing = true; 688 wroteToTimeBuffer = true; 689 } 690 } 691 } 692 693 commit(); 694 695 markCompletedInsts(); 696 697 threads = activeThreads->begin(); 698 699 while (threads != end) { 700 ThreadID tid = *threads++; 701 702 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 703 // The ROB has more instructions it can commit. Its next status 704 // will be active. 705 _nextStatus = Active; 706 707 DynInstPtr inst = rob->readHeadInst(tid); 708 709 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 710 " ROB and ready to commit\n", 711 tid, inst->seqNum, inst->pcState()); 712 713 } else if (!rob->isEmpty(tid)) { 714 DynInstPtr inst = rob->readHeadInst(tid); 715 716 ppCommitStall->notify(inst); 717 718 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 719 "%s is head of ROB and not ready\n", 720 tid, inst->seqNum, inst->pcState()); 721 } 722 723 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 724 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 725 } 726 727 728 if (wroteToTimeBuffer) { 729 DPRINTF(Activity, "Activity This Cycle.\n"); 730 cpu->activityThisCycle(); 731 } 732 733 updateStatus(); 734} 735 736template <class Impl> 737void 738DefaultCommit<Impl>::handleInterrupt() 739{ 740 // Verify that we still have an interrupt to handle 741 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 742 DPRINTF(Commit, "Pending interrupt is cleared by master before " 743 "it got handled. Restart fetching from the orig path.\n"); 744 toIEW->commitInfo[0].clearInterrupt = true; 745 interrupt = NoFault; 746 avoidQuiesceLiveLock = true; 747 return; 748 } 749 750 // Wait until all in flight instructions are finished before enterring 751 // the interrupt. 752 if (canHandleInterrupts && cpu->instList.empty()) { 753 // Squash or record that I need to squash this cycle if 754 // an interrupt needed to be handled. 755 DPRINTF(Commit, "Interrupt detected.\n"); 756 757 // Clear the interrupt now that it's going to be handled 758 toIEW->commitInfo[0].clearInterrupt = true; 759 760 assert(!thread[0]->noSquashFromTC); 761 thread[0]->noSquashFromTC = true; 762 763 if (cpu->checker) { 764 cpu->checker->handlePendingInt(); 765 } 766 767 // CPU will handle interrupt. Note that we ignore the local copy of 768 // interrupt. This is because the local copy may no longer be the 769 // interrupt that the interrupt controller thinks is being handled. 770 cpu->processInterrupts(cpu->getInterrupts()); 771 772 thread[0]->noSquashFromTC = false; 773 774 commitStatus[0] = TrapPending; 775 776 // Generate trap squash event. 777 generateTrapEvent(0); 778 779 interrupt = NoFault; 780 avoidQuiesceLiveLock = false; 781 } else { 782 DPRINTF(Commit, "Interrupt pending: instruction is %sin " 783 "flight, ROB is %sempty\n", 784 canHandleInterrupts ? "not " : "", 785 cpu->instList.empty() ? "" : "not " ); 786 } 787} 788 789template <class Impl> 790void 791DefaultCommit<Impl>::propagateInterrupt() 792{ 793 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 794 tcSquash[0]) 795 return; 796 797 // Process interrupts if interrupts are enabled, not in PAL 798 // mode, and no other traps or external squashes are currently 799 // pending. 800 // @todo: Allow other threads to handle interrupts. 801 802 // Get any interrupt that happened 803 interrupt = cpu->getInterrupts(); 804 805 // Tell fetch that there is an interrupt pending. This 806 // will make fetch wait until it sees a non PAL-mode PC, 807 // at which point it stops fetching instructions. 808 if (interrupt != NoFault) 809 toIEW->commitInfo[0].interruptPending = true; 810} 811 812template <class Impl> 813void 814DefaultCommit<Impl>::commit() 815{ 816 if (FullSystem) { 817 // Check if we have a interrupt and get read to handle it 818 if (cpu->checkInterrupts(cpu->tcBase(0))) 819 propagateInterrupt(); 820 } 821 822 //////////////////////////////////// 823 // Check for any possible squashes, handle them first 824 //////////////////////////////////// 825 list<ThreadID>::iterator threads = activeThreads->begin(); 826 list<ThreadID>::iterator end = activeThreads->end(); 827 828 while (threads != end) { 829 ThreadID tid = *threads++; 830 831 // Not sure which one takes priority. I think if we have 832 // both, that's a bad sign. 833 if (trapSquash[tid] == true) { 834 assert(!tcSquash[tid]); 835 squashFromTrap(tid); 836 } else if (tcSquash[tid] == true) { 837 assert(commitStatus[tid] != TrapPending); 838 squashFromTC(tid); 839 } else if (commitStatus[tid] == SquashAfterPending) { 840 // A squash from the previous cycle of the commit stage (i.e., 841 // commitInsts() called squashAfter) is pending. Squash the 842 // thread now. 843 squashFromSquashAfter(tid); 844 } 845 846 // Squashed sequence number must be older than youngest valid 847 // instruction in the ROB. This prevents squashes from younger 848 // instructions overriding squashes from older instructions. 849 if (fromIEW->squash[tid] && 850 commitStatus[tid] != TrapPending && 851 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 852 853 if (fromIEW->mispredictInst[tid]) { 854 DPRINTF(Commit, 855 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 856 tid, 857 fromIEW->mispredictInst[tid]->instAddr(), 858 fromIEW->squashedSeqNum[tid]); 859 } else { 860 DPRINTF(Commit, 861 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 862 tid, fromIEW->squashedSeqNum[tid]); 863 } 864 865 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 866 tid, 867 fromIEW->pc[tid].nextInstAddr()); 868 869 commitStatus[tid] = ROBSquashing; 870 871 // If we want to include the squashing instruction in the squash, 872 // then use one older sequence number. 873 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 874 875 if (fromIEW->includeSquashInst[tid] == true) { 876 squashed_inst--; 877 } 878 879 // All younger instructions will be squashed. Set the sequence 880 // number as the youngest instruction in the ROB. 881 youngestSeqNum[tid] = squashed_inst; 882 883 rob->squash(squashed_inst, tid); 884 changedROBNumEntries[tid] = true; 885 886 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 887 888 toIEW->commitInfo[tid].squash = true; 889 890 // Send back the rob squashing signal so other stages know that 891 // the ROB is in the process of squashing. 892 toIEW->commitInfo[tid].robSquashing = true; 893 894 toIEW->commitInfo[tid].mispredictInst = 895 fromIEW->mispredictInst[tid]; 896 toIEW->commitInfo[tid].branchTaken = 897 fromIEW->branchTaken[tid]; 898 toIEW->commitInfo[tid].squashInst = 899 rob->findInst(tid, squashed_inst); 900 if (toIEW->commitInfo[tid].mispredictInst) { 901 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 902 toIEW->commitInfo[tid].branchTaken = true; 903 } 904 } 905 906 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 907 908 if (toIEW->commitInfo[tid].mispredictInst) { 909 ++branchMispredicts; 910 } 911 } 912 913 } 914 915 setNextStatus(); 916 917 if (squashCounter != numThreads) { 918 // If we're not currently squashing, then get instructions. 919 getInsts(); 920 921 // Try to commit any instructions. 922 commitInsts(); 923 } 924 925 //Check for any activity 926 threads = activeThreads->begin(); 927 928 while (threads != end) { 929 ThreadID tid = *threads++; 930 931 if (changedROBNumEntries[tid]) { 932 toIEW->commitInfo[tid].usedROB = true; 933 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 934 935 wroteToTimeBuffer = true; 936 changedROBNumEntries[tid] = false; 937 if (rob->isEmpty(tid)) 938 checkEmptyROB[tid] = true; 939 } 940 941 // ROB is only considered "empty" for previous stages if: a) 942 // ROB is empty, b) there are no outstanding stores, c) IEW 943 // stage has received any information regarding stores that 944 // committed. 945 // c) is checked by making sure to not consider the ROB empty 946 // on the same cycle as when stores have been committed. 947 // @todo: Make this handle multi-cycle communication between 948 // commit and IEW. 949 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 950 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 951 checkEmptyROB[tid] = false; 952 toIEW->commitInfo[tid].usedROB = true; 953 toIEW->commitInfo[tid].emptyROB = true; 954 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 955 wroteToTimeBuffer = true; 956 } 957 958 } 959} 960 961template <class Impl> 962void 963DefaultCommit<Impl>::commitInsts() 964{ 965 //////////////////////////////////// 966 // Handle commit 967 // Note that commit will be handled prior to putting new 968 // instructions in the ROB so that the ROB only tries to commit 969 // instructions it has in this current cycle, and not instructions 970 // it is writing in during this cycle. Can't commit and squash 971 // things at the same time... 972 //////////////////////////////////// 973 974 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 975 976 unsigned num_committed = 0; 977 978 DynInstPtr head_inst; 979 980 // Commit as many instructions as possible until the commit bandwidth 981 // limit is reached, or it becomes impossible to commit any more. 982 while (num_committed < commitWidth) { 983 // Check for any interrupt that we've already squashed for 984 // and start processing it. 985 if (interrupt != NoFault) 986 handleInterrupt(); 987 988 int commit_thread = getCommittingThread(); 989 990 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 991 break; 992 993 head_inst = rob->readHeadInst(commit_thread); 994 995 ThreadID tid = head_inst->threadNumber; 996 997 assert(tid == commit_thread); 998 999 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 1000 head_inst->seqNum, tid); 1001 1002 // If the head instruction is squashed, it is ready to retire 1003 // (be removed from the ROB) at any time. 1004 if (head_inst->isSquashed()) { 1005 1006 DPRINTF(Commit, "Retiring squashed instruction from " 1007 "ROB.\n"); 1008 1009 rob->retireHead(commit_thread); 1010 1011 ++commitSquashedInsts; 1012 1013 // Record that the number of ROB entries has changed. 1014 changedROBNumEntries[tid] = true; 1015 } else { 1016 pc[tid] = head_inst->pcState(); 1017 1018 // Increment the total number of non-speculative instructions 1019 // executed. 1020 // Hack for now: it really shouldn't happen until after the 1021 // commit is deemed to be successful, but this count is needed 1022 // for syscalls. 1023 thread[tid]->funcExeInst++; 1024 1025 // Try to commit the head instruction. 1026 bool commit_success = commitHead(head_inst, num_committed); 1027 1028 if (commit_success) { 1029 ++num_committed; 1030 ppCommit->notify(head_inst); 1031 1032 changedROBNumEntries[tid] = true; 1033 1034 // Set the doneSeqNum to the youngest committed instruction. 1035 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 1036 1037 if (tid == 0) { 1038 canHandleInterrupts = (!head_inst->isDelayedCommit()) && 1039 ((THE_ISA != ALPHA_ISA) || 1040 (!(pc[0].instAddr() & 0x3))); 1041 } 1042 1043 // Updates misc. registers. 1044 head_inst->updateMiscRegs(); 1045 1046 // Check instruction execution if it successfully commits and 1047 // is not carrying a fault. 1048 if (cpu->checker) { 1049 cpu->checker->verify(head_inst); 1050 } 1051 1052 cpu->traceFunctions(pc[tid].instAddr()); 1053 1054 TheISA::advancePC(pc[tid], head_inst->staticInst); 1055 1056 // Keep track of the last sequence number commited 1057 lastCommitedSeqNum[tid] = head_inst->seqNum; 1058 1059 // If this is an instruction that doesn't play nicely with 1060 // others squash everything and restart fetch 1061 if (head_inst->isSquashAfter()) 1062 squashAfter(tid, head_inst); 1063 1064 if (drainPending) { 1065 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 1066 if (pc[tid].microPC() == 0 && interrupt == NoFault) { 1067 squashAfter(tid, head_inst); 1068 cpu->commitDrained(tid); 1069 } 1070 } 1071 1072 int count = 0; 1073 Addr oldpc; 1074 // Debug statement. Checks to make sure we're not 1075 // currently updating state while handling PC events. 1076 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending); 1077 do { 1078 oldpc = pc[tid].instAddr(); 1079 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1080 count++; 1081 } while (oldpc != pc[tid].instAddr()); 1082 if (count > 1) { 1083 DPRINTF(Commit, 1084 "PC skip function event, stopping commit\n"); 1085 break; 1086 } 1087 1088 // Check if an instruction just enabled interrupts and we've 1089 // previously had an interrupt pending that was not handled 1090 // because interrupts were subsequently disabled before the 1091 // pipeline reached a place to handle the interrupt. In that 1092 // case squash now to make sure the interrupt is handled. 1093 // 1094 // If we don't do this, we might end up in a live lock situation 1095 if (!interrupt && avoidQuiesceLiveLock && 1096 (!head_inst->isMicroop() || head_inst->isLastMicroop()) && 1097 cpu->checkInterrupts(cpu->tcBase(0))) 1098 squashAfter(tid, head_inst); 1099 } else { 1100 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1101 "[tid:%i] [sn:%i].\n", 1102 head_inst->pcState(), tid ,head_inst->seqNum); 1103 break; 1104 } 1105 } 1106 } 1107 1108 DPRINTF(CommitRate, "%i\n", num_committed); 1109 numCommittedDist.sample(num_committed); 1110 1111 if (num_committed == commitWidth) { 1112 commitEligibleSamples++; 1113 } 1114} 1115 1116template <class Impl> 1117bool 1118DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1119{ 1120 assert(head_inst); 1121 1122 ThreadID tid = head_inst->threadNumber; 1123 1124 // If the instruction is not executed yet, then it will need extra 1125 // handling. Signal backwards that it should be executed. 1126 if (!head_inst->isExecuted()) { 1127 // Keep this number correct. We have not yet actually executed 1128 // and committed this instruction. 1129 thread[tid]->funcExeInst--; 1130 1131 // Make sure we are only trying to commit un-executed instructions we 1132 // think are possible. 1133 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 1134 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 1135 (head_inst->isLoad() && head_inst->uncacheable())); 1136 1137 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1138 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1139 head_inst->seqNum, head_inst->pcState()); 1140 1141 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1142 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1143 return false; 1144 } 1145 1146 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1147 1148 // Change the instruction so it won't try to commit again until 1149 // it is executed. 1150 head_inst->clearCanCommit(); 1151 1152 if (head_inst->isLoad() && head_inst->uncacheable()) { 1153 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1154 head_inst->seqNum, head_inst->pcState()); 1155 toIEW->commitInfo[tid].uncached = true; 1156 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1157 } else { 1158 ++commitNonSpecStalls; 1159 } 1160 1161 return false; 1162 } 1163 1164 if (head_inst->isThreadSync()) { 1165 // Not handled for now. 1166 panic("Thread sync instructions are not handled yet.\n"); 1167 } 1168 1169 // Check if the instruction caused a fault. If so, trap. 1170 Fault inst_fault = head_inst->getFault(); 1171 1172 // Stores mark themselves as completed. 1173 if (!head_inst->isStore() && inst_fault == NoFault) { 1174 head_inst->setCompleted(); 1175 } 1176 1177 if (inst_fault != NoFault) { 1178 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1179 head_inst->seqNum, head_inst->pcState()); 1180 1181 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1182 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1183 return false; 1184 } 1185 1186 head_inst->setCompleted(); 1187 1188 // If instruction has faulted, let the checker execute it and 1189 // check if it sees the same fault and control flow. 1190 if (cpu->checker) { 1191 // Need to check the instruction before its fault is processed 1192 cpu->checker->verify(head_inst); 1193 } 1194 1195 assert(!thread[tid]->noSquashFromTC); 1196 1197 // Mark that we're in state update mode so that the trap's 1198 // execution doesn't generate extra squashes. 1199 thread[tid]->noSquashFromTC = true; 1200 1201 // Execute the trap. Although it's slightly unrealistic in 1202 // terms of timing (as it doesn't wait for the full timing of 1203 // the trap event to complete before updating state), it's 1204 // needed to update the state as soon as possible. This 1205 // prevents external agents from changing any specific state 1206 // that the trap need. 1207 cpu->trap(inst_fault, tid, head_inst->staticInst); 1208 1209 // Exit state update mode to avoid accidental updating. 1210 thread[tid]->noSquashFromTC = false; 1211 1212 commitStatus[tid] = TrapPending; 1213 1214 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1215 head_inst->seqNum); 1216 if (head_inst->traceData) { 1217 if (DTRACE(ExecFaulting)) { 1218 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1219 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1220 head_inst->traceData->dump(); 1221 } 1222 delete head_inst->traceData; 1223 head_inst->traceData = NULL; 1224 } 1225 1226 // Generate trap squash event. 1227 generateTrapEvent(tid); 1228 return false; 1229 } 1230 1231 updateComInstStats(head_inst); 1232 1233 if (FullSystem) { 1234 if (thread[tid]->profile) { 1235 thread[tid]->profilePC = head_inst->instAddr(); 1236 ProfileNode *node = thread[tid]->profile->consume( 1237 thread[tid]->getTC(), head_inst->staticInst); 1238 1239 if (node) 1240 thread[tid]->profileNode = node; 1241 } 1242 if (CPA::available()) { 1243 if (head_inst->isControl()) { 1244 ThreadContext *tc = thread[tid]->getTC(); 1245 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1246 } 1247 } 1248 } 1249 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1250 head_inst->seqNum, head_inst->pcState()); 1251 if (head_inst->traceData) { 1252 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1253 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1254 head_inst->traceData->dump(); 1255 delete head_inst->traceData; 1256 head_inst->traceData = NULL; 1257 } 1258 if (head_inst->isReturn()) { 1259 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 1260 head_inst->seqNum, head_inst->pcState()); 1261 } 1262 1263 // Update the commit rename map 1264 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1265 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1266 head_inst->renamedDestRegIdx(i)); 1267 } 1268 1269 // Finally clear the head ROB entry. 1270 rob->retireHead(tid); 1271 1272#if TRACING_ON 1273 if (DTRACE(O3PipeView)) { 1274 head_inst->commitTick = curTick() - head_inst->fetchTick; 1275 } 1276#endif 1277 1278 // If this was a store, record it for this cycle. 1279 if (head_inst->isStore()) 1280 committedStores[tid] = true; 1281 1282 // Return true to indicate that we have committed an instruction. 1283 return true; 1284} 1285 1286template <class Impl> 1287void 1288DefaultCommit<Impl>::getInsts() 1289{ 1290 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1291 1292 // Read any renamed instructions and place them into the ROB. 1293 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1294 1295 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1296 DynInstPtr inst; 1297 1298 inst = fromRename->insts[inst_num]; 1299 ThreadID tid = inst->threadNumber; 1300 1301 if (!inst->isSquashed() && 1302 commitStatus[tid] != ROBSquashing && 1303 commitStatus[tid] != TrapPending) { 1304 changedROBNumEntries[tid] = true; 1305 1306 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1307 inst->pcState(), inst->seqNum, tid); 1308 1309 rob->insertInst(inst); 1310 1311 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1312 1313 youngestSeqNum[tid] = inst->seqNum; 1314 } else { 1315 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1316 "squashed, skipping.\n", 1317 inst->pcState(), inst->seqNum, tid); 1318 } 1319 } 1320} 1321 1322template <class Impl> 1323void 1324DefaultCommit<Impl>::skidInsert() 1325{ 1326 DPRINTF(Commit, "Attempting to any instructions from rename into " 1327 "skidBuffer.\n"); 1328 1329 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1330 DynInstPtr inst = fromRename->insts[inst_num]; 1331 1332 if (!inst->isSquashed()) { 1333 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 1334 "skidBuffer.\n", inst->pcState(), inst->seqNum, 1335 inst->threadNumber); 1336 skidBuffer.push(inst); 1337 } else { 1338 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1339 "squashed, skipping.\n", 1340 inst->pcState(), inst->seqNum, inst->threadNumber); 1341 } 1342 } 1343} 1344 1345template <class Impl> 1346void 1347DefaultCommit<Impl>::markCompletedInsts() 1348{ 1349 // Grab completed insts out of the IEW instruction queue, and mark 1350 // instructions completed within the ROB. 1351 for (int inst_num = 0; 1352 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1353 ++inst_num) 1354 { 1355 if (!fromIEW->insts[inst_num]->isSquashed()) { 1356 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1357 "within ROB.\n", 1358 fromIEW->insts[inst_num]->threadNumber, 1359 fromIEW->insts[inst_num]->pcState(), 1360 fromIEW->insts[inst_num]->seqNum); 1361 1362 // Mark the instruction as ready to commit. 1363 fromIEW->insts[inst_num]->setCanCommit(); 1364 } 1365 } 1366} 1367 1368template <class Impl> 1369bool 1370DefaultCommit<Impl>::robDoneSquashing() 1371{ 1372 list<ThreadID>::iterator threads = activeThreads->begin(); 1373 list<ThreadID>::iterator end = activeThreads->end(); 1374 1375 while (threads != end) { 1376 ThreadID tid = *threads++; 1377 1378 if (!rob->isDoneSquashing(tid)) 1379 return false; 1380 } 1381 1382 return true; 1383} 1384 1385template <class Impl> 1386void 1387DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1388{ 1389 ThreadID tid = inst->threadNumber; 1390 1391 if (!inst->isMicroop() || inst->isLastMicroop()) 1392 instsCommitted[tid]++; 1393 opsCommitted[tid]++; 1394 1395 // To match the old model, don't count nops and instruction 1396 // prefetches towards the total commit count. 1397 if (!inst->isNop() && !inst->isInstPrefetch()) { 1398 cpu->instDone(tid, inst); 1399 } 1400 1401 // 1402 // Control Instructions 1403 // 1404 if (inst->isControl()) 1405 statComBranches[tid]++; 1406 1407 // 1408 // Memory references 1409 // 1410 if (inst->isMemRef()) { 1411 statComRefs[tid]++; 1412 1413 if (inst->isLoad()) { 1414 statComLoads[tid]++; 1415 } 1416 } 1417 1418 if (inst->isMemBarrier()) { 1419 statComMembars[tid]++; 1420 } 1421 1422 // Integer Instruction 1423 if (inst->isInteger()) 1424 statComInteger[tid]++; 1425 1426 // Floating Point Instruction 1427 if (inst->isFloating()) 1428 statComFloating[tid]++; 1429 1430 // Function Calls 1431 if (inst->isCall()) 1432 statComFunctionCalls[tid]++; 1433 1434} 1435 1436//////////////////////////////////////// 1437// // 1438// SMT COMMIT POLICY MAINTAINED HERE // 1439// // 1440//////////////////////////////////////// 1441template <class Impl> 1442ThreadID 1443DefaultCommit<Impl>::getCommittingThread() 1444{ 1445 if (numThreads > 1) { 1446 switch (commitPolicy) { 1447 1448 case Aggressive: 1449 //If Policy is Aggressive, commit will call 1450 //this function multiple times per 1451 //cycle 1452 return oldestReady(); 1453 1454 case RoundRobin: 1455 return roundRobin(); 1456 1457 case OldestReady: 1458 return oldestReady(); 1459 1460 default: 1461 return InvalidThreadID; 1462 } 1463 } else { 1464 assert(!activeThreads->empty()); 1465 ThreadID tid = activeThreads->front(); 1466 1467 if (commitStatus[tid] == Running || 1468 commitStatus[tid] == Idle || 1469 commitStatus[tid] == FetchTrapPending) { 1470 return tid; 1471 } else { 1472 return InvalidThreadID; 1473 } 1474 } 1475} 1476 1477template<class Impl> 1478ThreadID 1479DefaultCommit<Impl>::roundRobin() 1480{ 1481 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1482 list<ThreadID>::iterator end = priority_list.end(); 1483 1484 while (pri_iter != end) { 1485 ThreadID tid = *pri_iter; 1486 1487 if (commitStatus[tid] == Running || 1488 commitStatus[tid] == Idle || 1489 commitStatus[tid] == FetchTrapPending) { 1490 1491 if (rob->isHeadReady(tid)) { 1492 priority_list.erase(pri_iter); 1493 priority_list.push_back(tid); 1494 1495 return tid; 1496 } 1497 } 1498 1499 pri_iter++; 1500 } 1501 1502 return InvalidThreadID; 1503} 1504 1505template<class Impl> 1506ThreadID 1507DefaultCommit<Impl>::oldestReady() 1508{ 1509 unsigned oldest = 0; 1510 bool first = true; 1511 1512 list<ThreadID>::iterator threads = activeThreads->begin(); 1513 list<ThreadID>::iterator end = activeThreads->end(); 1514 1515 while (threads != end) { 1516 ThreadID tid = *threads++; 1517 1518 if (!rob->isEmpty(tid) && 1519 (commitStatus[tid] == Running || 1520 commitStatus[tid] == Idle || 1521 commitStatus[tid] == FetchTrapPending)) { 1522 1523 if (rob->isHeadReady(tid)) { 1524 1525 DynInstPtr head_inst = rob->readHeadInst(tid); 1526 1527 if (first) { 1528 oldest = tid; 1529 first = false; 1530 } else if (head_inst->seqNum < oldest) { 1531 oldest = tid; 1532 } 1533 } 1534 } 1535 } 1536 1537 if (!first) { 1538 return oldest; 1539 } else { 1540 return InvalidThreadID; 1541 } 1542} 1543 1544#endif//__CPU_O3_COMMIT_IMPL_HH__ 1545