commit_impl.hh revision 9624
11689SN/A/* 29427SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412965Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#include <algorithm> 459516SAli.Saidi@ARM.com#include <set> 462329SN/A#include <string> 472292SN/A 483577Sgblack@eecs.umich.edu#include "arch/utility.hh" 498229Snate@binkert.org#include "base/loader/symtab.hh" 505953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 528887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 531717SN/A#include "cpu/o3/commit.hh" 542292SN/A#include "cpu/o3/thread_state.hh" 558662SAli.Saidi@ARM.com#include "cpu/base.hh" 568229Snate@binkert.org#include "cpu/exetrace.hh" 578229Snate@binkert.org#include "cpu/timebuf.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 598232Snate@binkert.org#include "debug/Commit.hh" 608232Snate@binkert.org#include "debug/CommitRate.hh" 619444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 628232Snate@binkert.org#include "debug/ExecFaulting.hh" 639527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 646221Snate@binkert.org#include "params/DerivO3CPU.hh" 658230Snate@binkert.org#include "sim/faults.hh" 668793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 672292SN/A 686221Snate@binkert.orgusing namespace std; 695529Snate@binkert.org 701061SN/Atemplate <class Impl> 712292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 726221Snate@binkert.org ThreadID _tid) 738581Ssteve.reinhardt@amd.com : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 741060SN/A{ 751060SN/A} 761060SN/A 771061SN/Atemplate <class Impl> 781060SN/Avoid 792292SN/ADefaultCommit<Impl>::TrapEvent::process() 801062SN/A{ 812316SN/A // This will get reset by commit if it was switched out at the 822316SN/A // time of this event processing. 832292SN/A commit->trapSquash[tid] = true; 842292SN/A} 852292SN/A 862292SN/Atemplate <class Impl> 872292SN/Aconst char * 885336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 892292SN/A{ 904873Sstever@eecs.umich.edu return "Trap"; 912292SN/A} 922292SN/A 932292SN/Atemplate <class Impl> 945529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 954329Sktlim@umich.edu : cpu(_cpu), 964329Sktlim@umich.edu squashCounter(0), 972292SN/A iewToCommitDelay(params->iewToCommitDelay), 982292SN/A commitToIEWDelay(params->commitToIEWDelay), 992292SN/A renameToROBDelay(params->renameToROBDelay), 1002292SN/A fetchToCommitDelay(params->commitToFetchDelay), 1012292SN/A renameWidth(params->renameWidth), 1022292SN/A commitWidth(params->commitWidth), 1035529Snate@binkert.org numThreads(params->numThreads), 1042843Sktlim@umich.edu drainPending(false), 1058823Snilay@cs.wisc.edu trapLatency(params->trapLatency), 1069513SAli.Saidi@ARM.com canHandleInterrupts(true), 1079513SAli.Saidi@ARM.com avoidQuiesceLiveLock(false) 1082292SN/A{ 1092292SN/A _status = Active; 1102292SN/A _nextStatus = Inactive; 1112980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1122292SN/A 1132292SN/A //Convert string to lowercase 1142292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1152292SN/A (int(*)(int)) tolower); 1162292SN/A 1172292SN/A //Assign commit policy 1182292SN/A if (policy == "aggressive"){ 1192292SN/A commitPolicy = Aggressive; 1202292SN/A 1218346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 1222292SN/A } else if (policy == "roundrobin"){ 1232292SN/A commitPolicy = RoundRobin; 1242292SN/A 1252292SN/A //Set-Up Priority List 1266221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1272292SN/A priority_list.push_back(tid); 1282292SN/A } 1292292SN/A 1308346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 1312292SN/A } else if (policy == "oldestready"){ 1322292SN/A commitPolicy = OldestReady; 1332292SN/A 1344329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1352292SN/A } else { 1362292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1372292SN/A "RoundRobin,OldestReady}"); 1382292SN/A } 1392292SN/A 1406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1416221Snate@binkert.org commitStatus[tid] = Idle; 1426221Snate@binkert.org changedROBNumEntries[tid] = false; 1436221Snate@binkert.org checkEmptyROB[tid] = false; 1446221Snate@binkert.org trapInFlight[tid] = false; 1456221Snate@binkert.org committedStores[tid] = false; 1466221Snate@binkert.org trapSquash[tid] = false; 1476221Snate@binkert.org tcSquash[tid] = false; 1487720Sgblack@eecs.umich.edu pc[tid].set(0); 1497855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = 0; 1509437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 1512292SN/A } 1523640Sktlim@umich.edu interrupt = NoFault; 1532292SN/A} 1542292SN/A 1552292SN/Atemplate <class Impl> 1562292SN/Astd::string 1572292SN/ADefaultCommit<Impl>::name() const 1582292SN/A{ 1592292SN/A return cpu->name() + ".commit"; 1602292SN/A} 1612292SN/A 1622292SN/Atemplate <class Impl> 1632292SN/Avoid 1642292SN/ADefaultCommit<Impl>::regStats() 1652132SN/A{ 1662301SN/A using namespace Stats; 1671062SN/A commitSquashedInsts 1681062SN/A .name(name() + ".commitSquashedInsts") 1691062SN/A .desc("The number of squashed insts skipped by commit") 1701062SN/A .prereq(commitSquashedInsts); 1711062SN/A commitSquashEvents 1721062SN/A .name(name() + ".commitSquashEvents") 1731062SN/A .desc("The number of times commit is told to squash") 1741062SN/A .prereq(commitSquashEvents); 1751062SN/A commitNonSpecStalls 1761062SN/A .name(name() + ".commitNonSpecStalls") 1771062SN/A .desc("The number of times commit has been forced to stall to " 1781062SN/A "communicate backwards") 1791062SN/A .prereq(commitNonSpecStalls); 1801062SN/A branchMispredicts 1811062SN/A .name(name() + ".branchMispredicts") 1821062SN/A .desc("The number of times a branch was mispredicted") 1831062SN/A .prereq(branchMispredicts); 1842292SN/A numCommittedDist 1851062SN/A .init(0,commitWidth,1) 1868240Snate@binkert.org .name(name() + ".committed_per_cycle") 1871062SN/A .desc("Number of insts commited each cycle") 1881062SN/A .flags(Stats::pdf) 1891062SN/A ; 1902301SN/A 1918834Satgutier@umich.edu instsCommitted 1926221Snate@binkert.org .init(cpu->numThreads) 1938834Satgutier@umich.edu .name(name() + ".committedInsts") 1942301SN/A .desc("Number of instructions committed") 1952301SN/A .flags(total) 1962301SN/A ; 1972301SN/A 1988834Satgutier@umich.edu opsCommitted 1998834Satgutier@umich.edu .init(cpu->numThreads) 2008834Satgutier@umich.edu .name(name() + ".committedOps") 2018834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 2028834Satgutier@umich.edu .flags(total) 2038834Satgutier@umich.edu ; 2048834Satgutier@umich.edu 2052316SN/A statComSwp 2066221Snate@binkert.org .init(cpu->numThreads) 2078240Snate@binkert.org .name(name() + ".swp_count") 2082301SN/A .desc("Number of s/w prefetches committed") 2092301SN/A .flags(total) 2102301SN/A ; 2112301SN/A 2122316SN/A statComRefs 2136221Snate@binkert.org .init(cpu->numThreads) 2148240Snate@binkert.org .name(name() + ".refs") 2152301SN/A .desc("Number of memory references committed") 2162301SN/A .flags(total) 2172301SN/A ; 2182301SN/A 2192316SN/A statComLoads 2206221Snate@binkert.org .init(cpu->numThreads) 2218240Snate@binkert.org .name(name() + ".loads") 2222301SN/A .desc("Number of loads committed") 2232301SN/A .flags(total) 2242301SN/A ; 2252301SN/A 2262316SN/A statComMembars 2276221Snate@binkert.org .init(cpu->numThreads) 2288240Snate@binkert.org .name(name() + ".membars") 2292301SN/A .desc("Number of memory barriers committed") 2302301SN/A .flags(total) 2312301SN/A ; 2322301SN/A 2332316SN/A statComBranches 2346221Snate@binkert.org .init(cpu->numThreads) 2358240Snate@binkert.org .name(name() + ".branches") 2362301SN/A .desc("Number of branches committed") 2372301SN/A .flags(total) 2382301SN/A ; 2392301SN/A 2407897Shestness@cs.utexas.edu statComFloating 2417897Shestness@cs.utexas.edu .init(cpu->numThreads) 2428240Snate@binkert.org .name(name() + ".fp_insts") 2437897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2447897Shestness@cs.utexas.edu .flags(total) 2457897Shestness@cs.utexas.edu ; 2467897Shestness@cs.utexas.edu 2477897Shestness@cs.utexas.edu statComInteger 2487897Shestness@cs.utexas.edu .init(cpu->numThreads) 2498240Snate@binkert.org .name(name()+".int_insts") 2507897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2517897Shestness@cs.utexas.edu .flags(total) 2527897Shestness@cs.utexas.edu ; 2537897Shestness@cs.utexas.edu 2547897Shestness@cs.utexas.edu statComFunctionCalls 2557897Shestness@cs.utexas.edu .init(cpu->numThreads) 2568240Snate@binkert.org .name(name()+".function_calls") 2577897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2587897Shestness@cs.utexas.edu .flags(total) 2597897Shestness@cs.utexas.edu ; 2607897Shestness@cs.utexas.edu 2612316SN/A commitEligible 2626221Snate@binkert.org .init(cpu->numThreads) 2638240Snate@binkert.org .name(name() + ".bw_limited") 2642301SN/A .desc("number of insts not committed due to BW limits") 2652301SN/A .flags(total) 2662301SN/A ; 2672301SN/A 2682316SN/A commitEligibleSamples 2698240Snate@binkert.org .name(name() + ".bw_lim_events") 2702301SN/A .desc("number cycles where commit BW limit reached") 2712301SN/A ; 2721062SN/A} 2731062SN/A 2741062SN/Atemplate <class Impl> 2751062SN/Avoid 2762980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2772292SN/A{ 2782292SN/A thread = threads; 2792292SN/A} 2802292SN/A 2812292SN/Atemplate <class Impl> 2822292SN/Avoid 2832292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2841060SN/A{ 2851060SN/A timeBuffer = tb_ptr; 2861060SN/A 2871060SN/A // Setup wire to send information back to IEW. 2881060SN/A toIEW = timeBuffer->getWire(0); 2891060SN/A 2901060SN/A // Setup wire to read data from IEW (for the ROB). 2911060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2921060SN/A} 2931060SN/A 2941061SN/Atemplate <class Impl> 2951060SN/Avoid 2962292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2972292SN/A{ 2982292SN/A fetchQueue = fq_ptr; 2992292SN/A 3002292SN/A // Setup wire to get instructions from rename (for the ROB). 3012292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 3022292SN/A} 3032292SN/A 3042292SN/Atemplate <class Impl> 3052292SN/Avoid 3062292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3071060SN/A{ 3081060SN/A renameQueue = rq_ptr; 3091060SN/A 3101060SN/A // Setup wire to get instructions from rename (for the ROB). 3111060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3121060SN/A} 3131060SN/A 3141061SN/Atemplate <class Impl> 3151060SN/Avoid 3162292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3171060SN/A{ 3181060SN/A iewQueue = iq_ptr; 3191060SN/A 3201060SN/A // Setup wire to get instructions from IEW. 3211060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3221060SN/A} 3231060SN/A 3241061SN/Atemplate <class Impl> 3251060SN/Avoid 3262292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3272292SN/A{ 3282292SN/A iewStage = iew_stage; 3292292SN/A} 3302292SN/A 3312292SN/Atemplate<class Impl> 3322292SN/Avoid 3336221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3342292SN/A{ 3352292SN/A activeThreads = at_ptr; 3362292SN/A} 3372292SN/A 3382292SN/Atemplate <class Impl> 3392292SN/Avoid 3402292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3412292SN/A{ 3426221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3436221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3442292SN/A} 3452292SN/A 3462292SN/Atemplate <class Impl> 3472292SN/Avoid 3482292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3491060SN/A{ 3501060SN/A rob = rob_ptr; 3511060SN/A} 3521060SN/A 3531061SN/Atemplate <class Impl> 3541060SN/Avoid 3559427SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::startupStage() 3561060SN/A{ 3572292SN/A rob->setActiveThreads(activeThreads); 3582292SN/A rob->resetEntries(); 3591060SN/A 3602292SN/A // Broadcast the number of free entries. 3616221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3626221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3636221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3646221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3651060SN/A } 3661060SN/A 3674329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3684329Sktlim@umich.edu // start of the simulation, so it starts as active. 3694329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3704329Sktlim@umich.edu 3712292SN/A cpu->activityThisCycle(); 3721060SN/A} 3731060SN/A 3741061SN/Atemplate <class Impl> 3759444SAndreas.Sandberg@ARM.comvoid 3762843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3771060SN/A{ 3782843Sktlim@umich.edu drainPending = true; 3792316SN/A} 3802316SN/A 3812316SN/Atemplate <class Impl> 3822316SN/Avoid 3839444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainResume() 3842843Sktlim@umich.edu{ 3852864Sktlim@umich.edu drainPending = false; 3862843Sktlim@umich.edu} 3872843Sktlim@umich.edu 3882843Sktlim@umich.edutemplate <class Impl> 3892843Sktlim@umich.eduvoid 3909444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainSanityCheck() const 3919444SAndreas.Sandberg@ARM.com{ 3929444SAndreas.Sandberg@ARM.com assert(isDrained()); 3939444SAndreas.Sandberg@ARM.com rob->drainSanityCheck(); 3949444SAndreas.Sandberg@ARM.com} 3959444SAndreas.Sandberg@ARM.com 3969444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3979444SAndreas.Sandberg@ARM.combool 3989444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::isDrained() const 3999444SAndreas.Sandberg@ARM.com{ 4009444SAndreas.Sandberg@ARM.com /* Make sure no one is executing microcode. There are two reasons 4019444SAndreas.Sandberg@ARM.com * for this: 4029444SAndreas.Sandberg@ARM.com * - Hardware virtualized CPUs can't switch into the middle of a 4039444SAndreas.Sandberg@ARM.com * microcode sequence. 4049444SAndreas.Sandberg@ARM.com * - The current fetch implementation will most likely get very 4059444SAndreas.Sandberg@ARM.com * confused if it tries to start fetching an instruction that 4069444SAndreas.Sandberg@ARM.com * is executing in the middle of a ucode sequence that changes 4079444SAndreas.Sandberg@ARM.com * address mappings. This can happen on for example x86. 4089444SAndreas.Sandberg@ARM.com */ 4099444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 4109444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() != 0) 4119444SAndreas.Sandberg@ARM.com return false; 4129444SAndreas.Sandberg@ARM.com } 4139444SAndreas.Sandberg@ARM.com 4149444SAndreas.Sandberg@ARM.com /* Make sure that all instructions have finished committing before 4159444SAndreas.Sandberg@ARM.com * declaring the system as drained. We want the pipeline to be 4169444SAndreas.Sandberg@ARM.com * completely empty when we declare the CPU to be drained. This 4179444SAndreas.Sandberg@ARM.com * makes debugging easier since CPU handover and restoring from a 4189444SAndreas.Sandberg@ARM.com * checkpoint with a different CPU should have the same timing. 4199444SAndreas.Sandberg@ARM.com */ 4209444SAndreas.Sandberg@ARM.com return rob->isEmpty() && 4219444SAndreas.Sandberg@ARM.com interrupt == NoFault; 4229444SAndreas.Sandberg@ARM.com} 4239444SAndreas.Sandberg@ARM.com 4249444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4259444SAndreas.Sandberg@ARM.comvoid 4262307SN/ADefaultCommit<Impl>::takeOverFrom() 4272307SN/A{ 4282307SN/A _status = Active; 4292307SN/A _nextStatus = Inactive; 4306221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4316221Snate@binkert.org commitStatus[tid] = Idle; 4326221Snate@binkert.org changedROBNumEntries[tid] = false; 4336221Snate@binkert.org trapSquash[tid] = false; 4346221Snate@binkert.org tcSquash[tid] = false; 4359437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 4362307SN/A } 4372307SN/A squashCounter = 0; 4382307SN/A rob->takeOverFrom(); 4392307SN/A} 4402307SN/A 4412307SN/Atemplate <class Impl> 4422307SN/Avoid 4432292SN/ADefaultCommit<Impl>::updateStatus() 4442132SN/A{ 4452316SN/A // reset ROB changed variable 4466221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4476221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4483867Sbinkertn@umich.edu 4493867Sbinkertn@umich.edu while (threads != end) { 4506221Snate@binkert.org ThreadID tid = *threads++; 4513867Sbinkertn@umich.edu 4522316SN/A changedROBNumEntries[tid] = false; 4532316SN/A 4542316SN/A // Also check if any of the threads has a trap pending 4552316SN/A if (commitStatus[tid] == TrapPending || 4562316SN/A commitStatus[tid] == FetchTrapPending) { 4572316SN/A _nextStatus = Active; 4582316SN/A } 4592292SN/A } 4602292SN/A 4612292SN/A if (_nextStatus == Inactive && _status == Active) { 4622292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4632733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4642292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4652292SN/A DPRINTF(Activity, "Activating stage.\n"); 4662733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4672292SN/A } 4682292SN/A 4692292SN/A _status = _nextStatus; 4702292SN/A} 4712292SN/A 4722292SN/Atemplate <class Impl> 4732292SN/Avoid 4742292SN/ADefaultCommit<Impl>::setNextStatus() 4752292SN/A{ 4762292SN/A int squashes = 0; 4772292SN/A 4786221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4796221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4802292SN/A 4813867Sbinkertn@umich.edu while (threads != end) { 4826221Snate@binkert.org ThreadID tid = *threads++; 4832292SN/A 4842292SN/A if (commitStatus[tid] == ROBSquashing) { 4852292SN/A squashes++; 4862292SN/A } 4872292SN/A } 4882292SN/A 4892702Sktlim@umich.edu squashCounter = squashes; 4902292SN/A 4912292SN/A // If commit is currently squashing, then it will have activity for the 4922292SN/A // next cycle. Set its next status as active. 4932292SN/A if (squashCounter) { 4942292SN/A _nextStatus = Active; 4952292SN/A } 4962292SN/A} 4972292SN/A 4982292SN/Atemplate <class Impl> 4992292SN/Abool 5002292SN/ADefaultCommit<Impl>::changedROBEntries() 5012292SN/A{ 5026221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5036221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5042292SN/A 5053867Sbinkertn@umich.edu while (threads != end) { 5066221Snate@binkert.org ThreadID tid = *threads++; 5072292SN/A 5082292SN/A if (changedROBNumEntries[tid]) { 5092292SN/A return true; 5102292SN/A } 5112292SN/A } 5122292SN/A 5132292SN/A return false; 5142292SN/A} 5152292SN/A 5162292SN/Atemplate <class Impl> 5176221Snate@binkert.orgsize_t 5186221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 5192292SN/A{ 5202292SN/A return rob->numFreeEntries(tid); 5212292SN/A} 5222292SN/A 5232292SN/Atemplate <class Impl> 5242292SN/Avoid 5256221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 5262292SN/A{ 5272292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5282292SN/A 5292292SN/A TrapEvent *trap = new TrapEvent(this, tid); 5302292SN/A 5319179Sandreas.hansson@arm.com cpu->schedule(trap, cpu->clockEdge(trapLatency)); 5324035Sktlim@umich.edu trapInFlight[tid] = true; 5338518Sgeoffrey.blake@arm.com thread[tid]->trapPending = true; 5342292SN/A} 5352292SN/A 5362292SN/Atemplate <class Impl> 5372292SN/Avoid 5386221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5392292SN/A{ 5404035Sktlim@umich.edu assert(!trapInFlight[tid]); 5412680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5422292SN/A 5432680Sktlim@umich.edu tcSquash[tid] = true; 5442292SN/A} 5452292SN/A 5462292SN/Atemplate <class Impl> 5472292SN/Avoid 5486221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5492292SN/A{ 5502292SN/A // If we want to include the squashing instruction in the squash, 5512292SN/A // then use one older sequence number. 5522292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5532292SN/A // all instructions of this thread. 5542292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5557855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5562292SN/A 5572292SN/A // All younger instructions will be squashed. Set the sequence 5582292SN/A // number as the youngest instruction in the ROB (0 in this case. 5592292SN/A // Hopefully nothing breaks.) 5607855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5612292SN/A 5622292SN/A rob->squash(squashed_inst, tid); 5632292SN/A changedROBNumEntries[tid] = true; 5642292SN/A 5652292SN/A // Send back the sequence number of the squashed instruction. 5662292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5672292SN/A 5682292SN/A // Send back the squash signal to tell stages that they should 5692292SN/A // squash. 5702292SN/A toIEW->commitInfo[tid].squash = true; 5712292SN/A 5722292SN/A // Send back the rob squashing signal so other stages know that 5732292SN/A // the ROB is in the process of squashing. 5742292SN/A toIEW->commitInfo[tid].robSquashing = true; 5752292SN/A 5767851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 5778137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 5782292SN/A 5797720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5802316SN/A} 5812292SN/A 5822316SN/Atemplate <class Impl> 5832316SN/Avoid 5846221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5852316SN/A{ 5862316SN/A squashAll(tid); 5872316SN/A 5887720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5892316SN/A 5902316SN/A thread[tid]->trapPending = false; 5919382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 5924035Sktlim@umich.edu trapInFlight[tid] = false; 5932316SN/A 5942316SN/A trapSquash[tid] = false; 5952316SN/A 5962316SN/A commitStatus[tid] = ROBSquashing; 5972316SN/A cpu->activityThisCycle(); 5982316SN/A} 5992316SN/A 6002316SN/Atemplate <class Impl> 6012316SN/Avoid 6026221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 6032316SN/A{ 6042316SN/A squashAll(tid); 6052292SN/A 6067720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 6072292SN/A 6089382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6092292SN/A assert(!thread[tid]->trapPending); 6102316SN/A 6112292SN/A commitStatus[tid] = ROBSquashing; 6122292SN/A cpu->activityThisCycle(); 6132292SN/A 6142680Sktlim@umich.edu tcSquash[tid] = false; 6152292SN/A} 6162292SN/A 6172292SN/Atemplate <class Impl> 6182292SN/Avoid 6199437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 6207784SAli.Saidi@ARM.com{ 6219437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Squashing after squash after request, " 6229437SAndreas.Sandberg@ARM.com "restarting at PC %s\n", pc[tid]); 6237784SAli.Saidi@ARM.com 6249437SAndreas.Sandberg@ARM.com squashAll(tid); 6259437SAndreas.Sandberg@ARM.com // Make sure to inform the fetch stage of which instruction caused 6269437SAndreas.Sandberg@ARM.com // the squash. It'll try to re-fetch an instruction executing in 6279437SAndreas.Sandberg@ARM.com // microcode unless this is set. 6289437SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 6299437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 6307784SAli.Saidi@ARM.com 6319437SAndreas.Sandberg@ARM.com commitStatus[tid] = ROBSquashing; 6329437SAndreas.Sandberg@ARM.com cpu->activityThisCycle(); 6339437SAndreas.Sandberg@ARM.com} 6347784SAli.Saidi@ARM.com 6359437SAndreas.Sandberg@ARM.comtemplate <class Impl> 6369437SAndreas.Sandberg@ARM.comvoid 6379437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst) 6389437SAndreas.Sandberg@ARM.com{ 6399437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6409437SAndreas.Sandberg@ARM.com tid, head_inst->seqNum); 6417784SAli.Saidi@ARM.com 6429437SAndreas.Sandberg@ARM.com assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 6439437SAndreas.Sandberg@ARM.com commitStatus[tid] = SquashAfterPending; 6449437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = head_inst; 6457784SAli.Saidi@ARM.com} 6467784SAli.Saidi@ARM.com 6477784SAli.Saidi@ARM.comtemplate <class Impl> 6487784SAli.Saidi@ARM.comvoid 6492292SN/ADefaultCommit<Impl>::tick() 6502292SN/A{ 6512292SN/A wroteToTimeBuffer = false; 6522292SN/A _nextStatus = Inactive; 6532292SN/A 6543867Sbinkertn@umich.edu if (activeThreads->empty()) 6552875Sksewell@umich.edu return; 6562875Sksewell@umich.edu 6576221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6586221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6592292SN/A 6602316SN/A // Check if any of the threads are done squashing. Change the 6612316SN/A // status if they are done. 6623867Sbinkertn@umich.edu while (threads != end) { 6636221Snate@binkert.org ThreadID tid = *threads++; 6642292SN/A 6654035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6664035Sktlim@umich.edu // this cycle. 6674035Sktlim@umich.edu committedStores[tid] = false; 6684035Sktlim@umich.edu 6692292SN/A if (commitStatus[tid] == ROBSquashing) { 6702292SN/A 6712292SN/A if (rob->isDoneSquashing(tid)) { 6722292SN/A commitStatus[tid] = Running; 6732292SN/A } else { 6742292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6752877Sksewell@umich.edu " insts this cycle.\n", tid); 6762702Sktlim@umich.edu rob->doSquash(tid); 6772702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6782702Sktlim@umich.edu wroteToTimeBuffer = true; 6792292SN/A } 6802292SN/A } 6812292SN/A } 6822292SN/A 6832292SN/A commit(); 6842292SN/A 6852292SN/A markCompletedInsts(); 6862292SN/A 6873867Sbinkertn@umich.edu threads = activeThreads->begin(); 6882292SN/A 6893867Sbinkertn@umich.edu while (threads != end) { 6906221Snate@binkert.org ThreadID tid = *threads++; 6912292SN/A 6922292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6932292SN/A // The ROB has more instructions it can commit. Its next status 6942292SN/A // will be active. 6952292SN/A _nextStatus = Active; 6962292SN/A 6972292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6982292SN/A 6997720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 7002292SN/A " ROB and ready to commit\n", 7017720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7022292SN/A 7032292SN/A } else if (!rob->isEmpty(tid)) { 7042292SN/A DynInstPtr inst = rob->readHeadInst(tid); 7052292SN/A 7062292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 7077720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 7087720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7092292SN/A } 7102292SN/A 7112292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 7122292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 7132292SN/A } 7142292SN/A 7152292SN/A 7162292SN/A if (wroteToTimeBuffer) { 7172316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 7182292SN/A cpu->activityThisCycle(); 7192292SN/A } 7202292SN/A 7212292SN/A updateStatus(); 7222292SN/A} 7232292SN/A 7242292SN/Atemplate <class Impl> 7252292SN/Avoid 7264035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 7272292SN/A{ 7287847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7297847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7307847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7317847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7327847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7337847Sminkyu.jeong@arm.com interrupt = NoFault; 7349513SAli.Saidi@ARM.com avoidQuiesceLiveLock = true; 7357847Sminkyu.jeong@arm.com return; 7367847Sminkyu.jeong@arm.com } 7373633Sktlim@umich.edu 7388493Sgblack@eecs.umich.edu // Wait until all in flight instructions are finished before enterring 7398493Sgblack@eecs.umich.edu // the interrupt. 7408823Snilay@cs.wisc.edu if (canHandleInterrupts && cpu->instList.empty()) { 7417847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7427847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7437847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7444035Sktlim@umich.edu 7457847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7467847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7472292SN/A 7489382SAli.Saidi@ARM.com assert(!thread[0]->noSquashFromTC); 7499382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = true; 7502292SN/A 7518733Sgeoffrey.blake@arm.com if (cpu->checker) { 7528733Sgeoffrey.blake@arm.com cpu->checker->handlePendingInt(); 7538733Sgeoffrey.blake@arm.com } 7548733Sgeoffrey.blake@arm.com 7559624Snilay@cs.wisc.edu // CPU will handle interrupt. Note that we ignore the local copy of 7569624Snilay@cs.wisc.edu // interrupt. This is because the local copy may no longer be the 7579624Snilay@cs.wisc.edu // interrupt that the interrupt controller thinks is being handled. 7589624Snilay@cs.wisc.edu cpu->processInterrupts(cpu->getInterrupts()); 7593633Sktlim@umich.edu 7609382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = false; 7612292SN/A 7627847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7632292SN/A 7647847Sminkyu.jeong@arm.com // Generate trap squash event. 7657847Sminkyu.jeong@arm.com generateTrapEvent(0); 7663640Sktlim@umich.edu 7677847Sminkyu.jeong@arm.com interrupt = NoFault; 7689513SAli.Saidi@ARM.com avoidQuiesceLiveLock = false; 7697847Sminkyu.jeong@arm.com } else { 7708823Snilay@cs.wisc.edu DPRINTF(Commit, "Interrupt pending: instruction is %sin " 7718823Snilay@cs.wisc.edu "flight, ROB is %sempty\n", 7728823Snilay@cs.wisc.edu canHandleInterrupts ? "not " : "", 7738823Snilay@cs.wisc.edu cpu->instList.empty() ? "" : "not " ); 7741060SN/A } 7754035Sktlim@umich.edu} 7767847Sminkyu.jeong@arm.com 7777847Sminkyu.jeong@arm.comtemplate <class Impl> 7787847Sminkyu.jeong@arm.comvoid 7797847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 7807847Sminkyu.jeong@arm.com{ 7817847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 7827847Sminkyu.jeong@arm.com tcSquash[0]) 7837847Sminkyu.jeong@arm.com return; 7847847Sminkyu.jeong@arm.com 7857847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 7867847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 7877847Sminkyu.jeong@arm.com // pending. 7887847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 7897847Sminkyu.jeong@arm.com 7907847Sminkyu.jeong@arm.com // Get any interrupt that happened 7917847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 7927847Sminkyu.jeong@arm.com 7937847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 7947847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 7957847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 7967847Sminkyu.jeong@arm.com if (interrupt != NoFault) 7977847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 7987847Sminkyu.jeong@arm.com} 7997847Sminkyu.jeong@arm.com 8004035Sktlim@umich.edutemplate <class Impl> 8014035Sktlim@umich.eduvoid 8024035Sktlim@umich.eduDefaultCommit<Impl>::commit() 8034035Sktlim@umich.edu{ 8048793Sgblack@eecs.umich.edu if (FullSystem) { 8058793Sgblack@eecs.umich.edu // Check if we have a interrupt and get read to handle it 8068793Sgblack@eecs.umich.edu if (cpu->checkInterrupts(cpu->tcBase(0))) 8078793Sgblack@eecs.umich.edu propagateInterrupt(); 8088793Sgblack@eecs.umich.edu } 8091060SN/A 8101060SN/A //////////////////////////////////// 8112316SN/A // Check for any possible squashes, handle them first 8121060SN/A //////////////////////////////////// 8136221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8146221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8151060SN/A 8163867Sbinkertn@umich.edu while (threads != end) { 8176221Snate@binkert.org ThreadID tid = *threads++; 8181060SN/A 8192292SN/A // Not sure which one takes priority. I think if we have 8202292SN/A // both, that's a bad sign. 8212292SN/A if (trapSquash[tid] == true) { 8222680Sktlim@umich.edu assert(!tcSquash[tid]); 8232292SN/A squashFromTrap(tid); 8242680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 8254035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 8262680Sktlim@umich.edu squashFromTC(tid); 8279437SAndreas.Sandberg@ARM.com } else if (commitStatus[tid] == SquashAfterPending) { 8289437SAndreas.Sandberg@ARM.com // A squash from the previous cycle of the commit stage (i.e., 8299437SAndreas.Sandberg@ARM.com // commitInsts() called squashAfter) is pending. Squash the 8309437SAndreas.Sandberg@ARM.com // thread now. 8319437SAndreas.Sandberg@ARM.com squashFromSquashAfter(tid); 8322292SN/A } 8331061SN/A 8342292SN/A // Squashed sequence number must be older than youngest valid 8352292SN/A // instruction in the ROB. This prevents squashes from younger 8362292SN/A // instructions overriding squashes from older instructions. 8372292SN/A if (fromIEW->squash[tid] && 8382292SN/A commitStatus[tid] != TrapPending && 8392292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8401061SN/A 8418137SAli.Saidi@ARM.com if (fromIEW->mispredictInst[tid]) { 8428137SAli.Saidi@ARM.com DPRINTF(Commit, 8438137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 8442292SN/A tid, 8458137SAli.Saidi@ARM.com fromIEW->mispredictInst[tid]->instAddr(), 8462292SN/A fromIEW->squashedSeqNum[tid]); 8478137SAli.Saidi@ARM.com } else { 8488137SAli.Saidi@ARM.com DPRINTF(Commit, 8498137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to order violation [sn:%i]\n", 8508137SAli.Saidi@ARM.com tid, fromIEW->squashedSeqNum[tid]); 8518137SAli.Saidi@ARM.com } 8521061SN/A 8532292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8542292SN/A tid, 8557720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8561061SN/A 8572292SN/A commitStatus[tid] = ROBSquashing; 8581061SN/A 8592292SN/A // If we want to include the squashing instruction in the squash, 8602292SN/A // then use one older sequence number. 8612292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8621062SN/A 8632935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 8642292SN/A squashed_inst--; 8652935Sksewell@umich.edu } 8664035Sktlim@umich.edu 8672292SN/A // All younger instructions will be squashed. Set the sequence 8682292SN/A // number as the youngest instruction in the ROB. 8692292SN/A youngestSeqNum[tid] = squashed_inst; 8702292SN/A 8713093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8722292SN/A changedROBNumEntries[tid] = true; 8732292SN/A 8742292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8752292SN/A 8762292SN/A toIEW->commitInfo[tid].squash = true; 8772292SN/A 8782292SN/A // Send back the rob squashing signal so other stages know that 8792292SN/A // the ROB is in the process of squashing. 8802292SN/A toIEW->commitInfo[tid].robSquashing = true; 8812292SN/A 8827851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 8837851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 8842292SN/A toIEW->commitInfo[tid].branchTaken = 8852292SN/A fromIEW->branchTaken[tid]; 8868822Snilay@cs.wisc.edu toIEW->commitInfo[tid].squashInst = 8878822Snilay@cs.wisc.edu rob->findInst(tid, squashed_inst); 8888842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst) { 8898842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 8908842Smrinmoy.ghosh@arm.com toIEW->commitInfo[tid].branchTaken = true; 8918842Smrinmoy.ghosh@arm.com } 8928842Smrinmoy.ghosh@arm.com } 8932292SN/A 8947720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 8952292SN/A 8968137SAli.Saidi@ARM.com if (toIEW->commitInfo[tid].mispredictInst) { 8972292SN/A ++branchMispredicts; 8982292SN/A } 8991062SN/A } 9002292SN/A 9011060SN/A } 9021060SN/A 9032292SN/A setNextStatus(); 9042292SN/A 9052292SN/A if (squashCounter != numThreads) { 9061061SN/A // If we're not currently squashing, then get instructions. 9071060SN/A getInsts(); 9081060SN/A 9091061SN/A // Try to commit any instructions. 9101060SN/A commitInsts(); 9111060SN/A } 9121060SN/A 9132292SN/A //Check for any activity 9143867Sbinkertn@umich.edu threads = activeThreads->begin(); 9152292SN/A 9163867Sbinkertn@umich.edu while (threads != end) { 9176221Snate@binkert.org ThreadID tid = *threads++; 9182292SN/A 9192292SN/A if (changedROBNumEntries[tid]) { 9202292SN/A toIEW->commitInfo[tid].usedROB = true; 9212292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9222292SN/A 9232292SN/A wroteToTimeBuffer = true; 9242292SN/A changedROBNumEntries[tid] = false; 9254035Sktlim@umich.edu if (rob->isEmpty(tid)) 9264035Sktlim@umich.edu checkEmptyROB[tid] = true; 9272292SN/A } 9284035Sktlim@umich.edu 9294035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 9304035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 9314035Sktlim@umich.edu // stage has received any information regarding stores that 9324035Sktlim@umich.edu // committed. 9334035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 9344035Sktlim@umich.edu // on the same cycle as when stores have been committed. 9354035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 9364035Sktlim@umich.edu // commit and IEW. 9374035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9385557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9394035Sktlim@umich.edu checkEmptyROB[tid] = false; 9404035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 9414035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 9424035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9434035Sktlim@umich.edu wroteToTimeBuffer = true; 9444035Sktlim@umich.edu } 9454035Sktlim@umich.edu 9461060SN/A } 9471060SN/A} 9481060SN/A 9491061SN/Atemplate <class Impl> 9501060SN/Avoid 9512292SN/ADefaultCommit<Impl>::commitInsts() 9521060SN/A{ 9531060SN/A //////////////////////////////////// 9541060SN/A // Handle commit 9552316SN/A // Note that commit will be handled prior to putting new 9562316SN/A // instructions in the ROB so that the ROB only tries to commit 9572316SN/A // instructions it has in this current cycle, and not instructions 9582316SN/A // it is writing in during this cycle. Can't commit and squash 9592316SN/A // things at the same time... 9601060SN/A //////////////////////////////////// 9611060SN/A 9622292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9631060SN/A 9641060SN/A unsigned num_committed = 0; 9651060SN/A 9662292SN/A DynInstPtr head_inst; 9672316SN/A 9681060SN/A // Commit as many instructions as possible until the commit bandwidth 9691060SN/A // limit is reached, or it becomes impossible to commit any more. 9702292SN/A while (num_committed < commitWidth) { 9718823Snilay@cs.wisc.edu // Check for any interrupt that we've already squashed for 9728823Snilay@cs.wisc.edu // and start processing it. 9738823Snilay@cs.wisc.edu if (interrupt != NoFault) 9748823Snilay@cs.wisc.edu handleInterrupt(); 9758823Snilay@cs.wisc.edu 9762292SN/A int commit_thread = getCommittingThread(); 9771060SN/A 9782292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9792292SN/A break; 9802292SN/A 9812292SN/A head_inst = rob->readHeadInst(commit_thread); 9822292SN/A 9836221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 9842292SN/A 9852292SN/A assert(tid == commit_thread); 9862292SN/A 9872292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 9882292SN/A head_inst->seqNum, tid); 9892132SN/A 9902316SN/A // If the head instruction is squashed, it is ready to retire 9912316SN/A // (be removed from the ROB) at any time. 9921060SN/A if (head_inst->isSquashed()) { 9931060SN/A 9942292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 9951060SN/A "ROB.\n"); 9961060SN/A 9972292SN/A rob->retireHead(commit_thread); 9981060SN/A 9991062SN/A ++commitSquashedInsts; 10001062SN/A 10012292SN/A // Record that the number of ROB entries has changed. 10022292SN/A changedROBNumEntries[tid] = true; 10031060SN/A } else { 10047720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 10052292SN/A 10061060SN/A // Increment the total number of non-speculative instructions 10071060SN/A // executed. 10081060SN/A // Hack for now: it really shouldn't happen until after the 10091061SN/A // commit is deemed to be successful, but this count is needed 10101061SN/A // for syscalls. 10112292SN/A thread[tid]->funcExeInst++; 10121060SN/A 10131060SN/A // Try to commit the head instruction. 10141060SN/A bool commit_success = commitHead(head_inst, num_committed); 10151060SN/A 10161062SN/A if (commit_success) { 10171060SN/A ++num_committed; 10181060SN/A 10192292SN/A changedROBNumEntries[tid] = true; 10202292SN/A 10212292SN/A // Set the doneSeqNum to the youngest committed instruction. 10222292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 10231060SN/A 10248823Snilay@cs.wisc.edu if (tid == 0) { 10258823Snilay@cs.wisc.edu canHandleInterrupts = (!head_inst->isDelayedCommit()) && 10268823Snilay@cs.wisc.edu ((THE_ISA != ALPHA_ISA) || 10278823Snilay@cs.wisc.edu (!(pc[0].instAddr() & 0x3))); 10288823Snilay@cs.wisc.edu } 10298823Snilay@cs.wisc.edu 10307783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 10317783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 10327783SGiacomo.Gabrielli@arm.com 10338662SAli.Saidi@ARM.com cpu->traceFunctions(pc[tid].instAddr()); 10348662SAli.Saidi@ARM.com 10357720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 10362935Sksewell@umich.edu 10377855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 10387855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 10397855SAli.Saidi@ARM.com 10407784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 10417784SAli.Saidi@ARM.com // others squash everything and restart fetch 10427784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 10439437SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10447784SAli.Saidi@ARM.com 10459444SAndreas.Sandberg@ARM.com if (drainPending) { 10469444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 10479444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() == 0 && interrupt == NoFault) { 10489444SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10499444SAndreas.Sandberg@ARM.com cpu->commitDrained(tid); 10509444SAndreas.Sandberg@ARM.com } 10519444SAndreas.Sandberg@ARM.com } 10529444SAndreas.Sandberg@ARM.com 10532292SN/A int count = 0; 10542292SN/A Addr oldpc; 10555108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 10565108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 10579382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending); 10582292SN/A do { 10597720Sgblack@eecs.umich.edu oldpc = pc[tid].instAddr(); 10605108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 10612292SN/A count++; 10627720Sgblack@eecs.umich.edu } while (oldpc != pc[tid].instAddr()); 10632292SN/A if (count > 1) { 10645108Sgblack@eecs.umich.edu DPRINTF(Commit, 10655108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 10662292SN/A break; 10672292SN/A } 10689513SAli.Saidi@ARM.com 10699513SAli.Saidi@ARM.com // Check if an instruction just enabled interrupts and we've 10709513SAli.Saidi@ARM.com // previously had an interrupt pending that was not handled 10719513SAli.Saidi@ARM.com // because interrupts were subsequently disabled before the 10729513SAli.Saidi@ARM.com // pipeline reached a place to handle the interrupt. In that 10739513SAli.Saidi@ARM.com // case squash now to make sure the interrupt is handled. 10749513SAli.Saidi@ARM.com // 10759513SAli.Saidi@ARM.com // If we don't do this, we might end up in a live lock situation 10769513SAli.Saidi@ARM.com if (!interrupt && avoidQuiesceLiveLock && 10779513SAli.Saidi@ARM.com (!head_inst->isMicroop() || head_inst->isLastMicroop()) && 10789513SAli.Saidi@ARM.com cpu->checkInterrupts(cpu->tcBase(0))) 10799513SAli.Saidi@ARM.com squashAfter(tid, head_inst); 10801060SN/A } else { 10817720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 10822292SN/A "[tid:%i] [sn:%i].\n", 10837720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 10841060SN/A break; 10851060SN/A } 10861060SN/A } 10871060SN/A } 10881062SN/A 10891063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 10902292SN/A numCommittedDist.sample(num_committed); 10912307SN/A 10922307SN/A if (num_committed == commitWidth) { 10932349SN/A commitEligibleSamples++; 10942307SN/A } 10951060SN/A} 10961060SN/A 10971061SN/Atemplate <class Impl> 10981060SN/Abool 10992292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 11001060SN/A{ 11011060SN/A assert(head_inst); 11021060SN/A 11036221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 11042292SN/A 11052316SN/A // If the instruction is not executed yet, then it will need extra 11062316SN/A // handling. Signal backwards that it should be executed. 11071061SN/A if (!head_inst->isExecuted()) { 11081061SN/A // Keep this number correct. We have not yet actually executed 11091061SN/A // and committed this instruction. 11102292SN/A thread[tid]->funcExeInst--; 11111062SN/A 11122292SN/A if (head_inst->isNonSpeculative() || 11132348SN/A head_inst->isStoreConditional() || 11142292SN/A head_inst->isMemBarrier() || 11152292SN/A head_inst->isWriteBarrier()) { 11162316SN/A 11172316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 11187720Sgblack@eecs.umich.edu "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 11197720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11202316SN/A 11215557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 11222292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 11232292SN/A return false; 11242292SN/A } 11252292SN/A 11262292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 11271061SN/A 11281061SN/A // Change the instruction so it won't try to commit again until 11291061SN/A // it is executed. 11301061SN/A head_inst->clearCanCommit(); 11311061SN/A 11321062SN/A ++commitNonSpecStalls; 11331062SN/A 11341061SN/A return false; 11352292SN/A } else if (head_inst->isLoad()) { 11365557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 11374035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 11384035Sktlim@umich.edu return false; 11394035Sktlim@umich.edu } 11404035Sktlim@umich.edu 11414035Sktlim@umich.edu assert(head_inst->uncacheable()); 11427720Sgblack@eecs.umich.edu DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 11437720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11442292SN/A 11452292SN/A // Send back the non-speculative instruction's sequence 11462316SN/A // number. Tell the lsq to re-execute the load. 11472292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 11482292SN/A toIEW->commitInfo[tid].uncached = true; 11492292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 11502292SN/A 11512292SN/A head_inst->clearCanCommit(); 11522292SN/A 11532292SN/A return false; 11541061SN/A } else { 11552292SN/A panic("Trying to commit un-executed instruction " 11561061SN/A "of unknown type!\n"); 11571061SN/A } 11581060SN/A } 11591060SN/A 11602316SN/A if (head_inst->isThreadSync()) { 11612292SN/A // Not handled for now. 11622316SN/A panic("Thread sync instructions are not handled yet.\n"); 11632132SN/A } 11642132SN/A 11654035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 11664035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 11674035Sktlim@umich.edu 11682316SN/A // Stores mark themselves as completed. 11694035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 11702310SN/A head_inst->setCompleted(); 11712310SN/A } 11722310SN/A 11732316SN/A // Use checker prior to updating anything due to traps or PC 11742316SN/A // based events. 11752316SN/A if (cpu->checker) { 11762732Sktlim@umich.edu cpu->checker->verify(head_inst); 11771060SN/A } 11781060SN/A 11792112SN/A if (inst_fault != NoFault) { 11807720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 11817720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11822292SN/A 11835557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 11842316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 11852316SN/A return false; 11862316SN/A } 11872310SN/A 11884035Sktlim@umich.edu head_inst->setCompleted(); 11894035Sktlim@umich.edu 11908733Sgeoffrey.blake@arm.com if (cpu->checker) { 11918733Sgeoffrey.blake@arm.com // Need to check the instruction before its fault is processed 11922732Sktlim@umich.edu cpu->checker->verify(head_inst); 11932316SN/A } 11942292SN/A 11959382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC); 11962292SN/A 11972316SN/A // Mark that we're in state update mode so that the trap's 11982316SN/A // execution doesn't generate extra squashes. 11999382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 12002292SN/A 12012316SN/A // Execute the trap. Although it's slightly unrealistic in 12022316SN/A // terms of timing (as it doesn't wait for the full timing of 12032316SN/A // the trap event to complete before updating state), it's 12042316SN/A // needed to update the state as soon as possible. This 12052316SN/A // prevents external agents from changing any specific state 12062316SN/A // that the trap need. 12077684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 12082292SN/A 12092316SN/A // Exit state update mode to avoid accidental updating. 12109382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 12112292SN/A 12122316SN/A commitStatus[tid] = TrapPending; 12132292SN/A 12148067SAli.Saidi@ARM.com DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 12158067SAli.Saidi@ARM.com head_inst->seqNum); 12164035Sktlim@umich.edu if (head_inst->traceData) { 12176667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 12186667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 12198834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12206667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 12216667Ssteve.reinhardt@amd.com } 12224288Sktlim@umich.edu delete head_inst->traceData; 12234035Sktlim@umich.edu head_inst->traceData = NULL; 12244035Sktlim@umich.edu } 12254035Sktlim@umich.edu 12262316SN/A // Generate trap squash event. 12272316SN/A generateTrapEvent(tid); 12282316SN/A return false; 12291060SN/A } 12301060SN/A 12312301SN/A updateComInstStats(head_inst); 12322132SN/A 12338793Sgblack@eecs.umich.edu if (FullSystem) { 12348793Sgblack@eecs.umich.edu if (thread[tid]->profile) { 12358793Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 12368793Sgblack@eecs.umich.edu ProfileNode *node = thread[tid]->profile->consume( 12378793Sgblack@eecs.umich.edu thread[tid]->getTC(), head_inst->staticInst); 12382362SN/A 12398793Sgblack@eecs.umich.edu if (node) 12408793Sgblack@eecs.umich.edu thread[tid]->profileNode = node; 12418793Sgblack@eecs.umich.edu } 12428793Sgblack@eecs.umich.edu if (CPA::available()) { 12438793Sgblack@eecs.umich.edu if (head_inst->isControl()) { 12448793Sgblack@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 12458793Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 12468793Sgblack@eecs.umich.edu } 12475953Ssaidi@eecs.umich.edu } 12485953Ssaidi@eecs.umich.edu } 12498516SMrinmoy.Ghosh@arm.com DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 12508516SMrinmoy.Ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12512132SN/A if (head_inst->traceData) { 12522292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 12538834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12544046Sbinkertn@umich.edu head_inst->traceData->dump(); 12554046Sbinkertn@umich.edu delete head_inst->traceData; 12562292SN/A head_inst->traceData = NULL; 12571060SN/A } 12588843Smrinmoy.ghosh@arm.com if (head_inst->isReturn()) { 12598843Smrinmoy.ghosh@arm.com DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 12608843Smrinmoy.ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12618843Smrinmoy.ghosh@arm.com } 12621060SN/A 12632292SN/A // Update the commit rename map 12642292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 12653771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 12662292SN/A head_inst->renamedDestRegIdx(i)); 12671060SN/A } 12681062SN/A 12692292SN/A // Finally clear the head ROB entry. 12702292SN/A rob->retireHead(tid); 12711060SN/A 12728471SGiacomo.Gabrielli@arm.com#if TRACING_ON 12739527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 12749527SMatt.Horsnell@arm.com head_inst->commitTick = curTick() - head_inst->fetchTick; 12759527SMatt.Horsnell@arm.com } 12768471SGiacomo.Gabrielli@arm.com#endif 12778471SGiacomo.Gabrielli@arm.com 12784035Sktlim@umich.edu // If this was a store, record it for this cycle. 12794035Sktlim@umich.edu if (head_inst->isStore()) 12804035Sktlim@umich.edu committedStores[tid] = true; 12814035Sktlim@umich.edu 12821060SN/A // Return true to indicate that we have committed an instruction. 12831060SN/A return true; 12841060SN/A} 12851060SN/A 12861061SN/Atemplate <class Impl> 12871060SN/Avoid 12882292SN/ADefaultCommit<Impl>::getInsts() 12891060SN/A{ 12902935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 12912935Sksewell@umich.edu 12923093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 12933093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 12942965Sksewell@umich.edu 12952965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 12962965Sksewell@umich.edu DynInstPtr inst; 12972965Sksewell@umich.edu 12983093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 12996221Snate@binkert.org ThreadID tid = inst->threadNumber; 13002292SN/A 13012292SN/A if (!inst->isSquashed() && 13024035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 13034035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 13042292SN/A changedROBNumEntries[tid] = true; 13052292SN/A 13067720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 13077720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13082292SN/A 13092292SN/A rob->insertInst(inst); 13102292SN/A 13112292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 13122292SN/A 13132292SN/A youngestSeqNum[tid] = inst->seqNum; 13141061SN/A } else { 13157720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 13161061SN/A "squashed, skipping.\n", 13177720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13181061SN/A } 13191060SN/A } 13202965Sksewell@umich.edu} 13212965Sksewell@umich.edu 13222965Sksewell@umich.edutemplate <class Impl> 13232965Sksewell@umich.eduvoid 13242965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 13252965Sksewell@umich.edu{ 13262965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 13272965Sksewell@umich.edu "skidBuffer.\n"); 13282965Sksewell@umich.edu 13292965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 13302965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 13312965Sksewell@umich.edu 13322965Sksewell@umich.edu if (!inst->isSquashed()) { 13337720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 13347720Sgblack@eecs.umich.edu "skidBuffer.\n", inst->pcState(), inst->seqNum, 13353221Sktlim@umich.edu inst->threadNumber); 13362965Sksewell@umich.edu skidBuffer.push(inst); 13372965Sksewell@umich.edu } else { 13387720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 13392965Sksewell@umich.edu "squashed, skipping.\n", 13407720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->threadNumber); 13412965Sksewell@umich.edu } 13422965Sksewell@umich.edu } 13431060SN/A} 13441060SN/A 13451061SN/Atemplate <class Impl> 13461060SN/Avoid 13472292SN/ADefaultCommit<Impl>::markCompletedInsts() 13481060SN/A{ 13491060SN/A // Grab completed insts out of the IEW instruction queue, and mark 13501060SN/A // instructions completed within the ROB. 13511060SN/A for (int inst_num = 0; 13521681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 13531060SN/A ++inst_num) 13541060SN/A { 13552292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 13567720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 13572316SN/A "within ROB.\n", 13582292SN/A fromIEW->insts[inst_num]->threadNumber, 13597720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 13602292SN/A fromIEW->insts[inst_num]->seqNum); 13611060SN/A 13622292SN/A // Mark the instruction as ready to commit. 13632292SN/A fromIEW->insts[inst_num]->setCanCommit(); 13642292SN/A } 13651060SN/A } 13661060SN/A} 13671060SN/A 13681061SN/Atemplate <class Impl> 13692292SN/Abool 13702292SN/ADefaultCommit<Impl>::robDoneSquashing() 13711060SN/A{ 13726221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 13736221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 13742292SN/A 13753867Sbinkertn@umich.edu while (threads != end) { 13766221Snate@binkert.org ThreadID tid = *threads++; 13772292SN/A 13782292SN/A if (!rob->isDoneSquashing(tid)) 13792292SN/A return false; 13802292SN/A } 13812292SN/A 13822292SN/A return true; 13831060SN/A} 13842292SN/A 13852301SN/Atemplate <class Impl> 13862301SN/Avoid 13872301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 13882301SN/A{ 13896221Snate@binkert.org ThreadID tid = inst->threadNumber; 13902301SN/A 13918834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) 13928834Satgutier@umich.edu instsCommitted[tid]++; 13938834Satgutier@umich.edu opsCommitted[tid]++; 13942301SN/A 13959218Satgutier@umich.edu // To match the old model, don't count nops and instruction 13969218Satgutier@umich.edu // prefetches towards the total commit count. 13979218Satgutier@umich.edu if (!inst->isNop() && !inst->isInstPrefetch()) { 13989218Satgutier@umich.edu cpu->instDone(tid, inst); 13999218Satgutier@umich.edu } 14009218Satgutier@umich.edu 14012301SN/A // 14022301SN/A // Control Instructions 14032301SN/A // 14042301SN/A if (inst->isControl()) 14056221Snate@binkert.org statComBranches[tid]++; 14062301SN/A 14072301SN/A // 14082301SN/A // Memory references 14092301SN/A // 14102301SN/A if (inst->isMemRef()) { 14116221Snate@binkert.org statComRefs[tid]++; 14122301SN/A 14132301SN/A if (inst->isLoad()) { 14146221Snate@binkert.org statComLoads[tid]++; 14152301SN/A } 14162301SN/A } 14172301SN/A 14182301SN/A if (inst->isMemBarrier()) { 14196221Snate@binkert.org statComMembars[tid]++; 14202301SN/A } 14217897Shestness@cs.utexas.edu 14227897Shestness@cs.utexas.edu // Integer Instruction 14237897Shestness@cs.utexas.edu if (inst->isInteger()) 14247897Shestness@cs.utexas.edu statComInteger[tid]++; 14257897Shestness@cs.utexas.edu 14267897Shestness@cs.utexas.edu // Floating Point Instruction 14277897Shestness@cs.utexas.edu if (inst->isFloating()) 14287897Shestness@cs.utexas.edu statComFloating[tid]++; 14297897Shestness@cs.utexas.edu 14307897Shestness@cs.utexas.edu // Function Calls 14317897Shestness@cs.utexas.edu if (inst->isCall()) 14327897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 14337897Shestness@cs.utexas.edu 14342301SN/A} 14352301SN/A 14362292SN/A//////////////////////////////////////// 14372292SN/A// // 14382316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 14392292SN/A// // 14402292SN/A//////////////////////////////////////// 14412292SN/Atemplate <class Impl> 14426221Snate@binkert.orgThreadID 14432292SN/ADefaultCommit<Impl>::getCommittingThread() 14442292SN/A{ 14452292SN/A if (numThreads > 1) { 14462292SN/A switch (commitPolicy) { 14472292SN/A 14482292SN/A case Aggressive: 14492292SN/A //If Policy is Aggressive, commit will call 14502292SN/A //this function multiple times per 14512292SN/A //cycle 14522292SN/A return oldestReady(); 14532292SN/A 14542292SN/A case RoundRobin: 14552292SN/A return roundRobin(); 14562292SN/A 14572292SN/A case OldestReady: 14582292SN/A return oldestReady(); 14592292SN/A 14602292SN/A default: 14616221Snate@binkert.org return InvalidThreadID; 14622292SN/A } 14632292SN/A } else { 14643867Sbinkertn@umich.edu assert(!activeThreads->empty()); 14656221Snate@binkert.org ThreadID tid = activeThreads->front(); 14662292SN/A 14672292SN/A if (commitStatus[tid] == Running || 14682292SN/A commitStatus[tid] == Idle || 14692292SN/A commitStatus[tid] == FetchTrapPending) { 14702292SN/A return tid; 14712292SN/A } else { 14726221Snate@binkert.org return InvalidThreadID; 14732292SN/A } 14742292SN/A } 14752292SN/A} 14762292SN/A 14772292SN/Atemplate<class Impl> 14786221Snate@binkert.orgThreadID 14792292SN/ADefaultCommit<Impl>::roundRobin() 14802292SN/A{ 14816221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14826221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14832292SN/A 14842292SN/A while (pri_iter != end) { 14856221Snate@binkert.org ThreadID tid = *pri_iter; 14862292SN/A 14872292SN/A if (commitStatus[tid] == Running || 14882831Sksewell@umich.edu commitStatus[tid] == Idle || 14892831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 14902292SN/A 14912292SN/A if (rob->isHeadReady(tid)) { 14922292SN/A priority_list.erase(pri_iter); 14932292SN/A priority_list.push_back(tid); 14942292SN/A 14952292SN/A return tid; 14962292SN/A } 14972292SN/A } 14982292SN/A 14992292SN/A pri_iter++; 15002292SN/A } 15012292SN/A 15026221Snate@binkert.org return InvalidThreadID; 15032292SN/A} 15042292SN/A 15052292SN/Atemplate<class Impl> 15066221Snate@binkert.orgThreadID 15072292SN/ADefaultCommit<Impl>::oldestReady() 15082292SN/A{ 15092292SN/A unsigned oldest = 0; 15102292SN/A bool first = true; 15112292SN/A 15126221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15136221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15142292SN/A 15153867Sbinkertn@umich.edu while (threads != end) { 15166221Snate@binkert.org ThreadID tid = *threads++; 15172292SN/A 15182292SN/A if (!rob->isEmpty(tid) && 15192292SN/A (commitStatus[tid] == Running || 15202292SN/A commitStatus[tid] == Idle || 15212292SN/A commitStatus[tid] == FetchTrapPending)) { 15222292SN/A 15232292SN/A if (rob->isHeadReady(tid)) { 15242292SN/A 15252292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 15262292SN/A 15272292SN/A if (first) { 15282292SN/A oldest = tid; 15292292SN/A first = false; 15302292SN/A } else if (head_inst->seqNum < oldest) { 15312292SN/A oldest = tid; 15322292SN/A } 15332292SN/A } 15342292SN/A } 15352292SN/A } 15362292SN/A 15372292SN/A if (!first) { 15382292SN/A return oldest; 15392292SN/A } else { 15406221Snate@binkert.org return InvalidThreadID; 15412292SN/A } 15422292SN/A} 1543