commit_impl.hh revision 8662
11689SN/A/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412965Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#include <algorithm> 452329SN/A#include <string> 462292SN/A 473577Sgblack@eecs.umich.edu#include "arch/utility.hh" 488229Snate@binkert.org#include "base/loader/symtab.hh" 495953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 506221Snate@binkert.org#include "config/full_system.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 526221Snate@binkert.org#include "config/use_checker.hh" 531717SN/A#include "cpu/o3/commit.hh" 542292SN/A#include "cpu/o3/thread_state.hh" 558662SAli.Saidi@ARM.com#include "cpu/base.hh" 568229Snate@binkert.org#include "cpu/exetrace.hh" 578229Snate@binkert.org#include "cpu/timebuf.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 598232Snate@binkert.org#include "debug/Commit.hh" 608232Snate@binkert.org#include "debug/CommitRate.hh" 618232Snate@binkert.org#include "debug/ExecFaulting.hh" 628471SGiacomo.Gabrielli@arm.com#include "debug/O3PipeView.hh" 636221Snate@binkert.org#include "params/DerivO3CPU.hh" 648230Snate@binkert.org#include "sim/faults.hh" 652292SN/A 662790Sktlim@umich.edu#if USE_CHECKER 672790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 682790Sktlim@umich.edu#endif 692790Sktlim@umich.edu 706221Snate@binkert.orgusing namespace std; 715529Snate@binkert.org 721061SN/Atemplate <class Impl> 732292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 746221Snate@binkert.org ThreadID _tid) 758581Ssteve.reinhardt@amd.com : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 761060SN/A{ 771060SN/A} 781060SN/A 791061SN/Atemplate <class Impl> 801060SN/Avoid 812292SN/ADefaultCommit<Impl>::TrapEvent::process() 821062SN/A{ 832316SN/A // This will get reset by commit if it was switched out at the 842316SN/A // time of this event processing. 852292SN/A commit->trapSquash[tid] = true; 862292SN/A} 872292SN/A 882292SN/Atemplate <class Impl> 892292SN/Aconst char * 905336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 912292SN/A{ 924873Sstever@eecs.umich.edu return "Trap"; 932292SN/A} 942292SN/A 952292SN/Atemplate <class Impl> 965529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 974329Sktlim@umich.edu : cpu(_cpu), 984329Sktlim@umich.edu squashCounter(0), 992292SN/A iewToCommitDelay(params->iewToCommitDelay), 1002292SN/A commitToIEWDelay(params->commitToIEWDelay), 1012292SN/A renameToROBDelay(params->renameToROBDelay), 1022292SN/A fetchToCommitDelay(params->commitToFetchDelay), 1032292SN/A renameWidth(params->renameWidth), 1042292SN/A commitWidth(params->commitWidth), 1055529Snate@binkert.org numThreads(params->numThreads), 1062843Sktlim@umich.edu drainPending(false), 1072316SN/A switchedOut(false), 1082874Sktlim@umich.edu trapLatency(params->trapLatency) 1092292SN/A{ 1102292SN/A _status = Active; 1112292SN/A _nextStatus = Inactive; 1122980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1132292SN/A 1142292SN/A //Convert string to lowercase 1152292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1162292SN/A (int(*)(int)) tolower); 1172292SN/A 1182292SN/A //Assign commit policy 1192292SN/A if (policy == "aggressive"){ 1202292SN/A commitPolicy = Aggressive; 1212292SN/A 1228346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 1232292SN/A } else if (policy == "roundrobin"){ 1242292SN/A commitPolicy = RoundRobin; 1252292SN/A 1262292SN/A //Set-Up Priority List 1276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1282292SN/A priority_list.push_back(tid); 1292292SN/A } 1302292SN/A 1318346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 1322292SN/A } else if (policy == "oldestready"){ 1332292SN/A commitPolicy = OldestReady; 1342292SN/A 1354329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1362292SN/A } else { 1372292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1382292SN/A "RoundRobin,OldestReady}"); 1392292SN/A } 1402292SN/A 1416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1426221Snate@binkert.org commitStatus[tid] = Idle; 1436221Snate@binkert.org changedROBNumEntries[tid] = false; 1446221Snate@binkert.org checkEmptyROB[tid] = false; 1456221Snate@binkert.org trapInFlight[tid] = false; 1466221Snate@binkert.org committedStores[tid] = false; 1476221Snate@binkert.org trapSquash[tid] = false; 1486221Snate@binkert.org tcSquash[tid] = false; 1497720Sgblack@eecs.umich.edu pc[tid].set(0); 1507855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = 0; 1512292SN/A } 1523640Sktlim@umich.edu#if FULL_SYSTEM 1533640Sktlim@umich.edu interrupt = NoFault; 1543640Sktlim@umich.edu#endif 1552292SN/A} 1562292SN/A 1572292SN/Atemplate <class Impl> 1582292SN/Astd::string 1592292SN/ADefaultCommit<Impl>::name() const 1602292SN/A{ 1612292SN/A return cpu->name() + ".commit"; 1622292SN/A} 1632292SN/A 1642292SN/Atemplate <class Impl> 1652292SN/Avoid 1662292SN/ADefaultCommit<Impl>::regStats() 1672132SN/A{ 1682301SN/A using namespace Stats; 1691062SN/A commitCommittedInsts 1701062SN/A .name(name() + ".commitCommittedInsts") 1711062SN/A .desc("The number of committed instructions") 1721062SN/A .prereq(commitCommittedInsts); 1731062SN/A commitSquashedInsts 1741062SN/A .name(name() + ".commitSquashedInsts") 1751062SN/A .desc("The number of squashed insts skipped by commit") 1761062SN/A .prereq(commitSquashedInsts); 1771062SN/A commitSquashEvents 1781062SN/A .name(name() + ".commitSquashEvents") 1791062SN/A .desc("The number of times commit is told to squash") 1801062SN/A .prereq(commitSquashEvents); 1811062SN/A commitNonSpecStalls 1821062SN/A .name(name() + ".commitNonSpecStalls") 1831062SN/A .desc("The number of times commit has been forced to stall to " 1841062SN/A "communicate backwards") 1851062SN/A .prereq(commitNonSpecStalls); 1861062SN/A branchMispredicts 1871062SN/A .name(name() + ".branchMispredicts") 1881062SN/A .desc("The number of times a branch was mispredicted") 1891062SN/A .prereq(branchMispredicts); 1902292SN/A numCommittedDist 1911062SN/A .init(0,commitWidth,1) 1928240Snate@binkert.org .name(name() + ".committed_per_cycle") 1931062SN/A .desc("Number of insts commited each cycle") 1941062SN/A .flags(Stats::pdf) 1951062SN/A ; 1962301SN/A 1972316SN/A statComInst 1986221Snate@binkert.org .init(cpu->numThreads) 1998240Snate@binkert.org .name(name() + ".count") 2002301SN/A .desc("Number of instructions committed") 2012301SN/A .flags(total) 2022301SN/A ; 2032301SN/A 2042316SN/A statComSwp 2056221Snate@binkert.org .init(cpu->numThreads) 2068240Snate@binkert.org .name(name() + ".swp_count") 2072301SN/A .desc("Number of s/w prefetches committed") 2082301SN/A .flags(total) 2092301SN/A ; 2102301SN/A 2112316SN/A statComRefs 2126221Snate@binkert.org .init(cpu->numThreads) 2138240Snate@binkert.org .name(name() + ".refs") 2142301SN/A .desc("Number of memory references committed") 2152301SN/A .flags(total) 2162301SN/A ; 2172301SN/A 2182316SN/A statComLoads 2196221Snate@binkert.org .init(cpu->numThreads) 2208240Snate@binkert.org .name(name() + ".loads") 2212301SN/A .desc("Number of loads committed") 2222301SN/A .flags(total) 2232301SN/A ; 2242301SN/A 2252316SN/A statComMembars 2266221Snate@binkert.org .init(cpu->numThreads) 2278240Snate@binkert.org .name(name() + ".membars") 2282301SN/A .desc("Number of memory barriers committed") 2292301SN/A .flags(total) 2302301SN/A ; 2312301SN/A 2322316SN/A statComBranches 2336221Snate@binkert.org .init(cpu->numThreads) 2348240Snate@binkert.org .name(name() + ".branches") 2352301SN/A .desc("Number of branches committed") 2362301SN/A .flags(total) 2372301SN/A ; 2382301SN/A 2397897Shestness@cs.utexas.edu statComFloating 2407897Shestness@cs.utexas.edu .init(cpu->numThreads) 2418240Snate@binkert.org .name(name() + ".fp_insts") 2427897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2437897Shestness@cs.utexas.edu .flags(total) 2447897Shestness@cs.utexas.edu ; 2457897Shestness@cs.utexas.edu 2467897Shestness@cs.utexas.edu statComInteger 2477897Shestness@cs.utexas.edu .init(cpu->numThreads) 2488240Snate@binkert.org .name(name()+".int_insts") 2497897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2507897Shestness@cs.utexas.edu .flags(total) 2517897Shestness@cs.utexas.edu ; 2527897Shestness@cs.utexas.edu 2537897Shestness@cs.utexas.edu statComFunctionCalls 2547897Shestness@cs.utexas.edu .init(cpu->numThreads) 2558240Snate@binkert.org .name(name()+".function_calls") 2567897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2577897Shestness@cs.utexas.edu .flags(total) 2587897Shestness@cs.utexas.edu ; 2597897Shestness@cs.utexas.edu 2602316SN/A commitEligible 2616221Snate@binkert.org .init(cpu->numThreads) 2628240Snate@binkert.org .name(name() + ".bw_limited") 2632301SN/A .desc("number of insts not committed due to BW limits") 2642301SN/A .flags(total) 2652301SN/A ; 2662301SN/A 2672316SN/A commitEligibleSamples 2688240Snate@binkert.org .name(name() + ".bw_lim_events") 2692301SN/A .desc("number cycles where commit BW limit reached") 2702301SN/A ; 2711062SN/A} 2721062SN/A 2731062SN/Atemplate <class Impl> 2741062SN/Avoid 2752980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2762292SN/A{ 2772292SN/A thread = threads; 2782292SN/A} 2792292SN/A 2802292SN/Atemplate <class Impl> 2812292SN/Avoid 2822292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2831060SN/A{ 2841060SN/A timeBuffer = tb_ptr; 2851060SN/A 2861060SN/A // Setup wire to send information back to IEW. 2871060SN/A toIEW = timeBuffer->getWire(0); 2881060SN/A 2891060SN/A // Setup wire to read data from IEW (for the ROB). 2901060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2911060SN/A} 2921060SN/A 2931061SN/Atemplate <class Impl> 2941060SN/Avoid 2952292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2962292SN/A{ 2972292SN/A fetchQueue = fq_ptr; 2982292SN/A 2992292SN/A // Setup wire to get instructions from rename (for the ROB). 3002292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 3012292SN/A} 3022292SN/A 3032292SN/Atemplate <class Impl> 3042292SN/Avoid 3052292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3061060SN/A{ 3071060SN/A renameQueue = rq_ptr; 3081060SN/A 3091060SN/A // Setup wire to get instructions from rename (for the ROB). 3101060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3111060SN/A} 3121060SN/A 3131061SN/Atemplate <class Impl> 3141060SN/Avoid 3152292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3161060SN/A{ 3171060SN/A iewQueue = iq_ptr; 3181060SN/A 3191060SN/A // Setup wire to get instructions from IEW. 3201060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3211060SN/A} 3221060SN/A 3231061SN/Atemplate <class Impl> 3241060SN/Avoid 3252292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3262292SN/A{ 3272292SN/A iewStage = iew_stage; 3282292SN/A} 3292292SN/A 3302292SN/Atemplate<class Impl> 3312292SN/Avoid 3326221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3332292SN/A{ 3342292SN/A activeThreads = at_ptr; 3352292SN/A} 3362292SN/A 3372292SN/Atemplate <class Impl> 3382292SN/Avoid 3392292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3402292SN/A{ 3416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3426221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3432292SN/A} 3442292SN/A 3452292SN/Atemplate <class Impl> 3462292SN/Avoid 3472292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3481060SN/A{ 3491060SN/A rob = rob_ptr; 3501060SN/A} 3511060SN/A 3521061SN/Atemplate <class Impl> 3531060SN/Avoid 3542292SN/ADefaultCommit<Impl>::initStage() 3551060SN/A{ 3562292SN/A rob->setActiveThreads(activeThreads); 3572292SN/A rob->resetEntries(); 3581060SN/A 3592292SN/A // Broadcast the number of free entries. 3606221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3616221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3626221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3636221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3641060SN/A } 3651060SN/A 3664329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3674329Sktlim@umich.edu // start of the simulation, so it starts as active. 3684329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3694329Sktlim@umich.edu 3702292SN/A cpu->activityThisCycle(); 3715100Ssaidi@eecs.umich.edu trapLatency = cpu->ticks(trapLatency); 3721060SN/A} 3731060SN/A 3741061SN/Atemplate <class Impl> 3752863Sktlim@umich.edubool 3762843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3771060SN/A{ 3782843Sktlim@umich.edu drainPending = true; 3792863Sktlim@umich.edu 3802863Sktlim@umich.edu return false; 3812316SN/A} 3822316SN/A 3832316SN/Atemplate <class Impl> 3842316SN/Avoid 3852843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3862316SN/A{ 3872316SN/A switchedOut = true; 3882843Sktlim@umich.edu drainPending = false; 3892307SN/A rob->switchOut(); 3902307SN/A} 3912307SN/A 3922307SN/Atemplate <class Impl> 3932307SN/Avoid 3942843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3952843Sktlim@umich.edu{ 3962864Sktlim@umich.edu drainPending = false; 3972843Sktlim@umich.edu} 3982843Sktlim@umich.edu 3992843Sktlim@umich.edutemplate <class Impl> 4002843Sktlim@umich.eduvoid 4012307SN/ADefaultCommit<Impl>::takeOverFrom() 4022307SN/A{ 4032316SN/A switchedOut = false; 4042307SN/A _status = Active; 4052307SN/A _nextStatus = Inactive; 4066221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4076221Snate@binkert.org commitStatus[tid] = Idle; 4086221Snate@binkert.org changedROBNumEntries[tid] = false; 4096221Snate@binkert.org trapSquash[tid] = false; 4106221Snate@binkert.org tcSquash[tid] = false; 4112307SN/A } 4122307SN/A squashCounter = 0; 4132307SN/A rob->takeOverFrom(); 4142307SN/A} 4152307SN/A 4162307SN/Atemplate <class Impl> 4172307SN/Avoid 4182292SN/ADefaultCommit<Impl>::updateStatus() 4192132SN/A{ 4202316SN/A // reset ROB changed variable 4216221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4226221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4233867Sbinkertn@umich.edu 4243867Sbinkertn@umich.edu while (threads != end) { 4256221Snate@binkert.org ThreadID tid = *threads++; 4263867Sbinkertn@umich.edu 4272316SN/A changedROBNumEntries[tid] = false; 4282316SN/A 4292316SN/A // Also check if any of the threads has a trap pending 4302316SN/A if (commitStatus[tid] == TrapPending || 4312316SN/A commitStatus[tid] == FetchTrapPending) { 4322316SN/A _nextStatus = Active; 4332316SN/A } 4342292SN/A } 4352292SN/A 4362292SN/A if (_nextStatus == Inactive && _status == Active) { 4372292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4382733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4392292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4402292SN/A DPRINTF(Activity, "Activating stage.\n"); 4412733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4422292SN/A } 4432292SN/A 4442292SN/A _status = _nextStatus; 4452292SN/A} 4462292SN/A 4472292SN/Atemplate <class Impl> 4482292SN/Avoid 4492292SN/ADefaultCommit<Impl>::setNextStatus() 4502292SN/A{ 4512292SN/A int squashes = 0; 4522292SN/A 4536221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4546221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4552292SN/A 4563867Sbinkertn@umich.edu while (threads != end) { 4576221Snate@binkert.org ThreadID tid = *threads++; 4582292SN/A 4592292SN/A if (commitStatus[tid] == ROBSquashing) { 4602292SN/A squashes++; 4612292SN/A } 4622292SN/A } 4632292SN/A 4642702Sktlim@umich.edu squashCounter = squashes; 4652292SN/A 4662292SN/A // If commit is currently squashing, then it will have activity for the 4672292SN/A // next cycle. Set its next status as active. 4682292SN/A if (squashCounter) { 4692292SN/A _nextStatus = Active; 4702292SN/A } 4712292SN/A} 4722292SN/A 4732292SN/Atemplate <class Impl> 4742292SN/Abool 4752292SN/ADefaultCommit<Impl>::changedROBEntries() 4762292SN/A{ 4776221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4786221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4792292SN/A 4803867Sbinkertn@umich.edu while (threads != end) { 4816221Snate@binkert.org ThreadID tid = *threads++; 4822292SN/A 4832292SN/A if (changedROBNumEntries[tid]) { 4842292SN/A return true; 4852292SN/A } 4862292SN/A } 4872292SN/A 4882292SN/A return false; 4892292SN/A} 4902292SN/A 4912292SN/Atemplate <class Impl> 4926221Snate@binkert.orgsize_t 4936221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 4942292SN/A{ 4952292SN/A return rob->numFreeEntries(tid); 4962292SN/A} 4972292SN/A 4982292SN/Atemplate <class Impl> 4992292SN/Avoid 5006221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 5012292SN/A{ 5022292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5032292SN/A 5042292SN/A TrapEvent *trap = new TrapEvent(this, tid); 5052292SN/A 5067823Ssteve.reinhardt@amd.com cpu->schedule(trap, curTick() + trapLatency); 5074035Sktlim@umich.edu trapInFlight[tid] = true; 5088518Sgeoffrey.blake@arm.com thread[tid]->trapPending = true; 5092292SN/A} 5102292SN/A 5112292SN/Atemplate <class Impl> 5122292SN/Avoid 5136221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5142292SN/A{ 5154035Sktlim@umich.edu assert(!trapInFlight[tid]); 5162680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5172292SN/A 5182680Sktlim@umich.edu tcSquash[tid] = true; 5192292SN/A} 5202292SN/A 5212292SN/Atemplate <class Impl> 5222292SN/Avoid 5236221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5242292SN/A{ 5252292SN/A // If we want to include the squashing instruction in the squash, 5262292SN/A // then use one older sequence number. 5272292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5282292SN/A // all instructions of this thread. 5292292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5307855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5312292SN/A 5322292SN/A // All younger instructions will be squashed. Set the sequence 5332292SN/A // number as the youngest instruction in the ROB (0 in this case. 5342292SN/A // Hopefully nothing breaks.) 5357855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5362292SN/A 5372292SN/A rob->squash(squashed_inst, tid); 5382292SN/A changedROBNumEntries[tid] = true; 5392292SN/A 5402292SN/A // Send back the sequence number of the squashed instruction. 5412292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5422292SN/A 5432292SN/A // Send back the squash signal to tell stages that they should 5442292SN/A // squash. 5452292SN/A toIEW->commitInfo[tid].squash = true; 5462292SN/A 5472292SN/A // Send back the rob squashing signal so other stages know that 5482292SN/A // the ROB is in the process of squashing. 5492292SN/A toIEW->commitInfo[tid].robSquashing = true; 5502292SN/A 5517851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 5528137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 5532292SN/A 5547720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5552316SN/A} 5562292SN/A 5572316SN/Atemplate <class Impl> 5582316SN/Avoid 5596221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5602316SN/A{ 5612316SN/A squashAll(tid); 5622316SN/A 5637720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5642316SN/A 5652316SN/A thread[tid]->trapPending = false; 5662316SN/A thread[tid]->inSyscall = false; 5674035Sktlim@umich.edu trapInFlight[tid] = false; 5682316SN/A 5692316SN/A trapSquash[tid] = false; 5702316SN/A 5712316SN/A commitStatus[tid] = ROBSquashing; 5722316SN/A cpu->activityThisCycle(); 5732316SN/A} 5742316SN/A 5752316SN/Atemplate <class Impl> 5762316SN/Avoid 5776221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 5782316SN/A{ 5792316SN/A squashAll(tid); 5802292SN/A 5817720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 5822292SN/A 5832292SN/A thread[tid]->inSyscall = false; 5842292SN/A assert(!thread[tid]->trapPending); 5852316SN/A 5862292SN/A commitStatus[tid] = ROBSquashing; 5872292SN/A cpu->activityThisCycle(); 5882292SN/A 5892680Sktlim@umich.edu tcSquash[tid] = false; 5902292SN/A} 5912292SN/A 5922292SN/Atemplate <class Impl> 5932292SN/Avoid 5948137SAli.Saidi@ARM.comDefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst, 5958137SAli.Saidi@ARM.com uint64_t squash_after_seq_num) 5967784SAli.Saidi@ARM.com{ 5977784SAli.Saidi@ARM.com youngestSeqNum[tid] = squash_after_seq_num; 5987784SAli.Saidi@ARM.com 5997784SAli.Saidi@ARM.com rob->squash(squash_after_seq_num, tid); 6007784SAli.Saidi@ARM.com changedROBNumEntries[tid] = true; 6017784SAli.Saidi@ARM.com 6027784SAli.Saidi@ARM.com // Send back the sequence number of the squashed instruction. 6037784SAli.Saidi@ARM.com toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 6047784SAli.Saidi@ARM.com 6058137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = head_inst; 6067784SAli.Saidi@ARM.com // Send back the squash signal to tell stages that they should squash. 6077784SAli.Saidi@ARM.com toIEW->commitInfo[tid].squash = true; 6087784SAli.Saidi@ARM.com 6097784SAli.Saidi@ARM.com // Send back the rob squashing signal so other stages know that 6107784SAli.Saidi@ARM.com // the ROB is in the process of squashing. 6117784SAli.Saidi@ARM.com toIEW->commitInfo[tid].robSquashing = true; 6127784SAli.Saidi@ARM.com 6138137SAli.Saidi@ARM.com toIEW->commitInfo[tid].mispredictInst = NULL; 6147784SAli.Saidi@ARM.com 6157784SAli.Saidi@ARM.com toIEW->commitInfo[tid].pc = pc[tid]; 6167784SAli.Saidi@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6177784SAli.Saidi@ARM.com tid, squash_after_seq_num); 6187784SAli.Saidi@ARM.com commitStatus[tid] = ROBSquashing; 6197784SAli.Saidi@ARM.com} 6207784SAli.Saidi@ARM.com 6217784SAli.Saidi@ARM.comtemplate <class Impl> 6227784SAli.Saidi@ARM.comvoid 6232292SN/ADefaultCommit<Impl>::tick() 6242292SN/A{ 6252292SN/A wroteToTimeBuffer = false; 6262292SN/A _nextStatus = Inactive; 6272292SN/A 6282843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 6292843Sktlim@umich.edu cpu->signalDrained(); 6302843Sktlim@umich.edu drainPending = false; 6312316SN/A return; 6322316SN/A } 6332316SN/A 6343867Sbinkertn@umich.edu if (activeThreads->empty()) 6352875Sksewell@umich.edu return; 6362875Sksewell@umich.edu 6376221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6386221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6392292SN/A 6402316SN/A // Check if any of the threads are done squashing. Change the 6412316SN/A // status if they are done. 6423867Sbinkertn@umich.edu while (threads != end) { 6436221Snate@binkert.org ThreadID tid = *threads++; 6442292SN/A 6454035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6464035Sktlim@umich.edu // this cycle. 6474035Sktlim@umich.edu committedStores[tid] = false; 6484035Sktlim@umich.edu 6492292SN/A if (commitStatus[tid] == ROBSquashing) { 6502292SN/A 6512292SN/A if (rob->isDoneSquashing(tid)) { 6522292SN/A commitStatus[tid] = Running; 6532292SN/A } else { 6542292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6552877Sksewell@umich.edu " insts this cycle.\n", tid); 6562702Sktlim@umich.edu rob->doSquash(tid); 6572702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6582702Sktlim@umich.edu wroteToTimeBuffer = true; 6592292SN/A } 6602292SN/A } 6612292SN/A } 6622292SN/A 6632292SN/A commit(); 6642292SN/A 6652292SN/A markCompletedInsts(); 6662292SN/A 6673867Sbinkertn@umich.edu threads = activeThreads->begin(); 6682292SN/A 6693867Sbinkertn@umich.edu while (threads != end) { 6706221Snate@binkert.org ThreadID tid = *threads++; 6712292SN/A 6722292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6732292SN/A // The ROB has more instructions it can commit. Its next status 6742292SN/A // will be active. 6752292SN/A _nextStatus = Active; 6762292SN/A 6772292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6782292SN/A 6797720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 6802292SN/A " ROB and ready to commit\n", 6817720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6822292SN/A 6832292SN/A } else if (!rob->isEmpty(tid)) { 6842292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6852292SN/A 6862292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6877720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 6887720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6892292SN/A } 6902292SN/A 6912292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6922292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6932292SN/A } 6942292SN/A 6952292SN/A 6962292SN/A if (wroteToTimeBuffer) { 6972316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6982292SN/A cpu->activityThisCycle(); 6992292SN/A } 7002292SN/A 7012292SN/A updateStatus(); 7022292SN/A} 7032292SN/A 7044035Sktlim@umich.edu#if FULL_SYSTEM 7052292SN/Atemplate <class Impl> 7062292SN/Avoid 7074035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 7082292SN/A{ 7097847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7107847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7117847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7127847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7137847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7147847Sminkyu.jeong@arm.com interrupt = NoFault; 7157847Sminkyu.jeong@arm.com return; 7167847Sminkyu.jeong@arm.com } 7173633Sktlim@umich.edu 7188493Sgblack@eecs.umich.edu // Wait until all in flight instructions are finished before enterring 7198493Sgblack@eecs.umich.edu // the interrupt. 7208493Sgblack@eecs.umich.edu if (cpu->instList.empty()) { 7217847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7227847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7237847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7244035Sktlim@umich.edu 7257847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7267847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7272292SN/A 7287847Sminkyu.jeong@arm.com assert(!thread[0]->inSyscall); 7297847Sminkyu.jeong@arm.com thread[0]->inSyscall = true; 7302292SN/A 7317847Sminkyu.jeong@arm.com // CPU will handle interrupt. 7327847Sminkyu.jeong@arm.com cpu->processInterrupts(interrupt); 7333633Sktlim@umich.edu 7347847Sminkyu.jeong@arm.com thread[0]->inSyscall = false; 7352292SN/A 7367847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7372292SN/A 7387847Sminkyu.jeong@arm.com // Generate trap squash event. 7397847Sminkyu.jeong@arm.com generateTrapEvent(0); 7403640Sktlim@umich.edu 7417847Sminkyu.jeong@arm.com interrupt = NoFault; 7427847Sminkyu.jeong@arm.com } else { 7437847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 7441060SN/A } 7454035Sktlim@umich.edu} 7467847Sminkyu.jeong@arm.com 7477847Sminkyu.jeong@arm.comtemplate <class Impl> 7487847Sminkyu.jeong@arm.comvoid 7497847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 7507847Sminkyu.jeong@arm.com{ 7517847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 7527847Sminkyu.jeong@arm.com tcSquash[0]) 7537847Sminkyu.jeong@arm.com return; 7547847Sminkyu.jeong@arm.com 7557847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 7567847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 7577847Sminkyu.jeong@arm.com // pending. 7587847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 7597847Sminkyu.jeong@arm.com 7607847Sminkyu.jeong@arm.com // Get any interrupt that happened 7617847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 7627847Sminkyu.jeong@arm.com 7637847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 7647847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 7657847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 7667847Sminkyu.jeong@arm.com if (interrupt != NoFault) 7677847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 7687847Sminkyu.jeong@arm.com} 7697847Sminkyu.jeong@arm.com 7704035Sktlim@umich.edu#endif // FULL_SYSTEM 7713634Sktlim@umich.edu 7724035Sktlim@umich.edutemplate <class Impl> 7734035Sktlim@umich.eduvoid 7744035Sktlim@umich.eduDefaultCommit<Impl>::commit() 7754035Sktlim@umich.edu{ 7764035Sktlim@umich.edu 7774035Sktlim@umich.edu#if FULL_SYSTEM 7787847Sminkyu.jeong@arm.com // Check for any interrupt that we've already squashed for and start processing it. 7797847Sminkyu.jeong@arm.com if (interrupt != NoFault) 7804035Sktlim@umich.edu handleInterrupt(); 7817847Sminkyu.jeong@arm.com 7827847Sminkyu.jeong@arm.com // Check if we have a interrupt and get read to handle it 7837847Sminkyu.jeong@arm.com if (cpu->checkInterrupts(cpu->tcBase(0))) 7847847Sminkyu.jeong@arm.com propagateInterrupt(); 7851060SN/A#endif // FULL_SYSTEM 7861060SN/A 7871060SN/A //////////////////////////////////// 7882316SN/A // Check for any possible squashes, handle them first 7891060SN/A //////////////////////////////////// 7906221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7916221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7921060SN/A 7933867Sbinkertn@umich.edu while (threads != end) { 7946221Snate@binkert.org ThreadID tid = *threads++; 7951060SN/A 7962292SN/A // Not sure which one takes priority. I think if we have 7972292SN/A // both, that's a bad sign. 7982292SN/A if (trapSquash[tid] == true) { 7992680Sktlim@umich.edu assert(!tcSquash[tid]); 8002292SN/A squashFromTrap(tid); 8012680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 8024035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 8032680Sktlim@umich.edu squashFromTC(tid); 8042292SN/A } 8051061SN/A 8062292SN/A // Squashed sequence number must be older than youngest valid 8072292SN/A // instruction in the ROB. This prevents squashes from younger 8082292SN/A // instructions overriding squashes from older instructions. 8092292SN/A if (fromIEW->squash[tid] && 8102292SN/A commitStatus[tid] != TrapPending && 8112292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8121061SN/A 8138137SAli.Saidi@ARM.com if (fromIEW->mispredictInst[tid]) { 8148137SAli.Saidi@ARM.com DPRINTF(Commit, 8158137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 8162292SN/A tid, 8178137SAli.Saidi@ARM.com fromIEW->mispredictInst[tid]->instAddr(), 8182292SN/A fromIEW->squashedSeqNum[tid]); 8198137SAli.Saidi@ARM.com } else { 8208137SAli.Saidi@ARM.com DPRINTF(Commit, 8218137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to order violation [sn:%i]\n", 8228137SAli.Saidi@ARM.com tid, fromIEW->squashedSeqNum[tid]); 8238137SAli.Saidi@ARM.com } 8241061SN/A 8252292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8262292SN/A tid, 8277720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8281061SN/A 8292292SN/A commitStatus[tid] = ROBSquashing; 8301061SN/A 8312292SN/A // If we want to include the squashing instruction in the squash, 8322292SN/A // then use one older sequence number. 8332292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8341062SN/A 8352935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 8362292SN/A squashed_inst--; 8372935Sksewell@umich.edu } 8384035Sktlim@umich.edu 8392292SN/A // All younger instructions will be squashed. Set the sequence 8402292SN/A // number as the youngest instruction in the ROB. 8412292SN/A youngestSeqNum[tid] = squashed_inst; 8422292SN/A 8433093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8442292SN/A changedROBNumEntries[tid] = true; 8452292SN/A 8462292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8472292SN/A 8482292SN/A toIEW->commitInfo[tid].squash = true; 8492292SN/A 8502292SN/A // Send back the rob squashing signal so other stages know that 8512292SN/A // the ROB is in the process of squashing. 8522292SN/A toIEW->commitInfo[tid].robSquashing = true; 8532292SN/A 8547851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 8557851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 8562292SN/A toIEW->commitInfo[tid].branchTaken = 8572292SN/A fromIEW->branchTaken[tid]; 8588137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 8592292SN/A 8607720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 8612292SN/A 8628137SAli.Saidi@ARM.com if (toIEW->commitInfo[tid].mispredictInst) { 8632292SN/A ++branchMispredicts; 8642292SN/A } 8651062SN/A } 8662292SN/A 8671060SN/A } 8681060SN/A 8692292SN/A setNextStatus(); 8702292SN/A 8712292SN/A if (squashCounter != numThreads) { 8721061SN/A // If we're not currently squashing, then get instructions. 8731060SN/A getInsts(); 8741060SN/A 8751061SN/A // Try to commit any instructions. 8761060SN/A commitInsts(); 8771060SN/A } 8781060SN/A 8792292SN/A //Check for any activity 8803867Sbinkertn@umich.edu threads = activeThreads->begin(); 8812292SN/A 8823867Sbinkertn@umich.edu while (threads != end) { 8836221Snate@binkert.org ThreadID tid = *threads++; 8842292SN/A 8852292SN/A if (changedROBNumEntries[tid]) { 8862292SN/A toIEW->commitInfo[tid].usedROB = true; 8872292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8882292SN/A 8892292SN/A wroteToTimeBuffer = true; 8902292SN/A changedROBNumEntries[tid] = false; 8914035Sktlim@umich.edu if (rob->isEmpty(tid)) 8924035Sktlim@umich.edu checkEmptyROB[tid] = true; 8932292SN/A } 8944035Sktlim@umich.edu 8954035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8964035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 8974035Sktlim@umich.edu // stage has received any information regarding stores that 8984035Sktlim@umich.edu // committed. 8994035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 9004035Sktlim@umich.edu // on the same cycle as when stores have been committed. 9014035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 9024035Sktlim@umich.edu // commit and IEW. 9034035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9045557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9054035Sktlim@umich.edu checkEmptyROB[tid] = false; 9064035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 9074035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 9084035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9094035Sktlim@umich.edu wroteToTimeBuffer = true; 9104035Sktlim@umich.edu } 9114035Sktlim@umich.edu 9121060SN/A } 9131060SN/A} 9141060SN/A 9151061SN/Atemplate <class Impl> 9161060SN/Avoid 9172292SN/ADefaultCommit<Impl>::commitInsts() 9181060SN/A{ 9191060SN/A //////////////////////////////////// 9201060SN/A // Handle commit 9212316SN/A // Note that commit will be handled prior to putting new 9222316SN/A // instructions in the ROB so that the ROB only tries to commit 9232316SN/A // instructions it has in this current cycle, and not instructions 9242316SN/A // it is writing in during this cycle. Can't commit and squash 9252316SN/A // things at the same time... 9261060SN/A //////////////////////////////////// 9271060SN/A 9282292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9291060SN/A 9301060SN/A unsigned num_committed = 0; 9311060SN/A 9322292SN/A DynInstPtr head_inst; 9332316SN/A 9341060SN/A // Commit as many instructions as possible until the commit bandwidth 9351060SN/A // limit is reached, or it becomes impossible to commit any more. 9362292SN/A while (num_committed < commitWidth) { 9372292SN/A int commit_thread = getCommittingThread(); 9381060SN/A 9392292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9402292SN/A break; 9412292SN/A 9422292SN/A head_inst = rob->readHeadInst(commit_thread); 9432292SN/A 9446221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 9452292SN/A 9462292SN/A assert(tid == commit_thread); 9472292SN/A 9482292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 9492292SN/A head_inst->seqNum, tid); 9502132SN/A 9512316SN/A // If the head instruction is squashed, it is ready to retire 9522316SN/A // (be removed from the ROB) at any time. 9531060SN/A if (head_inst->isSquashed()) { 9541060SN/A 9552292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 9561060SN/A "ROB.\n"); 9571060SN/A 9582292SN/A rob->retireHead(commit_thread); 9591060SN/A 9601062SN/A ++commitSquashedInsts; 9611062SN/A 9622292SN/A // Record that the number of ROB entries has changed. 9632292SN/A changedROBNumEntries[tid] = true; 9641060SN/A } else { 9657720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 9662292SN/A 9671060SN/A // Increment the total number of non-speculative instructions 9681060SN/A // executed. 9691060SN/A // Hack for now: it really shouldn't happen until after the 9701061SN/A // commit is deemed to be successful, but this count is needed 9711061SN/A // for syscalls. 9722292SN/A thread[tid]->funcExeInst++; 9731060SN/A 9741060SN/A // Try to commit the head instruction. 9751060SN/A bool commit_success = commitHead(head_inst, num_committed); 9761060SN/A 9771062SN/A if (commit_success) { 9781060SN/A ++num_committed; 9791060SN/A 9802292SN/A changedROBNumEntries[tid] = true; 9812292SN/A 9822292SN/A // Set the doneSeqNum to the youngest committed instruction. 9832292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9841060SN/A 9851062SN/A ++commitCommittedInsts; 9861062SN/A 9872292SN/A // To match the old model, don't count nops and instruction 9882292SN/A // prefetches towards the total commit count. 9892292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9902292SN/A cpu->instDone(tid); 9911062SN/A } 9922292SN/A 9937783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 9947783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 9957783SGiacomo.Gabrielli@arm.com 9968662SAli.Saidi@ARM.com cpu->traceFunctions(pc[tid].instAddr()); 9978662SAli.Saidi@ARM.com 9987720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 9992935Sksewell@umich.edu 10007855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 10017855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 10027855SAli.Saidi@ARM.com 10037784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 10047784SAli.Saidi@ARM.com // others squash everything and restart fetch 10057784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 10068137SAli.Saidi@ARM.com squashAfter(tid, head_inst, head_inst->seqNum); 10077784SAli.Saidi@ARM.com 10082292SN/A int count = 0; 10092292SN/A Addr oldpc; 10105108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 10115108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 10125108Sgblack@eecs.umich.edu assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 10132292SN/A do { 10147720Sgblack@eecs.umich.edu oldpc = pc[tid].instAddr(); 10155108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 10162292SN/A count++; 10177720Sgblack@eecs.umich.edu } while (oldpc != pc[tid].instAddr()); 10182292SN/A if (count > 1) { 10195108Sgblack@eecs.umich.edu DPRINTF(Commit, 10205108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 10212292SN/A break; 10222292SN/A } 10231060SN/A } else { 10247720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 10252292SN/A "[tid:%i] [sn:%i].\n", 10267720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 10271060SN/A break; 10281060SN/A } 10291060SN/A } 10301060SN/A } 10311062SN/A 10321063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 10332292SN/A numCommittedDist.sample(num_committed); 10342307SN/A 10352307SN/A if (num_committed == commitWidth) { 10362349SN/A commitEligibleSamples++; 10372307SN/A } 10381060SN/A} 10391060SN/A 10401061SN/Atemplate <class Impl> 10411060SN/Abool 10422292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 10431060SN/A{ 10441060SN/A assert(head_inst); 10451060SN/A 10466221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 10472292SN/A 10482316SN/A // If the instruction is not executed yet, then it will need extra 10492316SN/A // handling. Signal backwards that it should be executed. 10501061SN/A if (!head_inst->isExecuted()) { 10511061SN/A // Keep this number correct. We have not yet actually executed 10521061SN/A // and committed this instruction. 10532292SN/A thread[tid]->funcExeInst--; 10541062SN/A 10552292SN/A if (head_inst->isNonSpeculative() || 10562348SN/A head_inst->isStoreConditional() || 10572292SN/A head_inst->isMemBarrier() || 10582292SN/A head_inst->isWriteBarrier()) { 10592316SN/A 10602316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 10617720Sgblack@eecs.umich.edu "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 10627720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 10632316SN/A 10645557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 10652292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10662292SN/A return false; 10672292SN/A } 10682292SN/A 10692292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10701061SN/A 10711061SN/A // Change the instruction so it won't try to commit again until 10721061SN/A // it is executed. 10731061SN/A head_inst->clearCanCommit(); 10741061SN/A 10751062SN/A ++commitNonSpecStalls; 10761062SN/A 10771061SN/A return false; 10782292SN/A } else if (head_inst->isLoad()) { 10795557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 10804035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10814035Sktlim@umich.edu return false; 10824035Sktlim@umich.edu } 10834035Sktlim@umich.edu 10844035Sktlim@umich.edu assert(head_inst->uncacheable()); 10857720Sgblack@eecs.umich.edu DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 10867720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 10872292SN/A 10882292SN/A // Send back the non-speculative instruction's sequence 10892316SN/A // number. Tell the lsq to re-execute the load. 10902292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10912292SN/A toIEW->commitInfo[tid].uncached = true; 10922292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10932292SN/A 10942292SN/A head_inst->clearCanCommit(); 10952292SN/A 10962292SN/A return false; 10971061SN/A } else { 10982292SN/A panic("Trying to commit un-executed instruction " 10991061SN/A "of unknown type!\n"); 11001061SN/A } 11011060SN/A } 11021060SN/A 11032316SN/A if (head_inst->isThreadSync()) { 11042292SN/A // Not handled for now. 11052316SN/A panic("Thread sync instructions are not handled yet.\n"); 11062132SN/A } 11072132SN/A 11084035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 11094035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 11104035Sktlim@umich.edu 11112316SN/A // Stores mark themselves as completed. 11124035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 11132310SN/A head_inst->setCompleted(); 11142310SN/A } 11152310SN/A 11162733Sktlim@umich.edu#if USE_CHECKER 11172316SN/A // Use checker prior to updating anything due to traps or PC 11182316SN/A // based events. 11192316SN/A if (cpu->checker) { 11202732Sktlim@umich.edu cpu->checker->verify(head_inst); 11211060SN/A } 11222733Sktlim@umich.edu#endif 11231060SN/A 11242112SN/A if (inst_fault != NoFault) { 11257720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 11267720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11272292SN/A 11285557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 11292316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 11302316SN/A return false; 11312316SN/A } 11322310SN/A 11334035Sktlim@umich.edu head_inst->setCompleted(); 11344035Sktlim@umich.edu 11352733Sktlim@umich.edu#if USE_CHECKER 11362316SN/A if (cpu->checker && head_inst->isStore()) { 11372732Sktlim@umich.edu cpu->checker->verify(head_inst); 11382316SN/A } 11392733Sktlim@umich.edu#endif 11402292SN/A 11412316SN/A assert(!thread[tid]->inSyscall); 11422292SN/A 11432316SN/A // Mark that we're in state update mode so that the trap's 11442316SN/A // execution doesn't generate extra squashes. 11452316SN/A thread[tid]->inSyscall = true; 11462292SN/A 11472316SN/A // Execute the trap. Although it's slightly unrealistic in 11482316SN/A // terms of timing (as it doesn't wait for the full timing of 11492316SN/A // the trap event to complete before updating state), it's 11502316SN/A // needed to update the state as soon as possible. This 11512316SN/A // prevents external agents from changing any specific state 11522316SN/A // that the trap need. 11537684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 11542292SN/A 11552316SN/A // Exit state update mode to avoid accidental updating. 11562316SN/A thread[tid]->inSyscall = false; 11572292SN/A 11582316SN/A commitStatus[tid] = TrapPending; 11592292SN/A 11608067SAli.Saidi@ARM.com DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 11618067SAli.Saidi@ARM.com head_inst->seqNum); 11624035Sktlim@umich.edu if (head_inst->traceData) { 11636667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 11646667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 11656667Ssteve.reinhardt@amd.com head_inst->traceData->setCPSeq(thread[tid]->numInst); 11666667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 11676667Ssteve.reinhardt@amd.com } 11684288Sktlim@umich.edu delete head_inst->traceData; 11694035Sktlim@umich.edu head_inst->traceData = NULL; 11704035Sktlim@umich.edu } 11714035Sktlim@umich.edu 11722316SN/A // Generate trap squash event. 11732316SN/A generateTrapEvent(tid); 11742316SN/A return false; 11751060SN/A } 11761060SN/A 11772301SN/A updateComInstStats(head_inst); 11782132SN/A 11792362SN/A#if FULL_SYSTEM 11802362SN/A if (thread[tid]->profile) { 11817720Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 11823126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 11832362SN/A head_inst->staticInst); 11842362SN/A 11852362SN/A if (node) 11862362SN/A thread[tid]->profileNode = node; 11872362SN/A } 11885953Ssaidi@eecs.umich.edu if (CPA::available()) { 11895953Ssaidi@eecs.umich.edu if (head_inst->isControl()) { 11905953Ssaidi@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 11917720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 11925953Ssaidi@eecs.umich.edu } 11935953Ssaidi@eecs.umich.edu } 11942362SN/A#endif 11958516SMrinmoy.Ghosh@arm.com DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 11968516SMrinmoy.Ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 11972132SN/A if (head_inst->traceData) { 11982292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11992292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 12004046Sbinkertn@umich.edu head_inst->traceData->dump(); 12014046Sbinkertn@umich.edu delete head_inst->traceData; 12022292SN/A head_inst->traceData = NULL; 12031060SN/A } 12041060SN/A 12052292SN/A // Update the commit rename map 12062292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 12073771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 12082292SN/A head_inst->renamedDestRegIdx(i)); 12091060SN/A } 12101062SN/A 12112292SN/A // Finally clear the head ROB entry. 12122292SN/A rob->retireHead(tid); 12131060SN/A 12148471SGiacomo.Gabrielli@arm.com#if TRACING_ON 12158471SGiacomo.Gabrielli@arm.com // Print info needed by the pipeline activity viewer. 12168471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", 12178471SGiacomo.Gabrielli@arm.com head_inst->fetchTick, 12188471SGiacomo.Gabrielli@arm.com head_inst->instAddr(), 12198471SGiacomo.Gabrielli@arm.com head_inst->microPC(), 12208471SGiacomo.Gabrielli@arm.com head_inst->seqNum, 12218471SGiacomo.Gabrielli@arm.com head_inst->staticInst->disassemble(head_inst->instAddr())); 12228471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick); 12238471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick); 12248471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick); 12258471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick); 12268471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick); 12278471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick()); 12288471SGiacomo.Gabrielli@arm.com#endif 12298471SGiacomo.Gabrielli@arm.com 12304035Sktlim@umich.edu // If this was a store, record it for this cycle. 12314035Sktlim@umich.edu if (head_inst->isStore()) 12324035Sktlim@umich.edu committedStores[tid] = true; 12334035Sktlim@umich.edu 12341060SN/A // Return true to indicate that we have committed an instruction. 12351060SN/A return true; 12361060SN/A} 12371060SN/A 12381061SN/Atemplate <class Impl> 12391060SN/Avoid 12402292SN/ADefaultCommit<Impl>::getInsts() 12411060SN/A{ 12422935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 12432935Sksewell@umich.edu 12443093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 12453093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 12462965Sksewell@umich.edu 12472965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 12482965Sksewell@umich.edu DynInstPtr inst; 12492965Sksewell@umich.edu 12503093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 12516221Snate@binkert.org ThreadID tid = inst->threadNumber; 12522292SN/A 12532292SN/A if (!inst->isSquashed() && 12544035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 12554035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 12562292SN/A changedROBNumEntries[tid] = true; 12572292SN/A 12587720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 12597720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 12602292SN/A 12612292SN/A rob->insertInst(inst); 12622292SN/A 12632292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 12642292SN/A 12652292SN/A youngestSeqNum[tid] = inst->seqNum; 12661061SN/A } else { 12677720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 12681061SN/A "squashed, skipping.\n", 12697720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 12701061SN/A } 12711060SN/A } 12722965Sksewell@umich.edu} 12732965Sksewell@umich.edu 12742965Sksewell@umich.edutemplate <class Impl> 12752965Sksewell@umich.eduvoid 12762965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 12772965Sksewell@umich.edu{ 12782965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 12792965Sksewell@umich.edu "skidBuffer.\n"); 12802965Sksewell@umich.edu 12812965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 12822965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 12832965Sksewell@umich.edu 12842965Sksewell@umich.edu if (!inst->isSquashed()) { 12857720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 12867720Sgblack@eecs.umich.edu "skidBuffer.\n", inst->pcState(), inst->seqNum, 12873221Sktlim@umich.edu inst->threadNumber); 12882965Sksewell@umich.edu skidBuffer.push(inst); 12892965Sksewell@umich.edu } else { 12907720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 12912965Sksewell@umich.edu "squashed, skipping.\n", 12927720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->threadNumber); 12932965Sksewell@umich.edu } 12942965Sksewell@umich.edu } 12951060SN/A} 12961060SN/A 12971061SN/Atemplate <class Impl> 12981060SN/Avoid 12992292SN/ADefaultCommit<Impl>::markCompletedInsts() 13001060SN/A{ 13011060SN/A // Grab completed insts out of the IEW instruction queue, and mark 13021060SN/A // instructions completed within the ROB. 13031060SN/A for (int inst_num = 0; 13041681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 13051060SN/A ++inst_num) 13061060SN/A { 13072292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 13087720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 13092316SN/A "within ROB.\n", 13102292SN/A fromIEW->insts[inst_num]->threadNumber, 13117720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 13122292SN/A fromIEW->insts[inst_num]->seqNum); 13131060SN/A 13142292SN/A // Mark the instruction as ready to commit. 13152292SN/A fromIEW->insts[inst_num]->setCanCommit(); 13162292SN/A } 13171060SN/A } 13181060SN/A} 13191060SN/A 13201061SN/Atemplate <class Impl> 13212292SN/Abool 13222292SN/ADefaultCommit<Impl>::robDoneSquashing() 13231060SN/A{ 13246221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 13256221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 13262292SN/A 13273867Sbinkertn@umich.edu while (threads != end) { 13286221Snate@binkert.org ThreadID tid = *threads++; 13292292SN/A 13302292SN/A if (!rob->isDoneSquashing(tid)) 13312292SN/A return false; 13322292SN/A } 13332292SN/A 13342292SN/A return true; 13351060SN/A} 13362292SN/A 13372301SN/Atemplate <class Impl> 13382301SN/Avoid 13392301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 13402301SN/A{ 13416221Snate@binkert.org ThreadID tid = inst->threadNumber; 13422301SN/A 13432301SN/A // 13442301SN/A // Pick off the software prefetches 13452301SN/A // 13462301SN/A#ifdef TARGET_ALPHA 13472301SN/A if (inst->isDataPrefetch()) { 13486221Snate@binkert.org statComSwp[tid]++; 13492301SN/A } else { 13506221Snate@binkert.org statComInst[tid]++; 13512301SN/A } 13522301SN/A#else 13536221Snate@binkert.org statComInst[tid]++; 13542301SN/A#endif 13552301SN/A 13562301SN/A // 13572301SN/A // Control Instructions 13582301SN/A // 13592301SN/A if (inst->isControl()) 13606221Snate@binkert.org statComBranches[tid]++; 13612301SN/A 13622301SN/A // 13632301SN/A // Memory references 13642301SN/A // 13652301SN/A if (inst->isMemRef()) { 13666221Snate@binkert.org statComRefs[tid]++; 13672301SN/A 13682301SN/A if (inst->isLoad()) { 13696221Snate@binkert.org statComLoads[tid]++; 13702301SN/A } 13712301SN/A } 13722301SN/A 13732301SN/A if (inst->isMemBarrier()) { 13746221Snate@binkert.org statComMembars[tid]++; 13752301SN/A } 13767897Shestness@cs.utexas.edu 13777897Shestness@cs.utexas.edu // Integer Instruction 13787897Shestness@cs.utexas.edu if (inst->isInteger()) 13797897Shestness@cs.utexas.edu statComInteger[tid]++; 13807897Shestness@cs.utexas.edu 13817897Shestness@cs.utexas.edu // Floating Point Instruction 13827897Shestness@cs.utexas.edu if (inst->isFloating()) 13837897Shestness@cs.utexas.edu statComFloating[tid]++; 13847897Shestness@cs.utexas.edu 13857897Shestness@cs.utexas.edu // Function Calls 13867897Shestness@cs.utexas.edu if (inst->isCall()) 13877897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 13887897Shestness@cs.utexas.edu 13892301SN/A} 13902301SN/A 13912292SN/A//////////////////////////////////////// 13922292SN/A// // 13932316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 13942292SN/A// // 13952292SN/A//////////////////////////////////////// 13962292SN/Atemplate <class Impl> 13976221Snate@binkert.orgThreadID 13982292SN/ADefaultCommit<Impl>::getCommittingThread() 13992292SN/A{ 14002292SN/A if (numThreads > 1) { 14012292SN/A switch (commitPolicy) { 14022292SN/A 14032292SN/A case Aggressive: 14042292SN/A //If Policy is Aggressive, commit will call 14052292SN/A //this function multiple times per 14062292SN/A //cycle 14072292SN/A return oldestReady(); 14082292SN/A 14092292SN/A case RoundRobin: 14102292SN/A return roundRobin(); 14112292SN/A 14122292SN/A case OldestReady: 14132292SN/A return oldestReady(); 14142292SN/A 14152292SN/A default: 14166221Snate@binkert.org return InvalidThreadID; 14172292SN/A } 14182292SN/A } else { 14193867Sbinkertn@umich.edu assert(!activeThreads->empty()); 14206221Snate@binkert.org ThreadID tid = activeThreads->front(); 14212292SN/A 14222292SN/A if (commitStatus[tid] == Running || 14232292SN/A commitStatus[tid] == Idle || 14242292SN/A commitStatus[tid] == FetchTrapPending) { 14252292SN/A return tid; 14262292SN/A } else { 14276221Snate@binkert.org return InvalidThreadID; 14282292SN/A } 14292292SN/A } 14302292SN/A} 14312292SN/A 14322292SN/Atemplate<class Impl> 14336221Snate@binkert.orgThreadID 14342292SN/ADefaultCommit<Impl>::roundRobin() 14352292SN/A{ 14366221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14376221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14382292SN/A 14392292SN/A while (pri_iter != end) { 14406221Snate@binkert.org ThreadID tid = *pri_iter; 14412292SN/A 14422292SN/A if (commitStatus[tid] == Running || 14432831Sksewell@umich.edu commitStatus[tid] == Idle || 14442831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 14452292SN/A 14462292SN/A if (rob->isHeadReady(tid)) { 14472292SN/A priority_list.erase(pri_iter); 14482292SN/A priority_list.push_back(tid); 14492292SN/A 14502292SN/A return tid; 14512292SN/A } 14522292SN/A } 14532292SN/A 14542292SN/A pri_iter++; 14552292SN/A } 14562292SN/A 14576221Snate@binkert.org return InvalidThreadID; 14582292SN/A} 14592292SN/A 14602292SN/Atemplate<class Impl> 14616221Snate@binkert.orgThreadID 14622292SN/ADefaultCommit<Impl>::oldestReady() 14632292SN/A{ 14642292SN/A unsigned oldest = 0; 14652292SN/A bool first = true; 14662292SN/A 14676221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14686221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14692292SN/A 14703867Sbinkertn@umich.edu while (threads != end) { 14716221Snate@binkert.org ThreadID tid = *threads++; 14722292SN/A 14732292SN/A if (!rob->isEmpty(tid) && 14742292SN/A (commitStatus[tid] == Running || 14752292SN/A commitStatus[tid] == Idle || 14762292SN/A commitStatus[tid] == FetchTrapPending)) { 14772292SN/A 14782292SN/A if (rob->isHeadReady(tid)) { 14792292SN/A 14802292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 14812292SN/A 14822292SN/A if (first) { 14832292SN/A oldest = tid; 14842292SN/A first = false; 14852292SN/A } else if (head_inst->seqNum < oldest) { 14862292SN/A oldest = tid; 14872292SN/A } 14882292SN/A } 14892292SN/A } 14902292SN/A } 14912292SN/A 14922292SN/A if (!first) { 14932292SN/A return oldest; 14942292SN/A } else { 14956221Snate@binkert.org return InvalidThreadID; 14962292SN/A } 14972292SN/A} 1498