commit_impl.hh revision 8581
11689SN/A/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412965Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#include <algorithm> 452329SN/A#include <string> 462292SN/A 473577Sgblack@eecs.umich.edu#include "arch/utility.hh" 488229Snate@binkert.org#include "base/loader/symtab.hh" 495953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 506221Snate@binkert.org#include "config/full_system.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 526221Snate@binkert.org#include "config/use_checker.hh" 531717SN/A#include "cpu/o3/commit.hh" 542292SN/A#include "cpu/o3/thread_state.hh" 558229Snate@binkert.org#include "cpu/exetrace.hh" 568229Snate@binkert.org#include "cpu/timebuf.hh" 578232Snate@binkert.org#include "debug/Activity.hh" 588232Snate@binkert.org#include "debug/Commit.hh" 598232Snate@binkert.org#include "debug/CommitRate.hh" 608232Snate@binkert.org#include "debug/ExecFaulting.hh" 618471SGiacomo.Gabrielli@arm.com#include "debug/O3PipeView.hh" 626221Snate@binkert.org#include "params/DerivO3CPU.hh" 638230Snate@binkert.org#include "sim/faults.hh" 642292SN/A 652790Sktlim@umich.edu#if USE_CHECKER 662790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 672790Sktlim@umich.edu#endif 682790Sktlim@umich.edu 696221Snate@binkert.orgusing namespace std; 705529Snate@binkert.org 711061SN/Atemplate <class Impl> 722292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 736221Snate@binkert.org ThreadID _tid) 748581Ssteve.reinhardt@amd.com : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 751060SN/A{ 761060SN/A} 771060SN/A 781061SN/Atemplate <class Impl> 791060SN/Avoid 802292SN/ADefaultCommit<Impl>::TrapEvent::process() 811062SN/A{ 822316SN/A // This will get reset by commit if it was switched out at the 832316SN/A // time of this event processing. 842292SN/A commit->trapSquash[tid] = true; 852292SN/A} 862292SN/A 872292SN/Atemplate <class Impl> 882292SN/Aconst char * 895336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 902292SN/A{ 914873Sstever@eecs.umich.edu return "Trap"; 922292SN/A} 932292SN/A 942292SN/Atemplate <class Impl> 955529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 964329Sktlim@umich.edu : cpu(_cpu), 974329Sktlim@umich.edu squashCounter(0), 982292SN/A iewToCommitDelay(params->iewToCommitDelay), 992292SN/A commitToIEWDelay(params->commitToIEWDelay), 1002292SN/A renameToROBDelay(params->renameToROBDelay), 1012292SN/A fetchToCommitDelay(params->commitToFetchDelay), 1022292SN/A renameWidth(params->renameWidth), 1032292SN/A commitWidth(params->commitWidth), 1045529Snate@binkert.org numThreads(params->numThreads), 1052843Sktlim@umich.edu drainPending(false), 1062316SN/A switchedOut(false), 1072874Sktlim@umich.edu trapLatency(params->trapLatency) 1082292SN/A{ 1092292SN/A _status = Active; 1102292SN/A _nextStatus = Inactive; 1112980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1122292SN/A 1132292SN/A //Convert string to lowercase 1142292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1152292SN/A (int(*)(int)) tolower); 1162292SN/A 1172292SN/A //Assign commit policy 1182292SN/A if (policy == "aggressive"){ 1192292SN/A commitPolicy = Aggressive; 1202292SN/A 1218346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 1222292SN/A } else if (policy == "roundrobin"){ 1232292SN/A commitPolicy = RoundRobin; 1242292SN/A 1252292SN/A //Set-Up Priority List 1266221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1272292SN/A priority_list.push_back(tid); 1282292SN/A } 1292292SN/A 1308346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 1312292SN/A } else if (policy == "oldestready"){ 1322292SN/A commitPolicy = OldestReady; 1332292SN/A 1344329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1352292SN/A } else { 1362292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1372292SN/A "RoundRobin,OldestReady}"); 1382292SN/A } 1392292SN/A 1406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1416221Snate@binkert.org commitStatus[tid] = Idle; 1426221Snate@binkert.org changedROBNumEntries[tid] = false; 1436221Snate@binkert.org checkEmptyROB[tid] = false; 1446221Snate@binkert.org trapInFlight[tid] = false; 1456221Snate@binkert.org committedStores[tid] = false; 1466221Snate@binkert.org trapSquash[tid] = false; 1476221Snate@binkert.org tcSquash[tid] = false; 1487720Sgblack@eecs.umich.edu pc[tid].set(0); 1497855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = 0; 1502292SN/A } 1513640Sktlim@umich.edu#if FULL_SYSTEM 1523640Sktlim@umich.edu interrupt = NoFault; 1533640Sktlim@umich.edu#endif 1542292SN/A} 1552292SN/A 1562292SN/Atemplate <class Impl> 1572292SN/Astd::string 1582292SN/ADefaultCommit<Impl>::name() const 1592292SN/A{ 1602292SN/A return cpu->name() + ".commit"; 1612292SN/A} 1622292SN/A 1632292SN/Atemplate <class Impl> 1642292SN/Avoid 1652292SN/ADefaultCommit<Impl>::regStats() 1662132SN/A{ 1672301SN/A using namespace Stats; 1681062SN/A commitCommittedInsts 1691062SN/A .name(name() + ".commitCommittedInsts") 1701062SN/A .desc("The number of committed instructions") 1711062SN/A .prereq(commitCommittedInsts); 1721062SN/A commitSquashedInsts 1731062SN/A .name(name() + ".commitSquashedInsts") 1741062SN/A .desc("The number of squashed insts skipped by commit") 1751062SN/A .prereq(commitSquashedInsts); 1761062SN/A commitSquashEvents 1771062SN/A .name(name() + ".commitSquashEvents") 1781062SN/A .desc("The number of times commit is told to squash") 1791062SN/A .prereq(commitSquashEvents); 1801062SN/A commitNonSpecStalls 1811062SN/A .name(name() + ".commitNonSpecStalls") 1821062SN/A .desc("The number of times commit has been forced to stall to " 1831062SN/A "communicate backwards") 1841062SN/A .prereq(commitNonSpecStalls); 1851062SN/A branchMispredicts 1861062SN/A .name(name() + ".branchMispredicts") 1871062SN/A .desc("The number of times a branch was mispredicted") 1881062SN/A .prereq(branchMispredicts); 1892292SN/A numCommittedDist 1901062SN/A .init(0,commitWidth,1) 1918240Snate@binkert.org .name(name() + ".committed_per_cycle") 1921062SN/A .desc("Number of insts commited each cycle") 1931062SN/A .flags(Stats::pdf) 1941062SN/A ; 1952301SN/A 1962316SN/A statComInst 1976221Snate@binkert.org .init(cpu->numThreads) 1988240Snate@binkert.org .name(name() + ".count") 1992301SN/A .desc("Number of instructions committed") 2002301SN/A .flags(total) 2012301SN/A ; 2022301SN/A 2032316SN/A statComSwp 2046221Snate@binkert.org .init(cpu->numThreads) 2058240Snate@binkert.org .name(name() + ".swp_count") 2062301SN/A .desc("Number of s/w prefetches committed") 2072301SN/A .flags(total) 2082301SN/A ; 2092301SN/A 2102316SN/A statComRefs 2116221Snate@binkert.org .init(cpu->numThreads) 2128240Snate@binkert.org .name(name() + ".refs") 2132301SN/A .desc("Number of memory references committed") 2142301SN/A .flags(total) 2152301SN/A ; 2162301SN/A 2172316SN/A statComLoads 2186221Snate@binkert.org .init(cpu->numThreads) 2198240Snate@binkert.org .name(name() + ".loads") 2202301SN/A .desc("Number of loads committed") 2212301SN/A .flags(total) 2222301SN/A ; 2232301SN/A 2242316SN/A statComMembars 2256221Snate@binkert.org .init(cpu->numThreads) 2268240Snate@binkert.org .name(name() + ".membars") 2272301SN/A .desc("Number of memory barriers committed") 2282301SN/A .flags(total) 2292301SN/A ; 2302301SN/A 2312316SN/A statComBranches 2326221Snate@binkert.org .init(cpu->numThreads) 2338240Snate@binkert.org .name(name() + ".branches") 2342301SN/A .desc("Number of branches committed") 2352301SN/A .flags(total) 2362301SN/A ; 2372301SN/A 2387897Shestness@cs.utexas.edu statComFloating 2397897Shestness@cs.utexas.edu .init(cpu->numThreads) 2408240Snate@binkert.org .name(name() + ".fp_insts") 2417897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2427897Shestness@cs.utexas.edu .flags(total) 2437897Shestness@cs.utexas.edu ; 2447897Shestness@cs.utexas.edu 2457897Shestness@cs.utexas.edu statComInteger 2467897Shestness@cs.utexas.edu .init(cpu->numThreads) 2478240Snate@binkert.org .name(name()+".int_insts") 2487897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2497897Shestness@cs.utexas.edu .flags(total) 2507897Shestness@cs.utexas.edu ; 2517897Shestness@cs.utexas.edu 2527897Shestness@cs.utexas.edu statComFunctionCalls 2537897Shestness@cs.utexas.edu .init(cpu->numThreads) 2548240Snate@binkert.org .name(name()+".function_calls") 2557897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2567897Shestness@cs.utexas.edu .flags(total) 2577897Shestness@cs.utexas.edu ; 2587897Shestness@cs.utexas.edu 2592316SN/A commitEligible 2606221Snate@binkert.org .init(cpu->numThreads) 2618240Snate@binkert.org .name(name() + ".bw_limited") 2622301SN/A .desc("number of insts not committed due to BW limits") 2632301SN/A .flags(total) 2642301SN/A ; 2652301SN/A 2662316SN/A commitEligibleSamples 2678240Snate@binkert.org .name(name() + ".bw_lim_events") 2682301SN/A .desc("number cycles where commit BW limit reached") 2692301SN/A ; 2701062SN/A} 2711062SN/A 2721062SN/Atemplate <class Impl> 2731062SN/Avoid 2742980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2752292SN/A{ 2762292SN/A thread = threads; 2772292SN/A} 2782292SN/A 2792292SN/Atemplate <class Impl> 2802292SN/Avoid 2812292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2821060SN/A{ 2831060SN/A timeBuffer = tb_ptr; 2841060SN/A 2851060SN/A // Setup wire to send information back to IEW. 2861060SN/A toIEW = timeBuffer->getWire(0); 2871060SN/A 2881060SN/A // Setup wire to read data from IEW (for the ROB). 2891060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2901060SN/A} 2911060SN/A 2921061SN/Atemplate <class Impl> 2931060SN/Avoid 2942292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2952292SN/A{ 2962292SN/A fetchQueue = fq_ptr; 2972292SN/A 2982292SN/A // Setup wire to get instructions from rename (for the ROB). 2992292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 3002292SN/A} 3012292SN/A 3022292SN/Atemplate <class Impl> 3032292SN/Avoid 3042292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3051060SN/A{ 3061060SN/A renameQueue = rq_ptr; 3071060SN/A 3081060SN/A // Setup wire to get instructions from rename (for the ROB). 3091060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3101060SN/A} 3111060SN/A 3121061SN/Atemplate <class Impl> 3131060SN/Avoid 3142292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3151060SN/A{ 3161060SN/A iewQueue = iq_ptr; 3171060SN/A 3181060SN/A // Setup wire to get instructions from IEW. 3191060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3201060SN/A} 3211060SN/A 3221061SN/Atemplate <class Impl> 3231060SN/Avoid 3242292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3252292SN/A{ 3262292SN/A iewStage = iew_stage; 3272292SN/A} 3282292SN/A 3292292SN/Atemplate<class Impl> 3302292SN/Avoid 3316221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3322292SN/A{ 3332292SN/A activeThreads = at_ptr; 3342292SN/A} 3352292SN/A 3362292SN/Atemplate <class Impl> 3372292SN/Avoid 3382292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3392292SN/A{ 3406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3416221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3422292SN/A} 3432292SN/A 3442292SN/Atemplate <class Impl> 3452292SN/Avoid 3462292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3471060SN/A{ 3481060SN/A rob = rob_ptr; 3491060SN/A} 3501060SN/A 3511061SN/Atemplate <class Impl> 3521060SN/Avoid 3532292SN/ADefaultCommit<Impl>::initStage() 3541060SN/A{ 3552292SN/A rob->setActiveThreads(activeThreads); 3562292SN/A rob->resetEntries(); 3571060SN/A 3582292SN/A // Broadcast the number of free entries. 3596221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3606221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3616221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3626221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3631060SN/A } 3641060SN/A 3654329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3664329Sktlim@umich.edu // start of the simulation, so it starts as active. 3674329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3684329Sktlim@umich.edu 3692292SN/A cpu->activityThisCycle(); 3705100Ssaidi@eecs.umich.edu trapLatency = cpu->ticks(trapLatency); 3711060SN/A} 3721060SN/A 3731061SN/Atemplate <class Impl> 3742863Sktlim@umich.edubool 3752843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3761060SN/A{ 3772843Sktlim@umich.edu drainPending = true; 3782863Sktlim@umich.edu 3792863Sktlim@umich.edu return false; 3802316SN/A} 3812316SN/A 3822316SN/Atemplate <class Impl> 3832316SN/Avoid 3842843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3852316SN/A{ 3862316SN/A switchedOut = true; 3872843Sktlim@umich.edu drainPending = false; 3882307SN/A rob->switchOut(); 3892307SN/A} 3902307SN/A 3912307SN/Atemplate <class Impl> 3922307SN/Avoid 3932843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3942843Sktlim@umich.edu{ 3952864Sktlim@umich.edu drainPending = false; 3962843Sktlim@umich.edu} 3972843Sktlim@umich.edu 3982843Sktlim@umich.edutemplate <class Impl> 3992843Sktlim@umich.eduvoid 4002307SN/ADefaultCommit<Impl>::takeOverFrom() 4012307SN/A{ 4022316SN/A switchedOut = false; 4032307SN/A _status = Active; 4042307SN/A _nextStatus = Inactive; 4056221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4066221Snate@binkert.org commitStatus[tid] = Idle; 4076221Snate@binkert.org changedROBNumEntries[tid] = false; 4086221Snate@binkert.org trapSquash[tid] = false; 4096221Snate@binkert.org tcSquash[tid] = false; 4102307SN/A } 4112307SN/A squashCounter = 0; 4122307SN/A rob->takeOverFrom(); 4132307SN/A} 4142307SN/A 4152307SN/Atemplate <class Impl> 4162307SN/Avoid 4172292SN/ADefaultCommit<Impl>::updateStatus() 4182132SN/A{ 4192316SN/A // reset ROB changed variable 4206221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4216221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4223867Sbinkertn@umich.edu 4233867Sbinkertn@umich.edu while (threads != end) { 4246221Snate@binkert.org ThreadID tid = *threads++; 4253867Sbinkertn@umich.edu 4262316SN/A changedROBNumEntries[tid] = false; 4272316SN/A 4282316SN/A // Also check if any of the threads has a trap pending 4292316SN/A if (commitStatus[tid] == TrapPending || 4302316SN/A commitStatus[tid] == FetchTrapPending) { 4312316SN/A _nextStatus = Active; 4322316SN/A } 4332292SN/A } 4342292SN/A 4352292SN/A if (_nextStatus == Inactive && _status == Active) { 4362292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4372733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4382292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4392292SN/A DPRINTF(Activity, "Activating stage.\n"); 4402733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4412292SN/A } 4422292SN/A 4432292SN/A _status = _nextStatus; 4442292SN/A} 4452292SN/A 4462292SN/Atemplate <class Impl> 4472292SN/Avoid 4482292SN/ADefaultCommit<Impl>::setNextStatus() 4492292SN/A{ 4502292SN/A int squashes = 0; 4512292SN/A 4526221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4536221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4542292SN/A 4553867Sbinkertn@umich.edu while (threads != end) { 4566221Snate@binkert.org ThreadID tid = *threads++; 4572292SN/A 4582292SN/A if (commitStatus[tid] == ROBSquashing) { 4592292SN/A squashes++; 4602292SN/A } 4612292SN/A } 4622292SN/A 4632702Sktlim@umich.edu squashCounter = squashes; 4642292SN/A 4652292SN/A // If commit is currently squashing, then it will have activity for the 4662292SN/A // next cycle. Set its next status as active. 4672292SN/A if (squashCounter) { 4682292SN/A _nextStatus = Active; 4692292SN/A } 4702292SN/A} 4712292SN/A 4722292SN/Atemplate <class Impl> 4732292SN/Abool 4742292SN/ADefaultCommit<Impl>::changedROBEntries() 4752292SN/A{ 4766221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4776221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4782292SN/A 4793867Sbinkertn@umich.edu while (threads != end) { 4806221Snate@binkert.org ThreadID tid = *threads++; 4812292SN/A 4822292SN/A if (changedROBNumEntries[tid]) { 4832292SN/A return true; 4842292SN/A } 4852292SN/A } 4862292SN/A 4872292SN/A return false; 4882292SN/A} 4892292SN/A 4902292SN/Atemplate <class Impl> 4916221Snate@binkert.orgsize_t 4926221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 4932292SN/A{ 4942292SN/A return rob->numFreeEntries(tid); 4952292SN/A} 4962292SN/A 4972292SN/Atemplate <class Impl> 4982292SN/Avoid 4996221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 5002292SN/A{ 5012292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5022292SN/A 5032292SN/A TrapEvent *trap = new TrapEvent(this, tid); 5042292SN/A 5057823Ssteve.reinhardt@amd.com cpu->schedule(trap, curTick() + trapLatency); 5064035Sktlim@umich.edu trapInFlight[tid] = true; 5078518Sgeoffrey.blake@arm.com thread[tid]->trapPending = true; 5082292SN/A} 5092292SN/A 5102292SN/Atemplate <class Impl> 5112292SN/Avoid 5126221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5132292SN/A{ 5144035Sktlim@umich.edu assert(!trapInFlight[tid]); 5152680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5162292SN/A 5172680Sktlim@umich.edu tcSquash[tid] = true; 5182292SN/A} 5192292SN/A 5202292SN/Atemplate <class Impl> 5212292SN/Avoid 5226221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5232292SN/A{ 5242292SN/A // If we want to include the squashing instruction in the squash, 5252292SN/A // then use one older sequence number. 5262292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5272292SN/A // all instructions of this thread. 5282292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5297855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5302292SN/A 5312292SN/A // All younger instructions will be squashed. Set the sequence 5322292SN/A // number as the youngest instruction in the ROB (0 in this case. 5332292SN/A // Hopefully nothing breaks.) 5347855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5352292SN/A 5362292SN/A rob->squash(squashed_inst, tid); 5372292SN/A changedROBNumEntries[tid] = true; 5382292SN/A 5392292SN/A // Send back the sequence number of the squashed instruction. 5402292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5412292SN/A 5422292SN/A // Send back the squash signal to tell stages that they should 5432292SN/A // squash. 5442292SN/A toIEW->commitInfo[tid].squash = true; 5452292SN/A 5462292SN/A // Send back the rob squashing signal so other stages know that 5472292SN/A // the ROB is in the process of squashing. 5482292SN/A toIEW->commitInfo[tid].robSquashing = true; 5492292SN/A 5507851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 5518137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 5522292SN/A 5537720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5542316SN/A} 5552292SN/A 5562316SN/Atemplate <class Impl> 5572316SN/Avoid 5586221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5592316SN/A{ 5602316SN/A squashAll(tid); 5612316SN/A 5627720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5632316SN/A 5642316SN/A thread[tid]->trapPending = false; 5652316SN/A thread[tid]->inSyscall = false; 5664035Sktlim@umich.edu trapInFlight[tid] = false; 5672316SN/A 5682316SN/A trapSquash[tid] = false; 5692316SN/A 5702316SN/A commitStatus[tid] = ROBSquashing; 5712316SN/A cpu->activityThisCycle(); 5722316SN/A} 5732316SN/A 5742316SN/Atemplate <class Impl> 5752316SN/Avoid 5766221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 5772316SN/A{ 5782316SN/A squashAll(tid); 5792292SN/A 5807720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 5812292SN/A 5822292SN/A thread[tid]->inSyscall = false; 5832292SN/A assert(!thread[tid]->trapPending); 5842316SN/A 5852292SN/A commitStatus[tid] = ROBSquashing; 5862292SN/A cpu->activityThisCycle(); 5872292SN/A 5882680Sktlim@umich.edu tcSquash[tid] = false; 5892292SN/A} 5902292SN/A 5912292SN/Atemplate <class Impl> 5922292SN/Avoid 5938137SAli.Saidi@ARM.comDefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst, 5948137SAli.Saidi@ARM.com uint64_t squash_after_seq_num) 5957784SAli.Saidi@ARM.com{ 5967784SAli.Saidi@ARM.com youngestSeqNum[tid] = squash_after_seq_num; 5977784SAli.Saidi@ARM.com 5987784SAli.Saidi@ARM.com rob->squash(squash_after_seq_num, tid); 5997784SAli.Saidi@ARM.com changedROBNumEntries[tid] = true; 6007784SAli.Saidi@ARM.com 6017784SAli.Saidi@ARM.com // Send back the sequence number of the squashed instruction. 6027784SAli.Saidi@ARM.com toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 6037784SAli.Saidi@ARM.com 6048137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = head_inst; 6057784SAli.Saidi@ARM.com // Send back the squash signal to tell stages that they should squash. 6067784SAli.Saidi@ARM.com toIEW->commitInfo[tid].squash = true; 6077784SAli.Saidi@ARM.com 6087784SAli.Saidi@ARM.com // Send back the rob squashing signal so other stages know that 6097784SAli.Saidi@ARM.com // the ROB is in the process of squashing. 6107784SAli.Saidi@ARM.com toIEW->commitInfo[tid].robSquashing = true; 6117784SAli.Saidi@ARM.com 6128137SAli.Saidi@ARM.com toIEW->commitInfo[tid].mispredictInst = NULL; 6137784SAli.Saidi@ARM.com 6147784SAli.Saidi@ARM.com toIEW->commitInfo[tid].pc = pc[tid]; 6157784SAli.Saidi@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6167784SAli.Saidi@ARM.com tid, squash_after_seq_num); 6177784SAli.Saidi@ARM.com commitStatus[tid] = ROBSquashing; 6187784SAli.Saidi@ARM.com} 6197784SAli.Saidi@ARM.com 6207784SAli.Saidi@ARM.comtemplate <class Impl> 6217784SAli.Saidi@ARM.comvoid 6222292SN/ADefaultCommit<Impl>::tick() 6232292SN/A{ 6242292SN/A wroteToTimeBuffer = false; 6252292SN/A _nextStatus = Inactive; 6262292SN/A 6272843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 6282843Sktlim@umich.edu cpu->signalDrained(); 6292843Sktlim@umich.edu drainPending = false; 6302316SN/A return; 6312316SN/A } 6322316SN/A 6333867Sbinkertn@umich.edu if (activeThreads->empty()) 6342875Sksewell@umich.edu return; 6352875Sksewell@umich.edu 6366221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6376221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6382292SN/A 6392316SN/A // Check if any of the threads are done squashing. Change the 6402316SN/A // status if they are done. 6413867Sbinkertn@umich.edu while (threads != end) { 6426221Snate@binkert.org ThreadID tid = *threads++; 6432292SN/A 6444035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6454035Sktlim@umich.edu // this cycle. 6464035Sktlim@umich.edu committedStores[tid] = false; 6474035Sktlim@umich.edu 6482292SN/A if (commitStatus[tid] == ROBSquashing) { 6492292SN/A 6502292SN/A if (rob->isDoneSquashing(tid)) { 6512292SN/A commitStatus[tid] = Running; 6522292SN/A } else { 6532292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6542877Sksewell@umich.edu " insts this cycle.\n", tid); 6552702Sktlim@umich.edu rob->doSquash(tid); 6562702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6572702Sktlim@umich.edu wroteToTimeBuffer = true; 6582292SN/A } 6592292SN/A } 6602292SN/A } 6612292SN/A 6622292SN/A commit(); 6632292SN/A 6642292SN/A markCompletedInsts(); 6652292SN/A 6663867Sbinkertn@umich.edu threads = activeThreads->begin(); 6672292SN/A 6683867Sbinkertn@umich.edu while (threads != end) { 6696221Snate@binkert.org ThreadID tid = *threads++; 6702292SN/A 6712292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6722292SN/A // The ROB has more instructions it can commit. Its next status 6732292SN/A // will be active. 6742292SN/A _nextStatus = Active; 6752292SN/A 6762292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6772292SN/A 6787720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 6792292SN/A " ROB and ready to commit\n", 6807720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6812292SN/A 6822292SN/A } else if (!rob->isEmpty(tid)) { 6832292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6842292SN/A 6852292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6867720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 6877720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6882292SN/A } 6892292SN/A 6902292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6912292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6922292SN/A } 6932292SN/A 6942292SN/A 6952292SN/A if (wroteToTimeBuffer) { 6962316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6972292SN/A cpu->activityThisCycle(); 6982292SN/A } 6992292SN/A 7002292SN/A updateStatus(); 7012292SN/A} 7022292SN/A 7034035Sktlim@umich.edu#if FULL_SYSTEM 7042292SN/Atemplate <class Impl> 7052292SN/Avoid 7064035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 7072292SN/A{ 7087847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7097847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7107847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7117847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7127847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7137847Sminkyu.jeong@arm.com interrupt = NoFault; 7147847Sminkyu.jeong@arm.com return; 7157847Sminkyu.jeong@arm.com } 7163633Sktlim@umich.edu 7178493Sgblack@eecs.umich.edu // Wait until all in flight instructions are finished before enterring 7188493Sgblack@eecs.umich.edu // the interrupt. 7198493Sgblack@eecs.umich.edu if (cpu->instList.empty()) { 7207847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7217847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7227847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7234035Sktlim@umich.edu 7247847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7257847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7262292SN/A 7277847Sminkyu.jeong@arm.com assert(!thread[0]->inSyscall); 7287847Sminkyu.jeong@arm.com thread[0]->inSyscall = true; 7292292SN/A 7307847Sminkyu.jeong@arm.com // CPU will handle interrupt. 7317847Sminkyu.jeong@arm.com cpu->processInterrupts(interrupt); 7323633Sktlim@umich.edu 7337847Sminkyu.jeong@arm.com thread[0]->inSyscall = false; 7342292SN/A 7357847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7362292SN/A 7377847Sminkyu.jeong@arm.com // Generate trap squash event. 7387847Sminkyu.jeong@arm.com generateTrapEvent(0); 7393640Sktlim@umich.edu 7407847Sminkyu.jeong@arm.com interrupt = NoFault; 7417847Sminkyu.jeong@arm.com } else { 7427847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 7431060SN/A } 7444035Sktlim@umich.edu} 7457847Sminkyu.jeong@arm.com 7467847Sminkyu.jeong@arm.comtemplate <class Impl> 7477847Sminkyu.jeong@arm.comvoid 7487847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 7497847Sminkyu.jeong@arm.com{ 7507847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 7517847Sminkyu.jeong@arm.com tcSquash[0]) 7527847Sminkyu.jeong@arm.com return; 7537847Sminkyu.jeong@arm.com 7547847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 7557847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 7567847Sminkyu.jeong@arm.com // pending. 7577847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 7587847Sminkyu.jeong@arm.com 7597847Sminkyu.jeong@arm.com // Get any interrupt that happened 7607847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 7617847Sminkyu.jeong@arm.com 7627847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 7637847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 7647847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 7657847Sminkyu.jeong@arm.com if (interrupt != NoFault) 7667847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 7677847Sminkyu.jeong@arm.com} 7687847Sminkyu.jeong@arm.com 7694035Sktlim@umich.edu#endif // FULL_SYSTEM 7703634Sktlim@umich.edu 7714035Sktlim@umich.edutemplate <class Impl> 7724035Sktlim@umich.eduvoid 7734035Sktlim@umich.eduDefaultCommit<Impl>::commit() 7744035Sktlim@umich.edu{ 7754035Sktlim@umich.edu 7764035Sktlim@umich.edu#if FULL_SYSTEM 7777847Sminkyu.jeong@arm.com // Check for any interrupt that we've already squashed for and start processing it. 7787847Sminkyu.jeong@arm.com if (interrupt != NoFault) 7794035Sktlim@umich.edu handleInterrupt(); 7807847Sminkyu.jeong@arm.com 7817847Sminkyu.jeong@arm.com // Check if we have a interrupt and get read to handle it 7827847Sminkyu.jeong@arm.com if (cpu->checkInterrupts(cpu->tcBase(0))) 7837847Sminkyu.jeong@arm.com propagateInterrupt(); 7841060SN/A#endif // FULL_SYSTEM 7851060SN/A 7861060SN/A //////////////////////////////////// 7872316SN/A // Check for any possible squashes, handle them first 7881060SN/A //////////////////////////////////// 7896221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7906221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7911060SN/A 7923867Sbinkertn@umich.edu while (threads != end) { 7936221Snate@binkert.org ThreadID tid = *threads++; 7941060SN/A 7952292SN/A // Not sure which one takes priority. I think if we have 7962292SN/A // both, that's a bad sign. 7972292SN/A if (trapSquash[tid] == true) { 7982680Sktlim@umich.edu assert(!tcSquash[tid]); 7992292SN/A squashFromTrap(tid); 8002680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 8014035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 8022680Sktlim@umich.edu squashFromTC(tid); 8032292SN/A } 8041061SN/A 8052292SN/A // Squashed sequence number must be older than youngest valid 8062292SN/A // instruction in the ROB. This prevents squashes from younger 8072292SN/A // instructions overriding squashes from older instructions. 8082292SN/A if (fromIEW->squash[tid] && 8092292SN/A commitStatus[tid] != TrapPending && 8102292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8111061SN/A 8128137SAli.Saidi@ARM.com if (fromIEW->mispredictInst[tid]) { 8138137SAli.Saidi@ARM.com DPRINTF(Commit, 8148137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 8152292SN/A tid, 8168137SAli.Saidi@ARM.com fromIEW->mispredictInst[tid]->instAddr(), 8172292SN/A fromIEW->squashedSeqNum[tid]); 8188137SAli.Saidi@ARM.com } else { 8198137SAli.Saidi@ARM.com DPRINTF(Commit, 8208137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to order violation [sn:%i]\n", 8218137SAli.Saidi@ARM.com tid, fromIEW->squashedSeqNum[tid]); 8228137SAli.Saidi@ARM.com } 8231061SN/A 8242292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8252292SN/A tid, 8267720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8271061SN/A 8282292SN/A commitStatus[tid] = ROBSquashing; 8291061SN/A 8302292SN/A // If we want to include the squashing instruction in the squash, 8312292SN/A // then use one older sequence number. 8322292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8331062SN/A 8342935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 8352292SN/A squashed_inst--; 8362935Sksewell@umich.edu } 8374035Sktlim@umich.edu 8382292SN/A // All younger instructions will be squashed. Set the sequence 8392292SN/A // number as the youngest instruction in the ROB. 8402292SN/A youngestSeqNum[tid] = squashed_inst; 8412292SN/A 8423093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8432292SN/A changedROBNumEntries[tid] = true; 8442292SN/A 8452292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8462292SN/A 8472292SN/A toIEW->commitInfo[tid].squash = true; 8482292SN/A 8492292SN/A // Send back the rob squashing signal so other stages know that 8502292SN/A // the ROB is in the process of squashing. 8512292SN/A toIEW->commitInfo[tid].robSquashing = true; 8522292SN/A 8537851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 8547851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 8552292SN/A toIEW->commitInfo[tid].branchTaken = 8562292SN/A fromIEW->branchTaken[tid]; 8578137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 8582292SN/A 8597720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 8602292SN/A 8618137SAli.Saidi@ARM.com if (toIEW->commitInfo[tid].mispredictInst) { 8622292SN/A ++branchMispredicts; 8632292SN/A } 8641062SN/A } 8652292SN/A 8661060SN/A } 8671060SN/A 8682292SN/A setNextStatus(); 8692292SN/A 8702292SN/A if (squashCounter != numThreads) { 8711061SN/A // If we're not currently squashing, then get instructions. 8721060SN/A getInsts(); 8731060SN/A 8741061SN/A // Try to commit any instructions. 8751060SN/A commitInsts(); 8761060SN/A } 8771060SN/A 8782292SN/A //Check for any activity 8793867Sbinkertn@umich.edu threads = activeThreads->begin(); 8802292SN/A 8813867Sbinkertn@umich.edu while (threads != end) { 8826221Snate@binkert.org ThreadID tid = *threads++; 8832292SN/A 8842292SN/A if (changedROBNumEntries[tid]) { 8852292SN/A toIEW->commitInfo[tid].usedROB = true; 8862292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8872292SN/A 8882292SN/A wroteToTimeBuffer = true; 8892292SN/A changedROBNumEntries[tid] = false; 8904035Sktlim@umich.edu if (rob->isEmpty(tid)) 8914035Sktlim@umich.edu checkEmptyROB[tid] = true; 8922292SN/A } 8934035Sktlim@umich.edu 8944035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8954035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 8964035Sktlim@umich.edu // stage has received any information regarding stores that 8974035Sktlim@umich.edu // committed. 8984035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 8994035Sktlim@umich.edu // on the same cycle as when stores have been committed. 9004035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 9014035Sktlim@umich.edu // commit and IEW. 9024035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9035557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9044035Sktlim@umich.edu checkEmptyROB[tid] = false; 9054035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 9064035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 9074035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9084035Sktlim@umich.edu wroteToTimeBuffer = true; 9094035Sktlim@umich.edu } 9104035Sktlim@umich.edu 9111060SN/A } 9121060SN/A} 9131060SN/A 9141061SN/Atemplate <class Impl> 9151060SN/Avoid 9162292SN/ADefaultCommit<Impl>::commitInsts() 9171060SN/A{ 9181060SN/A //////////////////////////////////// 9191060SN/A // Handle commit 9202316SN/A // Note that commit will be handled prior to putting new 9212316SN/A // instructions in the ROB so that the ROB only tries to commit 9222316SN/A // instructions it has in this current cycle, and not instructions 9232316SN/A // it is writing in during this cycle. Can't commit and squash 9242316SN/A // things at the same time... 9251060SN/A //////////////////////////////////// 9261060SN/A 9272292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9281060SN/A 9291060SN/A unsigned num_committed = 0; 9301060SN/A 9312292SN/A DynInstPtr head_inst; 9322316SN/A 9331060SN/A // Commit as many instructions as possible until the commit bandwidth 9341060SN/A // limit is reached, or it becomes impossible to commit any more. 9352292SN/A while (num_committed < commitWidth) { 9362292SN/A int commit_thread = getCommittingThread(); 9371060SN/A 9382292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9392292SN/A break; 9402292SN/A 9412292SN/A head_inst = rob->readHeadInst(commit_thread); 9422292SN/A 9436221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 9442292SN/A 9452292SN/A assert(tid == commit_thread); 9462292SN/A 9472292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 9482292SN/A head_inst->seqNum, tid); 9492132SN/A 9502316SN/A // If the head instruction is squashed, it is ready to retire 9512316SN/A // (be removed from the ROB) at any time. 9521060SN/A if (head_inst->isSquashed()) { 9531060SN/A 9542292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 9551060SN/A "ROB.\n"); 9561060SN/A 9572292SN/A rob->retireHead(commit_thread); 9581060SN/A 9591062SN/A ++commitSquashedInsts; 9601062SN/A 9612292SN/A // Record that the number of ROB entries has changed. 9622292SN/A changedROBNumEntries[tid] = true; 9631060SN/A } else { 9647720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 9652292SN/A 9661060SN/A // Increment the total number of non-speculative instructions 9671060SN/A // executed. 9681060SN/A // Hack for now: it really shouldn't happen until after the 9691061SN/A // commit is deemed to be successful, but this count is needed 9701061SN/A // for syscalls. 9712292SN/A thread[tid]->funcExeInst++; 9721060SN/A 9731060SN/A // Try to commit the head instruction. 9741060SN/A bool commit_success = commitHead(head_inst, num_committed); 9751060SN/A 9761062SN/A if (commit_success) { 9771060SN/A ++num_committed; 9781060SN/A 9792292SN/A changedROBNumEntries[tid] = true; 9802292SN/A 9812292SN/A // Set the doneSeqNum to the youngest committed instruction. 9822292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9831060SN/A 9841062SN/A ++commitCommittedInsts; 9851062SN/A 9862292SN/A // To match the old model, don't count nops and instruction 9872292SN/A // prefetches towards the total commit count. 9882292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9892292SN/A cpu->instDone(tid); 9901062SN/A } 9912292SN/A 9927783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 9937783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 9947783SGiacomo.Gabrielli@arm.com 9957720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 9962935Sksewell@umich.edu 9977855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 9987855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 9997855SAli.Saidi@ARM.com 10007784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 10017784SAli.Saidi@ARM.com // others squash everything and restart fetch 10027784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 10038137SAli.Saidi@ARM.com squashAfter(tid, head_inst, head_inst->seqNum); 10047784SAli.Saidi@ARM.com 10052292SN/A int count = 0; 10062292SN/A Addr oldpc; 10075108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 10085108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 10095108Sgblack@eecs.umich.edu assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 10102292SN/A do { 10117720Sgblack@eecs.umich.edu oldpc = pc[tid].instAddr(); 10125108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 10132292SN/A count++; 10147720Sgblack@eecs.umich.edu } while (oldpc != pc[tid].instAddr()); 10152292SN/A if (count > 1) { 10165108Sgblack@eecs.umich.edu DPRINTF(Commit, 10175108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 10182292SN/A break; 10192292SN/A } 10201060SN/A } else { 10217720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 10222292SN/A "[tid:%i] [sn:%i].\n", 10237720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 10241060SN/A break; 10251060SN/A } 10261060SN/A } 10271060SN/A } 10281062SN/A 10291063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 10302292SN/A numCommittedDist.sample(num_committed); 10312307SN/A 10322307SN/A if (num_committed == commitWidth) { 10332349SN/A commitEligibleSamples++; 10342307SN/A } 10351060SN/A} 10361060SN/A 10371061SN/Atemplate <class Impl> 10381060SN/Abool 10392292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 10401060SN/A{ 10411060SN/A assert(head_inst); 10421060SN/A 10436221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 10442292SN/A 10452316SN/A // If the instruction is not executed yet, then it will need extra 10462316SN/A // handling. Signal backwards that it should be executed. 10471061SN/A if (!head_inst->isExecuted()) { 10481061SN/A // Keep this number correct. We have not yet actually executed 10491061SN/A // and committed this instruction. 10502292SN/A thread[tid]->funcExeInst--; 10511062SN/A 10522292SN/A if (head_inst->isNonSpeculative() || 10532348SN/A head_inst->isStoreConditional() || 10542292SN/A head_inst->isMemBarrier() || 10552292SN/A head_inst->isWriteBarrier()) { 10562316SN/A 10572316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 10587720Sgblack@eecs.umich.edu "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 10597720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 10602316SN/A 10615557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 10622292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10632292SN/A return false; 10642292SN/A } 10652292SN/A 10662292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10671061SN/A 10681061SN/A // Change the instruction so it won't try to commit again until 10691061SN/A // it is executed. 10701061SN/A head_inst->clearCanCommit(); 10711061SN/A 10721062SN/A ++commitNonSpecStalls; 10731062SN/A 10741061SN/A return false; 10752292SN/A } else if (head_inst->isLoad()) { 10765557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 10774035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10784035Sktlim@umich.edu return false; 10794035Sktlim@umich.edu } 10804035Sktlim@umich.edu 10814035Sktlim@umich.edu assert(head_inst->uncacheable()); 10827720Sgblack@eecs.umich.edu DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 10837720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 10842292SN/A 10852292SN/A // Send back the non-speculative instruction's sequence 10862316SN/A // number. Tell the lsq to re-execute the load. 10872292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10882292SN/A toIEW->commitInfo[tid].uncached = true; 10892292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10902292SN/A 10912292SN/A head_inst->clearCanCommit(); 10922292SN/A 10932292SN/A return false; 10941061SN/A } else { 10952292SN/A panic("Trying to commit un-executed instruction " 10961061SN/A "of unknown type!\n"); 10971061SN/A } 10981060SN/A } 10991060SN/A 11002316SN/A if (head_inst->isThreadSync()) { 11012292SN/A // Not handled for now. 11022316SN/A panic("Thread sync instructions are not handled yet.\n"); 11032132SN/A } 11042132SN/A 11054035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 11064035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 11074035Sktlim@umich.edu 11082316SN/A // Stores mark themselves as completed. 11094035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 11102310SN/A head_inst->setCompleted(); 11112310SN/A } 11122310SN/A 11132733Sktlim@umich.edu#if USE_CHECKER 11142316SN/A // Use checker prior to updating anything due to traps or PC 11152316SN/A // based events. 11162316SN/A if (cpu->checker) { 11172732Sktlim@umich.edu cpu->checker->verify(head_inst); 11181060SN/A } 11192733Sktlim@umich.edu#endif 11201060SN/A 11212112SN/A if (inst_fault != NoFault) { 11227720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 11237720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11242292SN/A 11255557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 11262316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 11272316SN/A return false; 11282316SN/A } 11292310SN/A 11304035Sktlim@umich.edu head_inst->setCompleted(); 11314035Sktlim@umich.edu 11322733Sktlim@umich.edu#if USE_CHECKER 11332316SN/A if (cpu->checker && head_inst->isStore()) { 11342732Sktlim@umich.edu cpu->checker->verify(head_inst); 11352316SN/A } 11362733Sktlim@umich.edu#endif 11372292SN/A 11382316SN/A assert(!thread[tid]->inSyscall); 11392292SN/A 11402316SN/A // Mark that we're in state update mode so that the trap's 11412316SN/A // execution doesn't generate extra squashes. 11422316SN/A thread[tid]->inSyscall = true; 11432292SN/A 11442316SN/A // Execute the trap. Although it's slightly unrealistic in 11452316SN/A // terms of timing (as it doesn't wait for the full timing of 11462316SN/A // the trap event to complete before updating state), it's 11472316SN/A // needed to update the state as soon as possible. This 11482316SN/A // prevents external agents from changing any specific state 11492316SN/A // that the trap need. 11507684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 11512292SN/A 11522316SN/A // Exit state update mode to avoid accidental updating. 11532316SN/A thread[tid]->inSyscall = false; 11542292SN/A 11552316SN/A commitStatus[tid] = TrapPending; 11562292SN/A 11578067SAli.Saidi@ARM.com DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 11588067SAli.Saidi@ARM.com head_inst->seqNum); 11594035Sktlim@umich.edu if (head_inst->traceData) { 11606667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 11616667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 11626667Ssteve.reinhardt@amd.com head_inst->traceData->setCPSeq(thread[tid]->numInst); 11636667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 11646667Ssteve.reinhardt@amd.com } 11654288Sktlim@umich.edu delete head_inst->traceData; 11664035Sktlim@umich.edu head_inst->traceData = NULL; 11674035Sktlim@umich.edu } 11684035Sktlim@umich.edu 11692316SN/A // Generate trap squash event. 11702316SN/A generateTrapEvent(tid); 11712316SN/A return false; 11721060SN/A } 11731060SN/A 11742301SN/A updateComInstStats(head_inst); 11752132SN/A 11762362SN/A#if FULL_SYSTEM 11772362SN/A if (thread[tid]->profile) { 11787720Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 11793126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 11802362SN/A head_inst->staticInst); 11812362SN/A 11822362SN/A if (node) 11832362SN/A thread[tid]->profileNode = node; 11842362SN/A } 11855953Ssaidi@eecs.umich.edu if (CPA::available()) { 11865953Ssaidi@eecs.umich.edu if (head_inst->isControl()) { 11875953Ssaidi@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 11887720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 11895953Ssaidi@eecs.umich.edu } 11905953Ssaidi@eecs.umich.edu } 11912362SN/A#endif 11928516SMrinmoy.Ghosh@arm.com DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 11938516SMrinmoy.Ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 11942132SN/A if (head_inst->traceData) { 11952292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11962292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11974046Sbinkertn@umich.edu head_inst->traceData->dump(); 11984046Sbinkertn@umich.edu delete head_inst->traceData; 11992292SN/A head_inst->traceData = NULL; 12001060SN/A } 12011060SN/A 12022292SN/A // Update the commit rename map 12032292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 12043771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 12052292SN/A head_inst->renamedDestRegIdx(i)); 12061060SN/A } 12071062SN/A 12082292SN/A // Finally clear the head ROB entry. 12092292SN/A rob->retireHead(tid); 12101060SN/A 12118471SGiacomo.Gabrielli@arm.com#if TRACING_ON 12128471SGiacomo.Gabrielli@arm.com // Print info needed by the pipeline activity viewer. 12138471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", 12148471SGiacomo.Gabrielli@arm.com head_inst->fetchTick, 12158471SGiacomo.Gabrielli@arm.com head_inst->instAddr(), 12168471SGiacomo.Gabrielli@arm.com head_inst->microPC(), 12178471SGiacomo.Gabrielli@arm.com head_inst->seqNum, 12188471SGiacomo.Gabrielli@arm.com head_inst->staticInst->disassemble(head_inst->instAddr())); 12198471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick); 12208471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick); 12218471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick); 12228471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick); 12238471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick); 12248471SGiacomo.Gabrielli@arm.com DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick()); 12258471SGiacomo.Gabrielli@arm.com#endif 12268471SGiacomo.Gabrielli@arm.com 12274035Sktlim@umich.edu // If this was a store, record it for this cycle. 12284035Sktlim@umich.edu if (head_inst->isStore()) 12294035Sktlim@umich.edu committedStores[tid] = true; 12304035Sktlim@umich.edu 12311060SN/A // Return true to indicate that we have committed an instruction. 12321060SN/A return true; 12331060SN/A} 12341060SN/A 12351061SN/Atemplate <class Impl> 12361060SN/Avoid 12372292SN/ADefaultCommit<Impl>::getInsts() 12381060SN/A{ 12392935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 12402935Sksewell@umich.edu 12413093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 12423093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 12432965Sksewell@umich.edu 12442965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 12452965Sksewell@umich.edu DynInstPtr inst; 12462965Sksewell@umich.edu 12473093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 12486221Snate@binkert.org ThreadID tid = inst->threadNumber; 12492292SN/A 12502292SN/A if (!inst->isSquashed() && 12514035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 12524035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 12532292SN/A changedROBNumEntries[tid] = true; 12542292SN/A 12557720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 12567720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 12572292SN/A 12582292SN/A rob->insertInst(inst); 12592292SN/A 12602292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 12612292SN/A 12622292SN/A youngestSeqNum[tid] = inst->seqNum; 12631061SN/A } else { 12647720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 12651061SN/A "squashed, skipping.\n", 12667720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 12671061SN/A } 12681060SN/A } 12692965Sksewell@umich.edu} 12702965Sksewell@umich.edu 12712965Sksewell@umich.edutemplate <class Impl> 12722965Sksewell@umich.eduvoid 12732965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 12742965Sksewell@umich.edu{ 12752965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 12762965Sksewell@umich.edu "skidBuffer.\n"); 12772965Sksewell@umich.edu 12782965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 12792965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 12802965Sksewell@umich.edu 12812965Sksewell@umich.edu if (!inst->isSquashed()) { 12827720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 12837720Sgblack@eecs.umich.edu "skidBuffer.\n", inst->pcState(), inst->seqNum, 12843221Sktlim@umich.edu inst->threadNumber); 12852965Sksewell@umich.edu skidBuffer.push(inst); 12862965Sksewell@umich.edu } else { 12877720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 12882965Sksewell@umich.edu "squashed, skipping.\n", 12897720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->threadNumber); 12902965Sksewell@umich.edu } 12912965Sksewell@umich.edu } 12921060SN/A} 12931060SN/A 12941061SN/Atemplate <class Impl> 12951060SN/Avoid 12962292SN/ADefaultCommit<Impl>::markCompletedInsts() 12971060SN/A{ 12981060SN/A // Grab completed insts out of the IEW instruction queue, and mark 12991060SN/A // instructions completed within the ROB. 13001060SN/A for (int inst_num = 0; 13011681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 13021060SN/A ++inst_num) 13031060SN/A { 13042292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 13057720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 13062316SN/A "within ROB.\n", 13072292SN/A fromIEW->insts[inst_num]->threadNumber, 13087720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 13092292SN/A fromIEW->insts[inst_num]->seqNum); 13101060SN/A 13112292SN/A // Mark the instruction as ready to commit. 13122292SN/A fromIEW->insts[inst_num]->setCanCommit(); 13132292SN/A } 13141060SN/A } 13151060SN/A} 13161060SN/A 13171061SN/Atemplate <class Impl> 13182292SN/Abool 13192292SN/ADefaultCommit<Impl>::robDoneSquashing() 13201060SN/A{ 13216221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 13226221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 13232292SN/A 13243867Sbinkertn@umich.edu while (threads != end) { 13256221Snate@binkert.org ThreadID tid = *threads++; 13262292SN/A 13272292SN/A if (!rob->isDoneSquashing(tid)) 13282292SN/A return false; 13292292SN/A } 13302292SN/A 13312292SN/A return true; 13321060SN/A} 13332292SN/A 13342301SN/Atemplate <class Impl> 13352301SN/Avoid 13362301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 13372301SN/A{ 13386221Snate@binkert.org ThreadID tid = inst->threadNumber; 13392301SN/A 13402301SN/A // 13412301SN/A // Pick off the software prefetches 13422301SN/A // 13432301SN/A#ifdef TARGET_ALPHA 13442301SN/A if (inst->isDataPrefetch()) { 13456221Snate@binkert.org statComSwp[tid]++; 13462301SN/A } else { 13476221Snate@binkert.org statComInst[tid]++; 13482301SN/A } 13492301SN/A#else 13506221Snate@binkert.org statComInst[tid]++; 13512301SN/A#endif 13522301SN/A 13532301SN/A // 13542301SN/A // Control Instructions 13552301SN/A // 13562301SN/A if (inst->isControl()) 13576221Snate@binkert.org statComBranches[tid]++; 13582301SN/A 13592301SN/A // 13602301SN/A // Memory references 13612301SN/A // 13622301SN/A if (inst->isMemRef()) { 13636221Snate@binkert.org statComRefs[tid]++; 13642301SN/A 13652301SN/A if (inst->isLoad()) { 13666221Snate@binkert.org statComLoads[tid]++; 13672301SN/A } 13682301SN/A } 13692301SN/A 13702301SN/A if (inst->isMemBarrier()) { 13716221Snate@binkert.org statComMembars[tid]++; 13722301SN/A } 13737897Shestness@cs.utexas.edu 13747897Shestness@cs.utexas.edu // Integer Instruction 13757897Shestness@cs.utexas.edu if (inst->isInteger()) 13767897Shestness@cs.utexas.edu statComInteger[tid]++; 13777897Shestness@cs.utexas.edu 13787897Shestness@cs.utexas.edu // Floating Point Instruction 13797897Shestness@cs.utexas.edu if (inst->isFloating()) 13807897Shestness@cs.utexas.edu statComFloating[tid]++; 13817897Shestness@cs.utexas.edu 13827897Shestness@cs.utexas.edu // Function Calls 13837897Shestness@cs.utexas.edu if (inst->isCall()) 13847897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 13857897Shestness@cs.utexas.edu 13862301SN/A} 13872301SN/A 13882292SN/A//////////////////////////////////////// 13892292SN/A// // 13902316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 13912292SN/A// // 13922292SN/A//////////////////////////////////////// 13932292SN/Atemplate <class Impl> 13946221Snate@binkert.orgThreadID 13952292SN/ADefaultCommit<Impl>::getCommittingThread() 13962292SN/A{ 13972292SN/A if (numThreads > 1) { 13982292SN/A switch (commitPolicy) { 13992292SN/A 14002292SN/A case Aggressive: 14012292SN/A //If Policy is Aggressive, commit will call 14022292SN/A //this function multiple times per 14032292SN/A //cycle 14042292SN/A return oldestReady(); 14052292SN/A 14062292SN/A case RoundRobin: 14072292SN/A return roundRobin(); 14082292SN/A 14092292SN/A case OldestReady: 14102292SN/A return oldestReady(); 14112292SN/A 14122292SN/A default: 14136221Snate@binkert.org return InvalidThreadID; 14142292SN/A } 14152292SN/A } else { 14163867Sbinkertn@umich.edu assert(!activeThreads->empty()); 14176221Snate@binkert.org ThreadID tid = activeThreads->front(); 14182292SN/A 14192292SN/A if (commitStatus[tid] == Running || 14202292SN/A commitStatus[tid] == Idle || 14212292SN/A commitStatus[tid] == FetchTrapPending) { 14222292SN/A return tid; 14232292SN/A } else { 14246221Snate@binkert.org return InvalidThreadID; 14252292SN/A } 14262292SN/A } 14272292SN/A} 14282292SN/A 14292292SN/Atemplate<class Impl> 14306221Snate@binkert.orgThreadID 14312292SN/ADefaultCommit<Impl>::roundRobin() 14322292SN/A{ 14336221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14346221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14352292SN/A 14362292SN/A while (pri_iter != end) { 14376221Snate@binkert.org ThreadID tid = *pri_iter; 14382292SN/A 14392292SN/A if (commitStatus[tid] == Running || 14402831Sksewell@umich.edu commitStatus[tid] == Idle || 14412831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 14422292SN/A 14432292SN/A if (rob->isHeadReady(tid)) { 14442292SN/A priority_list.erase(pri_iter); 14452292SN/A priority_list.push_back(tid); 14462292SN/A 14472292SN/A return tid; 14482292SN/A } 14492292SN/A } 14502292SN/A 14512292SN/A pri_iter++; 14522292SN/A } 14532292SN/A 14546221Snate@binkert.org return InvalidThreadID; 14552292SN/A} 14562292SN/A 14572292SN/Atemplate<class Impl> 14586221Snate@binkert.orgThreadID 14592292SN/ADefaultCommit<Impl>::oldestReady() 14602292SN/A{ 14612292SN/A unsigned oldest = 0; 14622292SN/A bool first = true; 14632292SN/A 14646221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14656221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14662292SN/A 14673867Sbinkertn@umich.edu while (threads != end) { 14686221Snate@binkert.org ThreadID tid = *threads++; 14692292SN/A 14702292SN/A if (!rob->isEmpty(tid) && 14712292SN/A (commitStatus[tid] == Running || 14722292SN/A commitStatus[tid] == Idle || 14732292SN/A commitStatus[tid] == FetchTrapPending)) { 14742292SN/A 14752292SN/A if (rob->isHeadReady(tid)) { 14762292SN/A 14772292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 14782292SN/A 14792292SN/A if (first) { 14802292SN/A oldest = tid; 14812292SN/A first = false; 14822292SN/A } else if (head_inst->seqNum < oldest) { 14832292SN/A oldest = tid; 14842292SN/A } 14852292SN/A } 14862292SN/A } 14872292SN/A } 14882292SN/A 14892292SN/A if (!first) { 14902292SN/A return oldest; 14912292SN/A } else { 14926221Snate@binkert.org return InvalidThreadID; 14932292SN/A } 14942292SN/A} 1495