commit_impl.hh revision 8067
11689SN/A/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412965Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#include <algorithm> 452329SN/A#include <string> 462292SN/A 473577Sgblack@eecs.umich.edu#include "arch/utility.hh" 485953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 492292SN/A#include "base/loader/symtab.hh" 507813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 516221Snate@binkert.org#include "config/full_system.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 536221Snate@binkert.org#include "config/use_checker.hh" 542292SN/A#include "cpu/exetrace.hh" 551717SN/A#include "cpu/o3/commit.hh" 562292SN/A#include "cpu/o3/thread_state.hh" 576221Snate@binkert.org#include "params/DerivO3CPU.hh" 582292SN/A 592790Sktlim@umich.edu#if USE_CHECKER 602790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 612790Sktlim@umich.edu#endif 622790Sktlim@umich.edu 636221Snate@binkert.orgusing namespace std; 645529Snate@binkert.org 651061SN/Atemplate <class Impl> 662292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 676221Snate@binkert.org ThreadID _tid) 685606Snate@binkert.org : Event(CPU_Tick_Pri), commit(_commit), tid(_tid) 691060SN/A{ 705769Snate@binkert.org this->setFlags(AutoDelete); 711060SN/A} 721060SN/A 731061SN/Atemplate <class Impl> 741060SN/Avoid 752292SN/ADefaultCommit<Impl>::TrapEvent::process() 761062SN/A{ 772316SN/A // This will get reset by commit if it was switched out at the 782316SN/A // time of this event processing. 792292SN/A commit->trapSquash[tid] = true; 802292SN/A} 812292SN/A 822292SN/Atemplate <class Impl> 832292SN/Aconst char * 845336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 852292SN/A{ 864873Sstever@eecs.umich.edu return "Trap"; 872292SN/A} 882292SN/A 892292SN/Atemplate <class Impl> 905529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 914329Sktlim@umich.edu : cpu(_cpu), 924329Sktlim@umich.edu squashCounter(0), 932292SN/A iewToCommitDelay(params->iewToCommitDelay), 942292SN/A commitToIEWDelay(params->commitToIEWDelay), 952292SN/A renameToROBDelay(params->renameToROBDelay), 962292SN/A fetchToCommitDelay(params->commitToFetchDelay), 972292SN/A renameWidth(params->renameWidth), 982292SN/A commitWidth(params->commitWidth), 995529Snate@binkert.org numThreads(params->numThreads), 1002843Sktlim@umich.edu drainPending(false), 1012316SN/A switchedOut(false), 1022874Sktlim@umich.edu trapLatency(params->trapLatency) 1032292SN/A{ 1042292SN/A _status = Active; 1052292SN/A _nextStatus = Inactive; 1062980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1072292SN/A 1082292SN/A //Convert string to lowercase 1092292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1102292SN/A (int(*)(int)) tolower); 1112292SN/A 1122292SN/A //Assign commit policy 1132292SN/A if (policy == "aggressive"){ 1142292SN/A commitPolicy = Aggressive; 1152292SN/A 1164329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive."); 1172292SN/A } else if (policy == "roundrobin"){ 1182292SN/A commitPolicy = RoundRobin; 1192292SN/A 1202292SN/A //Set-Up Priority List 1216221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1222292SN/A priority_list.push_back(tid); 1232292SN/A } 1242292SN/A 1254329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 1262292SN/A } else if (policy == "oldestready"){ 1272292SN/A commitPolicy = OldestReady; 1282292SN/A 1294329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1302292SN/A } else { 1312292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1322292SN/A "RoundRobin,OldestReady}"); 1332292SN/A } 1342292SN/A 1356221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1366221Snate@binkert.org commitStatus[tid] = Idle; 1376221Snate@binkert.org changedROBNumEntries[tid] = false; 1386221Snate@binkert.org checkEmptyROB[tid] = false; 1396221Snate@binkert.org trapInFlight[tid] = false; 1406221Snate@binkert.org committedStores[tid] = false; 1416221Snate@binkert.org trapSquash[tid] = false; 1426221Snate@binkert.org tcSquash[tid] = false; 1437720Sgblack@eecs.umich.edu pc[tid].set(0); 1447855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = 0; 1452292SN/A } 1463640Sktlim@umich.edu#if FULL_SYSTEM 1473640Sktlim@umich.edu interrupt = NoFault; 1483640Sktlim@umich.edu#endif 1492292SN/A} 1502292SN/A 1512292SN/Atemplate <class Impl> 1522292SN/Astd::string 1532292SN/ADefaultCommit<Impl>::name() const 1542292SN/A{ 1552292SN/A return cpu->name() + ".commit"; 1562292SN/A} 1572292SN/A 1582292SN/Atemplate <class Impl> 1592292SN/Avoid 1602292SN/ADefaultCommit<Impl>::regStats() 1612132SN/A{ 1622301SN/A using namespace Stats; 1631062SN/A commitCommittedInsts 1641062SN/A .name(name() + ".commitCommittedInsts") 1651062SN/A .desc("The number of committed instructions") 1661062SN/A .prereq(commitCommittedInsts); 1671062SN/A commitSquashedInsts 1681062SN/A .name(name() + ".commitSquashedInsts") 1691062SN/A .desc("The number of squashed insts skipped by commit") 1701062SN/A .prereq(commitSquashedInsts); 1711062SN/A commitSquashEvents 1721062SN/A .name(name() + ".commitSquashEvents") 1731062SN/A .desc("The number of times commit is told to squash") 1741062SN/A .prereq(commitSquashEvents); 1751062SN/A commitNonSpecStalls 1761062SN/A .name(name() + ".commitNonSpecStalls") 1771062SN/A .desc("The number of times commit has been forced to stall to " 1781062SN/A "communicate backwards") 1791062SN/A .prereq(commitNonSpecStalls); 1801062SN/A branchMispredicts 1811062SN/A .name(name() + ".branchMispredicts") 1821062SN/A .desc("The number of times a branch was mispredicted") 1831062SN/A .prereq(branchMispredicts); 1842292SN/A numCommittedDist 1851062SN/A .init(0,commitWidth,1) 1861062SN/A .name(name() + ".COM:committed_per_cycle") 1871062SN/A .desc("Number of insts commited each cycle") 1881062SN/A .flags(Stats::pdf) 1891062SN/A ; 1902301SN/A 1912316SN/A statComInst 1926221Snate@binkert.org .init(cpu->numThreads) 1932301SN/A .name(name() + ".COM:count") 1942301SN/A .desc("Number of instructions committed") 1952301SN/A .flags(total) 1962301SN/A ; 1972301SN/A 1982316SN/A statComSwp 1996221Snate@binkert.org .init(cpu->numThreads) 2002301SN/A .name(name() + ".COM:swp_count") 2012301SN/A .desc("Number of s/w prefetches committed") 2022301SN/A .flags(total) 2032301SN/A ; 2042301SN/A 2052316SN/A statComRefs 2066221Snate@binkert.org .init(cpu->numThreads) 2072301SN/A .name(name() + ".COM:refs") 2082301SN/A .desc("Number of memory references committed") 2092301SN/A .flags(total) 2102301SN/A ; 2112301SN/A 2122316SN/A statComLoads 2136221Snate@binkert.org .init(cpu->numThreads) 2142301SN/A .name(name() + ".COM:loads") 2152301SN/A .desc("Number of loads committed") 2162301SN/A .flags(total) 2172301SN/A ; 2182301SN/A 2192316SN/A statComMembars 2206221Snate@binkert.org .init(cpu->numThreads) 2212301SN/A .name(name() + ".COM:membars") 2222301SN/A .desc("Number of memory barriers committed") 2232301SN/A .flags(total) 2242301SN/A ; 2252301SN/A 2262316SN/A statComBranches 2276221Snate@binkert.org .init(cpu->numThreads) 2282301SN/A .name(name() + ".COM:branches") 2292301SN/A .desc("Number of branches committed") 2302301SN/A .flags(total) 2312301SN/A ; 2322301SN/A 2337897Shestness@cs.utexas.edu statComFloating 2347897Shestness@cs.utexas.edu .init(cpu->numThreads) 2357897Shestness@cs.utexas.edu .name(name() + ".COM:fp_insts") 2367897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2377897Shestness@cs.utexas.edu .flags(total) 2387897Shestness@cs.utexas.edu ; 2397897Shestness@cs.utexas.edu 2407897Shestness@cs.utexas.edu statComInteger 2417897Shestness@cs.utexas.edu .init(cpu->numThreads) 2427897Shestness@cs.utexas.edu .name(name()+".COM:int_insts") 2437897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2447897Shestness@cs.utexas.edu .flags(total) 2457897Shestness@cs.utexas.edu ; 2467897Shestness@cs.utexas.edu 2477897Shestness@cs.utexas.edu statComFunctionCalls 2487897Shestness@cs.utexas.edu .init(cpu->numThreads) 2497897Shestness@cs.utexas.edu .name(name()+".COM:function_calls") 2507897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2517897Shestness@cs.utexas.edu .flags(total) 2527897Shestness@cs.utexas.edu ; 2537897Shestness@cs.utexas.edu 2542316SN/A commitEligible 2556221Snate@binkert.org .init(cpu->numThreads) 2562301SN/A .name(name() + ".COM:bw_limited") 2572301SN/A .desc("number of insts not committed due to BW limits") 2582301SN/A .flags(total) 2592301SN/A ; 2602301SN/A 2612316SN/A commitEligibleSamples 2622301SN/A .name(name() + ".COM:bw_lim_events") 2632301SN/A .desc("number cycles where commit BW limit reached") 2642301SN/A ; 2651062SN/A} 2661062SN/A 2671062SN/Atemplate <class Impl> 2681062SN/Avoid 2692980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2702292SN/A{ 2712292SN/A thread = threads; 2722292SN/A} 2732292SN/A 2742292SN/Atemplate <class Impl> 2752292SN/Avoid 2762292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2771060SN/A{ 2781060SN/A timeBuffer = tb_ptr; 2791060SN/A 2801060SN/A // Setup wire to send information back to IEW. 2811060SN/A toIEW = timeBuffer->getWire(0); 2821060SN/A 2831060SN/A // Setup wire to read data from IEW (for the ROB). 2841060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2851060SN/A} 2861060SN/A 2871061SN/Atemplate <class Impl> 2881060SN/Avoid 2892292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2902292SN/A{ 2912292SN/A fetchQueue = fq_ptr; 2922292SN/A 2932292SN/A // Setup wire to get instructions from rename (for the ROB). 2942292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2952292SN/A} 2962292SN/A 2972292SN/Atemplate <class Impl> 2982292SN/Avoid 2992292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3001060SN/A{ 3011060SN/A renameQueue = rq_ptr; 3021060SN/A 3031060SN/A // Setup wire to get instructions from rename (for the ROB). 3041060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3051060SN/A} 3061060SN/A 3071061SN/Atemplate <class Impl> 3081060SN/Avoid 3092292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3101060SN/A{ 3111060SN/A iewQueue = iq_ptr; 3121060SN/A 3131060SN/A // Setup wire to get instructions from IEW. 3141060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3151060SN/A} 3161060SN/A 3171061SN/Atemplate <class Impl> 3181060SN/Avoid 3192292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3202292SN/A{ 3212292SN/A iewStage = iew_stage; 3222292SN/A} 3232292SN/A 3242292SN/Atemplate<class Impl> 3252292SN/Avoid 3266221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3272292SN/A{ 3282292SN/A activeThreads = at_ptr; 3292292SN/A} 3302292SN/A 3312292SN/Atemplate <class Impl> 3322292SN/Avoid 3332292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3342292SN/A{ 3356221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3366221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3372292SN/A} 3382292SN/A 3392292SN/Atemplate <class Impl> 3402292SN/Avoid 3412292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3421060SN/A{ 3431060SN/A rob = rob_ptr; 3441060SN/A} 3451060SN/A 3461061SN/Atemplate <class Impl> 3471060SN/Avoid 3482292SN/ADefaultCommit<Impl>::initStage() 3491060SN/A{ 3502292SN/A rob->setActiveThreads(activeThreads); 3512292SN/A rob->resetEntries(); 3521060SN/A 3532292SN/A // Broadcast the number of free entries. 3546221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3556221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3566221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3576221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3581060SN/A } 3591060SN/A 3604329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3614329Sktlim@umich.edu // start of the simulation, so it starts as active. 3624329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3634329Sktlim@umich.edu 3642292SN/A cpu->activityThisCycle(); 3655100Ssaidi@eecs.umich.edu trapLatency = cpu->ticks(trapLatency); 3661060SN/A} 3671060SN/A 3681061SN/Atemplate <class Impl> 3692863Sktlim@umich.edubool 3702843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3711060SN/A{ 3722843Sktlim@umich.edu drainPending = true; 3732863Sktlim@umich.edu 3742863Sktlim@umich.edu return false; 3752316SN/A} 3762316SN/A 3772316SN/Atemplate <class Impl> 3782316SN/Avoid 3792843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3802316SN/A{ 3812316SN/A switchedOut = true; 3822843Sktlim@umich.edu drainPending = false; 3832307SN/A rob->switchOut(); 3842307SN/A} 3852307SN/A 3862307SN/Atemplate <class Impl> 3872307SN/Avoid 3882843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3892843Sktlim@umich.edu{ 3902864Sktlim@umich.edu drainPending = false; 3912843Sktlim@umich.edu} 3922843Sktlim@umich.edu 3932843Sktlim@umich.edutemplate <class Impl> 3942843Sktlim@umich.eduvoid 3952307SN/ADefaultCommit<Impl>::takeOverFrom() 3962307SN/A{ 3972316SN/A switchedOut = false; 3982307SN/A _status = Active; 3992307SN/A _nextStatus = Inactive; 4006221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4016221Snate@binkert.org commitStatus[tid] = Idle; 4026221Snate@binkert.org changedROBNumEntries[tid] = false; 4036221Snate@binkert.org trapSquash[tid] = false; 4046221Snate@binkert.org tcSquash[tid] = false; 4052307SN/A } 4062307SN/A squashCounter = 0; 4072307SN/A rob->takeOverFrom(); 4082307SN/A} 4092307SN/A 4102307SN/Atemplate <class Impl> 4112307SN/Avoid 4122292SN/ADefaultCommit<Impl>::updateStatus() 4132132SN/A{ 4142316SN/A // reset ROB changed variable 4156221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4166221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4173867Sbinkertn@umich.edu 4183867Sbinkertn@umich.edu while (threads != end) { 4196221Snate@binkert.org ThreadID tid = *threads++; 4203867Sbinkertn@umich.edu 4212316SN/A changedROBNumEntries[tid] = false; 4222316SN/A 4232316SN/A // Also check if any of the threads has a trap pending 4242316SN/A if (commitStatus[tid] == TrapPending || 4252316SN/A commitStatus[tid] == FetchTrapPending) { 4262316SN/A _nextStatus = Active; 4272316SN/A } 4282292SN/A } 4292292SN/A 4302292SN/A if (_nextStatus == Inactive && _status == Active) { 4312292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4322733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4332292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4342292SN/A DPRINTF(Activity, "Activating stage.\n"); 4352733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4362292SN/A } 4372292SN/A 4382292SN/A _status = _nextStatus; 4392292SN/A} 4402292SN/A 4412292SN/Atemplate <class Impl> 4422292SN/Avoid 4432292SN/ADefaultCommit<Impl>::setNextStatus() 4442292SN/A{ 4452292SN/A int squashes = 0; 4462292SN/A 4476221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4486221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4492292SN/A 4503867Sbinkertn@umich.edu while (threads != end) { 4516221Snate@binkert.org ThreadID tid = *threads++; 4522292SN/A 4532292SN/A if (commitStatus[tid] == ROBSquashing) { 4542292SN/A squashes++; 4552292SN/A } 4562292SN/A } 4572292SN/A 4582702Sktlim@umich.edu squashCounter = squashes; 4592292SN/A 4602292SN/A // If commit is currently squashing, then it will have activity for the 4612292SN/A // next cycle. Set its next status as active. 4622292SN/A if (squashCounter) { 4632292SN/A _nextStatus = Active; 4642292SN/A } 4652292SN/A} 4662292SN/A 4672292SN/Atemplate <class Impl> 4682292SN/Abool 4692292SN/ADefaultCommit<Impl>::changedROBEntries() 4702292SN/A{ 4716221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4726221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4732292SN/A 4743867Sbinkertn@umich.edu while (threads != end) { 4756221Snate@binkert.org ThreadID tid = *threads++; 4762292SN/A 4772292SN/A if (changedROBNumEntries[tid]) { 4782292SN/A return true; 4792292SN/A } 4802292SN/A } 4812292SN/A 4822292SN/A return false; 4832292SN/A} 4842292SN/A 4852292SN/Atemplate <class Impl> 4866221Snate@binkert.orgsize_t 4876221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 4882292SN/A{ 4892292SN/A return rob->numFreeEntries(tid); 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4932292SN/Avoid 4946221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 4952292SN/A{ 4962292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4972292SN/A 4982292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4992292SN/A 5007823Ssteve.reinhardt@amd.com cpu->schedule(trap, curTick() + trapLatency); 5014035Sktlim@umich.edu trapInFlight[tid] = true; 5022292SN/A} 5032292SN/A 5042292SN/Atemplate <class Impl> 5052292SN/Avoid 5066221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5072292SN/A{ 5084035Sktlim@umich.edu assert(!trapInFlight[tid]); 5092680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5102292SN/A 5112680Sktlim@umich.edu tcSquash[tid] = true; 5122292SN/A} 5132292SN/A 5142292SN/Atemplate <class Impl> 5152292SN/Avoid 5166221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5172292SN/A{ 5182292SN/A // If we want to include the squashing instruction in the squash, 5192292SN/A // then use one older sequence number. 5202292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5212292SN/A // all instructions of this thread. 5222292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5237855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5242292SN/A 5252292SN/A // All younger instructions will be squashed. Set the sequence 5262292SN/A // number as the youngest instruction in the ROB (0 in this case. 5272292SN/A // Hopefully nothing breaks.) 5287855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5292292SN/A 5302292SN/A rob->squash(squashed_inst, tid); 5312292SN/A changedROBNumEntries[tid] = true; 5322292SN/A 5332292SN/A // Send back the sequence number of the squashed instruction. 5342292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5352292SN/A 5362292SN/A // Send back the squash signal to tell stages that they should 5372292SN/A // squash. 5382292SN/A toIEW->commitInfo[tid].squash = true; 5392292SN/A 5402292SN/A // Send back the rob squashing signal so other stages know that 5412292SN/A // the ROB is in the process of squashing. 5422292SN/A toIEW->commitInfo[tid].robSquashing = true; 5432292SN/A 5442292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5457851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 5462292SN/A 5477720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5482316SN/A} 5492292SN/A 5502316SN/Atemplate <class Impl> 5512316SN/Avoid 5526221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5532316SN/A{ 5542316SN/A squashAll(tid); 5552316SN/A 5567720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5572316SN/A 5582316SN/A thread[tid]->trapPending = false; 5592316SN/A thread[tid]->inSyscall = false; 5604035Sktlim@umich.edu trapInFlight[tid] = false; 5612316SN/A 5622316SN/A trapSquash[tid] = false; 5632316SN/A 5642316SN/A commitStatus[tid] = ROBSquashing; 5652316SN/A cpu->activityThisCycle(); 5662316SN/A} 5672316SN/A 5682316SN/Atemplate <class Impl> 5692316SN/Avoid 5706221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 5712316SN/A{ 5722316SN/A squashAll(tid); 5732292SN/A 5747720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 5752292SN/A 5762292SN/A thread[tid]->inSyscall = false; 5772292SN/A assert(!thread[tid]->trapPending); 5782316SN/A 5792292SN/A commitStatus[tid] = ROBSquashing; 5802292SN/A cpu->activityThisCycle(); 5812292SN/A 5822680Sktlim@umich.edu tcSquash[tid] = false; 5832292SN/A} 5842292SN/A 5852292SN/Atemplate <class Impl> 5862292SN/Avoid 5877784SAli.Saidi@ARM.comDefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num) 5887784SAli.Saidi@ARM.com{ 5897784SAli.Saidi@ARM.com youngestSeqNum[tid] = squash_after_seq_num; 5907784SAli.Saidi@ARM.com 5917784SAli.Saidi@ARM.com rob->squash(squash_after_seq_num, tid); 5927784SAli.Saidi@ARM.com changedROBNumEntries[tid] = true; 5937784SAli.Saidi@ARM.com 5947784SAli.Saidi@ARM.com // Send back the sequence number of the squashed instruction. 5957784SAli.Saidi@ARM.com toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 5967784SAli.Saidi@ARM.com 5977784SAli.Saidi@ARM.com // Send back the squash signal to tell stages that they should squash. 5987784SAli.Saidi@ARM.com toIEW->commitInfo[tid].squash = true; 5997784SAli.Saidi@ARM.com 6007784SAli.Saidi@ARM.com // Send back the rob squashing signal so other stages know that 6017784SAli.Saidi@ARM.com // the ROB is in the process of squashing. 6027784SAli.Saidi@ARM.com toIEW->commitInfo[tid].robSquashing = true; 6037784SAli.Saidi@ARM.com 6047784SAli.Saidi@ARM.com toIEW->commitInfo[tid].branchMispredict = false; 6057784SAli.Saidi@ARM.com 6067784SAli.Saidi@ARM.com toIEW->commitInfo[tid].pc = pc[tid]; 6077784SAli.Saidi@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6087784SAli.Saidi@ARM.com tid, squash_after_seq_num); 6097784SAli.Saidi@ARM.com commitStatus[tid] = ROBSquashing; 6107784SAli.Saidi@ARM.com} 6117784SAli.Saidi@ARM.com 6127784SAli.Saidi@ARM.comtemplate <class Impl> 6137784SAli.Saidi@ARM.comvoid 6142292SN/ADefaultCommit<Impl>::tick() 6152292SN/A{ 6162292SN/A wroteToTimeBuffer = false; 6172292SN/A _nextStatus = Inactive; 6182292SN/A 6192843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 6202843Sktlim@umich.edu cpu->signalDrained(); 6212843Sktlim@umich.edu drainPending = false; 6222316SN/A return; 6232316SN/A } 6242316SN/A 6253867Sbinkertn@umich.edu if (activeThreads->empty()) 6262875Sksewell@umich.edu return; 6272875Sksewell@umich.edu 6286221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6296221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6302292SN/A 6312316SN/A // Check if any of the threads are done squashing. Change the 6322316SN/A // status if they are done. 6333867Sbinkertn@umich.edu while (threads != end) { 6346221Snate@binkert.org ThreadID tid = *threads++; 6352292SN/A 6364035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6374035Sktlim@umich.edu // this cycle. 6384035Sktlim@umich.edu committedStores[tid] = false; 6394035Sktlim@umich.edu 6402292SN/A if (commitStatus[tid] == ROBSquashing) { 6412292SN/A 6422292SN/A if (rob->isDoneSquashing(tid)) { 6432292SN/A commitStatus[tid] = Running; 6442292SN/A } else { 6452292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6462877Sksewell@umich.edu " insts this cycle.\n", tid); 6472702Sktlim@umich.edu rob->doSquash(tid); 6482702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6492702Sktlim@umich.edu wroteToTimeBuffer = true; 6502292SN/A } 6512292SN/A } 6522292SN/A } 6532292SN/A 6542292SN/A commit(); 6552292SN/A 6562292SN/A markCompletedInsts(); 6572292SN/A 6583867Sbinkertn@umich.edu threads = activeThreads->begin(); 6592292SN/A 6603867Sbinkertn@umich.edu while (threads != end) { 6616221Snate@binkert.org ThreadID tid = *threads++; 6622292SN/A 6632292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6642292SN/A // The ROB has more instructions it can commit. Its next status 6652292SN/A // will be active. 6662292SN/A _nextStatus = Active; 6672292SN/A 6682292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6692292SN/A 6707720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 6712292SN/A " ROB and ready to commit\n", 6727720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6732292SN/A 6742292SN/A } else if (!rob->isEmpty(tid)) { 6752292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6762292SN/A 6772292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6787720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 6797720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6802292SN/A } 6812292SN/A 6822292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6832292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6842292SN/A } 6852292SN/A 6862292SN/A 6872292SN/A if (wroteToTimeBuffer) { 6882316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6892292SN/A cpu->activityThisCycle(); 6902292SN/A } 6912292SN/A 6922292SN/A updateStatus(); 6932292SN/A} 6942292SN/A 6954035Sktlim@umich.edu#if FULL_SYSTEM 6962292SN/Atemplate <class Impl> 6972292SN/Avoid 6984035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 6992292SN/A{ 7007847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7017847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7027847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7037847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7047847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7057847Sminkyu.jeong@arm.com interrupt = NoFault; 7067847Sminkyu.jeong@arm.com return; 7077847Sminkyu.jeong@arm.com } 7083633Sktlim@umich.edu 7097847Sminkyu.jeong@arm.com // Wait until the ROB is empty and all stores have drained in 7107847Sminkyu.jeong@arm.com // order to enter the interrupt. 7117847Sminkyu.jeong@arm.com if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 7127847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7137847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7147847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7154035Sktlim@umich.edu 7167847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7177847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7182292SN/A 7197847Sminkyu.jeong@arm.com assert(!thread[0]->inSyscall); 7207847Sminkyu.jeong@arm.com thread[0]->inSyscall = true; 7212292SN/A 7227847Sminkyu.jeong@arm.com // CPU will handle interrupt. 7237847Sminkyu.jeong@arm.com cpu->processInterrupts(interrupt); 7243633Sktlim@umich.edu 7257847Sminkyu.jeong@arm.com thread[0]->inSyscall = false; 7262292SN/A 7277847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7282292SN/A 7297847Sminkyu.jeong@arm.com // Generate trap squash event. 7307847Sminkyu.jeong@arm.com generateTrapEvent(0); 7313640Sktlim@umich.edu 7327847Sminkyu.jeong@arm.com interrupt = NoFault; 7337847Sminkyu.jeong@arm.com } else { 7347847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 7351060SN/A } 7364035Sktlim@umich.edu} 7377847Sminkyu.jeong@arm.com 7387847Sminkyu.jeong@arm.comtemplate <class Impl> 7397847Sminkyu.jeong@arm.comvoid 7407847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 7417847Sminkyu.jeong@arm.com{ 7427847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 7437847Sminkyu.jeong@arm.com tcSquash[0]) 7447847Sminkyu.jeong@arm.com return; 7457847Sminkyu.jeong@arm.com 7467847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 7477847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 7487847Sminkyu.jeong@arm.com // pending. 7497847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 7507847Sminkyu.jeong@arm.com 7517847Sminkyu.jeong@arm.com // Get any interrupt that happened 7527847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 7537847Sminkyu.jeong@arm.com 7547847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 7557847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 7567847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 7577847Sminkyu.jeong@arm.com if (interrupt != NoFault) 7587847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 7597847Sminkyu.jeong@arm.com} 7607847Sminkyu.jeong@arm.com 7614035Sktlim@umich.edu#endif // FULL_SYSTEM 7623634Sktlim@umich.edu 7634035Sktlim@umich.edutemplate <class Impl> 7644035Sktlim@umich.eduvoid 7654035Sktlim@umich.eduDefaultCommit<Impl>::commit() 7664035Sktlim@umich.edu{ 7674035Sktlim@umich.edu 7684035Sktlim@umich.edu#if FULL_SYSTEM 7697847Sminkyu.jeong@arm.com // Check for any interrupt that we've already squashed for and start processing it. 7707847Sminkyu.jeong@arm.com if (interrupt != NoFault) 7714035Sktlim@umich.edu handleInterrupt(); 7727847Sminkyu.jeong@arm.com 7737847Sminkyu.jeong@arm.com // Check if we have a interrupt and get read to handle it 7747847Sminkyu.jeong@arm.com if (cpu->checkInterrupts(cpu->tcBase(0))) 7757847Sminkyu.jeong@arm.com propagateInterrupt(); 7761060SN/A#endif // FULL_SYSTEM 7771060SN/A 7781060SN/A //////////////////////////////////// 7792316SN/A // Check for any possible squashes, handle them first 7801060SN/A //////////////////////////////////// 7816221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7826221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7831060SN/A 7843867Sbinkertn@umich.edu while (threads != end) { 7856221Snate@binkert.org ThreadID tid = *threads++; 7861060SN/A 7872292SN/A // Not sure which one takes priority. I think if we have 7882292SN/A // both, that's a bad sign. 7892292SN/A if (trapSquash[tid] == true) { 7902680Sktlim@umich.edu assert(!tcSquash[tid]); 7912292SN/A squashFromTrap(tid); 7922680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7934035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 7942680Sktlim@umich.edu squashFromTC(tid); 7952292SN/A } 7961061SN/A 7972292SN/A // Squashed sequence number must be older than youngest valid 7982292SN/A // instruction in the ROB. This prevents squashes from younger 7992292SN/A // instructions overriding squashes from older instructions. 8002292SN/A if (fromIEW->squash[tid] && 8012292SN/A commitStatus[tid] != TrapPending && 8022292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8031061SN/A 8042292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 8052292SN/A tid, 8062292SN/A fromIEW->mispredPC[tid], 8072292SN/A fromIEW->squashedSeqNum[tid]); 8081061SN/A 8092292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8102292SN/A tid, 8117720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8121061SN/A 8132292SN/A commitStatus[tid] = ROBSquashing; 8141061SN/A 8152292SN/A // If we want to include the squashing instruction in the squash, 8162292SN/A // then use one older sequence number. 8172292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8181062SN/A 8192935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 8202292SN/A squashed_inst--; 8212935Sksewell@umich.edu } 8224035Sktlim@umich.edu 8232292SN/A // All younger instructions will be squashed. Set the sequence 8242292SN/A // number as the youngest instruction in the ROB. 8252292SN/A youngestSeqNum[tid] = squashed_inst; 8262292SN/A 8273093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8282292SN/A changedROBNumEntries[tid] = true; 8292292SN/A 8302292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8312292SN/A 8322292SN/A toIEW->commitInfo[tid].squash = true; 8332292SN/A 8342292SN/A // Send back the rob squashing signal so other stages know that 8352292SN/A // the ROB is in the process of squashing. 8362292SN/A toIEW->commitInfo[tid].robSquashing = true; 8372292SN/A 8382292SN/A toIEW->commitInfo[tid].branchMispredict = 8392292SN/A fromIEW->branchMispredict[tid]; 8407851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 8417851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 8422292SN/A toIEW->commitInfo[tid].branchTaken = 8432292SN/A fromIEW->branchTaken[tid]; 8442292SN/A 8457720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 8462292SN/A 8472316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 8482292SN/A 8492292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 8502292SN/A ++branchMispredicts; 8512292SN/A } 8521062SN/A } 8532292SN/A 8541060SN/A } 8551060SN/A 8562292SN/A setNextStatus(); 8572292SN/A 8582292SN/A if (squashCounter != numThreads) { 8591061SN/A // If we're not currently squashing, then get instructions. 8601060SN/A getInsts(); 8611060SN/A 8621061SN/A // Try to commit any instructions. 8631060SN/A commitInsts(); 8641060SN/A } 8651060SN/A 8662292SN/A //Check for any activity 8673867Sbinkertn@umich.edu threads = activeThreads->begin(); 8682292SN/A 8693867Sbinkertn@umich.edu while (threads != end) { 8706221Snate@binkert.org ThreadID tid = *threads++; 8712292SN/A 8722292SN/A if (changedROBNumEntries[tid]) { 8732292SN/A toIEW->commitInfo[tid].usedROB = true; 8742292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8752292SN/A 8762292SN/A wroteToTimeBuffer = true; 8772292SN/A changedROBNumEntries[tid] = false; 8784035Sktlim@umich.edu if (rob->isEmpty(tid)) 8794035Sktlim@umich.edu checkEmptyROB[tid] = true; 8802292SN/A } 8814035Sktlim@umich.edu 8824035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8834035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 8844035Sktlim@umich.edu // stage has received any information regarding stores that 8854035Sktlim@umich.edu // committed. 8864035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 8874035Sktlim@umich.edu // on the same cycle as when stores have been committed. 8884035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 8894035Sktlim@umich.edu // commit and IEW. 8904035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 8915557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 8924035Sktlim@umich.edu checkEmptyROB[tid] = false; 8934035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 8944035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 8954035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8964035Sktlim@umich.edu wroteToTimeBuffer = true; 8974035Sktlim@umich.edu } 8984035Sktlim@umich.edu 8991060SN/A } 9001060SN/A} 9011060SN/A 9021061SN/Atemplate <class Impl> 9031060SN/Avoid 9042292SN/ADefaultCommit<Impl>::commitInsts() 9051060SN/A{ 9061060SN/A //////////////////////////////////// 9071060SN/A // Handle commit 9082316SN/A // Note that commit will be handled prior to putting new 9092316SN/A // instructions in the ROB so that the ROB only tries to commit 9102316SN/A // instructions it has in this current cycle, and not instructions 9112316SN/A // it is writing in during this cycle. Can't commit and squash 9122316SN/A // things at the same time... 9131060SN/A //////////////////////////////////// 9141060SN/A 9152292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9161060SN/A 9171060SN/A unsigned num_committed = 0; 9181060SN/A 9192292SN/A DynInstPtr head_inst; 9202316SN/A 9211060SN/A // Commit as many instructions as possible until the commit bandwidth 9221060SN/A // limit is reached, or it becomes impossible to commit any more. 9232292SN/A while (num_committed < commitWidth) { 9242292SN/A int commit_thread = getCommittingThread(); 9251060SN/A 9262292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9272292SN/A break; 9282292SN/A 9292292SN/A head_inst = rob->readHeadInst(commit_thread); 9302292SN/A 9316221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 9322292SN/A 9332292SN/A assert(tid == commit_thread); 9342292SN/A 9352292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 9362292SN/A head_inst->seqNum, tid); 9372132SN/A 9382316SN/A // If the head instruction is squashed, it is ready to retire 9392316SN/A // (be removed from the ROB) at any time. 9401060SN/A if (head_inst->isSquashed()) { 9411060SN/A 9422292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 9431060SN/A "ROB.\n"); 9441060SN/A 9452292SN/A rob->retireHead(commit_thread); 9461060SN/A 9471062SN/A ++commitSquashedInsts; 9481062SN/A 9492292SN/A // Record that the number of ROB entries has changed. 9502292SN/A changedROBNumEntries[tid] = true; 9511060SN/A } else { 9527720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 9532292SN/A 9541060SN/A // Increment the total number of non-speculative instructions 9551060SN/A // executed. 9561060SN/A // Hack for now: it really shouldn't happen until after the 9571061SN/A // commit is deemed to be successful, but this count is needed 9581061SN/A // for syscalls. 9592292SN/A thread[tid]->funcExeInst++; 9601060SN/A 9611060SN/A // Try to commit the head instruction. 9621060SN/A bool commit_success = commitHead(head_inst, num_committed); 9631060SN/A 9641062SN/A if (commit_success) { 9651060SN/A ++num_committed; 9661060SN/A 9672292SN/A changedROBNumEntries[tid] = true; 9682292SN/A 9692292SN/A // Set the doneSeqNum to the youngest committed instruction. 9702292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9711060SN/A 9721062SN/A ++commitCommittedInsts; 9731062SN/A 9742292SN/A // To match the old model, don't count nops and instruction 9752292SN/A // prefetches towards the total commit count. 9762292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9772292SN/A cpu->instDone(tid); 9781062SN/A } 9792292SN/A 9807783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 9817783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 9827783SGiacomo.Gabrielli@arm.com 9837720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 9842935Sksewell@umich.edu 9857855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 9867855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 9877855SAli.Saidi@ARM.com 9887784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 9897784SAli.Saidi@ARM.com // others squash everything and restart fetch 9907784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 9917784SAli.Saidi@ARM.com squashAfter(tid, head_inst->seqNum); 9927784SAli.Saidi@ARM.com 9932292SN/A int count = 0; 9942292SN/A Addr oldpc; 9955108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 9965108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 9975108Sgblack@eecs.umich.edu assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 9982292SN/A do { 9997720Sgblack@eecs.umich.edu oldpc = pc[tid].instAddr(); 10005108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 10012292SN/A count++; 10027720Sgblack@eecs.umich.edu } while (oldpc != pc[tid].instAddr()); 10032292SN/A if (count > 1) { 10045108Sgblack@eecs.umich.edu DPRINTF(Commit, 10055108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 10062292SN/A break; 10072292SN/A } 10081060SN/A } else { 10097720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 10102292SN/A "[tid:%i] [sn:%i].\n", 10117720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 10121060SN/A break; 10131060SN/A } 10141060SN/A } 10151060SN/A } 10161062SN/A 10171063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 10182292SN/A numCommittedDist.sample(num_committed); 10192307SN/A 10202307SN/A if (num_committed == commitWidth) { 10212349SN/A commitEligibleSamples++; 10222307SN/A } 10231060SN/A} 10241060SN/A 10251061SN/Atemplate <class Impl> 10261060SN/Abool 10272292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 10281060SN/A{ 10291060SN/A assert(head_inst); 10301060SN/A 10316221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 10322292SN/A 10332316SN/A // If the instruction is not executed yet, then it will need extra 10342316SN/A // handling. Signal backwards that it should be executed. 10351061SN/A if (!head_inst->isExecuted()) { 10361061SN/A // Keep this number correct. We have not yet actually executed 10371061SN/A // and committed this instruction. 10382292SN/A thread[tid]->funcExeInst--; 10391062SN/A 10402292SN/A if (head_inst->isNonSpeculative() || 10412348SN/A head_inst->isStoreConditional() || 10422292SN/A head_inst->isMemBarrier() || 10432292SN/A head_inst->isWriteBarrier()) { 10442316SN/A 10452316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 10467720Sgblack@eecs.umich.edu "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 10477720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 10482316SN/A 10495557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 10502292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10512292SN/A return false; 10522292SN/A } 10532292SN/A 10542292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10551061SN/A 10561061SN/A // Change the instruction so it won't try to commit again until 10571061SN/A // it is executed. 10581061SN/A head_inst->clearCanCommit(); 10591061SN/A 10601062SN/A ++commitNonSpecStalls; 10611062SN/A 10621061SN/A return false; 10632292SN/A } else if (head_inst->isLoad()) { 10645557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 10654035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10664035Sktlim@umich.edu return false; 10674035Sktlim@umich.edu } 10684035Sktlim@umich.edu 10694035Sktlim@umich.edu assert(head_inst->uncacheable()); 10707720Sgblack@eecs.umich.edu DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 10717720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 10722292SN/A 10732292SN/A // Send back the non-speculative instruction's sequence 10742316SN/A // number. Tell the lsq to re-execute the load. 10752292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10762292SN/A toIEW->commitInfo[tid].uncached = true; 10772292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10782292SN/A 10792292SN/A head_inst->clearCanCommit(); 10802292SN/A 10812292SN/A return false; 10821061SN/A } else { 10832292SN/A panic("Trying to commit un-executed instruction " 10841061SN/A "of unknown type!\n"); 10851061SN/A } 10861060SN/A } 10871060SN/A 10882316SN/A if (head_inst->isThreadSync()) { 10892292SN/A // Not handled for now. 10902316SN/A panic("Thread sync instructions are not handled yet.\n"); 10912132SN/A } 10922132SN/A 10934035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 10944035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 10954035Sktlim@umich.edu 10962316SN/A // Stores mark themselves as completed. 10974035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 10982310SN/A head_inst->setCompleted(); 10992310SN/A } 11002310SN/A 11012733Sktlim@umich.edu#if USE_CHECKER 11022316SN/A // Use checker prior to updating anything due to traps or PC 11032316SN/A // based events. 11042316SN/A if (cpu->checker) { 11052732Sktlim@umich.edu cpu->checker->verify(head_inst); 11061060SN/A } 11072733Sktlim@umich.edu#endif 11081060SN/A 11092112SN/A if (inst_fault != NoFault) { 11107720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 11117720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11122292SN/A 11135557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 11142316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 11152316SN/A return false; 11162316SN/A } 11172310SN/A 11184035Sktlim@umich.edu head_inst->setCompleted(); 11194035Sktlim@umich.edu 11202733Sktlim@umich.edu#if USE_CHECKER 11212316SN/A if (cpu->checker && head_inst->isStore()) { 11222732Sktlim@umich.edu cpu->checker->verify(head_inst); 11232316SN/A } 11242733Sktlim@umich.edu#endif 11252292SN/A 11262316SN/A assert(!thread[tid]->inSyscall); 11272292SN/A 11282316SN/A // Mark that we're in state update mode so that the trap's 11292316SN/A // execution doesn't generate extra squashes. 11302316SN/A thread[tid]->inSyscall = true; 11312292SN/A 11322316SN/A // Execute the trap. Although it's slightly unrealistic in 11332316SN/A // terms of timing (as it doesn't wait for the full timing of 11342316SN/A // the trap event to complete before updating state), it's 11352316SN/A // needed to update the state as soon as possible. This 11362316SN/A // prevents external agents from changing any specific state 11372316SN/A // that the trap need. 11387684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 11392292SN/A 11402316SN/A // Exit state update mode to avoid accidental updating. 11412316SN/A thread[tid]->inSyscall = false; 11422292SN/A 11432316SN/A commitStatus[tid] = TrapPending; 11442292SN/A 11458067SAli.Saidi@ARM.com DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 11468067SAli.Saidi@ARM.com head_inst->seqNum); 11474035Sktlim@umich.edu if (head_inst->traceData) { 11486667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 11496667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 11506667Ssteve.reinhardt@amd.com head_inst->traceData->setCPSeq(thread[tid]->numInst); 11516667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 11526667Ssteve.reinhardt@amd.com } 11534288Sktlim@umich.edu delete head_inst->traceData; 11544035Sktlim@umich.edu head_inst->traceData = NULL; 11554035Sktlim@umich.edu } 11564035Sktlim@umich.edu 11572316SN/A // Generate trap squash event. 11582316SN/A generateTrapEvent(tid); 11592316SN/A return false; 11601060SN/A } 11611060SN/A 11622301SN/A updateComInstStats(head_inst); 11632132SN/A 11642362SN/A#if FULL_SYSTEM 11652362SN/A if (thread[tid]->profile) { 11667720Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 11673126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 11682362SN/A head_inst->staticInst); 11692362SN/A 11702362SN/A if (node) 11712362SN/A thread[tid]->profileNode = node; 11722362SN/A } 11735953Ssaidi@eecs.umich.edu if (CPA::available()) { 11745953Ssaidi@eecs.umich.edu if (head_inst->isControl()) { 11755953Ssaidi@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 11767720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 11775953Ssaidi@eecs.umich.edu } 11785953Ssaidi@eecs.umich.edu } 11792362SN/A#endif 11802362SN/A 11812132SN/A if (head_inst->traceData) { 11822292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11832292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11844046Sbinkertn@umich.edu head_inst->traceData->dump(); 11854046Sbinkertn@umich.edu delete head_inst->traceData; 11862292SN/A head_inst->traceData = NULL; 11871060SN/A } 11881060SN/A 11892292SN/A // Update the commit rename map 11902292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11913771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 11922292SN/A head_inst->renamedDestRegIdx(i)); 11931060SN/A } 11941062SN/A 11952353SN/A if (head_inst->isCopy()) 11962353SN/A panic("Should not commit any copy instructions!"); 11972353SN/A 11982292SN/A // Finally clear the head ROB entry. 11992292SN/A rob->retireHead(tid); 12001060SN/A 12014035Sktlim@umich.edu // If this was a store, record it for this cycle. 12024035Sktlim@umich.edu if (head_inst->isStore()) 12034035Sktlim@umich.edu committedStores[tid] = true; 12044035Sktlim@umich.edu 12051060SN/A // Return true to indicate that we have committed an instruction. 12061060SN/A return true; 12071060SN/A} 12081060SN/A 12091061SN/Atemplate <class Impl> 12101060SN/Avoid 12112292SN/ADefaultCommit<Impl>::getInsts() 12121060SN/A{ 12132935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 12142935Sksewell@umich.edu 12153093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 12163093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 12172965Sksewell@umich.edu 12182965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 12192965Sksewell@umich.edu DynInstPtr inst; 12202965Sksewell@umich.edu 12213093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 12226221Snate@binkert.org ThreadID tid = inst->threadNumber; 12232292SN/A 12242292SN/A if (!inst->isSquashed() && 12254035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 12264035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 12272292SN/A changedROBNumEntries[tid] = true; 12282292SN/A 12297720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 12307720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 12312292SN/A 12322292SN/A rob->insertInst(inst); 12332292SN/A 12342292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 12352292SN/A 12362292SN/A youngestSeqNum[tid] = inst->seqNum; 12371061SN/A } else { 12387720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 12391061SN/A "squashed, skipping.\n", 12407720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 12411061SN/A } 12421060SN/A } 12432965Sksewell@umich.edu} 12442965Sksewell@umich.edu 12452965Sksewell@umich.edutemplate <class Impl> 12462965Sksewell@umich.eduvoid 12472965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 12482965Sksewell@umich.edu{ 12492965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 12502965Sksewell@umich.edu "skidBuffer.\n"); 12512965Sksewell@umich.edu 12522965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 12532965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 12542965Sksewell@umich.edu 12552965Sksewell@umich.edu if (!inst->isSquashed()) { 12567720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 12577720Sgblack@eecs.umich.edu "skidBuffer.\n", inst->pcState(), inst->seqNum, 12583221Sktlim@umich.edu inst->threadNumber); 12592965Sksewell@umich.edu skidBuffer.push(inst); 12602965Sksewell@umich.edu } else { 12617720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 12622965Sksewell@umich.edu "squashed, skipping.\n", 12637720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->threadNumber); 12642965Sksewell@umich.edu } 12652965Sksewell@umich.edu } 12661060SN/A} 12671060SN/A 12681061SN/Atemplate <class Impl> 12691060SN/Avoid 12702292SN/ADefaultCommit<Impl>::markCompletedInsts() 12711060SN/A{ 12721060SN/A // Grab completed insts out of the IEW instruction queue, and mark 12731060SN/A // instructions completed within the ROB. 12741060SN/A for (int inst_num = 0; 12751681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 12761060SN/A ++inst_num) 12771060SN/A { 12782292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12797720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 12802316SN/A "within ROB.\n", 12812292SN/A fromIEW->insts[inst_num]->threadNumber, 12827720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 12832292SN/A fromIEW->insts[inst_num]->seqNum); 12841060SN/A 12852292SN/A // Mark the instruction as ready to commit. 12862292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12872292SN/A } 12881060SN/A } 12891060SN/A} 12901060SN/A 12911061SN/Atemplate <class Impl> 12922292SN/Abool 12932292SN/ADefaultCommit<Impl>::robDoneSquashing() 12941060SN/A{ 12956221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12966221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12972292SN/A 12983867Sbinkertn@umich.edu while (threads != end) { 12996221Snate@binkert.org ThreadID tid = *threads++; 13002292SN/A 13012292SN/A if (!rob->isDoneSquashing(tid)) 13022292SN/A return false; 13032292SN/A } 13042292SN/A 13052292SN/A return true; 13061060SN/A} 13072292SN/A 13082301SN/Atemplate <class Impl> 13092301SN/Avoid 13102301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 13112301SN/A{ 13126221Snate@binkert.org ThreadID tid = inst->threadNumber; 13132301SN/A 13142301SN/A // 13152301SN/A // Pick off the software prefetches 13162301SN/A // 13172301SN/A#ifdef TARGET_ALPHA 13182301SN/A if (inst->isDataPrefetch()) { 13196221Snate@binkert.org statComSwp[tid]++; 13202301SN/A } else { 13216221Snate@binkert.org statComInst[tid]++; 13222301SN/A } 13232301SN/A#else 13246221Snate@binkert.org statComInst[tid]++; 13252301SN/A#endif 13262301SN/A 13272301SN/A // 13282301SN/A // Control Instructions 13292301SN/A // 13302301SN/A if (inst->isControl()) 13316221Snate@binkert.org statComBranches[tid]++; 13322301SN/A 13332301SN/A // 13342301SN/A // Memory references 13352301SN/A // 13362301SN/A if (inst->isMemRef()) { 13376221Snate@binkert.org statComRefs[tid]++; 13382301SN/A 13392301SN/A if (inst->isLoad()) { 13406221Snate@binkert.org statComLoads[tid]++; 13412301SN/A } 13422301SN/A } 13432301SN/A 13442301SN/A if (inst->isMemBarrier()) { 13456221Snate@binkert.org statComMembars[tid]++; 13462301SN/A } 13477897Shestness@cs.utexas.edu 13487897Shestness@cs.utexas.edu // Integer Instruction 13497897Shestness@cs.utexas.edu if (inst->isInteger()) 13507897Shestness@cs.utexas.edu statComInteger[tid]++; 13517897Shestness@cs.utexas.edu 13527897Shestness@cs.utexas.edu // Floating Point Instruction 13537897Shestness@cs.utexas.edu if (inst->isFloating()) 13547897Shestness@cs.utexas.edu statComFloating[tid]++; 13557897Shestness@cs.utexas.edu 13567897Shestness@cs.utexas.edu // Function Calls 13577897Shestness@cs.utexas.edu if (inst->isCall()) 13587897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 13597897Shestness@cs.utexas.edu 13602301SN/A} 13612301SN/A 13622292SN/A//////////////////////////////////////// 13632292SN/A// // 13642316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 13652292SN/A// // 13662292SN/A//////////////////////////////////////// 13672292SN/Atemplate <class Impl> 13686221Snate@binkert.orgThreadID 13692292SN/ADefaultCommit<Impl>::getCommittingThread() 13702292SN/A{ 13712292SN/A if (numThreads > 1) { 13722292SN/A switch (commitPolicy) { 13732292SN/A 13742292SN/A case Aggressive: 13752292SN/A //If Policy is Aggressive, commit will call 13762292SN/A //this function multiple times per 13772292SN/A //cycle 13782292SN/A return oldestReady(); 13792292SN/A 13802292SN/A case RoundRobin: 13812292SN/A return roundRobin(); 13822292SN/A 13832292SN/A case OldestReady: 13842292SN/A return oldestReady(); 13852292SN/A 13862292SN/A default: 13876221Snate@binkert.org return InvalidThreadID; 13882292SN/A } 13892292SN/A } else { 13903867Sbinkertn@umich.edu assert(!activeThreads->empty()); 13916221Snate@binkert.org ThreadID tid = activeThreads->front(); 13922292SN/A 13932292SN/A if (commitStatus[tid] == Running || 13942292SN/A commitStatus[tid] == Idle || 13952292SN/A commitStatus[tid] == FetchTrapPending) { 13962292SN/A return tid; 13972292SN/A } else { 13986221Snate@binkert.org return InvalidThreadID; 13992292SN/A } 14002292SN/A } 14012292SN/A} 14022292SN/A 14032292SN/Atemplate<class Impl> 14046221Snate@binkert.orgThreadID 14052292SN/ADefaultCommit<Impl>::roundRobin() 14062292SN/A{ 14076221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14086221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14092292SN/A 14102292SN/A while (pri_iter != end) { 14116221Snate@binkert.org ThreadID tid = *pri_iter; 14122292SN/A 14132292SN/A if (commitStatus[tid] == Running || 14142831Sksewell@umich.edu commitStatus[tid] == Idle || 14152831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 14162292SN/A 14172292SN/A if (rob->isHeadReady(tid)) { 14182292SN/A priority_list.erase(pri_iter); 14192292SN/A priority_list.push_back(tid); 14202292SN/A 14212292SN/A return tid; 14222292SN/A } 14232292SN/A } 14242292SN/A 14252292SN/A pri_iter++; 14262292SN/A } 14272292SN/A 14286221Snate@binkert.org return InvalidThreadID; 14292292SN/A} 14302292SN/A 14312292SN/Atemplate<class Impl> 14326221Snate@binkert.orgThreadID 14332292SN/ADefaultCommit<Impl>::oldestReady() 14342292SN/A{ 14352292SN/A unsigned oldest = 0; 14362292SN/A bool first = true; 14372292SN/A 14386221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14396221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14402292SN/A 14413867Sbinkertn@umich.edu while (threads != end) { 14426221Snate@binkert.org ThreadID tid = *threads++; 14432292SN/A 14442292SN/A if (!rob->isEmpty(tid) && 14452292SN/A (commitStatus[tid] == Running || 14462292SN/A commitStatus[tid] == Idle || 14472292SN/A commitStatus[tid] == FetchTrapPending)) { 14482292SN/A 14492292SN/A if (rob->isHeadReady(tid)) { 14502292SN/A 14512292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 14522292SN/A 14532292SN/A if (first) { 14542292SN/A oldest = tid; 14552292SN/A first = false; 14562292SN/A } else if (head_inst->seqNum < oldest) { 14572292SN/A oldest = tid; 14582292SN/A } 14592292SN/A } 14602292SN/A } 14612292SN/A } 14622292SN/A 14632292SN/A if (!first) { 14642292SN/A return oldest; 14652292SN/A } else { 14666221Snate@binkert.org return InvalidThreadID; 14672292SN/A } 14682292SN/A} 1469