commit_impl.hh revision 7823
11689SN/A/*
27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited
37783SGiacomo.Gabrielli@arm.com * All rights reserved
47783SGiacomo.Gabrielli@arm.com *
57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall
67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual
77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating
87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software
97783SGiacomo.Gabrielli@arm.com * licensed hereunder.  You may use the software subject to the license
107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated
117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software,
127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form.
137783SGiacomo.Gabrielli@arm.com *
142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
151689SN/A * All rights reserved.
161689SN/A *
171689SN/A * Redistribution and use in source and binary forms, with or without
181689SN/A * modification, are permitted provided that the following conditions are
191689SN/A * met: redistributions of source code must retain the above copyright
201689SN/A * notice, this list of conditions and the following disclaimer;
211689SN/A * redistributions in binary form must reproduce the above copyright
221689SN/A * notice, this list of conditions and the following disclaimer in the
231689SN/A * documentation and/or other materials provided with the distribution;
241689SN/A * neither the name of the copyright holders nor the names of its
251689SN/A * contributors may be used to endorse or promote products derived from
261689SN/A * this software without specific prior written permission.
271689SN/A *
281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665Ssaidi@eecs.umich.edu *
402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
412965Sksewell@umich.edu *          Korey Sewell
421689SN/A */
431689SN/A
442292SN/A#include <algorithm>
452329SN/A#include <string>
462292SN/A
473577Sgblack@eecs.umich.edu#include "arch/utility.hh"
485953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh"
492292SN/A#include "base/loader/symtab.hh"
507813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh"
516221Snate@binkert.org#include "config/full_system.hh"
526658Snate@binkert.org#include "config/the_isa.hh"
536221Snate@binkert.org#include "config/use_checker.hh"
542292SN/A#include "cpu/exetrace.hh"
551717SN/A#include "cpu/o3/commit.hh"
562292SN/A#include "cpu/o3/thread_state.hh"
576221Snate@binkert.org#include "params/DerivO3CPU.hh"
582292SN/A
592790Sktlim@umich.edu#if USE_CHECKER
602790Sktlim@umich.edu#include "cpu/checker/cpu.hh"
612790Sktlim@umich.edu#endif
622790Sktlim@umich.edu
636221Snate@binkert.orgusing namespace std;
645529Snate@binkert.org
651061SN/Atemplate <class Impl>
662292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
676221Snate@binkert.org                                          ThreadID _tid)
685606Snate@binkert.org    : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
691060SN/A{
705769Snate@binkert.org    this->setFlags(AutoDelete);
711060SN/A}
721060SN/A
731061SN/Atemplate <class Impl>
741060SN/Avoid
752292SN/ADefaultCommit<Impl>::TrapEvent::process()
761062SN/A{
772316SN/A    // This will get reset by commit if it was switched out at the
782316SN/A    // time of this event processing.
792292SN/A    commit->trapSquash[tid] = true;
802292SN/A}
812292SN/A
822292SN/Atemplate <class Impl>
832292SN/Aconst char *
845336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const
852292SN/A{
864873Sstever@eecs.umich.edu    return "Trap";
872292SN/A}
882292SN/A
892292SN/Atemplate <class Impl>
905529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
914329Sktlim@umich.edu    : cpu(_cpu),
924329Sktlim@umich.edu      squashCounter(0),
932292SN/A      iewToCommitDelay(params->iewToCommitDelay),
942292SN/A      commitToIEWDelay(params->commitToIEWDelay),
952292SN/A      renameToROBDelay(params->renameToROBDelay),
962292SN/A      fetchToCommitDelay(params->commitToFetchDelay),
972292SN/A      renameWidth(params->renameWidth),
982292SN/A      commitWidth(params->commitWidth),
995529Snate@binkert.org      numThreads(params->numThreads),
1002843Sktlim@umich.edu      drainPending(false),
1012316SN/A      switchedOut(false),
1022874Sktlim@umich.edu      trapLatency(params->trapLatency)
1032292SN/A{
1042292SN/A    _status = Active;
1052292SN/A    _nextStatus = Inactive;
1062980Sgblack@eecs.umich.edu    std::string policy = params->smtCommitPolicy;
1072292SN/A
1082292SN/A    //Convert string to lowercase
1092292SN/A    std::transform(policy.begin(), policy.end(), policy.begin(),
1102292SN/A                   (int(*)(int)) tolower);
1112292SN/A
1122292SN/A    //Assign commit policy
1132292SN/A    if (policy == "aggressive"){
1142292SN/A        commitPolicy = Aggressive;
1152292SN/A
1164329Sktlim@umich.edu        DPRINTF(Commit,"Commit Policy set to Aggressive.");
1172292SN/A    } else if (policy == "roundrobin"){
1182292SN/A        commitPolicy = RoundRobin;
1192292SN/A
1202292SN/A        //Set-Up Priority List
1216221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
1222292SN/A            priority_list.push_back(tid);
1232292SN/A        }
1242292SN/A
1254329Sktlim@umich.edu        DPRINTF(Commit,"Commit Policy set to Round Robin.");
1262292SN/A    } else if (policy == "oldestready"){
1272292SN/A        commitPolicy = OldestReady;
1282292SN/A
1294329Sktlim@umich.edu        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
1302292SN/A    } else {
1312292SN/A        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
1322292SN/A               "RoundRobin,OldestReady}");
1332292SN/A    }
1342292SN/A
1356221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
1366221Snate@binkert.org        commitStatus[tid] = Idle;
1376221Snate@binkert.org        changedROBNumEntries[tid] = false;
1386221Snate@binkert.org        checkEmptyROB[tid] = false;
1396221Snate@binkert.org        trapInFlight[tid] = false;
1406221Snate@binkert.org        committedStores[tid] = false;
1416221Snate@binkert.org        trapSquash[tid] = false;
1426221Snate@binkert.org        tcSquash[tid] = false;
1437720Sgblack@eecs.umich.edu        pc[tid].set(0);
1442292SN/A    }
1453640Sktlim@umich.edu#if FULL_SYSTEM
1463640Sktlim@umich.edu    interrupt = NoFault;
1473640Sktlim@umich.edu#endif
1482292SN/A}
1492292SN/A
1502292SN/Atemplate <class Impl>
1512292SN/Astd::string
1522292SN/ADefaultCommit<Impl>::name() const
1532292SN/A{
1542292SN/A    return cpu->name() + ".commit";
1552292SN/A}
1562292SN/A
1572292SN/Atemplate <class Impl>
1582292SN/Avoid
1592292SN/ADefaultCommit<Impl>::regStats()
1602132SN/A{
1612301SN/A    using namespace Stats;
1621062SN/A    commitCommittedInsts
1631062SN/A        .name(name() + ".commitCommittedInsts")
1641062SN/A        .desc("The number of committed instructions")
1651062SN/A        .prereq(commitCommittedInsts);
1661062SN/A    commitSquashedInsts
1671062SN/A        .name(name() + ".commitSquashedInsts")
1681062SN/A        .desc("The number of squashed insts skipped by commit")
1691062SN/A        .prereq(commitSquashedInsts);
1701062SN/A    commitSquashEvents
1711062SN/A        .name(name() + ".commitSquashEvents")
1721062SN/A        .desc("The number of times commit is told to squash")
1731062SN/A        .prereq(commitSquashEvents);
1741062SN/A    commitNonSpecStalls
1751062SN/A        .name(name() + ".commitNonSpecStalls")
1761062SN/A        .desc("The number of times commit has been forced to stall to "
1771062SN/A              "communicate backwards")
1781062SN/A        .prereq(commitNonSpecStalls);
1791062SN/A    branchMispredicts
1801062SN/A        .name(name() + ".branchMispredicts")
1811062SN/A        .desc("The number of times a branch was mispredicted")
1821062SN/A        .prereq(branchMispredicts);
1832292SN/A    numCommittedDist
1841062SN/A        .init(0,commitWidth,1)
1851062SN/A        .name(name() + ".COM:committed_per_cycle")
1861062SN/A        .desc("Number of insts commited each cycle")
1871062SN/A        .flags(Stats::pdf)
1881062SN/A        ;
1892301SN/A
1902316SN/A    statComInst
1916221Snate@binkert.org        .init(cpu->numThreads)
1922301SN/A        .name(name() + ".COM:count")
1932301SN/A        .desc("Number of instructions committed")
1942301SN/A        .flags(total)
1952301SN/A        ;
1962301SN/A
1972316SN/A    statComSwp
1986221Snate@binkert.org        .init(cpu->numThreads)
1992301SN/A        .name(name() + ".COM:swp_count")
2002301SN/A        .desc("Number of s/w prefetches committed")
2012301SN/A        .flags(total)
2022301SN/A        ;
2032301SN/A
2042316SN/A    statComRefs
2056221Snate@binkert.org        .init(cpu->numThreads)
2062301SN/A        .name(name() +  ".COM:refs")
2072301SN/A        .desc("Number of memory references committed")
2082301SN/A        .flags(total)
2092301SN/A        ;
2102301SN/A
2112316SN/A    statComLoads
2126221Snate@binkert.org        .init(cpu->numThreads)
2132301SN/A        .name(name() +  ".COM:loads")
2142301SN/A        .desc("Number of loads committed")
2152301SN/A        .flags(total)
2162301SN/A        ;
2172301SN/A
2182316SN/A    statComMembars
2196221Snate@binkert.org        .init(cpu->numThreads)
2202301SN/A        .name(name() +  ".COM:membars")
2212301SN/A        .desc("Number of memory barriers committed")
2222301SN/A        .flags(total)
2232301SN/A        ;
2242301SN/A
2252316SN/A    statComBranches
2266221Snate@binkert.org        .init(cpu->numThreads)
2272301SN/A        .name(name() + ".COM:branches")
2282301SN/A        .desc("Number of branches committed")
2292301SN/A        .flags(total)
2302301SN/A        ;
2312301SN/A
2322316SN/A    commitEligible
2336221Snate@binkert.org        .init(cpu->numThreads)
2342301SN/A        .name(name() + ".COM:bw_limited")
2352301SN/A        .desc("number of insts not committed due to BW limits")
2362301SN/A        .flags(total)
2372301SN/A        ;
2382301SN/A
2392316SN/A    commitEligibleSamples
2402301SN/A        .name(name() + ".COM:bw_lim_events")
2412301SN/A        .desc("number cycles where commit BW limit reached")
2422301SN/A        ;
2431062SN/A}
2441062SN/A
2451062SN/Atemplate <class Impl>
2461062SN/Avoid
2472980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
2482292SN/A{
2492292SN/A    thread = threads;
2502292SN/A}
2512292SN/A
2522292SN/Atemplate <class Impl>
2532292SN/Avoid
2542292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
2551060SN/A{
2561060SN/A    timeBuffer = tb_ptr;
2571060SN/A
2581060SN/A    // Setup wire to send information back to IEW.
2591060SN/A    toIEW = timeBuffer->getWire(0);
2601060SN/A
2611060SN/A    // Setup wire to read data from IEW (for the ROB).
2621060SN/A    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
2631060SN/A}
2641060SN/A
2651061SN/Atemplate <class Impl>
2661060SN/Avoid
2672292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
2682292SN/A{
2692292SN/A    fetchQueue = fq_ptr;
2702292SN/A
2712292SN/A    // Setup wire to get instructions from rename (for the ROB).
2722292SN/A    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
2732292SN/A}
2742292SN/A
2752292SN/Atemplate <class Impl>
2762292SN/Avoid
2772292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
2781060SN/A{
2791060SN/A    renameQueue = rq_ptr;
2801060SN/A
2811060SN/A    // Setup wire to get instructions from rename (for the ROB).
2821060SN/A    fromRename = renameQueue->getWire(-renameToROBDelay);
2831060SN/A}
2841060SN/A
2851061SN/Atemplate <class Impl>
2861060SN/Avoid
2872292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
2881060SN/A{
2891060SN/A    iewQueue = iq_ptr;
2901060SN/A
2911060SN/A    // Setup wire to get instructions from IEW.
2921060SN/A    fromIEW = iewQueue->getWire(-iewToCommitDelay);
2931060SN/A}
2941060SN/A
2951061SN/Atemplate <class Impl>
2961060SN/Avoid
2972292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
2982292SN/A{
2992292SN/A    iewStage = iew_stage;
3002292SN/A}
3012292SN/A
3022292SN/Atemplate<class Impl>
3032292SN/Avoid
3046221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
3052292SN/A{
3062292SN/A    activeThreads = at_ptr;
3072292SN/A}
3082292SN/A
3092292SN/Atemplate <class Impl>
3102292SN/Avoid
3112292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
3122292SN/A{
3136221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++)
3146221Snate@binkert.org        renameMap[tid] = &rm_ptr[tid];
3152292SN/A}
3162292SN/A
3172292SN/Atemplate <class Impl>
3182292SN/Avoid
3192292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr)
3201060SN/A{
3211060SN/A    rob = rob_ptr;
3221060SN/A}
3231060SN/A
3241061SN/Atemplate <class Impl>
3251060SN/Avoid
3262292SN/ADefaultCommit<Impl>::initStage()
3271060SN/A{
3282292SN/A    rob->setActiveThreads(activeThreads);
3292292SN/A    rob->resetEntries();
3301060SN/A
3312292SN/A    // Broadcast the number of free entries.
3326221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
3336221Snate@binkert.org        toIEW->commitInfo[tid].usedROB = true;
3346221Snate@binkert.org        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
3356221Snate@binkert.org        toIEW->commitInfo[tid].emptyROB = true;
3361060SN/A    }
3371060SN/A
3384329Sktlim@umich.edu    // Commit must broadcast the number of free entries it has at the
3394329Sktlim@umich.edu    // start of the simulation, so it starts as active.
3404329Sktlim@umich.edu    cpu->activateStage(O3CPU::CommitIdx);
3414329Sktlim@umich.edu
3422292SN/A    cpu->activityThisCycle();
3435100Ssaidi@eecs.umich.edu    trapLatency = cpu->ticks(trapLatency);
3441060SN/A}
3451060SN/A
3461061SN/Atemplate <class Impl>
3472863Sktlim@umich.edubool
3482843Sktlim@umich.eduDefaultCommit<Impl>::drain()
3491060SN/A{
3502843Sktlim@umich.edu    drainPending = true;
3512863Sktlim@umich.edu
3522863Sktlim@umich.edu    return false;
3532316SN/A}
3542316SN/A
3552316SN/Atemplate <class Impl>
3562316SN/Avoid
3572843Sktlim@umich.eduDefaultCommit<Impl>::switchOut()
3582316SN/A{
3592316SN/A    switchedOut = true;
3602843Sktlim@umich.edu    drainPending = false;
3612307SN/A    rob->switchOut();
3622307SN/A}
3632307SN/A
3642307SN/Atemplate <class Impl>
3652307SN/Avoid
3662843Sktlim@umich.eduDefaultCommit<Impl>::resume()
3672843Sktlim@umich.edu{
3682864Sktlim@umich.edu    drainPending = false;
3692843Sktlim@umich.edu}
3702843Sktlim@umich.edu
3712843Sktlim@umich.edutemplate <class Impl>
3722843Sktlim@umich.eduvoid
3732307SN/ADefaultCommit<Impl>::takeOverFrom()
3742307SN/A{
3752316SN/A    switchedOut = false;
3762307SN/A    _status = Active;
3772307SN/A    _nextStatus = Inactive;
3786221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
3796221Snate@binkert.org        commitStatus[tid] = Idle;
3806221Snate@binkert.org        changedROBNumEntries[tid] = false;
3816221Snate@binkert.org        trapSquash[tid] = false;
3826221Snate@binkert.org        tcSquash[tid] = false;
3832307SN/A    }
3842307SN/A    squashCounter = 0;
3852307SN/A    rob->takeOverFrom();
3862307SN/A}
3872307SN/A
3882307SN/Atemplate <class Impl>
3892307SN/Avoid
3902292SN/ADefaultCommit<Impl>::updateStatus()
3912132SN/A{
3922316SN/A    // reset ROB changed variable
3936221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
3946221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
3953867Sbinkertn@umich.edu
3963867Sbinkertn@umich.edu    while (threads != end) {
3976221Snate@binkert.org        ThreadID tid = *threads++;
3983867Sbinkertn@umich.edu
3992316SN/A        changedROBNumEntries[tid] = false;
4002316SN/A
4012316SN/A        // Also check if any of the threads has a trap pending
4022316SN/A        if (commitStatus[tid] == TrapPending ||
4032316SN/A            commitStatus[tid] == FetchTrapPending) {
4042316SN/A            _nextStatus = Active;
4052316SN/A        }
4062292SN/A    }
4072292SN/A
4082292SN/A    if (_nextStatus == Inactive && _status == Active) {
4092292SN/A        DPRINTF(Activity, "Deactivating stage.\n");
4102733Sktlim@umich.edu        cpu->deactivateStage(O3CPU::CommitIdx);
4112292SN/A    } else if (_nextStatus == Active && _status == Inactive) {
4122292SN/A        DPRINTF(Activity, "Activating stage.\n");
4132733Sktlim@umich.edu        cpu->activateStage(O3CPU::CommitIdx);
4142292SN/A    }
4152292SN/A
4162292SN/A    _status = _nextStatus;
4172292SN/A}
4182292SN/A
4192292SN/Atemplate <class Impl>
4202292SN/Avoid
4212292SN/ADefaultCommit<Impl>::setNextStatus()
4222292SN/A{
4232292SN/A    int squashes = 0;
4242292SN/A
4256221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
4266221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
4272292SN/A
4283867Sbinkertn@umich.edu    while (threads != end) {
4296221Snate@binkert.org        ThreadID tid = *threads++;
4302292SN/A
4312292SN/A        if (commitStatus[tid] == ROBSquashing) {
4322292SN/A            squashes++;
4332292SN/A        }
4342292SN/A    }
4352292SN/A
4362702Sktlim@umich.edu    squashCounter = squashes;
4372292SN/A
4382292SN/A    // If commit is currently squashing, then it will have activity for the
4392292SN/A    // next cycle. Set its next status as active.
4402292SN/A    if (squashCounter) {
4412292SN/A        _nextStatus = Active;
4422292SN/A    }
4432292SN/A}
4442292SN/A
4452292SN/Atemplate <class Impl>
4462292SN/Abool
4472292SN/ADefaultCommit<Impl>::changedROBEntries()
4482292SN/A{
4496221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
4506221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
4512292SN/A
4523867Sbinkertn@umich.edu    while (threads != end) {
4536221Snate@binkert.org        ThreadID tid = *threads++;
4542292SN/A
4552292SN/A        if (changedROBNumEntries[tid]) {
4562292SN/A            return true;
4572292SN/A        }
4582292SN/A    }
4592292SN/A
4602292SN/A    return false;
4612292SN/A}
4622292SN/A
4632292SN/Atemplate <class Impl>
4646221Snate@binkert.orgsize_t
4656221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
4662292SN/A{
4672292SN/A    return rob->numFreeEntries(tid);
4682292SN/A}
4692292SN/A
4702292SN/Atemplate <class Impl>
4712292SN/Avoid
4726221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
4732292SN/A{
4742292SN/A    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
4752292SN/A
4762292SN/A    TrapEvent *trap = new TrapEvent(this, tid);
4772292SN/A
4787823Ssteve.reinhardt@amd.com    cpu->schedule(trap, curTick() + trapLatency);
4794035Sktlim@umich.edu    trapInFlight[tid] = true;
4802292SN/A}
4812292SN/A
4822292SN/Atemplate <class Impl>
4832292SN/Avoid
4846221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid)
4852292SN/A{
4864035Sktlim@umich.edu    assert(!trapInFlight[tid]);
4872680Sktlim@umich.edu    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
4882292SN/A
4892680Sktlim@umich.edu    tcSquash[tid] = true;
4902292SN/A}
4912292SN/A
4922292SN/Atemplate <class Impl>
4932292SN/Avoid
4946221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid)
4952292SN/A{
4962292SN/A    // If we want to include the squashing instruction in the squash,
4972292SN/A    // then use one older sequence number.
4982292SN/A    // Hopefully this doesn't mess things up.  Basically I want to squash
4992292SN/A    // all instructions of this thread.
5002292SN/A    InstSeqNum squashed_inst = rob->isEmpty() ?
5014035Sktlim@umich.edu        0 : rob->readHeadInst(tid)->seqNum - 1;
5022292SN/A
5032292SN/A    // All younger instructions will be squashed. Set the sequence
5042292SN/A    // number as the youngest instruction in the ROB (0 in this case.
5052292SN/A    // Hopefully nothing breaks.)
5062292SN/A    youngestSeqNum[tid] = 0;
5072292SN/A
5082292SN/A    rob->squash(squashed_inst, tid);
5092292SN/A    changedROBNumEntries[tid] = true;
5102292SN/A
5112292SN/A    // Send back the sequence number of the squashed instruction.
5122292SN/A    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
5132292SN/A
5142292SN/A    // Send back the squash signal to tell stages that they should
5152292SN/A    // squash.
5162292SN/A    toIEW->commitInfo[tid].squash = true;
5172292SN/A
5182292SN/A    // Send back the rob squashing signal so other stages know that
5192292SN/A    // the ROB is in the process of squashing.
5202292SN/A    toIEW->commitInfo[tid].robSquashing = true;
5212292SN/A
5222292SN/A    toIEW->commitInfo[tid].branchMispredict = false;
5237851SMatt.Horsnell@arm.com
5242292SN/A    toIEW->commitInfo[tid].pc = pc[tid];
5257720Sgblack@eecs.umich.edu}
5262316SN/A
5272292SN/Atemplate <class Impl>
5282316SN/Avoid
5292316SN/ADefaultCommit<Impl>::squashFromTrap(ThreadID tid)
5306221Snate@binkert.org{
5312316SN/A    squashAll(tid);
5322316SN/A
5332316SN/A    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
5347720Sgblack@eecs.umich.edu
5352316SN/A    thread[tid]->trapPending = false;
5362316SN/A    thread[tid]->inSyscall = false;
5372316SN/A    trapInFlight[tid] = false;
5384035Sktlim@umich.edu
5392316SN/A    trapSquash[tid] = false;
5402316SN/A
5412316SN/A    commitStatus[tid] = ROBSquashing;
5422316SN/A    cpu->activityThisCycle();
5432316SN/A}
5442316SN/A
5452316SN/Atemplate <class Impl>
5462316SN/Avoid
5472316SN/ADefaultCommit<Impl>::squashFromTC(ThreadID tid)
5486221Snate@binkert.org{
5492316SN/A    squashAll(tid);
5502316SN/A
5512292SN/A    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
5527720Sgblack@eecs.umich.edu
5532292SN/A    thread[tid]->inSyscall = false;
5542292SN/A    assert(!thread[tid]->trapPending);
5552292SN/A
5562316SN/A    commitStatus[tid] = ROBSquashing;
5572292SN/A    cpu->activityThisCycle();
5582292SN/A
5592292SN/A    tcSquash[tid] = false;
5602680Sktlim@umich.edu}
5612292SN/A
5622292SN/Atemplate <class Impl>
5632292SN/Avoid
5642292SN/ADefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
5657784SAli.Saidi@ARM.com{
5667784SAli.Saidi@ARM.com    youngestSeqNum[tid] = squash_after_seq_num;
5677784SAli.Saidi@ARM.com
5687784SAli.Saidi@ARM.com    rob->squash(squash_after_seq_num, tid);
5697784SAli.Saidi@ARM.com    changedROBNumEntries[tid] = true;
5707784SAli.Saidi@ARM.com
5717784SAli.Saidi@ARM.com    // Send back the sequence number of the squashed instruction.
5727784SAli.Saidi@ARM.com    toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
5737784SAli.Saidi@ARM.com
5747784SAli.Saidi@ARM.com    // Send back the squash signal to tell stages that they should squash.
5757784SAli.Saidi@ARM.com    toIEW->commitInfo[tid].squash = true;
5767784SAli.Saidi@ARM.com
5777784SAli.Saidi@ARM.com    // Send back the rob squashing signal so other stages know that
5787784SAli.Saidi@ARM.com    // the ROB is in the process of squashing.
5797784SAli.Saidi@ARM.com    toIEW->commitInfo[tid].robSquashing = true;
5807784SAli.Saidi@ARM.com
5817784SAli.Saidi@ARM.com    toIEW->commitInfo[tid].branchMispredict = false;
5827784SAli.Saidi@ARM.com
5837784SAli.Saidi@ARM.com    toIEW->commitInfo[tid].pc = pc[tid];
5847784SAli.Saidi@ARM.com    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
5857784SAli.Saidi@ARM.com            tid, squash_after_seq_num);
5867784SAli.Saidi@ARM.com    commitStatus[tid] = ROBSquashing;
5877784SAli.Saidi@ARM.com}
5887784SAli.Saidi@ARM.com
5897784SAli.Saidi@ARM.comtemplate <class Impl>
5907784SAli.Saidi@ARM.comvoid
5917784SAli.Saidi@ARM.comDefaultCommit<Impl>::tick()
5922292SN/A{
5932292SN/A    wroteToTimeBuffer = false;
5942292SN/A    _nextStatus = Inactive;
5952292SN/A
5962292SN/A    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
5972843Sktlim@umich.edu        cpu->signalDrained();
5982843Sktlim@umich.edu        drainPending = false;
5992843Sktlim@umich.edu        return;
6002316SN/A    }
6012316SN/A
6022316SN/A    if (activeThreads->empty())
6033867Sbinkertn@umich.edu        return;
6042875Sksewell@umich.edu
6052875Sksewell@umich.edu    list<ThreadID>::iterator threads = activeThreads->begin();
6066221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
6076221Snate@binkert.org
6082292SN/A    // Check if any of the threads are done squashing.  Change the
6092316SN/A    // status if they are done.
6102316SN/A    while (threads != end) {
6113867Sbinkertn@umich.edu        ThreadID tid = *threads++;
6126221Snate@binkert.org
6132292SN/A        // Clear the bit saying if the thread has committed stores
6144035Sktlim@umich.edu        // this cycle.
6154035Sktlim@umich.edu        committedStores[tid] = false;
6164035Sktlim@umich.edu
6174035Sktlim@umich.edu        if (commitStatus[tid] == ROBSquashing) {
6182292SN/A
6192292SN/A            if (rob->isDoneSquashing(tid)) {
6202292SN/A                commitStatus[tid] = Running;
6212292SN/A            } else {
6222292SN/A                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
6232292SN/A                        " insts this cycle.\n", tid);
6242877Sksewell@umich.edu                rob->doSquash(tid);
6252702Sktlim@umich.edu                toIEW->commitInfo[tid].robSquashing = true;
6262702Sktlim@umich.edu                wroteToTimeBuffer = true;
6272702Sktlim@umich.edu            }
6282292SN/A        }
6292292SN/A    }
6302292SN/A
6312292SN/A    commit();
6322292SN/A
6332292SN/A    markCompletedInsts();
6342292SN/A
6352292SN/A    threads = activeThreads->begin();
6363867Sbinkertn@umich.edu
6372292SN/A    while (threads != end) {
6383867Sbinkertn@umich.edu        ThreadID tid = *threads++;
6396221Snate@binkert.org
6402292SN/A        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
6412292SN/A            // The ROB has more instructions it can commit. Its next status
6422292SN/A            // will be active.
6432292SN/A            _nextStatus = Active;
6442292SN/A
6452292SN/A            DynInstPtr inst = rob->readHeadInst(tid);
6462292SN/A
6472292SN/A            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
6487720Sgblack@eecs.umich.edu                    " ROB and ready to commit\n",
6492292SN/A                    tid, inst->seqNum, inst->pcState());
6507720Sgblack@eecs.umich.edu
6512292SN/A        } else if (!rob->isEmpty(tid)) {
6522292SN/A            DynInstPtr inst = rob->readHeadInst(tid);
6532292SN/A
6542292SN/A            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
6552292SN/A                    "%s is head of ROB and not ready\n",
6567720Sgblack@eecs.umich.edu                    tid, inst->seqNum, inst->pcState());
6577720Sgblack@eecs.umich.edu        }
6582292SN/A
6592292SN/A        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
6602292SN/A                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
6612292SN/A    }
6622292SN/A
6632292SN/A
6642292SN/A    if (wroteToTimeBuffer) {
6652292SN/A        DPRINTF(Activity, "Activity This Cycle.\n");
6662316SN/A        cpu->activityThisCycle();
6672292SN/A    }
6682292SN/A
6692292SN/A    updateStatus();
6702292SN/A}
6712292SN/A
6722292SN/A#if FULL_SYSTEM
6734035Sktlim@umich.edutemplate <class Impl>
6742292SN/Avoid
6752292SN/ADefaultCommit<Impl>::handleInterrupt()
6764035Sktlim@umich.edu{
6772292SN/A    if (interrupt != NoFault) {
6787847Sminkyu.jeong@arm.com        // Wait until the ROB is empty and all stores have drained in
6797847Sminkyu.jeong@arm.com        // order to enter the interrupt.
6807847Sminkyu.jeong@arm.com        if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
6817847Sminkyu.jeong@arm.com            // Squash or record that I need to squash this cycle if
6827847Sminkyu.jeong@arm.com            // an interrupt needed to be handled.
6837847Sminkyu.jeong@arm.com            DPRINTF(Commit, "Interrupt detected.\n");
6847847Sminkyu.jeong@arm.com
6857847Sminkyu.jeong@arm.com            // Clear the interrupt now that it's going to be handled
6863633Sktlim@umich.edu            toIEW->commitInfo[0].clearInterrupt = true;
6877847Sminkyu.jeong@arm.com
6887847Sminkyu.jeong@arm.com            assert(!thread[0]->inSyscall);
6897847Sminkyu.jeong@arm.com            thread[0]->inSyscall = true;
6907847Sminkyu.jeong@arm.com
6917847Sminkyu.jeong@arm.com            // CPU will handle interrupt.
6927847Sminkyu.jeong@arm.com            cpu->processInterrupts(interrupt);
6934035Sktlim@umich.edu
6947847Sminkyu.jeong@arm.com            thread[0]->inSyscall = false;
6957847Sminkyu.jeong@arm.com
6962292SN/A            commitStatus[0] = TrapPending;
6977847Sminkyu.jeong@arm.com
6987847Sminkyu.jeong@arm.com            // Generate trap squash event.
6992292SN/A            generateTrapEvent(0);
7007847Sminkyu.jeong@arm.com
7017847Sminkyu.jeong@arm.com            interrupt = NoFault;
7023633Sktlim@umich.edu        } else {
7037847Sminkyu.jeong@arm.com            DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
7042292SN/A        }
7057847Sminkyu.jeong@arm.com    } else if (commitStatus[0] != TrapPending &&
7062292SN/A               cpu->checkInterrupts(cpu->tcBase(0)) &&
7077847Sminkyu.jeong@arm.com               !trapSquash[0] &&
7087847Sminkyu.jeong@arm.com               !tcSquash[0]) {
7093640Sktlim@umich.edu        // Process interrupts if interrupts are enabled, not in PAL
7107847Sminkyu.jeong@arm.com        // mode, and no other traps or external squashes are currently
7117847Sminkyu.jeong@arm.com        // pending.
7127847Sminkyu.jeong@arm.com        // @todo: Allow other threads to handle interrupts.
7131060SN/A
7144035Sktlim@umich.edu        // Get any interrupt that happened
7157847Sminkyu.jeong@arm.com        interrupt = cpu->getInterrupts();
7167847Sminkyu.jeong@arm.com
7177847Sminkyu.jeong@arm.com        if (interrupt != NoFault) {
7187847Sminkyu.jeong@arm.com            // Tell fetch that there is an interrupt pending.  This
7197847Sminkyu.jeong@arm.com            // will make fetch wait until it sees a non PAL-mode PC,
7207847Sminkyu.jeong@arm.com            // at which point it stops fetching instructions.
7217847Sminkyu.jeong@arm.com            toIEW->commitInfo[0].interruptPending = true;
7227847Sminkyu.jeong@arm.com        }
7237847Sminkyu.jeong@arm.com    }
7247847Sminkyu.jeong@arm.com}
7257847Sminkyu.jeong@arm.com#endif // FULL_SYSTEM
7267847Sminkyu.jeong@arm.com
7277847Sminkyu.jeong@arm.comtemplate <class Impl>
7287847Sminkyu.jeong@arm.comvoid
7297847Sminkyu.jeong@arm.comDefaultCommit<Impl>::commit()
7307847Sminkyu.jeong@arm.com{
7317847Sminkyu.jeong@arm.com
7327847Sminkyu.jeong@arm.com#if FULL_SYSTEM
7337847Sminkyu.jeong@arm.com    // Check for any interrupt, and start processing it.  Or if we
7347847Sminkyu.jeong@arm.com    // have an outstanding interrupt and are at a point when it is
7357847Sminkyu.jeong@arm.com    // valid to take an interrupt, process it.
7367847Sminkyu.jeong@arm.com    if (cpu->checkInterrupts(cpu->tcBase(0))) {
7377847Sminkyu.jeong@arm.com        handleInterrupt();
7387847Sminkyu.jeong@arm.com    }
7394035Sktlim@umich.edu#endif // FULL_SYSTEM
7403634Sktlim@umich.edu
7414035Sktlim@umich.edu    ////////////////////////////////////
7424035Sktlim@umich.edu    // Check for any possible squashes, handle them first
7434035Sktlim@umich.edu    ////////////////////////////////////
7444035Sktlim@umich.edu    list<ThreadID>::iterator threads = activeThreads->begin();
7454035Sktlim@umich.edu    list<ThreadID>::iterator end = activeThreads->end();
7464035Sktlim@umich.edu
7477847Sminkyu.jeong@arm.com    while (threads != end) {
7487847Sminkyu.jeong@arm.com        ThreadID tid = *threads++;
7494035Sktlim@umich.edu
7507847Sminkyu.jeong@arm.com        // Not sure which one takes priority.  I think if we have
7517847Sminkyu.jeong@arm.com        // both, that's a bad sign.
7527847Sminkyu.jeong@arm.com        if (trapSquash[tid] == true) {
7537847Sminkyu.jeong@arm.com            assert(!tcSquash[tid]);
7541060SN/A            squashFromTrap(tid);
7551060SN/A        } else if (tcSquash[tid] == true) {
7561060SN/A            assert(commitStatus[tid] != TrapPending);
7572316SN/A            squashFromTC(tid);
7581060SN/A        }
7596221Snate@binkert.org
7606221Snate@binkert.org        // Squashed sequence number must be older than youngest valid
7611060SN/A        // instruction in the ROB. This prevents squashes from younger
7623867Sbinkertn@umich.edu        // instructions overriding squashes from older instructions.
7636221Snate@binkert.org        if (fromIEW->squash[tid] &&
7641060SN/A            commitStatus[tid] != TrapPending &&
7652292SN/A            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
7662292SN/A
7672292SN/A            DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
7682680Sktlim@umich.edu                    tid,
7692292SN/A                    fromIEW->mispredPC[tid],
7702680Sktlim@umich.edu                    fromIEW->squashedSeqNum[tid]);
7714035Sktlim@umich.edu
7722680Sktlim@umich.edu            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
7732292SN/A                    tid,
7741061SN/A                    fromIEW->pc[tid].nextInstAddr());
7752292SN/A
7762292SN/A            commitStatus[tid] = ROBSquashing;
7772292SN/A
7782292SN/A            // If we want to include the squashing instruction in the squash,
7792292SN/A            // then use one older sequence number.
7802292SN/A            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
7811061SN/A
7822292SN/A            if (fromIEW->includeSquashInst[tid] == true) {
7832292SN/A                squashed_inst--;
7842292SN/A            }
7852292SN/A
7861061SN/A            // All younger instructions will be squashed. Set the sequence
7872292SN/A            // number as the youngest instruction in the ROB.
7882292SN/A            youngestSeqNum[tid] = squashed_inst;
7897720Sgblack@eecs.umich.edu
7901061SN/A            rob->squash(squashed_inst, tid);
7912292SN/A            changedROBNumEntries[tid] = true;
7921061SN/A
7932292SN/A            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
7942292SN/A
7952292SN/A            toIEW->commitInfo[tid].squash = true;
7961062SN/A
7972935Sksewell@umich.edu            // Send back the rob squashing signal so other stages know that
7982292SN/A            // the ROB is in the process of squashing.
7992935Sksewell@umich.edu            toIEW->commitInfo[tid].robSquashing = true;
8004035Sktlim@umich.edu
8012292SN/A            toIEW->commitInfo[tid].branchMispredict =
8022292SN/A                fromIEW->branchMispredict[tid];
8032292SN/A
8042292SN/A            toIEW->commitInfo[tid].branchTaken =
8053093Sksewell@umich.edu                fromIEW->branchTaken[tid];
8062292SN/A
8072292SN/A            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
8082292SN/A
8092292SN/A            toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
8102292SN/A
8112292SN/A            if (toIEW->commitInfo[tid].branchMispredict) {
8122292SN/A                ++branchMispredicts;
8132292SN/A            }
8142292SN/A        }
8152292SN/A
8162292SN/A    }
8172292SN/A
8187851SMatt.Horsnell@arm.com    setNextStatus();
8197851SMatt.Horsnell@arm.com
8202292SN/A    if (squashCounter != numThreads) {
8212292SN/A        // If we're not currently squashing, then get instructions.
8222292SN/A        getInsts();
8237720Sgblack@eecs.umich.edu
8242292SN/A        // Try to commit any instructions.
8252316SN/A        commitInsts();
8262292SN/A    }
8272292SN/A
8282292SN/A    //Check for any activity
8292292SN/A    threads = activeThreads->begin();
8301062SN/A
8312292SN/A    while (threads != end) {
8321060SN/A        ThreadID tid = *threads++;
8331060SN/A
8342292SN/A        if (changedROBNumEntries[tid]) {
8352292SN/A            toIEW->commitInfo[tid].usedROB = true;
8362292SN/A            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
8371061SN/A
8381060SN/A            wroteToTimeBuffer = true;
8391060SN/A            changedROBNumEntries[tid] = false;
8401061SN/A            if (rob->isEmpty(tid))
8411060SN/A                checkEmptyROB[tid] = true;
8421060SN/A        }
8431060SN/A
8442292SN/A        // ROB is only considered "empty" for previous stages if: a)
8453867Sbinkertn@umich.edu        // ROB is empty, b) there are no outstanding stores, c) IEW
8462292SN/A        // stage has received any information regarding stores that
8473867Sbinkertn@umich.edu        // committed.
8486221Snate@binkert.org        // c) is checked by making sure to not consider the ROB empty
8492292SN/A        // on the same cycle as when stores have been committed.
8502292SN/A        // @todo: Make this handle multi-cycle communication between
8512292SN/A        // commit and IEW.
8522292SN/A        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
8532292SN/A            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
8542292SN/A            checkEmptyROB[tid] = false;
8552292SN/A            toIEW->commitInfo[tid].usedROB = true;
8564035Sktlim@umich.edu            toIEW->commitInfo[tid].emptyROB = true;
8574035Sktlim@umich.edu            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
8582292SN/A            wroteToTimeBuffer = true;
8594035Sktlim@umich.edu        }
8604035Sktlim@umich.edu
8614035Sktlim@umich.edu    }
8624035Sktlim@umich.edu}
8634035Sktlim@umich.edu
8644035Sktlim@umich.edutemplate <class Impl>
8654035Sktlim@umich.eduvoid
8664035Sktlim@umich.eduDefaultCommit<Impl>::commitInsts()
8674035Sktlim@umich.edu{
8684035Sktlim@umich.edu    ////////////////////////////////////
8695557Sktlim@umich.edu    // Handle commit
8704035Sktlim@umich.edu    // Note that commit will be handled prior to putting new
8714035Sktlim@umich.edu    // instructions in the ROB so that the ROB only tries to commit
8724035Sktlim@umich.edu    // instructions it has in this current cycle, and not instructions
8734035Sktlim@umich.edu    // it is writing in during this cycle.  Can't commit and squash
8744035Sktlim@umich.edu    // things at the same time...
8754035Sktlim@umich.edu    ////////////////////////////////////
8764035Sktlim@umich.edu
8771060SN/A    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
8781060SN/A
8791060SN/A    unsigned num_committed = 0;
8801061SN/A
8811060SN/A    DynInstPtr head_inst;
8822292SN/A
8831060SN/A    // Commit as many instructions as possible until the commit bandwidth
8841060SN/A    // limit is reached, or it becomes impossible to commit any more.
8851060SN/A    while (num_committed < commitWidth) {
8862316SN/A        int commit_thread = getCommittingThread();
8872316SN/A
8882316SN/A        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
8892316SN/A            break;
8902316SN/A
8911060SN/A        head_inst = rob->readHeadInst(commit_thread);
8921060SN/A
8932292SN/A        ThreadID tid = head_inst->threadNumber;
8941060SN/A
8951060SN/A        assert(tid == commit_thread);
8961060SN/A
8972292SN/A        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
8982316SN/A                head_inst->seqNum, tid);
8991060SN/A
9001060SN/A        // If the head instruction is squashed, it is ready to retire
9012292SN/A        // (be removed from the ROB) at any time.
9022292SN/A        if (head_inst->isSquashed()) {
9031060SN/A
9042292SN/A            DPRINTF(Commit, "Retiring squashed instruction from "
9052292SN/A                    "ROB.\n");
9062292SN/A
9072292SN/A            rob->retireHead(commit_thread);
9082292SN/A
9096221Snate@binkert.org            ++commitSquashedInsts;
9102292SN/A
9112292SN/A            // Record that the number of ROB entries has changed.
9122292SN/A            changedROBNumEntries[tid] = true;
9132292SN/A        } else {
9142292SN/A            pc[tid] = head_inst->pcState();
9152132SN/A
9162316SN/A            // Increment the total number of non-speculative instructions
9172316SN/A            // executed.
9181060SN/A            // Hack for now: it really shouldn't happen until after the
9191060SN/A            // commit is deemed to be successful, but this count is needed
9202292SN/A            // for syscalls.
9211060SN/A            thread[tid]->funcExeInst++;
9221060SN/A
9232292SN/A            // Try to commit the head instruction.
9241060SN/A            bool commit_success = commitHead(head_inst, num_committed);
9251062SN/A
9261062SN/A            if (commit_success) {
9272292SN/A                ++num_committed;
9282292SN/A
9291060SN/A                changedROBNumEntries[tid] = true;
9307720Sgblack@eecs.umich.edu
9312292SN/A                // Set the doneSeqNum to the youngest committed instruction.
9321060SN/A                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
9331060SN/A
9341060SN/A                ++commitCommittedInsts;
9351061SN/A
9361061SN/A                // To match the old model, don't count nops and instruction
9372292SN/A                // prefetches towards the total commit count.
9381060SN/A                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
9391060SN/A                    cpu->instDone(tid);
9401060SN/A                }
9411060SN/A
9421062SN/A                // Updates misc. registers.
9431060SN/A                head_inst->updateMiscRegs();
9441060SN/A
9452292SN/A                TheISA::advancePC(pc[tid], head_inst->staticInst);
9462292SN/A
9472292SN/A                // If this is an instruction that doesn't play nicely with
9482292SN/A                // others squash everything and restart fetch
9491060SN/A                if (head_inst->isSquashAfter())
9501062SN/A                    squashAfter(tid, head_inst->seqNum);
9511062SN/A
9522292SN/A                int count = 0;
9532292SN/A                Addr oldpc;
9542292SN/A                // Debug statement.  Checks to make sure we're not
9552292SN/A                // currently updating state while handling PC events.
9561062SN/A                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
9572292SN/A                do {
9587783SGiacomo.Gabrielli@arm.com                    oldpc = pc[tid].instAddr();
9597783SGiacomo.Gabrielli@arm.com                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
9607783SGiacomo.Gabrielli@arm.com                    count++;
9617720Sgblack@eecs.umich.edu                } while (oldpc != pc[tid].instAddr());
9622935Sksewell@umich.edu                if (count > 1) {
9637784SAli.Saidi@ARM.com                    DPRINTF(Commit,
9647784SAli.Saidi@ARM.com                            "PC skip function event, stopping commit\n");
9657784SAli.Saidi@ARM.com                    break;
9667784SAli.Saidi@ARM.com                }
9677784SAli.Saidi@ARM.com            } else {
9682292SN/A                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
9692292SN/A                        "[tid:%i] [sn:%i].\n",
9705108Sgblack@eecs.umich.edu                        head_inst->pcState(), tid ,head_inst->seqNum);
9715108Sgblack@eecs.umich.edu                break;
9725108Sgblack@eecs.umich.edu            }
9732292SN/A        }
9747720Sgblack@eecs.umich.edu    }
9755108Sgblack@eecs.umich.edu
9762292SN/A    DPRINTF(CommitRate, "%i\n", num_committed);
9777720Sgblack@eecs.umich.edu    numCommittedDist.sample(num_committed);
9782292SN/A
9795108Sgblack@eecs.umich.edu    if (num_committed == commitWidth) {
9805108Sgblack@eecs.umich.edu        commitEligibleSamples++;
9812292SN/A    }
9822292SN/A}
9831060SN/A
9847720Sgblack@eecs.umich.edutemplate <class Impl>
9852292SN/Abool
9867720Sgblack@eecs.umich.eduDefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
9871060SN/A{
9881060SN/A    assert(head_inst);
9891060SN/A
9901060SN/A    ThreadID tid = head_inst->threadNumber;
9911062SN/A
9921063SN/A    // If the instruction is not executed yet, then it will need extra
9932292SN/A    // handling.  Signal backwards that it should be executed.
9942307SN/A    if (!head_inst->isExecuted()) {
9952307SN/A        // Keep this number correct.  We have not yet actually executed
9962349SN/A        // and committed this instruction.
9972307SN/A        thread[tid]->funcExeInst--;
9981060SN/A
9991060SN/A        if (head_inst->isNonSpeculative() ||
10001061SN/A            head_inst->isStoreConditional() ||
10011060SN/A            head_inst->isMemBarrier() ||
10022292SN/A            head_inst->isWriteBarrier()) {
10031060SN/A
10041060SN/A            DPRINTF(Commit, "Encountered a barrier or non-speculative "
10051060SN/A                    "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
10066221Snate@binkert.org                    head_inst->seqNum, head_inst->pcState());
10072292SN/A
10082316SN/A            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
10092316SN/A                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
10101061SN/A                return false;
10111061SN/A            }
10121061SN/A
10132292SN/A            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
10141062SN/A
10152292SN/A            // Change the instruction so it won't try to commit again until
10162348SN/A            // it is executed.
10172292SN/A            head_inst->clearCanCommit();
10182292SN/A
10192316SN/A            ++commitNonSpecStalls;
10202316SN/A
10217720Sgblack@eecs.umich.edu            return false;
10227720Sgblack@eecs.umich.edu        } else if (head_inst->isLoad()) {
10232316SN/A            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
10245557Sktlim@umich.edu                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
10252292SN/A                return false;
10262292SN/A            }
10272292SN/A
10282292SN/A            assert(head_inst->uncacheable());
10292292SN/A            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
10301061SN/A                    head_inst->seqNum, head_inst->pcState());
10311061SN/A
10321061SN/A            // Send back the non-speculative instruction's sequence
10331061SN/A            // number.  Tell the lsq to re-execute the load.
10341061SN/A            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
10351062SN/A            toIEW->commitInfo[tid].uncached = true;
10361062SN/A            toIEW->commitInfo[tid].uncachedLoad = head_inst;
10371061SN/A
10382292SN/A            head_inst->clearCanCommit();
10395557Sktlim@umich.edu
10404035Sktlim@umich.edu            return false;
10414035Sktlim@umich.edu        } else {
10424035Sktlim@umich.edu            panic("Trying to commit un-executed instruction "
10434035Sktlim@umich.edu                  "of unknown type!\n");
10444035Sktlim@umich.edu        }
10457720Sgblack@eecs.umich.edu    }
10467720Sgblack@eecs.umich.edu
10472292SN/A    if (head_inst->isThreadSync()) {
10482292SN/A        // Not handled for now.
10492316SN/A        panic("Thread sync instructions are not handled yet.\n");
10502292SN/A    }
10512292SN/A
10522292SN/A    // Check if the instruction caused a fault.  If so, trap.
10532292SN/A    Fault inst_fault = head_inst->getFault();
10542292SN/A
10552292SN/A    // Stores mark themselves as completed.
10562292SN/A    if (!head_inst->isStore() && inst_fault == NoFault) {
10571061SN/A        head_inst->setCompleted();
10582292SN/A    }
10591061SN/A
10601061SN/A#if USE_CHECKER
10611060SN/A    // Use checker prior to updating anything due to traps or PC
10621060SN/A    // based events.
10632316SN/A    if (cpu->checker) {
10642292SN/A        cpu->checker->verify(head_inst);
10652316SN/A    }
10662132SN/A#endif
10672132SN/A
10684035Sktlim@umich.edu    if (inst_fault != NoFault) {
10694035Sktlim@umich.edu        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
10704035Sktlim@umich.edu                head_inst->seqNum, head_inst->pcState());
10712316SN/A
10724035Sktlim@umich.edu        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
10732310SN/A            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
10742310SN/A            return false;
10752310SN/A        }
10762733Sktlim@umich.edu
10772316SN/A        head_inst->setCompleted();
10782316SN/A
10792316SN/A#if USE_CHECKER
10802732Sktlim@umich.edu        if (cpu->checker && head_inst->isStore()) {
10811060SN/A            cpu->checker->verify(head_inst);
10822733Sktlim@umich.edu        }
10831060SN/A#endif
10842112SN/A
10857720Sgblack@eecs.umich.edu        assert(!thread[tid]->inSyscall);
10867720Sgblack@eecs.umich.edu
10872292SN/A        // Mark that we're in state update mode so that the trap's
10885557Sktlim@umich.edu        // execution doesn't generate extra squashes.
10892316SN/A        thread[tid]->inSyscall = true;
10902316SN/A
10912316SN/A        // Execute the trap.  Although it's slightly unrealistic in
10922310SN/A        // terms of timing (as it doesn't wait for the full timing of
10934035Sktlim@umich.edu        // the trap event to complete before updating state), it's
10944035Sktlim@umich.edu        // needed to update the state as soon as possible.  This
10952733Sktlim@umich.edu        // prevents external agents from changing any specific state
10962316SN/A        // that the trap need.
10972732Sktlim@umich.edu        cpu->trap(inst_fault, tid, head_inst->staticInst);
10982316SN/A
10992733Sktlim@umich.edu        // Exit state update mode to avoid accidental updating.
11002292SN/A        thread[tid]->inSyscall = false;
11012316SN/A
11022292SN/A        commitStatus[tid] = TrapPending;
11032316SN/A
11042316SN/A        if (head_inst->traceData) {
11052316SN/A            if (DTRACE(ExecFaulting)) {
11062292SN/A                head_inst->traceData->setFetchSeq(head_inst->seqNum);
11072316SN/A                head_inst->traceData->setCPSeq(thread[tid]->numInst);
11082316SN/A                head_inst->traceData->dump();
11092316SN/A            }
11102316SN/A            delete head_inst->traceData;
11112316SN/A            head_inst->traceData = NULL;
11122316SN/A        }
11137684Sgblack@eecs.umich.edu
11142292SN/A        // Generate trap squash event.
11152316SN/A        generateTrapEvent(tid);
11162316SN/A        return false;
11172292SN/A    }
11182316SN/A
11192292SN/A    updateComInstStats(head_inst);
11204035Sktlim@umich.edu
11216667Ssteve.reinhardt@amd.com#if FULL_SYSTEM
11226667Ssteve.reinhardt@amd.com    if (thread[tid]->profile) {
11236667Ssteve.reinhardt@amd.com        thread[tid]->profilePC = head_inst->instAddr();
11246667Ssteve.reinhardt@amd.com        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
11256667Ssteve.reinhardt@amd.com                                                          head_inst->staticInst);
11264288Sktlim@umich.edu
11274035Sktlim@umich.edu        if (node)
11284035Sktlim@umich.edu            thread[tid]->profileNode = node;
11294035Sktlim@umich.edu    }
11302316SN/A    if (CPA::available()) {
11312316SN/A        if (head_inst->isControl()) {
11322316SN/A            ThreadContext *tc = thread[tid]->getTC();
11331060SN/A            CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
11341060SN/A        }
11352301SN/A    }
11362132SN/A#endif
11372362SN/A
11382362SN/A    if (head_inst->traceData) {
11397720Sgblack@eecs.umich.edu        head_inst->traceData->setFetchSeq(head_inst->seqNum);
11403126Sktlim@umich.edu        head_inst->traceData->setCPSeq(thread[tid]->numInst);
11412362SN/A        head_inst->traceData->dump();
11422362SN/A        delete head_inst->traceData;
11432362SN/A        head_inst->traceData = NULL;
11442362SN/A    }
11452362SN/A
11465953Ssaidi@eecs.umich.edu    // Update the commit rename map
11475953Ssaidi@eecs.umich.edu    for (int i = 0; i < head_inst->numDestRegs(); i++) {
11485953Ssaidi@eecs.umich.edu        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
11497720Sgblack@eecs.umich.edu                                 head_inst->renamedDestRegIdx(i));
11505953Ssaidi@eecs.umich.edu    }
11515953Ssaidi@eecs.umich.edu
11522362SN/A    if (head_inst->isCopy())
11532362SN/A        panic("Should not commit any copy instructions!");
11542132SN/A
11552292SN/A    // Finally clear the head ROB entry.
11562292SN/A    rob->retireHead(tid);
11574046Sbinkertn@umich.edu
11584046Sbinkertn@umich.edu    // If this was a store, record it for this cycle.
11592292SN/A    if (head_inst->isStore())
11601060SN/A        committedStores[tid] = true;
11611060SN/A
11622292SN/A    // Return true to indicate that we have committed an instruction.
11632292SN/A    return true;
11643771Sgblack@eecs.umich.edu}
11652292SN/A
11661060SN/Atemplate <class Impl>
11671062SN/Avoid
11682353SN/ADefaultCommit<Impl>::getInsts()
11692353SN/A{
11702353SN/A    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
11712292SN/A
11722292SN/A    // Read any renamed instructions and place them into the ROB.
11731060SN/A    int insts_to_process = std::min((int)renameWidth, fromRename->size);
11744035Sktlim@umich.edu
11754035Sktlim@umich.edu    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
11764035Sktlim@umich.edu        DynInstPtr inst;
11774035Sktlim@umich.edu
11781060SN/A        inst = fromRename->insts[inst_num];
11791060SN/A        ThreadID tid = inst->threadNumber;
11801060SN/A
11811060SN/A        if (!inst->isSquashed() &&
11821061SN/A            commitStatus[tid] != ROBSquashing &&
11831060SN/A            commitStatus[tid] != TrapPending) {
11842292SN/A            changedROBNumEntries[tid] = true;
11851060SN/A
11862935Sksewell@umich.edu            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
11872935Sksewell@umich.edu                    inst->pcState(), inst->seqNum, tid);
11883093Sksewell@umich.edu
11893093Sksewell@umich.edu            rob->insertInst(inst);
11902965Sksewell@umich.edu
11912965Sksewell@umich.edu            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
11922965Sksewell@umich.edu
11932965Sksewell@umich.edu            youngestSeqNum[tid] = inst->seqNum;
11943093Sksewell@umich.edu        } else {
11956221Snate@binkert.org            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
11962292SN/A                    "squashed, skipping.\n",
11972292SN/A                    inst->pcState(), inst->seqNum, tid);
11984035Sktlim@umich.edu        }
11994035Sktlim@umich.edu    }
12002292SN/A}
12012292SN/A
12027720Sgblack@eecs.umich.edutemplate <class Impl>
12037720Sgblack@eecs.umich.eduvoid
12042292SN/ADefaultCommit<Impl>::skidInsert()
12052292SN/A{
12062292SN/A    DPRINTF(Commit, "Attempting to any instructions from rename into "
12072292SN/A            "skidBuffer.\n");
12082292SN/A
12092292SN/A    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
12101061SN/A        DynInstPtr inst = fromRename->insts[inst_num];
12117720Sgblack@eecs.umich.edu
12121061SN/A        if (!inst->isSquashed()) {
12137720Sgblack@eecs.umich.edu            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
12141061SN/A                    "skidBuffer.\n", inst->pcState(), inst->seqNum,
12151060SN/A                    inst->threadNumber);
12162965Sksewell@umich.edu            skidBuffer.push(inst);
12172965Sksewell@umich.edu        } else {
12182965Sksewell@umich.edu            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
12192965Sksewell@umich.edu                    "squashed, skipping.\n",
12202965Sksewell@umich.edu                    inst->pcState(), inst->seqNum, inst->threadNumber);
12212965Sksewell@umich.edu        }
12222965Sksewell@umich.edu    }
12232965Sksewell@umich.edu}
12242965Sksewell@umich.edu
12252965Sksewell@umich.edutemplate <class Impl>
12262965Sksewell@umich.eduvoid
12272965Sksewell@umich.eduDefaultCommit<Impl>::markCompletedInsts()
12282965Sksewell@umich.edu{
12297720Sgblack@eecs.umich.edu    // Grab completed insts out of the IEW instruction queue, and mark
12307720Sgblack@eecs.umich.edu    // instructions completed within the ROB.
12313221Sktlim@umich.edu    for (int inst_num = 0;
12322965Sksewell@umich.edu         inst_num < fromIEW->size && fromIEW->insts[inst_num];
12332965Sksewell@umich.edu         ++inst_num)
12347720Sgblack@eecs.umich.edu    {
12352965Sksewell@umich.edu        if (!fromIEW->insts[inst_num]->isSquashed()) {
12367720Sgblack@eecs.umich.edu            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
12372965Sksewell@umich.edu                    "within ROB.\n",
12382965Sksewell@umich.edu                    fromIEW->insts[inst_num]->threadNumber,
12391060SN/A                    fromIEW->insts[inst_num]->pcState(),
12401060SN/A                    fromIEW->insts[inst_num]->seqNum);
12411061SN/A
12421060SN/A            // Mark the instruction as ready to commit.
12432292SN/A            fromIEW->insts[inst_num]->setCanCommit();
12441060SN/A        }
12451060SN/A    }
12461060SN/A}
12471060SN/A
12481681SN/Atemplate <class Impl>
12491060SN/Abool
12501060SN/ADefaultCommit<Impl>::robDoneSquashing()
12512292SN/A{
12527720Sgblack@eecs.umich.edu    list<ThreadID>::iterator threads = activeThreads->begin();
12532316SN/A    list<ThreadID>::iterator end = activeThreads->end();
12542292SN/A
12557720Sgblack@eecs.umich.edu    while (threads != end) {
12562292SN/A        ThreadID tid = *threads++;
12571060SN/A
12582292SN/A        if (!rob->isDoneSquashing(tid))
12592292SN/A            return false;
12602292SN/A    }
12611060SN/A
12621060SN/A    return true;
12631060SN/A}
12641061SN/A
12652292SN/Atemplate <class Impl>
12662292SN/Avoid
12671060SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
12686221Snate@binkert.org{
12696221Snate@binkert.org    ThreadID tid = inst->threadNumber;
12702292SN/A
12713867Sbinkertn@umich.edu    //
12726221Snate@binkert.org    //  Pick off the software prefetches
12732292SN/A    //
12742292SN/A#ifdef TARGET_ALPHA
12752292SN/A    if (inst->isDataPrefetch()) {
12762292SN/A        statComSwp[tid]++;
12772292SN/A    } else {
12782292SN/A        statComInst[tid]++;
12791060SN/A    }
12802292SN/A#else
12812301SN/A    statComInst[tid]++;
12822301SN/A#endif
12832301SN/A
12842301SN/A    //
12856221Snate@binkert.org    //  Control Instructions
12862301SN/A    //
12872301SN/A    if (inst->isControl())
12882301SN/A        statComBranches[tid]++;
12892301SN/A
12902301SN/A    //
12912301SN/A    //  Memory references
12926221Snate@binkert.org    //
12932301SN/A    if (inst->isMemRef()) {
12946221Snate@binkert.org        statComRefs[tid]++;
12952301SN/A
12962301SN/A        if (inst->isLoad()) {
12976221Snate@binkert.org            statComLoads[tid]++;
12982301SN/A        }
12992301SN/A    }
13002301SN/A
13012301SN/A    if (inst->isMemBarrier()) {
13022301SN/A        statComMembars[tid]++;
13032301SN/A    }
13046221Snate@binkert.org}
13052301SN/A
13062301SN/A////////////////////////////////////////
13072301SN/A//                                    //
13082301SN/A//  SMT COMMIT POLICY MAINTAINED HERE //
13092301SN/A//                                    //
13106221Snate@binkert.org////////////////////////////////////////
13112301SN/Atemplate <class Impl>
13122301SN/AThreadID
13136221Snate@binkert.orgDefaultCommit<Impl>::getCommittingThread()
13142301SN/A{
13152301SN/A    if (numThreads > 1) {
13162301SN/A        switch (commitPolicy) {
13172301SN/A
13186221Snate@binkert.org          case Aggressive:
13192301SN/A            //If Policy is Aggressive, commit will call
13202301SN/A            //this function multiple times per
13212301SN/A            //cycle
13222292SN/A            return oldestReady();
13232292SN/A
13242316SN/A          case RoundRobin:
13252292SN/A            return roundRobin();
13262292SN/A
13272292SN/A          case OldestReady:
13286221Snate@binkert.org            return oldestReady();
13292292SN/A
13302292SN/A          default:
13312292SN/A            return InvalidThreadID;
13322292SN/A        }
13332292SN/A    } else {
13342292SN/A        assert(!activeThreads->empty());
13352292SN/A        ThreadID tid = activeThreads->front();
13362292SN/A
13372292SN/A        if (commitStatus[tid] == Running ||
13382292SN/A            commitStatus[tid] == Idle ||
13392292SN/A            commitStatus[tid] == FetchTrapPending) {
13402292SN/A            return tid;
13412292SN/A        } else {
13422292SN/A            return InvalidThreadID;
13432292SN/A        }
13442292SN/A    }
13452292SN/A}
13462292SN/A
13476221Snate@binkert.orgtemplate<class Impl>
13482292SN/AThreadID
13492292SN/ADefaultCommit<Impl>::roundRobin()
13503867Sbinkertn@umich.edu{
13516221Snate@binkert.org    list<ThreadID>::iterator pri_iter = priority_list.begin();
13522292SN/A    list<ThreadID>::iterator end      = priority_list.end();
13532292SN/A
13542292SN/A    while (pri_iter != end) {
13552292SN/A        ThreadID tid = *pri_iter;
13562292SN/A
13572292SN/A        if (commitStatus[tid] == Running ||
13586221Snate@binkert.org            commitStatus[tid] == Idle ||
13592292SN/A            commitStatus[tid] == FetchTrapPending) {
13602292SN/A
13612292SN/A            if (rob->isHeadReady(tid)) {
13622292SN/A                priority_list.erase(pri_iter);
13632292SN/A                priority_list.push_back(tid);
13646221Snate@binkert.org
13652292SN/A                return tid;
13662292SN/A            }
13676221Snate@binkert.org        }
13686221Snate@binkert.org
13692292SN/A        pri_iter++;
13702292SN/A    }
13716221Snate@binkert.org
13722292SN/A    return InvalidThreadID;
13732292SN/A}
13742831Sksewell@umich.edu
13752831Sksewell@umich.edutemplate<class Impl>
13762292SN/AThreadID
13772292SN/ADefaultCommit<Impl>::oldestReady()
13782292SN/A{
13792292SN/A    unsigned oldest = 0;
13802292SN/A    bool first = true;
13812292SN/A
13822292SN/A    list<ThreadID>::iterator threads = activeThreads->begin();
13832292SN/A    list<ThreadID>::iterator end = activeThreads->end();
13842292SN/A
13852292SN/A    while (threads != end) {
13862292SN/A        ThreadID tid = *threads++;
13872292SN/A
13886221Snate@binkert.org        if (!rob->isEmpty(tid) &&
13892292SN/A            (commitStatus[tid] == Running ||
13902292SN/A             commitStatus[tid] == Idle ||
13912292SN/A             commitStatus[tid] == FetchTrapPending)) {
13926221Snate@binkert.org
13932292SN/A            if (rob->isHeadReady(tid)) {
13942292SN/A
13952292SN/A                DynInstPtr head_inst = rob->readHeadInst(tid);
13962292SN/A
13972292SN/A                if (first) {
13986221Snate@binkert.org                    oldest = tid;
13996221Snate@binkert.org                    first = false;
14002292SN/A                } else if (head_inst->seqNum < oldest) {
14013867Sbinkertn@umich.edu                    oldest = tid;
14026221Snate@binkert.org                }
14032292SN/A            }
14042292SN/A        }
14052292SN/A    }
14062292SN/A
14072292SN/A    if (!first) {
14082292SN/A        return oldest;
14092292SN/A    } else {
14102292SN/A        return InvalidThreadID;
14112292SN/A    }
14122292SN/A}
14132292SN/A