commit_impl.hh revision 7783
11689SN/A/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412965Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#include <algorithm> 452329SN/A#include <string> 462292SN/A 473577Sgblack@eecs.umich.edu#include "arch/utility.hh" 485953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 492292SN/A#include "base/loader/symtab.hh" 501060SN/A#include "base/timebuf.hh" 516221Snate@binkert.org#include "config/full_system.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 536221Snate@binkert.org#include "config/use_checker.hh" 542292SN/A#include "cpu/exetrace.hh" 551717SN/A#include "cpu/o3/commit.hh" 562292SN/A#include "cpu/o3/thread_state.hh" 576221Snate@binkert.org#include "params/DerivO3CPU.hh" 582292SN/A 592790Sktlim@umich.edu#if USE_CHECKER 602790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 612790Sktlim@umich.edu#endif 622790Sktlim@umich.edu 636221Snate@binkert.orgusing namespace std; 645529Snate@binkert.org 651061SN/Atemplate <class Impl> 662292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 676221Snate@binkert.org ThreadID _tid) 685606Snate@binkert.org : Event(CPU_Tick_Pri), commit(_commit), tid(_tid) 691060SN/A{ 705769Snate@binkert.org this->setFlags(AutoDelete); 711060SN/A} 721060SN/A 731061SN/Atemplate <class Impl> 741060SN/Avoid 752292SN/ADefaultCommit<Impl>::TrapEvent::process() 761062SN/A{ 772316SN/A // This will get reset by commit if it was switched out at the 782316SN/A // time of this event processing. 792292SN/A commit->trapSquash[tid] = true; 802292SN/A} 812292SN/A 822292SN/Atemplate <class Impl> 832292SN/Aconst char * 845336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 852292SN/A{ 864873Sstever@eecs.umich.edu return "Trap"; 872292SN/A} 882292SN/A 892292SN/Atemplate <class Impl> 905529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 914329Sktlim@umich.edu : cpu(_cpu), 924329Sktlim@umich.edu squashCounter(0), 932292SN/A iewToCommitDelay(params->iewToCommitDelay), 942292SN/A commitToIEWDelay(params->commitToIEWDelay), 952292SN/A renameToROBDelay(params->renameToROBDelay), 962292SN/A fetchToCommitDelay(params->commitToFetchDelay), 972292SN/A renameWidth(params->renameWidth), 982292SN/A commitWidth(params->commitWidth), 995529Snate@binkert.org numThreads(params->numThreads), 1002843Sktlim@umich.edu drainPending(false), 1012316SN/A switchedOut(false), 1022874Sktlim@umich.edu trapLatency(params->trapLatency) 1032292SN/A{ 1042292SN/A _status = Active; 1052292SN/A _nextStatus = Inactive; 1062980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1072292SN/A 1082292SN/A //Convert string to lowercase 1092292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1102292SN/A (int(*)(int)) tolower); 1112292SN/A 1122292SN/A //Assign commit policy 1132292SN/A if (policy == "aggressive"){ 1142292SN/A commitPolicy = Aggressive; 1152292SN/A 1164329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive."); 1172292SN/A } else if (policy == "roundrobin"){ 1182292SN/A commitPolicy = RoundRobin; 1192292SN/A 1202292SN/A //Set-Up Priority List 1216221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1222292SN/A priority_list.push_back(tid); 1232292SN/A } 1242292SN/A 1254329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 1262292SN/A } else if (policy == "oldestready"){ 1272292SN/A commitPolicy = OldestReady; 1282292SN/A 1294329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1302292SN/A } else { 1312292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1322292SN/A "RoundRobin,OldestReady}"); 1332292SN/A } 1342292SN/A 1356221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1366221Snate@binkert.org commitStatus[tid] = Idle; 1376221Snate@binkert.org changedROBNumEntries[tid] = false; 1386221Snate@binkert.org checkEmptyROB[tid] = false; 1396221Snate@binkert.org trapInFlight[tid] = false; 1406221Snate@binkert.org committedStores[tid] = false; 1416221Snate@binkert.org trapSquash[tid] = false; 1426221Snate@binkert.org tcSquash[tid] = false; 1437720Sgblack@eecs.umich.edu pc[tid].set(0); 1442292SN/A } 1453640Sktlim@umich.edu#if FULL_SYSTEM 1463640Sktlim@umich.edu interrupt = NoFault; 1473640Sktlim@umich.edu#endif 1482292SN/A} 1492292SN/A 1502292SN/Atemplate <class Impl> 1512292SN/Astd::string 1522292SN/ADefaultCommit<Impl>::name() const 1532292SN/A{ 1542292SN/A return cpu->name() + ".commit"; 1552292SN/A} 1562292SN/A 1572292SN/Atemplate <class Impl> 1582292SN/Avoid 1592292SN/ADefaultCommit<Impl>::regStats() 1602132SN/A{ 1612301SN/A using namespace Stats; 1621062SN/A commitCommittedInsts 1631062SN/A .name(name() + ".commitCommittedInsts") 1641062SN/A .desc("The number of committed instructions") 1651062SN/A .prereq(commitCommittedInsts); 1661062SN/A commitSquashedInsts 1671062SN/A .name(name() + ".commitSquashedInsts") 1681062SN/A .desc("The number of squashed insts skipped by commit") 1691062SN/A .prereq(commitSquashedInsts); 1701062SN/A commitSquashEvents 1711062SN/A .name(name() + ".commitSquashEvents") 1721062SN/A .desc("The number of times commit is told to squash") 1731062SN/A .prereq(commitSquashEvents); 1741062SN/A commitNonSpecStalls 1751062SN/A .name(name() + ".commitNonSpecStalls") 1761062SN/A .desc("The number of times commit has been forced to stall to " 1771062SN/A "communicate backwards") 1781062SN/A .prereq(commitNonSpecStalls); 1791062SN/A branchMispredicts 1801062SN/A .name(name() + ".branchMispredicts") 1811062SN/A .desc("The number of times a branch was mispredicted") 1821062SN/A .prereq(branchMispredicts); 1832292SN/A numCommittedDist 1841062SN/A .init(0,commitWidth,1) 1851062SN/A .name(name() + ".COM:committed_per_cycle") 1861062SN/A .desc("Number of insts commited each cycle") 1871062SN/A .flags(Stats::pdf) 1881062SN/A ; 1892301SN/A 1902316SN/A statComInst 1916221Snate@binkert.org .init(cpu->numThreads) 1922301SN/A .name(name() + ".COM:count") 1932301SN/A .desc("Number of instructions committed") 1942301SN/A .flags(total) 1952301SN/A ; 1962301SN/A 1972316SN/A statComSwp 1986221Snate@binkert.org .init(cpu->numThreads) 1992301SN/A .name(name() + ".COM:swp_count") 2002301SN/A .desc("Number of s/w prefetches committed") 2012301SN/A .flags(total) 2022301SN/A ; 2032301SN/A 2042316SN/A statComRefs 2056221Snate@binkert.org .init(cpu->numThreads) 2062301SN/A .name(name() + ".COM:refs") 2072301SN/A .desc("Number of memory references committed") 2082301SN/A .flags(total) 2092301SN/A ; 2102301SN/A 2112316SN/A statComLoads 2126221Snate@binkert.org .init(cpu->numThreads) 2132301SN/A .name(name() + ".COM:loads") 2142301SN/A .desc("Number of loads committed") 2152301SN/A .flags(total) 2162301SN/A ; 2172301SN/A 2182316SN/A statComMembars 2196221Snate@binkert.org .init(cpu->numThreads) 2202301SN/A .name(name() + ".COM:membars") 2212301SN/A .desc("Number of memory barriers committed") 2222301SN/A .flags(total) 2232301SN/A ; 2242301SN/A 2252316SN/A statComBranches 2266221Snate@binkert.org .init(cpu->numThreads) 2272301SN/A .name(name() + ".COM:branches") 2282301SN/A .desc("Number of branches committed") 2292301SN/A .flags(total) 2302301SN/A ; 2312301SN/A 2322316SN/A commitEligible 2336221Snate@binkert.org .init(cpu->numThreads) 2342301SN/A .name(name() + ".COM:bw_limited") 2352301SN/A .desc("number of insts not committed due to BW limits") 2362301SN/A .flags(total) 2372301SN/A ; 2382301SN/A 2392316SN/A commitEligibleSamples 2402301SN/A .name(name() + ".COM:bw_lim_events") 2412301SN/A .desc("number cycles where commit BW limit reached") 2422301SN/A ; 2431062SN/A} 2441062SN/A 2451062SN/Atemplate <class Impl> 2461062SN/Avoid 2472980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2482292SN/A{ 2492292SN/A thread = threads; 2502292SN/A} 2512292SN/A 2522292SN/Atemplate <class Impl> 2532292SN/Avoid 2542292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2551060SN/A{ 2561060SN/A timeBuffer = tb_ptr; 2571060SN/A 2581060SN/A // Setup wire to send information back to IEW. 2591060SN/A toIEW = timeBuffer->getWire(0); 2601060SN/A 2611060SN/A // Setup wire to read data from IEW (for the ROB). 2621060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2631060SN/A} 2641060SN/A 2651061SN/Atemplate <class Impl> 2661060SN/Avoid 2672292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2682292SN/A{ 2692292SN/A fetchQueue = fq_ptr; 2702292SN/A 2712292SN/A // Setup wire to get instructions from rename (for the ROB). 2722292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2732292SN/A} 2742292SN/A 2752292SN/Atemplate <class Impl> 2762292SN/Avoid 2772292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2781060SN/A{ 2791060SN/A renameQueue = rq_ptr; 2801060SN/A 2811060SN/A // Setup wire to get instructions from rename (for the ROB). 2821060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2831060SN/A} 2841060SN/A 2851061SN/Atemplate <class Impl> 2861060SN/Avoid 2872292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2881060SN/A{ 2891060SN/A iewQueue = iq_ptr; 2901060SN/A 2911060SN/A // Setup wire to get instructions from IEW. 2921060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2931060SN/A} 2941060SN/A 2951061SN/Atemplate <class Impl> 2961060SN/Avoid 2972292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2982292SN/A{ 2992292SN/A iewStage = iew_stage; 3002292SN/A} 3012292SN/A 3022292SN/Atemplate<class Impl> 3032292SN/Avoid 3046221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3052292SN/A{ 3062292SN/A activeThreads = at_ptr; 3072292SN/A} 3082292SN/A 3092292SN/Atemplate <class Impl> 3102292SN/Avoid 3112292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3122292SN/A{ 3136221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3146221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3152292SN/A} 3162292SN/A 3172292SN/Atemplate <class Impl> 3182292SN/Avoid 3192292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3201060SN/A{ 3211060SN/A rob = rob_ptr; 3221060SN/A} 3231060SN/A 3241061SN/Atemplate <class Impl> 3251060SN/Avoid 3262292SN/ADefaultCommit<Impl>::initStage() 3271060SN/A{ 3282292SN/A rob->setActiveThreads(activeThreads); 3292292SN/A rob->resetEntries(); 3301060SN/A 3312292SN/A // Broadcast the number of free entries. 3326221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3336221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3346221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3356221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3361060SN/A } 3371060SN/A 3384329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3394329Sktlim@umich.edu // start of the simulation, so it starts as active. 3404329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3414329Sktlim@umich.edu 3422292SN/A cpu->activityThisCycle(); 3435100Ssaidi@eecs.umich.edu trapLatency = cpu->ticks(trapLatency); 3441060SN/A} 3451060SN/A 3461061SN/Atemplate <class Impl> 3472863Sktlim@umich.edubool 3482843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3491060SN/A{ 3502843Sktlim@umich.edu drainPending = true; 3512863Sktlim@umich.edu 3522863Sktlim@umich.edu return false; 3532316SN/A} 3542316SN/A 3552316SN/Atemplate <class Impl> 3562316SN/Avoid 3572843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3582316SN/A{ 3592316SN/A switchedOut = true; 3602843Sktlim@umich.edu drainPending = false; 3612307SN/A rob->switchOut(); 3622307SN/A} 3632307SN/A 3642307SN/Atemplate <class Impl> 3652307SN/Avoid 3662843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3672843Sktlim@umich.edu{ 3682864Sktlim@umich.edu drainPending = false; 3692843Sktlim@umich.edu} 3702843Sktlim@umich.edu 3712843Sktlim@umich.edutemplate <class Impl> 3722843Sktlim@umich.eduvoid 3732307SN/ADefaultCommit<Impl>::takeOverFrom() 3742307SN/A{ 3752316SN/A switchedOut = false; 3762307SN/A _status = Active; 3772307SN/A _nextStatus = Inactive; 3786221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3796221Snate@binkert.org commitStatus[tid] = Idle; 3806221Snate@binkert.org changedROBNumEntries[tid] = false; 3816221Snate@binkert.org trapSquash[tid] = false; 3826221Snate@binkert.org tcSquash[tid] = false; 3832307SN/A } 3842307SN/A squashCounter = 0; 3852307SN/A rob->takeOverFrom(); 3862307SN/A} 3872307SN/A 3882307SN/Atemplate <class Impl> 3892307SN/Avoid 3902292SN/ADefaultCommit<Impl>::updateStatus() 3912132SN/A{ 3922316SN/A // reset ROB changed variable 3936221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3946221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3953867Sbinkertn@umich.edu 3963867Sbinkertn@umich.edu while (threads != end) { 3976221Snate@binkert.org ThreadID tid = *threads++; 3983867Sbinkertn@umich.edu 3992316SN/A changedROBNumEntries[tid] = false; 4002316SN/A 4012316SN/A // Also check if any of the threads has a trap pending 4022316SN/A if (commitStatus[tid] == TrapPending || 4032316SN/A commitStatus[tid] == FetchTrapPending) { 4042316SN/A _nextStatus = Active; 4052316SN/A } 4062292SN/A } 4072292SN/A 4082292SN/A if (_nextStatus == Inactive && _status == Active) { 4092292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4102733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4112292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4122292SN/A DPRINTF(Activity, "Activating stage.\n"); 4132733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4142292SN/A } 4152292SN/A 4162292SN/A _status = _nextStatus; 4172292SN/A} 4182292SN/A 4192292SN/Atemplate <class Impl> 4202292SN/Avoid 4212292SN/ADefaultCommit<Impl>::setNextStatus() 4222292SN/A{ 4232292SN/A int squashes = 0; 4242292SN/A 4256221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4266221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4272292SN/A 4283867Sbinkertn@umich.edu while (threads != end) { 4296221Snate@binkert.org ThreadID tid = *threads++; 4302292SN/A 4312292SN/A if (commitStatus[tid] == ROBSquashing) { 4322292SN/A squashes++; 4332292SN/A } 4342292SN/A } 4352292SN/A 4362702Sktlim@umich.edu squashCounter = squashes; 4372292SN/A 4382292SN/A // If commit is currently squashing, then it will have activity for the 4392292SN/A // next cycle. Set its next status as active. 4402292SN/A if (squashCounter) { 4412292SN/A _nextStatus = Active; 4422292SN/A } 4432292SN/A} 4442292SN/A 4452292SN/Atemplate <class Impl> 4462292SN/Abool 4472292SN/ADefaultCommit<Impl>::changedROBEntries() 4482292SN/A{ 4496221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4506221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4512292SN/A 4523867Sbinkertn@umich.edu while (threads != end) { 4536221Snate@binkert.org ThreadID tid = *threads++; 4542292SN/A 4552292SN/A if (changedROBNumEntries[tid]) { 4562292SN/A return true; 4572292SN/A } 4582292SN/A } 4592292SN/A 4602292SN/A return false; 4612292SN/A} 4622292SN/A 4632292SN/Atemplate <class Impl> 4646221Snate@binkert.orgsize_t 4656221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 4662292SN/A{ 4672292SN/A return rob->numFreeEntries(tid); 4682292SN/A} 4692292SN/A 4702292SN/Atemplate <class Impl> 4712292SN/Avoid 4726221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 4732292SN/A{ 4742292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4752292SN/A 4762292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4772292SN/A 4785606Snate@binkert.org cpu->schedule(trap, curTick + trapLatency); 4794035Sktlim@umich.edu trapInFlight[tid] = true; 4802292SN/A} 4812292SN/A 4822292SN/Atemplate <class Impl> 4832292SN/Avoid 4846221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 4852292SN/A{ 4864035Sktlim@umich.edu assert(!trapInFlight[tid]); 4872680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4882292SN/A 4892680Sktlim@umich.edu tcSquash[tid] = true; 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4932292SN/Avoid 4946221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 4952292SN/A{ 4962292SN/A // If we want to include the squashing instruction in the squash, 4972292SN/A // then use one older sequence number. 4982292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4992292SN/A // all instructions of this thread. 5002292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5014035Sktlim@umich.edu 0 : rob->readHeadInst(tid)->seqNum - 1; 5022292SN/A 5032292SN/A // All younger instructions will be squashed. Set the sequence 5042292SN/A // number as the youngest instruction in the ROB (0 in this case. 5052292SN/A // Hopefully nothing breaks.) 5062292SN/A youngestSeqNum[tid] = 0; 5072292SN/A 5082292SN/A rob->squash(squashed_inst, tid); 5092292SN/A changedROBNumEntries[tid] = true; 5102292SN/A 5112292SN/A // Send back the sequence number of the squashed instruction. 5122292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5132292SN/A 5142292SN/A // Send back the squash signal to tell stages that they should 5152292SN/A // squash. 5162292SN/A toIEW->commitInfo[tid].squash = true; 5172292SN/A 5182292SN/A // Send back the rob squashing signal so other stages know that 5192292SN/A // the ROB is in the process of squashing. 5202292SN/A toIEW->commitInfo[tid].robSquashing = true; 5212292SN/A 5222292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5232292SN/A 5247720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5252316SN/A} 5262292SN/A 5272316SN/Atemplate <class Impl> 5282316SN/Avoid 5296221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5302316SN/A{ 5312316SN/A squashAll(tid); 5322316SN/A 5337720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5342316SN/A 5352316SN/A thread[tid]->trapPending = false; 5362316SN/A thread[tid]->inSyscall = false; 5374035Sktlim@umich.edu trapInFlight[tid] = false; 5382316SN/A 5392316SN/A trapSquash[tid] = false; 5402316SN/A 5412316SN/A commitStatus[tid] = ROBSquashing; 5422316SN/A cpu->activityThisCycle(); 5432316SN/A} 5442316SN/A 5452316SN/Atemplate <class Impl> 5462316SN/Avoid 5476221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 5482316SN/A{ 5492316SN/A squashAll(tid); 5502292SN/A 5517720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 5522292SN/A 5532292SN/A thread[tid]->inSyscall = false; 5542292SN/A assert(!thread[tid]->trapPending); 5552316SN/A 5562292SN/A commitStatus[tid] = ROBSquashing; 5572292SN/A cpu->activityThisCycle(); 5582292SN/A 5592680Sktlim@umich.edu tcSquash[tid] = false; 5602292SN/A} 5612292SN/A 5622292SN/Atemplate <class Impl> 5632292SN/Avoid 5642292SN/ADefaultCommit<Impl>::tick() 5652292SN/A{ 5662292SN/A wroteToTimeBuffer = false; 5672292SN/A _nextStatus = Inactive; 5682292SN/A 5692843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5702843Sktlim@umich.edu cpu->signalDrained(); 5712843Sktlim@umich.edu drainPending = false; 5722316SN/A return; 5732316SN/A } 5742316SN/A 5753867Sbinkertn@umich.edu if (activeThreads->empty()) 5762875Sksewell@umich.edu return; 5772875Sksewell@umich.edu 5786221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5796221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5802292SN/A 5812316SN/A // Check if any of the threads are done squashing. Change the 5822316SN/A // status if they are done. 5833867Sbinkertn@umich.edu while (threads != end) { 5846221Snate@binkert.org ThreadID tid = *threads++; 5852292SN/A 5864035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 5874035Sktlim@umich.edu // this cycle. 5884035Sktlim@umich.edu committedStores[tid] = false; 5894035Sktlim@umich.edu 5902292SN/A if (commitStatus[tid] == ROBSquashing) { 5912292SN/A 5922292SN/A if (rob->isDoneSquashing(tid)) { 5932292SN/A commitStatus[tid] = Running; 5942292SN/A } else { 5952292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5962877Sksewell@umich.edu " insts this cycle.\n", tid); 5972702Sktlim@umich.edu rob->doSquash(tid); 5982702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5992702Sktlim@umich.edu wroteToTimeBuffer = true; 6002292SN/A } 6012292SN/A } 6022292SN/A } 6032292SN/A 6042292SN/A commit(); 6052292SN/A 6062292SN/A markCompletedInsts(); 6072292SN/A 6083867Sbinkertn@umich.edu threads = activeThreads->begin(); 6092292SN/A 6103867Sbinkertn@umich.edu while (threads != end) { 6116221Snate@binkert.org ThreadID tid = *threads++; 6122292SN/A 6132292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6142292SN/A // The ROB has more instructions it can commit. Its next status 6152292SN/A // will be active. 6162292SN/A _nextStatus = Active; 6172292SN/A 6182292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6192292SN/A 6207720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 6212292SN/A " ROB and ready to commit\n", 6227720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6232292SN/A 6242292SN/A } else if (!rob->isEmpty(tid)) { 6252292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6262292SN/A 6272292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6287720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 6297720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6302292SN/A } 6312292SN/A 6322292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6332292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6342292SN/A } 6352292SN/A 6362292SN/A 6372292SN/A if (wroteToTimeBuffer) { 6382316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6392292SN/A cpu->activityThisCycle(); 6402292SN/A } 6412292SN/A 6422292SN/A updateStatus(); 6432292SN/A} 6442292SN/A 6454035Sktlim@umich.edu#if FULL_SYSTEM 6462292SN/Atemplate <class Impl> 6472292SN/Avoid 6484035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 6492292SN/A{ 6503640Sktlim@umich.edu if (interrupt != NoFault) { 6512316SN/A // Wait until the ROB is empty and all stores have drained in 6522316SN/A // order to enter the interrupt. 6532292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6543633Sktlim@umich.edu // Squash or record that I need to squash this cycle if 6553633Sktlim@umich.edu // an interrupt needed to be handled. 6563633Sktlim@umich.edu DPRINTF(Commit, "Interrupt detected.\n"); 6573633Sktlim@umich.edu 6584035Sktlim@umich.edu // Clear the interrupt now that it's going to be handled 6594035Sktlim@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 6604035Sktlim@umich.edu 6612292SN/A assert(!thread[0]->inSyscall); 6622292SN/A thread[0]->inSyscall = true; 6632292SN/A 6643633Sktlim@umich.edu // CPU will handle interrupt. 6653640Sktlim@umich.edu cpu->processInterrupts(interrupt); 6662292SN/A 6673633Sktlim@umich.edu thread[0]->inSyscall = false; 6683633Sktlim@umich.edu 6692292SN/A commitStatus[0] = TrapPending; 6702292SN/A 6712292SN/A // Generate trap squash event. 6722292SN/A generateTrapEvent(0); 6732292SN/A 6743640Sktlim@umich.edu interrupt = NoFault; 6752292SN/A } else { 6762292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6772292SN/A } 6784035Sktlim@umich.edu } else if (commitStatus[0] != TrapPending && 6795704Snate@binkert.org cpu->checkInterrupts(cpu->tcBase(0)) && 6804035Sktlim@umich.edu !trapSquash[0] && 6814035Sktlim@umich.edu !tcSquash[0]) { 6823640Sktlim@umich.edu // Process interrupts if interrupts are enabled, not in PAL 6833640Sktlim@umich.edu // mode, and no other traps or external squashes are currently 6843640Sktlim@umich.edu // pending. 6853640Sktlim@umich.edu // @todo: Allow other threads to handle interrupts. 6863640Sktlim@umich.edu 6873640Sktlim@umich.edu // Get any interrupt that happened 6883640Sktlim@umich.edu interrupt = cpu->getInterrupts(); 6893640Sktlim@umich.edu 6903640Sktlim@umich.edu if (interrupt != NoFault) { 6913640Sktlim@umich.edu // Tell fetch that there is an interrupt pending. This 6923640Sktlim@umich.edu // will make fetch wait until it sees a non PAL-mode PC, 6933640Sktlim@umich.edu // at which point it stops fetching instructions. 6943640Sktlim@umich.edu toIEW->commitInfo[0].interruptPending = true; 6953640Sktlim@umich.edu } 6961060SN/A } 6974035Sktlim@umich.edu} 6984035Sktlim@umich.edu#endif // FULL_SYSTEM 6993634Sktlim@umich.edu 7004035Sktlim@umich.edutemplate <class Impl> 7014035Sktlim@umich.eduvoid 7024035Sktlim@umich.eduDefaultCommit<Impl>::commit() 7034035Sktlim@umich.edu{ 7044035Sktlim@umich.edu 7054035Sktlim@umich.edu#if FULL_SYSTEM 7064035Sktlim@umich.edu // Check for any interrupt, and start processing it. Or if we 7074035Sktlim@umich.edu // have an outstanding interrupt and are at a point when it is 7084035Sktlim@umich.edu // valid to take an interrupt, process it. 7095704Snate@binkert.org if (cpu->checkInterrupts(cpu->tcBase(0))) { 7104035Sktlim@umich.edu handleInterrupt(); 7114035Sktlim@umich.edu } 7121060SN/A#endif // FULL_SYSTEM 7131060SN/A 7141060SN/A //////////////////////////////////// 7152316SN/A // Check for any possible squashes, handle them first 7161060SN/A //////////////////////////////////// 7176221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7186221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7191060SN/A 7203867Sbinkertn@umich.edu while (threads != end) { 7216221Snate@binkert.org ThreadID tid = *threads++; 7221060SN/A 7232292SN/A // Not sure which one takes priority. I think if we have 7242292SN/A // both, that's a bad sign. 7252292SN/A if (trapSquash[tid] == true) { 7262680Sktlim@umich.edu assert(!tcSquash[tid]); 7272292SN/A squashFromTrap(tid); 7282680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7294035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 7302680Sktlim@umich.edu squashFromTC(tid); 7312292SN/A } 7321061SN/A 7332292SN/A // Squashed sequence number must be older than youngest valid 7342292SN/A // instruction in the ROB. This prevents squashes from younger 7352292SN/A // instructions overriding squashes from older instructions. 7362292SN/A if (fromIEW->squash[tid] && 7372292SN/A commitStatus[tid] != TrapPending && 7382292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7391061SN/A 7402292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7412292SN/A tid, 7422292SN/A fromIEW->mispredPC[tid], 7432292SN/A fromIEW->squashedSeqNum[tid]); 7441061SN/A 7452292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7462292SN/A tid, 7477720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 7481061SN/A 7492292SN/A commitStatus[tid] = ROBSquashing; 7501061SN/A 7512292SN/A // If we want to include the squashing instruction in the squash, 7522292SN/A // then use one older sequence number. 7532292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7541062SN/A 7552935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 7562292SN/A squashed_inst--; 7572935Sksewell@umich.edu } 7584035Sktlim@umich.edu 7592292SN/A // All younger instructions will be squashed. Set the sequence 7602292SN/A // number as the youngest instruction in the ROB. 7612292SN/A youngestSeqNum[tid] = squashed_inst; 7622292SN/A 7633093Sksewell@umich.edu rob->squash(squashed_inst, tid); 7642292SN/A changedROBNumEntries[tid] = true; 7652292SN/A 7662292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7672292SN/A 7682292SN/A toIEW->commitInfo[tid].squash = true; 7692292SN/A 7702292SN/A // Send back the rob squashing signal so other stages know that 7712292SN/A // the ROB is in the process of squashing. 7722292SN/A toIEW->commitInfo[tid].robSquashing = true; 7732292SN/A 7742292SN/A toIEW->commitInfo[tid].branchMispredict = 7752292SN/A fromIEW->branchMispredict[tid]; 7762292SN/A 7772292SN/A toIEW->commitInfo[tid].branchTaken = 7782292SN/A fromIEW->branchTaken[tid]; 7792292SN/A 7807720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 7812292SN/A 7822316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7832292SN/A 7842292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7852292SN/A ++branchMispredicts; 7862292SN/A } 7871062SN/A } 7882292SN/A 7891060SN/A } 7901060SN/A 7912292SN/A setNextStatus(); 7922292SN/A 7932292SN/A if (squashCounter != numThreads) { 7941061SN/A // If we're not currently squashing, then get instructions. 7951060SN/A getInsts(); 7961060SN/A 7971061SN/A // Try to commit any instructions. 7981060SN/A commitInsts(); 7991060SN/A } 8001060SN/A 8012292SN/A //Check for any activity 8023867Sbinkertn@umich.edu threads = activeThreads->begin(); 8032292SN/A 8043867Sbinkertn@umich.edu while (threads != end) { 8056221Snate@binkert.org ThreadID tid = *threads++; 8062292SN/A 8072292SN/A if (changedROBNumEntries[tid]) { 8082292SN/A toIEW->commitInfo[tid].usedROB = true; 8092292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8102292SN/A 8112292SN/A wroteToTimeBuffer = true; 8122292SN/A changedROBNumEntries[tid] = false; 8134035Sktlim@umich.edu if (rob->isEmpty(tid)) 8144035Sktlim@umich.edu checkEmptyROB[tid] = true; 8152292SN/A } 8164035Sktlim@umich.edu 8174035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8184035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 8194035Sktlim@umich.edu // stage has received any information regarding stores that 8204035Sktlim@umich.edu // committed. 8214035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 8224035Sktlim@umich.edu // on the same cycle as when stores have been committed. 8234035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 8244035Sktlim@umich.edu // commit and IEW. 8254035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 8265557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 8274035Sktlim@umich.edu checkEmptyROB[tid] = false; 8284035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 8294035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 8304035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8314035Sktlim@umich.edu wroteToTimeBuffer = true; 8324035Sktlim@umich.edu } 8334035Sktlim@umich.edu 8341060SN/A } 8351060SN/A} 8361060SN/A 8371061SN/Atemplate <class Impl> 8381060SN/Avoid 8392292SN/ADefaultCommit<Impl>::commitInsts() 8401060SN/A{ 8411060SN/A //////////////////////////////////// 8421060SN/A // Handle commit 8432316SN/A // Note that commit will be handled prior to putting new 8442316SN/A // instructions in the ROB so that the ROB only tries to commit 8452316SN/A // instructions it has in this current cycle, and not instructions 8462316SN/A // it is writing in during this cycle. Can't commit and squash 8472316SN/A // things at the same time... 8481060SN/A //////////////////////////////////// 8491060SN/A 8502292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8511060SN/A 8521060SN/A unsigned num_committed = 0; 8531060SN/A 8542292SN/A DynInstPtr head_inst; 8552316SN/A 8561060SN/A // Commit as many instructions as possible until the commit bandwidth 8571060SN/A // limit is reached, or it becomes impossible to commit any more. 8582292SN/A while (num_committed < commitWidth) { 8592292SN/A int commit_thread = getCommittingThread(); 8601060SN/A 8612292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8622292SN/A break; 8632292SN/A 8642292SN/A head_inst = rob->readHeadInst(commit_thread); 8652292SN/A 8666221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 8672292SN/A 8682292SN/A assert(tid == commit_thread); 8692292SN/A 8702292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8712292SN/A head_inst->seqNum, tid); 8722132SN/A 8732316SN/A // If the head instruction is squashed, it is ready to retire 8742316SN/A // (be removed from the ROB) at any time. 8751060SN/A if (head_inst->isSquashed()) { 8761060SN/A 8772292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8781060SN/A "ROB.\n"); 8791060SN/A 8802292SN/A rob->retireHead(commit_thread); 8811060SN/A 8821062SN/A ++commitSquashedInsts; 8831062SN/A 8842292SN/A // Record that the number of ROB entries has changed. 8852292SN/A changedROBNumEntries[tid] = true; 8861060SN/A } else { 8877720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 8882292SN/A 8891060SN/A // Increment the total number of non-speculative instructions 8901060SN/A // executed. 8911060SN/A // Hack for now: it really shouldn't happen until after the 8921061SN/A // commit is deemed to be successful, but this count is needed 8931061SN/A // for syscalls. 8942292SN/A thread[tid]->funcExeInst++; 8951060SN/A 8961060SN/A // Try to commit the head instruction. 8971060SN/A bool commit_success = commitHead(head_inst, num_committed); 8981060SN/A 8991062SN/A if (commit_success) { 9001060SN/A ++num_committed; 9011060SN/A 9022292SN/A changedROBNumEntries[tid] = true; 9032292SN/A 9042292SN/A // Set the doneSeqNum to the youngest committed instruction. 9052292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9061060SN/A 9071062SN/A ++commitCommittedInsts; 9081062SN/A 9092292SN/A // To match the old model, don't count nops and instruction 9102292SN/A // prefetches towards the total commit count. 9112292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9122292SN/A cpu->instDone(tid); 9131062SN/A } 9142292SN/A 9157783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 9167783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 9177783SGiacomo.Gabrielli@arm.com 9187720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 9192935Sksewell@umich.edu 9202292SN/A int count = 0; 9212292SN/A Addr oldpc; 9225108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 9235108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 9245108Sgblack@eecs.umich.edu assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 9252292SN/A do { 9267720Sgblack@eecs.umich.edu oldpc = pc[tid].instAddr(); 9275108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 9282292SN/A count++; 9297720Sgblack@eecs.umich.edu } while (oldpc != pc[tid].instAddr()); 9302292SN/A if (count > 1) { 9315108Sgblack@eecs.umich.edu DPRINTF(Commit, 9325108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 9332292SN/A break; 9342292SN/A } 9351060SN/A } else { 9367720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 9372292SN/A "[tid:%i] [sn:%i].\n", 9387720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 9391060SN/A break; 9401060SN/A } 9411060SN/A } 9421060SN/A } 9431062SN/A 9441063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9452292SN/A numCommittedDist.sample(num_committed); 9462307SN/A 9472307SN/A if (num_committed == commitWidth) { 9482349SN/A commitEligibleSamples++; 9492307SN/A } 9501060SN/A} 9511060SN/A 9521061SN/Atemplate <class Impl> 9531060SN/Abool 9542292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9551060SN/A{ 9561060SN/A assert(head_inst); 9571060SN/A 9586221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 9592292SN/A 9602316SN/A // If the instruction is not executed yet, then it will need extra 9612316SN/A // handling. Signal backwards that it should be executed. 9621061SN/A if (!head_inst->isExecuted()) { 9631061SN/A // Keep this number correct. We have not yet actually executed 9641061SN/A // and committed this instruction. 9652292SN/A thread[tid]->funcExeInst--; 9661062SN/A 9672292SN/A if (head_inst->isNonSpeculative() || 9682348SN/A head_inst->isStoreConditional() || 9692292SN/A head_inst->isMemBarrier() || 9702292SN/A head_inst->isWriteBarrier()) { 9712316SN/A 9722316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9737720Sgblack@eecs.umich.edu "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 9747720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 9752316SN/A 9765557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 9772292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9782292SN/A return false; 9792292SN/A } 9802292SN/A 9812292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9821061SN/A 9831061SN/A // Change the instruction so it won't try to commit again until 9841061SN/A // it is executed. 9851061SN/A head_inst->clearCanCommit(); 9861061SN/A 9871062SN/A ++commitNonSpecStalls; 9881062SN/A 9891061SN/A return false; 9902292SN/A } else if (head_inst->isLoad()) { 9915557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 9924035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9934035Sktlim@umich.edu return false; 9944035Sktlim@umich.edu } 9954035Sktlim@umich.edu 9964035Sktlim@umich.edu assert(head_inst->uncacheable()); 9977720Sgblack@eecs.umich.edu DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 9987720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 9992292SN/A 10002292SN/A // Send back the non-speculative instruction's sequence 10012316SN/A // number. Tell the lsq to re-execute the load. 10022292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10032292SN/A toIEW->commitInfo[tid].uncached = true; 10042292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10052292SN/A 10062292SN/A head_inst->clearCanCommit(); 10072292SN/A 10082292SN/A return false; 10091061SN/A } else { 10102292SN/A panic("Trying to commit un-executed instruction " 10111061SN/A "of unknown type!\n"); 10121061SN/A } 10131060SN/A } 10141060SN/A 10152316SN/A if (head_inst->isThreadSync()) { 10162292SN/A // Not handled for now. 10172316SN/A panic("Thread sync instructions are not handled yet.\n"); 10182132SN/A } 10192132SN/A 10204035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 10214035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 10224035Sktlim@umich.edu 10232316SN/A // Stores mark themselves as completed. 10244035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 10252310SN/A head_inst->setCompleted(); 10262310SN/A } 10272310SN/A 10282733Sktlim@umich.edu#if USE_CHECKER 10292316SN/A // Use checker prior to updating anything due to traps or PC 10302316SN/A // based events. 10312316SN/A if (cpu->checker) { 10322732Sktlim@umich.edu cpu->checker->verify(head_inst); 10331060SN/A } 10342733Sktlim@umich.edu#endif 10351060SN/A 10362112SN/A if (inst_fault != NoFault) { 10377720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 10387720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 10392292SN/A 10405557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 10412316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10422316SN/A return false; 10432316SN/A } 10442310SN/A 10454035Sktlim@umich.edu head_inst->setCompleted(); 10464035Sktlim@umich.edu 10472733Sktlim@umich.edu#if USE_CHECKER 10482316SN/A if (cpu->checker && head_inst->isStore()) { 10492732Sktlim@umich.edu cpu->checker->verify(head_inst); 10502316SN/A } 10512733Sktlim@umich.edu#endif 10522292SN/A 10532316SN/A assert(!thread[tid]->inSyscall); 10542292SN/A 10552316SN/A // Mark that we're in state update mode so that the trap's 10562316SN/A // execution doesn't generate extra squashes. 10572316SN/A thread[tid]->inSyscall = true; 10582292SN/A 10592316SN/A // Execute the trap. Although it's slightly unrealistic in 10602316SN/A // terms of timing (as it doesn't wait for the full timing of 10612316SN/A // the trap event to complete before updating state), it's 10622316SN/A // needed to update the state as soon as possible. This 10632316SN/A // prevents external agents from changing any specific state 10642316SN/A // that the trap need. 10657684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 10662292SN/A 10672316SN/A // Exit state update mode to avoid accidental updating. 10682316SN/A thread[tid]->inSyscall = false; 10692292SN/A 10702316SN/A commitStatus[tid] = TrapPending; 10712292SN/A 10724035Sktlim@umich.edu if (head_inst->traceData) { 10736667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 10746667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 10756667Ssteve.reinhardt@amd.com head_inst->traceData->setCPSeq(thread[tid]->numInst); 10766667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 10776667Ssteve.reinhardt@amd.com } 10784288Sktlim@umich.edu delete head_inst->traceData; 10794035Sktlim@umich.edu head_inst->traceData = NULL; 10804035Sktlim@umich.edu } 10814035Sktlim@umich.edu 10822316SN/A // Generate trap squash event. 10832316SN/A generateTrapEvent(tid); 10842316SN/A return false; 10851060SN/A } 10861060SN/A 10872301SN/A updateComInstStats(head_inst); 10882132SN/A 10892362SN/A#if FULL_SYSTEM 10902362SN/A if (thread[tid]->profile) { 10917720Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 10923126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 10932362SN/A head_inst->staticInst); 10942362SN/A 10952362SN/A if (node) 10962362SN/A thread[tid]->profileNode = node; 10972362SN/A } 10985953Ssaidi@eecs.umich.edu if (CPA::available()) { 10995953Ssaidi@eecs.umich.edu if (head_inst->isControl()) { 11005953Ssaidi@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 11017720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 11025953Ssaidi@eecs.umich.edu } 11035953Ssaidi@eecs.umich.edu } 11042362SN/A#endif 11052362SN/A 11062132SN/A if (head_inst->traceData) { 11072292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11082292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11094046Sbinkertn@umich.edu head_inst->traceData->dump(); 11104046Sbinkertn@umich.edu delete head_inst->traceData; 11112292SN/A head_inst->traceData = NULL; 11121060SN/A } 11131060SN/A 11142292SN/A // Update the commit rename map 11152292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11163771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 11172292SN/A head_inst->renamedDestRegIdx(i)); 11181060SN/A } 11191062SN/A 11202353SN/A if (head_inst->isCopy()) 11212353SN/A panic("Should not commit any copy instructions!"); 11222353SN/A 11232292SN/A // Finally clear the head ROB entry. 11242292SN/A rob->retireHead(tid); 11251060SN/A 11264035Sktlim@umich.edu // If this was a store, record it for this cycle. 11274035Sktlim@umich.edu if (head_inst->isStore()) 11284035Sktlim@umich.edu committedStores[tid] = true; 11294035Sktlim@umich.edu 11301060SN/A // Return true to indicate that we have committed an instruction. 11311060SN/A return true; 11321060SN/A} 11331060SN/A 11341061SN/Atemplate <class Impl> 11351060SN/Avoid 11362292SN/ADefaultCommit<Impl>::getInsts() 11371060SN/A{ 11382935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 11392935Sksewell@umich.edu 11403093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11413093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 11422965Sksewell@umich.edu 11432965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 11442965Sksewell@umich.edu DynInstPtr inst; 11452965Sksewell@umich.edu 11463093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 11476221Snate@binkert.org ThreadID tid = inst->threadNumber; 11482292SN/A 11492292SN/A if (!inst->isSquashed() && 11504035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 11514035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 11522292SN/A changedROBNumEntries[tid] = true; 11532292SN/A 11547720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 11557720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 11562292SN/A 11572292SN/A rob->insertInst(inst); 11582292SN/A 11592292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 11602292SN/A 11612292SN/A youngestSeqNum[tid] = inst->seqNum; 11621061SN/A } else { 11637720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 11641061SN/A "squashed, skipping.\n", 11657720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 11661061SN/A } 11671060SN/A } 11682965Sksewell@umich.edu} 11692965Sksewell@umich.edu 11702965Sksewell@umich.edutemplate <class Impl> 11712965Sksewell@umich.eduvoid 11722965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 11732965Sksewell@umich.edu{ 11742965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 11752965Sksewell@umich.edu "skidBuffer.\n"); 11762965Sksewell@umich.edu 11772965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 11782965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 11792965Sksewell@umich.edu 11802965Sksewell@umich.edu if (!inst->isSquashed()) { 11817720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 11827720Sgblack@eecs.umich.edu "skidBuffer.\n", inst->pcState(), inst->seqNum, 11833221Sktlim@umich.edu inst->threadNumber); 11842965Sksewell@umich.edu skidBuffer.push(inst); 11852965Sksewell@umich.edu } else { 11867720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 11872965Sksewell@umich.edu "squashed, skipping.\n", 11887720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->threadNumber); 11892965Sksewell@umich.edu } 11902965Sksewell@umich.edu } 11911060SN/A} 11921060SN/A 11931061SN/Atemplate <class Impl> 11941060SN/Avoid 11952292SN/ADefaultCommit<Impl>::markCompletedInsts() 11961060SN/A{ 11971060SN/A // Grab completed insts out of the IEW instruction queue, and mark 11981060SN/A // instructions completed within the ROB. 11991060SN/A for (int inst_num = 0; 12001681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 12011060SN/A ++inst_num) 12021060SN/A { 12032292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12047720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 12052316SN/A "within ROB.\n", 12062292SN/A fromIEW->insts[inst_num]->threadNumber, 12077720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 12082292SN/A fromIEW->insts[inst_num]->seqNum); 12091060SN/A 12102292SN/A // Mark the instruction as ready to commit. 12112292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12122292SN/A } 12131060SN/A } 12141060SN/A} 12151060SN/A 12161061SN/Atemplate <class Impl> 12172292SN/Abool 12182292SN/ADefaultCommit<Impl>::robDoneSquashing() 12191060SN/A{ 12206221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12216221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12222292SN/A 12233867Sbinkertn@umich.edu while (threads != end) { 12246221Snate@binkert.org ThreadID tid = *threads++; 12252292SN/A 12262292SN/A if (!rob->isDoneSquashing(tid)) 12272292SN/A return false; 12282292SN/A } 12292292SN/A 12302292SN/A return true; 12311060SN/A} 12322292SN/A 12332301SN/Atemplate <class Impl> 12342301SN/Avoid 12352301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 12362301SN/A{ 12376221Snate@binkert.org ThreadID tid = inst->threadNumber; 12382301SN/A 12392301SN/A // 12402301SN/A // Pick off the software prefetches 12412301SN/A // 12422301SN/A#ifdef TARGET_ALPHA 12432301SN/A if (inst->isDataPrefetch()) { 12446221Snate@binkert.org statComSwp[tid]++; 12452301SN/A } else { 12466221Snate@binkert.org statComInst[tid]++; 12472301SN/A } 12482301SN/A#else 12496221Snate@binkert.org statComInst[tid]++; 12502301SN/A#endif 12512301SN/A 12522301SN/A // 12532301SN/A // Control Instructions 12542301SN/A // 12552301SN/A if (inst->isControl()) 12566221Snate@binkert.org statComBranches[tid]++; 12572301SN/A 12582301SN/A // 12592301SN/A // Memory references 12602301SN/A // 12612301SN/A if (inst->isMemRef()) { 12626221Snate@binkert.org statComRefs[tid]++; 12632301SN/A 12642301SN/A if (inst->isLoad()) { 12656221Snate@binkert.org statComLoads[tid]++; 12662301SN/A } 12672301SN/A } 12682301SN/A 12692301SN/A if (inst->isMemBarrier()) { 12706221Snate@binkert.org statComMembars[tid]++; 12712301SN/A } 12722301SN/A} 12732301SN/A 12742292SN/A//////////////////////////////////////// 12752292SN/A// // 12762316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 12772292SN/A// // 12782292SN/A//////////////////////////////////////// 12792292SN/Atemplate <class Impl> 12806221Snate@binkert.orgThreadID 12812292SN/ADefaultCommit<Impl>::getCommittingThread() 12822292SN/A{ 12832292SN/A if (numThreads > 1) { 12842292SN/A switch (commitPolicy) { 12852292SN/A 12862292SN/A case Aggressive: 12872292SN/A //If Policy is Aggressive, commit will call 12882292SN/A //this function multiple times per 12892292SN/A //cycle 12902292SN/A return oldestReady(); 12912292SN/A 12922292SN/A case RoundRobin: 12932292SN/A return roundRobin(); 12942292SN/A 12952292SN/A case OldestReady: 12962292SN/A return oldestReady(); 12972292SN/A 12982292SN/A default: 12996221Snate@binkert.org return InvalidThreadID; 13002292SN/A } 13012292SN/A } else { 13023867Sbinkertn@umich.edu assert(!activeThreads->empty()); 13036221Snate@binkert.org ThreadID tid = activeThreads->front(); 13042292SN/A 13052292SN/A if (commitStatus[tid] == Running || 13062292SN/A commitStatus[tid] == Idle || 13072292SN/A commitStatus[tid] == FetchTrapPending) { 13082292SN/A return tid; 13092292SN/A } else { 13106221Snate@binkert.org return InvalidThreadID; 13112292SN/A } 13122292SN/A } 13132292SN/A} 13142292SN/A 13152292SN/Atemplate<class Impl> 13166221Snate@binkert.orgThreadID 13172292SN/ADefaultCommit<Impl>::roundRobin() 13182292SN/A{ 13196221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 13206221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 13212292SN/A 13222292SN/A while (pri_iter != end) { 13236221Snate@binkert.org ThreadID tid = *pri_iter; 13242292SN/A 13252292SN/A if (commitStatus[tid] == Running || 13262831Sksewell@umich.edu commitStatus[tid] == Idle || 13272831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 13282292SN/A 13292292SN/A if (rob->isHeadReady(tid)) { 13302292SN/A priority_list.erase(pri_iter); 13312292SN/A priority_list.push_back(tid); 13322292SN/A 13332292SN/A return tid; 13342292SN/A } 13352292SN/A } 13362292SN/A 13372292SN/A pri_iter++; 13382292SN/A } 13392292SN/A 13406221Snate@binkert.org return InvalidThreadID; 13412292SN/A} 13422292SN/A 13432292SN/Atemplate<class Impl> 13446221Snate@binkert.orgThreadID 13452292SN/ADefaultCommit<Impl>::oldestReady() 13462292SN/A{ 13472292SN/A unsigned oldest = 0; 13482292SN/A bool first = true; 13492292SN/A 13506221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 13516221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 13522292SN/A 13533867Sbinkertn@umich.edu while (threads != end) { 13546221Snate@binkert.org ThreadID tid = *threads++; 13552292SN/A 13562292SN/A if (!rob->isEmpty(tid) && 13572292SN/A (commitStatus[tid] == Running || 13582292SN/A commitStatus[tid] == Idle || 13592292SN/A commitStatus[tid] == FetchTrapPending)) { 13602292SN/A 13612292SN/A if (rob->isHeadReady(tid)) { 13622292SN/A 13632292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 13642292SN/A 13652292SN/A if (first) { 13662292SN/A oldest = tid; 13672292SN/A first = false; 13682292SN/A } else if (head_inst->seqNum < oldest) { 13692292SN/A oldest = tid; 13702292SN/A } 13712292SN/A } 13722292SN/A } 13732292SN/A } 13742292SN/A 13752292SN/A if (!first) { 13762292SN/A return oldest; 13772292SN/A } else { 13786221Snate@binkert.org return InvalidThreadID; 13792292SN/A } 13802292SN/A} 1381