commit_impl.hh revision 7684
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292965Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322292SN/A#include <algorithm> 332329SN/A#include <string> 342292SN/A 353577Sgblack@eecs.umich.edu#include "arch/utility.hh" 365953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 372292SN/A#include "base/loader/symtab.hh" 381060SN/A#include "base/timebuf.hh" 396221Snate@binkert.org#include "config/full_system.hh" 406658Snate@binkert.org#include "config/the_isa.hh" 416221Snate@binkert.org#include "config/use_checker.hh" 422292SN/A#include "cpu/exetrace.hh" 431717SN/A#include "cpu/o3/commit.hh" 442292SN/A#include "cpu/o3/thread_state.hh" 456221Snate@binkert.org#include "params/DerivO3CPU.hh" 462292SN/A 472790Sktlim@umich.edu#if USE_CHECKER 482790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 492790Sktlim@umich.edu#endif 502790Sktlim@umich.edu 516221Snate@binkert.orgusing namespace std; 525529Snate@binkert.org 531061SN/Atemplate <class Impl> 542292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 556221Snate@binkert.org ThreadID _tid) 565606Snate@binkert.org : Event(CPU_Tick_Pri), commit(_commit), tid(_tid) 571060SN/A{ 585769Snate@binkert.org this->setFlags(AutoDelete); 591060SN/A} 601060SN/A 611061SN/Atemplate <class Impl> 621060SN/Avoid 632292SN/ADefaultCommit<Impl>::TrapEvent::process() 641062SN/A{ 652316SN/A // This will get reset by commit if it was switched out at the 662316SN/A // time of this event processing. 672292SN/A commit->trapSquash[tid] = true; 682292SN/A} 692292SN/A 702292SN/Atemplate <class Impl> 712292SN/Aconst char * 725336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 732292SN/A{ 744873Sstever@eecs.umich.edu return "Trap"; 752292SN/A} 762292SN/A 772292SN/Atemplate <class Impl> 785529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 794329Sktlim@umich.edu : cpu(_cpu), 804329Sktlim@umich.edu squashCounter(0), 812292SN/A iewToCommitDelay(params->iewToCommitDelay), 822292SN/A commitToIEWDelay(params->commitToIEWDelay), 832292SN/A renameToROBDelay(params->renameToROBDelay), 842292SN/A fetchToCommitDelay(params->commitToFetchDelay), 852292SN/A renameWidth(params->renameWidth), 862292SN/A commitWidth(params->commitWidth), 875529Snate@binkert.org numThreads(params->numThreads), 882843Sktlim@umich.edu drainPending(false), 892316SN/A switchedOut(false), 902874Sktlim@umich.edu trapLatency(params->trapLatency) 912292SN/A{ 922292SN/A _status = Active; 932292SN/A _nextStatus = Inactive; 942980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 952292SN/A 962292SN/A //Convert string to lowercase 972292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 982292SN/A (int(*)(int)) tolower); 992292SN/A 1002292SN/A //Assign commit policy 1012292SN/A if (policy == "aggressive"){ 1022292SN/A commitPolicy = Aggressive; 1032292SN/A 1044329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive."); 1052292SN/A } else if (policy == "roundrobin"){ 1062292SN/A commitPolicy = RoundRobin; 1072292SN/A 1082292SN/A //Set-Up Priority List 1096221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1102292SN/A priority_list.push_back(tid); 1112292SN/A } 1122292SN/A 1134329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 1142292SN/A } else if (policy == "oldestready"){ 1152292SN/A commitPolicy = OldestReady; 1162292SN/A 1174329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1182292SN/A } else { 1192292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1202292SN/A "RoundRobin,OldestReady}"); 1212292SN/A } 1222292SN/A 1236221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1246221Snate@binkert.org commitStatus[tid] = Idle; 1256221Snate@binkert.org changedROBNumEntries[tid] = false; 1266221Snate@binkert.org checkEmptyROB[tid] = false; 1276221Snate@binkert.org trapInFlight[tid] = false; 1286221Snate@binkert.org committedStores[tid] = false; 1296221Snate@binkert.org trapSquash[tid] = false; 1306221Snate@binkert.org tcSquash[tid] = false; 1316221Snate@binkert.org microPC[tid] = 0; 1326221Snate@binkert.org nextMicroPC[tid] = 0; 1336221Snate@binkert.org PC[tid] = 0; 1346221Snate@binkert.org nextPC[tid] = 0; 1356221Snate@binkert.org nextNPC[tid] = 0; 1362292SN/A } 1373640Sktlim@umich.edu#if FULL_SYSTEM 1383640Sktlim@umich.edu interrupt = NoFault; 1393640Sktlim@umich.edu#endif 1402292SN/A} 1412292SN/A 1422292SN/Atemplate <class Impl> 1432292SN/Astd::string 1442292SN/ADefaultCommit<Impl>::name() const 1452292SN/A{ 1462292SN/A return cpu->name() + ".commit"; 1472292SN/A} 1482292SN/A 1492292SN/Atemplate <class Impl> 1502292SN/Avoid 1512292SN/ADefaultCommit<Impl>::regStats() 1522132SN/A{ 1532301SN/A using namespace Stats; 1541062SN/A commitCommittedInsts 1551062SN/A .name(name() + ".commitCommittedInsts") 1561062SN/A .desc("The number of committed instructions") 1571062SN/A .prereq(commitCommittedInsts); 1581062SN/A commitSquashedInsts 1591062SN/A .name(name() + ".commitSquashedInsts") 1601062SN/A .desc("The number of squashed insts skipped by commit") 1611062SN/A .prereq(commitSquashedInsts); 1621062SN/A commitSquashEvents 1631062SN/A .name(name() + ".commitSquashEvents") 1641062SN/A .desc("The number of times commit is told to squash") 1651062SN/A .prereq(commitSquashEvents); 1661062SN/A commitNonSpecStalls 1671062SN/A .name(name() + ".commitNonSpecStalls") 1681062SN/A .desc("The number of times commit has been forced to stall to " 1691062SN/A "communicate backwards") 1701062SN/A .prereq(commitNonSpecStalls); 1711062SN/A branchMispredicts 1721062SN/A .name(name() + ".branchMispredicts") 1731062SN/A .desc("The number of times a branch was mispredicted") 1741062SN/A .prereq(branchMispredicts); 1752292SN/A numCommittedDist 1761062SN/A .init(0,commitWidth,1) 1771062SN/A .name(name() + ".COM:committed_per_cycle") 1781062SN/A .desc("Number of insts commited each cycle") 1791062SN/A .flags(Stats::pdf) 1801062SN/A ; 1812301SN/A 1822316SN/A statComInst 1836221Snate@binkert.org .init(cpu->numThreads) 1842301SN/A .name(name() + ".COM:count") 1852301SN/A .desc("Number of instructions committed") 1862301SN/A .flags(total) 1872301SN/A ; 1882301SN/A 1892316SN/A statComSwp 1906221Snate@binkert.org .init(cpu->numThreads) 1912301SN/A .name(name() + ".COM:swp_count") 1922301SN/A .desc("Number of s/w prefetches committed") 1932301SN/A .flags(total) 1942301SN/A ; 1952301SN/A 1962316SN/A statComRefs 1976221Snate@binkert.org .init(cpu->numThreads) 1982301SN/A .name(name() + ".COM:refs") 1992301SN/A .desc("Number of memory references committed") 2002301SN/A .flags(total) 2012301SN/A ; 2022301SN/A 2032316SN/A statComLoads 2046221Snate@binkert.org .init(cpu->numThreads) 2052301SN/A .name(name() + ".COM:loads") 2062301SN/A .desc("Number of loads committed") 2072301SN/A .flags(total) 2082301SN/A ; 2092301SN/A 2102316SN/A statComMembars 2116221Snate@binkert.org .init(cpu->numThreads) 2122301SN/A .name(name() + ".COM:membars") 2132301SN/A .desc("Number of memory barriers committed") 2142301SN/A .flags(total) 2152301SN/A ; 2162301SN/A 2172316SN/A statComBranches 2186221Snate@binkert.org .init(cpu->numThreads) 2192301SN/A .name(name() + ".COM:branches") 2202301SN/A .desc("Number of branches committed") 2212301SN/A .flags(total) 2222301SN/A ; 2232301SN/A 2242316SN/A commitEligible 2256221Snate@binkert.org .init(cpu->numThreads) 2262301SN/A .name(name() + ".COM:bw_limited") 2272301SN/A .desc("number of insts not committed due to BW limits") 2282301SN/A .flags(total) 2292301SN/A ; 2302301SN/A 2312316SN/A commitEligibleSamples 2322301SN/A .name(name() + ".COM:bw_lim_events") 2332301SN/A .desc("number cycles where commit BW limit reached") 2342301SN/A ; 2351062SN/A} 2361062SN/A 2371062SN/Atemplate <class Impl> 2381062SN/Avoid 2392980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2402292SN/A{ 2412292SN/A thread = threads; 2422292SN/A} 2432292SN/A 2442292SN/Atemplate <class Impl> 2452292SN/Avoid 2462292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2471060SN/A{ 2481060SN/A timeBuffer = tb_ptr; 2491060SN/A 2501060SN/A // Setup wire to send information back to IEW. 2511060SN/A toIEW = timeBuffer->getWire(0); 2521060SN/A 2531060SN/A // Setup wire to read data from IEW (for the ROB). 2541060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2551060SN/A} 2561060SN/A 2571061SN/Atemplate <class Impl> 2581060SN/Avoid 2592292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2602292SN/A{ 2612292SN/A fetchQueue = fq_ptr; 2622292SN/A 2632292SN/A // Setup wire to get instructions from rename (for the ROB). 2642292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2652292SN/A} 2662292SN/A 2672292SN/Atemplate <class Impl> 2682292SN/Avoid 2692292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2701060SN/A{ 2711060SN/A renameQueue = rq_ptr; 2721060SN/A 2731060SN/A // Setup wire to get instructions from rename (for the ROB). 2741060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2751060SN/A} 2761060SN/A 2771061SN/Atemplate <class Impl> 2781060SN/Avoid 2792292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2801060SN/A{ 2811060SN/A iewQueue = iq_ptr; 2821060SN/A 2831060SN/A // Setup wire to get instructions from IEW. 2841060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2851060SN/A} 2861060SN/A 2871061SN/Atemplate <class Impl> 2881060SN/Avoid 2892292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2902292SN/A{ 2912292SN/A iewStage = iew_stage; 2922292SN/A} 2932292SN/A 2942292SN/Atemplate<class Impl> 2952292SN/Avoid 2966221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2972292SN/A{ 2982292SN/A activeThreads = at_ptr; 2992292SN/A} 3002292SN/A 3012292SN/Atemplate <class Impl> 3022292SN/Avoid 3032292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3042292SN/A{ 3056221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3066221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3072292SN/A} 3082292SN/A 3092292SN/Atemplate <class Impl> 3102292SN/Avoid 3112292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3121060SN/A{ 3131060SN/A rob = rob_ptr; 3141060SN/A} 3151060SN/A 3161061SN/Atemplate <class Impl> 3171060SN/Avoid 3182292SN/ADefaultCommit<Impl>::initStage() 3191060SN/A{ 3202292SN/A rob->setActiveThreads(activeThreads); 3212292SN/A rob->resetEntries(); 3221060SN/A 3232292SN/A // Broadcast the number of free entries. 3246221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3256221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3266221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3276221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3281060SN/A } 3291060SN/A 3304329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3314329Sktlim@umich.edu // start of the simulation, so it starts as active. 3324329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3334329Sktlim@umich.edu 3342292SN/A cpu->activityThisCycle(); 3355100Ssaidi@eecs.umich.edu trapLatency = cpu->ticks(trapLatency); 3361060SN/A} 3371060SN/A 3381061SN/Atemplate <class Impl> 3392863Sktlim@umich.edubool 3402843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3411060SN/A{ 3422843Sktlim@umich.edu drainPending = true; 3432863Sktlim@umich.edu 3442863Sktlim@umich.edu return false; 3452316SN/A} 3462316SN/A 3472316SN/Atemplate <class Impl> 3482316SN/Avoid 3492843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3502316SN/A{ 3512316SN/A switchedOut = true; 3522843Sktlim@umich.edu drainPending = false; 3532307SN/A rob->switchOut(); 3542307SN/A} 3552307SN/A 3562307SN/Atemplate <class Impl> 3572307SN/Avoid 3582843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3592843Sktlim@umich.edu{ 3602864Sktlim@umich.edu drainPending = false; 3612843Sktlim@umich.edu} 3622843Sktlim@umich.edu 3632843Sktlim@umich.edutemplate <class Impl> 3642843Sktlim@umich.eduvoid 3652307SN/ADefaultCommit<Impl>::takeOverFrom() 3662307SN/A{ 3672316SN/A switchedOut = false; 3682307SN/A _status = Active; 3692307SN/A _nextStatus = Inactive; 3706221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3716221Snate@binkert.org commitStatus[tid] = Idle; 3726221Snate@binkert.org changedROBNumEntries[tid] = false; 3736221Snate@binkert.org trapSquash[tid] = false; 3746221Snate@binkert.org tcSquash[tid] = false; 3752307SN/A } 3762307SN/A squashCounter = 0; 3772307SN/A rob->takeOverFrom(); 3782307SN/A} 3792307SN/A 3802307SN/Atemplate <class Impl> 3812307SN/Avoid 3822292SN/ADefaultCommit<Impl>::updateStatus() 3832132SN/A{ 3842316SN/A // reset ROB changed variable 3856221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3866221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3873867Sbinkertn@umich.edu 3883867Sbinkertn@umich.edu while (threads != end) { 3896221Snate@binkert.org ThreadID tid = *threads++; 3903867Sbinkertn@umich.edu 3912316SN/A changedROBNumEntries[tid] = false; 3922316SN/A 3932316SN/A // Also check if any of the threads has a trap pending 3942316SN/A if (commitStatus[tid] == TrapPending || 3952316SN/A commitStatus[tid] == FetchTrapPending) { 3962316SN/A _nextStatus = Active; 3972316SN/A } 3982292SN/A } 3992292SN/A 4002292SN/A if (_nextStatus == Inactive && _status == Active) { 4012292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4022733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4032292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4042292SN/A DPRINTF(Activity, "Activating stage.\n"); 4052733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4062292SN/A } 4072292SN/A 4082292SN/A _status = _nextStatus; 4092292SN/A} 4102292SN/A 4112292SN/Atemplate <class Impl> 4122292SN/Avoid 4132292SN/ADefaultCommit<Impl>::setNextStatus() 4142292SN/A{ 4152292SN/A int squashes = 0; 4162292SN/A 4176221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4186221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4192292SN/A 4203867Sbinkertn@umich.edu while (threads != end) { 4216221Snate@binkert.org ThreadID tid = *threads++; 4222292SN/A 4232292SN/A if (commitStatus[tid] == ROBSquashing) { 4242292SN/A squashes++; 4252292SN/A } 4262292SN/A } 4272292SN/A 4282702Sktlim@umich.edu squashCounter = squashes; 4292292SN/A 4302292SN/A // If commit is currently squashing, then it will have activity for the 4312292SN/A // next cycle. Set its next status as active. 4322292SN/A if (squashCounter) { 4332292SN/A _nextStatus = Active; 4342292SN/A } 4352292SN/A} 4362292SN/A 4372292SN/Atemplate <class Impl> 4382292SN/Abool 4392292SN/ADefaultCommit<Impl>::changedROBEntries() 4402292SN/A{ 4416221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4426221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4432292SN/A 4443867Sbinkertn@umich.edu while (threads != end) { 4456221Snate@binkert.org ThreadID tid = *threads++; 4462292SN/A 4472292SN/A if (changedROBNumEntries[tid]) { 4482292SN/A return true; 4492292SN/A } 4502292SN/A } 4512292SN/A 4522292SN/A return false; 4532292SN/A} 4542292SN/A 4552292SN/Atemplate <class Impl> 4566221Snate@binkert.orgsize_t 4576221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 4582292SN/A{ 4592292SN/A return rob->numFreeEntries(tid); 4602292SN/A} 4612292SN/A 4622292SN/Atemplate <class Impl> 4632292SN/Avoid 4646221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 4652292SN/A{ 4662292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4672292SN/A 4682292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4692292SN/A 4705606Snate@binkert.org cpu->schedule(trap, curTick + trapLatency); 4714035Sktlim@umich.edu trapInFlight[tid] = true; 4722292SN/A} 4732292SN/A 4742292SN/Atemplate <class Impl> 4752292SN/Avoid 4766221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 4772292SN/A{ 4784035Sktlim@umich.edu assert(!trapInFlight[tid]); 4792680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4802292SN/A 4812680Sktlim@umich.edu tcSquash[tid] = true; 4822292SN/A} 4832292SN/A 4842292SN/Atemplate <class Impl> 4852292SN/Avoid 4866221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 4872292SN/A{ 4882292SN/A // If we want to include the squashing instruction in the squash, 4892292SN/A // then use one older sequence number. 4902292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4912292SN/A // all instructions of this thread. 4922292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 4934035Sktlim@umich.edu 0 : rob->readHeadInst(tid)->seqNum - 1; 4942292SN/A 4952292SN/A // All younger instructions will be squashed. Set the sequence 4962292SN/A // number as the youngest instruction in the ROB (0 in this case. 4972292SN/A // Hopefully nothing breaks.) 4982292SN/A youngestSeqNum[tid] = 0; 4992292SN/A 5002292SN/A rob->squash(squashed_inst, tid); 5012292SN/A changedROBNumEntries[tid] = true; 5022292SN/A 5032292SN/A // Send back the sequence number of the squashed instruction. 5042292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5052292SN/A 5062292SN/A // Send back the squash signal to tell stages that they should 5072292SN/A // squash. 5082292SN/A toIEW->commitInfo[tid].squash = true; 5092292SN/A 5102292SN/A // Send back the rob squashing signal so other stages know that 5112292SN/A // the ROB is in the process of squashing. 5122292SN/A toIEW->commitInfo[tid].robSquashing = true; 5132292SN/A 5142292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5152292SN/A 5162316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5173795Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextNPC = nextPC[tid]; 5184636Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid]; 5192316SN/A} 5202292SN/A 5212316SN/Atemplate <class Impl> 5222316SN/Avoid 5236221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5242316SN/A{ 5252316SN/A squashAll(tid); 5262316SN/A 5272316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5282316SN/A 5292316SN/A thread[tid]->trapPending = false; 5302316SN/A thread[tid]->inSyscall = false; 5314035Sktlim@umich.edu trapInFlight[tid] = false; 5322316SN/A 5332316SN/A trapSquash[tid] = false; 5342316SN/A 5352316SN/A commitStatus[tid] = ROBSquashing; 5362316SN/A cpu->activityThisCycle(); 5372316SN/A} 5382316SN/A 5392316SN/Atemplate <class Impl> 5402316SN/Avoid 5416221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 5422316SN/A{ 5432316SN/A squashAll(tid); 5442292SN/A 5452680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5462292SN/A 5472292SN/A thread[tid]->inSyscall = false; 5482292SN/A assert(!thread[tid]->trapPending); 5492316SN/A 5502292SN/A commitStatus[tid] = ROBSquashing; 5512292SN/A cpu->activityThisCycle(); 5522292SN/A 5532680Sktlim@umich.edu tcSquash[tid] = false; 5542292SN/A} 5552292SN/A 5562292SN/Atemplate <class Impl> 5572292SN/Avoid 5582292SN/ADefaultCommit<Impl>::tick() 5592292SN/A{ 5602292SN/A wroteToTimeBuffer = false; 5612292SN/A _nextStatus = Inactive; 5622292SN/A 5632843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5642843Sktlim@umich.edu cpu->signalDrained(); 5652843Sktlim@umich.edu drainPending = false; 5662316SN/A return; 5672316SN/A } 5682316SN/A 5693867Sbinkertn@umich.edu if (activeThreads->empty()) 5702875Sksewell@umich.edu return; 5712875Sksewell@umich.edu 5726221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5736221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5742292SN/A 5752316SN/A // Check if any of the threads are done squashing. Change the 5762316SN/A // status if they are done. 5773867Sbinkertn@umich.edu while (threads != end) { 5786221Snate@binkert.org ThreadID tid = *threads++; 5792292SN/A 5804035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 5814035Sktlim@umich.edu // this cycle. 5824035Sktlim@umich.edu committedStores[tid] = false; 5834035Sktlim@umich.edu 5842292SN/A if (commitStatus[tid] == ROBSquashing) { 5852292SN/A 5862292SN/A if (rob->isDoneSquashing(tid)) { 5872292SN/A commitStatus[tid] = Running; 5882292SN/A } else { 5892292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5902877Sksewell@umich.edu " insts this cycle.\n", tid); 5912702Sktlim@umich.edu rob->doSquash(tid); 5922702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5932702Sktlim@umich.edu wroteToTimeBuffer = true; 5942292SN/A } 5952292SN/A } 5962292SN/A } 5972292SN/A 5982292SN/A commit(); 5992292SN/A 6002292SN/A markCompletedInsts(); 6012292SN/A 6023867Sbinkertn@umich.edu threads = activeThreads->begin(); 6032292SN/A 6043867Sbinkertn@umich.edu while (threads != end) { 6056221Snate@binkert.org ThreadID tid = *threads++; 6062292SN/A 6072292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6082292SN/A // The ROB has more instructions it can commit. Its next status 6092292SN/A // will be active. 6102292SN/A _nextStatus = Active; 6112292SN/A 6122292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6132292SN/A 6142292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6152292SN/A " ROB and ready to commit\n", 6162292SN/A tid, inst->seqNum, inst->readPC()); 6172292SN/A 6182292SN/A } else if (!rob->isEmpty(tid)) { 6192292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6202292SN/A 6212292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6222292SN/A "%#x is head of ROB and not ready\n", 6232292SN/A tid, inst->seqNum, inst->readPC()); 6242292SN/A } 6252292SN/A 6262292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6272292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6282292SN/A } 6292292SN/A 6302292SN/A 6312292SN/A if (wroteToTimeBuffer) { 6322316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6332292SN/A cpu->activityThisCycle(); 6342292SN/A } 6352292SN/A 6362292SN/A updateStatus(); 6372292SN/A} 6382292SN/A 6394035Sktlim@umich.edu#if FULL_SYSTEM 6402292SN/Atemplate <class Impl> 6412292SN/Avoid 6424035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 6432292SN/A{ 6443640Sktlim@umich.edu if (interrupt != NoFault) { 6452316SN/A // Wait until the ROB is empty and all stores have drained in 6462316SN/A // order to enter the interrupt. 6472292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6483633Sktlim@umich.edu // Squash or record that I need to squash this cycle if 6493633Sktlim@umich.edu // an interrupt needed to be handled. 6503633Sktlim@umich.edu DPRINTF(Commit, "Interrupt detected.\n"); 6513633Sktlim@umich.edu 6524035Sktlim@umich.edu // Clear the interrupt now that it's going to be handled 6534035Sktlim@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 6544035Sktlim@umich.edu 6552292SN/A assert(!thread[0]->inSyscall); 6562292SN/A thread[0]->inSyscall = true; 6572292SN/A 6583633Sktlim@umich.edu // CPU will handle interrupt. 6593640Sktlim@umich.edu cpu->processInterrupts(interrupt); 6602292SN/A 6613633Sktlim@umich.edu thread[0]->inSyscall = false; 6623633Sktlim@umich.edu 6632292SN/A commitStatus[0] = TrapPending; 6642292SN/A 6652292SN/A // Generate trap squash event. 6662292SN/A generateTrapEvent(0); 6672292SN/A 6683640Sktlim@umich.edu interrupt = NoFault; 6692292SN/A } else { 6702292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6712292SN/A } 6724035Sktlim@umich.edu } else if (commitStatus[0] != TrapPending && 6735704Snate@binkert.org cpu->checkInterrupts(cpu->tcBase(0)) && 6744035Sktlim@umich.edu !trapSquash[0] && 6754035Sktlim@umich.edu !tcSquash[0]) { 6763640Sktlim@umich.edu // Process interrupts if interrupts are enabled, not in PAL 6773640Sktlim@umich.edu // mode, and no other traps or external squashes are currently 6783640Sktlim@umich.edu // pending. 6793640Sktlim@umich.edu // @todo: Allow other threads to handle interrupts. 6803640Sktlim@umich.edu 6813640Sktlim@umich.edu // Get any interrupt that happened 6823640Sktlim@umich.edu interrupt = cpu->getInterrupts(); 6833640Sktlim@umich.edu 6843640Sktlim@umich.edu if (interrupt != NoFault) { 6853640Sktlim@umich.edu // Tell fetch that there is an interrupt pending. This 6863640Sktlim@umich.edu // will make fetch wait until it sees a non PAL-mode PC, 6873640Sktlim@umich.edu // at which point it stops fetching instructions. 6883640Sktlim@umich.edu toIEW->commitInfo[0].interruptPending = true; 6893640Sktlim@umich.edu } 6901060SN/A } 6914035Sktlim@umich.edu} 6924035Sktlim@umich.edu#endif // FULL_SYSTEM 6933634Sktlim@umich.edu 6944035Sktlim@umich.edutemplate <class Impl> 6954035Sktlim@umich.eduvoid 6964035Sktlim@umich.eduDefaultCommit<Impl>::commit() 6974035Sktlim@umich.edu{ 6984035Sktlim@umich.edu 6994035Sktlim@umich.edu#if FULL_SYSTEM 7004035Sktlim@umich.edu // Check for any interrupt, and start processing it. Or if we 7014035Sktlim@umich.edu // have an outstanding interrupt and are at a point when it is 7024035Sktlim@umich.edu // valid to take an interrupt, process it. 7035704Snate@binkert.org if (cpu->checkInterrupts(cpu->tcBase(0))) { 7044035Sktlim@umich.edu handleInterrupt(); 7054035Sktlim@umich.edu } 7061060SN/A#endif // FULL_SYSTEM 7071060SN/A 7081060SN/A //////////////////////////////////// 7092316SN/A // Check for any possible squashes, handle them first 7101060SN/A //////////////////////////////////// 7116221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7126221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7131060SN/A 7143867Sbinkertn@umich.edu while (threads != end) { 7156221Snate@binkert.org ThreadID tid = *threads++; 7161060SN/A 7172292SN/A // Not sure which one takes priority. I think if we have 7182292SN/A // both, that's a bad sign. 7192292SN/A if (trapSquash[tid] == true) { 7202680Sktlim@umich.edu assert(!tcSquash[tid]); 7212292SN/A squashFromTrap(tid); 7222680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7234035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 7242680Sktlim@umich.edu squashFromTC(tid); 7252292SN/A } 7261061SN/A 7272292SN/A // Squashed sequence number must be older than youngest valid 7282292SN/A // instruction in the ROB. This prevents squashes from younger 7292292SN/A // instructions overriding squashes from older instructions. 7302292SN/A if (fromIEW->squash[tid] && 7312292SN/A commitStatus[tid] != TrapPending && 7322292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7331061SN/A 7342292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7352292SN/A tid, 7362292SN/A fromIEW->mispredPC[tid], 7372292SN/A fromIEW->squashedSeqNum[tid]); 7381061SN/A 7392292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7402292SN/A tid, 7412292SN/A fromIEW->nextPC[tid]); 7421061SN/A 7432292SN/A commitStatus[tid] = ROBSquashing; 7441061SN/A 7452292SN/A // If we want to include the squashing instruction in the squash, 7462292SN/A // then use one older sequence number. 7472292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7481062SN/A 7492935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 7502292SN/A squashed_inst--; 7512935Sksewell@umich.edu } 7524035Sktlim@umich.edu 7532292SN/A // All younger instructions will be squashed. Set the sequence 7542292SN/A // number as the youngest instruction in the ROB. 7552292SN/A youngestSeqNum[tid] = squashed_inst; 7562292SN/A 7573093Sksewell@umich.edu rob->squash(squashed_inst, tid); 7582292SN/A changedROBNumEntries[tid] = true; 7592292SN/A 7602292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7612292SN/A 7622292SN/A toIEW->commitInfo[tid].squash = true; 7632292SN/A 7642292SN/A // Send back the rob squashing signal so other stages know that 7652292SN/A // the ROB is in the process of squashing. 7662292SN/A toIEW->commitInfo[tid].robSquashing = true; 7672292SN/A 7682292SN/A toIEW->commitInfo[tid].branchMispredict = 7692292SN/A fromIEW->branchMispredict[tid]; 7702292SN/A 7712292SN/A toIEW->commitInfo[tid].branchTaken = 7722292SN/A fromIEW->branchTaken[tid]; 7732292SN/A 7742292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7753795Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid]; 7764636Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid]; 7772292SN/A 7782316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7792292SN/A 7802292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7812292SN/A ++branchMispredicts; 7822292SN/A } 7831062SN/A } 7842292SN/A 7851060SN/A } 7861060SN/A 7872292SN/A setNextStatus(); 7882292SN/A 7892292SN/A if (squashCounter != numThreads) { 7901061SN/A // If we're not currently squashing, then get instructions. 7911060SN/A getInsts(); 7921060SN/A 7931061SN/A // Try to commit any instructions. 7941060SN/A commitInsts(); 7951060SN/A } 7961060SN/A 7972292SN/A //Check for any activity 7983867Sbinkertn@umich.edu threads = activeThreads->begin(); 7992292SN/A 8003867Sbinkertn@umich.edu while (threads != end) { 8016221Snate@binkert.org ThreadID tid = *threads++; 8022292SN/A 8032292SN/A if (changedROBNumEntries[tid]) { 8042292SN/A toIEW->commitInfo[tid].usedROB = true; 8052292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8062292SN/A 8072292SN/A wroteToTimeBuffer = true; 8082292SN/A changedROBNumEntries[tid] = false; 8094035Sktlim@umich.edu if (rob->isEmpty(tid)) 8104035Sktlim@umich.edu checkEmptyROB[tid] = true; 8112292SN/A } 8124035Sktlim@umich.edu 8134035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8144035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 8154035Sktlim@umich.edu // stage has received any information regarding stores that 8164035Sktlim@umich.edu // committed. 8174035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 8184035Sktlim@umich.edu // on the same cycle as when stores have been committed. 8194035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 8204035Sktlim@umich.edu // commit and IEW. 8214035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 8225557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 8234035Sktlim@umich.edu checkEmptyROB[tid] = false; 8244035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 8254035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 8264035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8274035Sktlim@umich.edu wroteToTimeBuffer = true; 8284035Sktlim@umich.edu } 8294035Sktlim@umich.edu 8301060SN/A } 8311060SN/A} 8321060SN/A 8331061SN/Atemplate <class Impl> 8341060SN/Avoid 8352292SN/ADefaultCommit<Impl>::commitInsts() 8361060SN/A{ 8371060SN/A //////////////////////////////////// 8381060SN/A // Handle commit 8392316SN/A // Note that commit will be handled prior to putting new 8402316SN/A // instructions in the ROB so that the ROB only tries to commit 8412316SN/A // instructions it has in this current cycle, and not instructions 8422316SN/A // it is writing in during this cycle. Can't commit and squash 8432316SN/A // things at the same time... 8441060SN/A //////////////////////////////////// 8451060SN/A 8462292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8471060SN/A 8481060SN/A unsigned num_committed = 0; 8491060SN/A 8502292SN/A DynInstPtr head_inst; 8512316SN/A 8521060SN/A // Commit as many instructions as possible until the commit bandwidth 8531060SN/A // limit is reached, or it becomes impossible to commit any more. 8542292SN/A while (num_committed < commitWidth) { 8552292SN/A int commit_thread = getCommittingThread(); 8561060SN/A 8572292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8582292SN/A break; 8592292SN/A 8602292SN/A head_inst = rob->readHeadInst(commit_thread); 8612292SN/A 8626221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 8632292SN/A 8642292SN/A assert(tid == commit_thread); 8652292SN/A 8662292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8672292SN/A head_inst->seqNum, tid); 8682132SN/A 8692316SN/A // If the head instruction is squashed, it is ready to retire 8702316SN/A // (be removed from the ROB) at any time. 8711060SN/A if (head_inst->isSquashed()) { 8721060SN/A 8732292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8741060SN/A "ROB.\n"); 8751060SN/A 8762292SN/A rob->retireHead(commit_thread); 8771060SN/A 8781062SN/A ++commitSquashedInsts; 8791062SN/A 8802292SN/A // Record that the number of ROB entries has changed. 8812292SN/A changedROBNumEntries[tid] = true; 8821060SN/A } else { 8832292SN/A PC[tid] = head_inst->readPC(); 8842292SN/A nextPC[tid] = head_inst->readNextPC(); 8852935Sksewell@umich.edu nextNPC[tid] = head_inst->readNextNPC(); 8864636Sgblack@eecs.umich.edu nextMicroPC[tid] = head_inst->readNextMicroPC(); 8872292SN/A 8881060SN/A // Increment the total number of non-speculative instructions 8891060SN/A // executed. 8901060SN/A // Hack for now: it really shouldn't happen until after the 8911061SN/A // commit is deemed to be successful, but this count is needed 8921061SN/A // for syscalls. 8932292SN/A thread[tid]->funcExeInst++; 8941060SN/A 8951060SN/A // Try to commit the head instruction. 8961060SN/A bool commit_success = commitHead(head_inst, num_committed); 8971060SN/A 8981062SN/A if (commit_success) { 8991060SN/A ++num_committed; 9001060SN/A 9012292SN/A changedROBNumEntries[tid] = true; 9022292SN/A 9032292SN/A // Set the doneSeqNum to the youngest committed instruction. 9042292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9051060SN/A 9061062SN/A ++commitCommittedInsts; 9071062SN/A 9082292SN/A // To match the old model, don't count nops and instruction 9092292SN/A // prefetches towards the total commit count. 9102292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9112292SN/A cpu->instDone(tid); 9121062SN/A } 9132292SN/A 9142292SN/A PC[tid] = nextPC[tid]; 9152935Sksewell@umich.edu nextPC[tid] = nextNPC[tid]; 9162935Sksewell@umich.edu nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 9174636Sgblack@eecs.umich.edu microPC[tid] = nextMicroPC[tid]; 9184636Sgblack@eecs.umich.edu nextMicroPC[tid] = microPC[tid] + 1; 9192935Sksewell@umich.edu 9202292SN/A int count = 0; 9212292SN/A Addr oldpc; 9225108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 9235108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 9245108Sgblack@eecs.umich.edu assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 9252292SN/A do { 9262292SN/A oldpc = PC[tid]; 9275108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 9282292SN/A count++; 9292292SN/A } while (oldpc != PC[tid]); 9302292SN/A if (count > 1) { 9315108Sgblack@eecs.umich.edu DPRINTF(Commit, 9325108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 9332292SN/A break; 9342292SN/A } 9351060SN/A } else { 9362292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9372292SN/A "[tid:%i] [sn:%i].\n", 9382292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9391060SN/A break; 9401060SN/A } 9411060SN/A } 9421060SN/A } 9431062SN/A 9441063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9452292SN/A numCommittedDist.sample(num_committed); 9462307SN/A 9472307SN/A if (num_committed == commitWidth) { 9482349SN/A commitEligibleSamples++; 9492307SN/A } 9501060SN/A} 9511060SN/A 9521061SN/Atemplate <class Impl> 9531060SN/Abool 9542292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9551060SN/A{ 9561060SN/A assert(head_inst); 9571060SN/A 9586221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 9592292SN/A 9602316SN/A // If the instruction is not executed yet, then it will need extra 9612316SN/A // handling. Signal backwards that it should be executed. 9621061SN/A if (!head_inst->isExecuted()) { 9631061SN/A // Keep this number correct. We have not yet actually executed 9641061SN/A // and committed this instruction. 9652292SN/A thread[tid]->funcExeInst--; 9661062SN/A 9672292SN/A if (head_inst->isNonSpeculative() || 9682348SN/A head_inst->isStoreConditional() || 9692292SN/A head_inst->isMemBarrier() || 9702292SN/A head_inst->isWriteBarrier()) { 9712316SN/A 9722316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9732316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9742316SN/A head_inst->seqNum, head_inst->readPC()); 9752316SN/A 9765557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 9772292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9782292SN/A return false; 9792292SN/A } 9802292SN/A 9812292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9821061SN/A 9831061SN/A // Change the instruction so it won't try to commit again until 9841061SN/A // it is executed. 9851061SN/A head_inst->clearCanCommit(); 9861061SN/A 9871062SN/A ++commitNonSpecStalls; 9881062SN/A 9891061SN/A return false; 9902292SN/A } else if (head_inst->isLoad()) { 9915557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 9924035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9934035Sktlim@umich.edu return false; 9944035Sktlim@umich.edu } 9954035Sktlim@umich.edu 9964035Sktlim@umich.edu assert(head_inst->uncacheable()); 9972292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9982292SN/A head_inst->seqNum, head_inst->readPC()); 9992292SN/A 10002292SN/A // Send back the non-speculative instruction's sequence 10012316SN/A // number. Tell the lsq to re-execute the load. 10022292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10032292SN/A toIEW->commitInfo[tid].uncached = true; 10042292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10052292SN/A 10062292SN/A head_inst->clearCanCommit(); 10072292SN/A 10082292SN/A return false; 10091061SN/A } else { 10102292SN/A panic("Trying to commit un-executed instruction " 10111061SN/A "of unknown type!\n"); 10121061SN/A } 10131060SN/A } 10141060SN/A 10152316SN/A if (head_inst->isThreadSync()) { 10162292SN/A // Not handled for now. 10172316SN/A panic("Thread sync instructions are not handled yet.\n"); 10182132SN/A } 10192132SN/A 10204035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 10214035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 10224035Sktlim@umich.edu 10232316SN/A // Stores mark themselves as completed. 10244035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 10252310SN/A head_inst->setCompleted(); 10262310SN/A } 10272310SN/A 10282733Sktlim@umich.edu#if USE_CHECKER 10292316SN/A // Use checker prior to updating anything due to traps or PC 10302316SN/A // based events. 10312316SN/A if (cpu->checker) { 10322732Sktlim@umich.edu cpu->checker->verify(head_inst); 10331060SN/A } 10342733Sktlim@umich.edu#endif 10351060SN/A 10362112SN/A if (inst_fault != NoFault) { 10372316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10382316SN/A head_inst->seqNum, head_inst->readPC()); 10392292SN/A 10405557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 10412316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10422316SN/A return false; 10432316SN/A } 10442310SN/A 10454035Sktlim@umich.edu head_inst->setCompleted(); 10464035Sktlim@umich.edu 10472733Sktlim@umich.edu#if USE_CHECKER 10482316SN/A if (cpu->checker && head_inst->isStore()) { 10492732Sktlim@umich.edu cpu->checker->verify(head_inst); 10502316SN/A } 10512733Sktlim@umich.edu#endif 10522292SN/A 10532316SN/A assert(!thread[tid]->inSyscall); 10542292SN/A 10552316SN/A // Mark that we're in state update mode so that the trap's 10562316SN/A // execution doesn't generate extra squashes. 10572316SN/A thread[tid]->inSyscall = true; 10582292SN/A 10592316SN/A // Execute the trap. Although it's slightly unrealistic in 10602316SN/A // terms of timing (as it doesn't wait for the full timing of 10612316SN/A // the trap event to complete before updating state), it's 10622316SN/A // needed to update the state as soon as possible. This 10632316SN/A // prevents external agents from changing any specific state 10642316SN/A // that the trap need. 10657684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 10662292SN/A 10672316SN/A // Exit state update mode to avoid accidental updating. 10682316SN/A thread[tid]->inSyscall = false; 10692292SN/A 10702316SN/A commitStatus[tid] = TrapPending; 10712292SN/A 10724035Sktlim@umich.edu if (head_inst->traceData) { 10736667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 10746667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 10756667Ssteve.reinhardt@amd.com head_inst->traceData->setCPSeq(thread[tid]->numInst); 10766667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 10776667Ssteve.reinhardt@amd.com } 10784288Sktlim@umich.edu delete head_inst->traceData; 10794035Sktlim@umich.edu head_inst->traceData = NULL; 10804035Sktlim@umich.edu } 10814035Sktlim@umich.edu 10822316SN/A // Generate trap squash event. 10832316SN/A generateTrapEvent(tid); 10842353SN/A// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 10852316SN/A return false; 10861060SN/A } 10871060SN/A 10882301SN/A updateComInstStats(head_inst); 10892132SN/A 10902362SN/A#if FULL_SYSTEM 10912362SN/A if (thread[tid]->profile) { 10923577Sgblack@eecs.umich.edu// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 10932362SN/A// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 10942362SN/A thread[tid]->profilePC = head_inst->readPC(); 10953126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 10962362SN/A head_inst->staticInst); 10972362SN/A 10982362SN/A if (node) 10992362SN/A thread[tid]->profileNode = node; 11002362SN/A } 11015953Ssaidi@eecs.umich.edu if (CPA::available()) { 11025953Ssaidi@eecs.umich.edu if (head_inst->isControl()) { 11035953Ssaidi@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 11045953Ssaidi@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->readNextPC()); 11055953Ssaidi@eecs.umich.edu } 11065953Ssaidi@eecs.umich.edu } 11072362SN/A#endif 11082362SN/A 11092132SN/A if (head_inst->traceData) { 11102292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11112292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11124046Sbinkertn@umich.edu head_inst->traceData->dump(); 11134046Sbinkertn@umich.edu delete head_inst->traceData; 11142292SN/A head_inst->traceData = NULL; 11151060SN/A } 11161060SN/A 11172292SN/A // Update the commit rename map 11182292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11193771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 11202292SN/A head_inst->renamedDestRegIdx(i)); 11211060SN/A } 11221062SN/A 11232353SN/A if (head_inst->isCopy()) 11242353SN/A panic("Should not commit any copy instructions!"); 11252353SN/A 11262292SN/A // Finally clear the head ROB entry. 11272292SN/A rob->retireHead(tid); 11281060SN/A 11294035Sktlim@umich.edu // If this was a store, record it for this cycle. 11304035Sktlim@umich.edu if (head_inst->isStore()) 11314035Sktlim@umich.edu committedStores[tid] = true; 11324035Sktlim@umich.edu 11331060SN/A // Return true to indicate that we have committed an instruction. 11341060SN/A return true; 11351060SN/A} 11361060SN/A 11371061SN/Atemplate <class Impl> 11381060SN/Avoid 11392292SN/ADefaultCommit<Impl>::getInsts() 11401060SN/A{ 11412935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 11422935Sksewell@umich.edu 11433093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11443093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 11452965Sksewell@umich.edu 11462965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 11472965Sksewell@umich.edu DynInstPtr inst; 11482965Sksewell@umich.edu 11493093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 11506221Snate@binkert.org ThreadID tid = inst->threadNumber; 11512292SN/A 11522292SN/A if (!inst->isSquashed() && 11534035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 11544035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 11552292SN/A changedROBNumEntries[tid] = true; 11562292SN/A 11572292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 11582292SN/A inst->readPC(), inst->seqNum, tid); 11592292SN/A 11602292SN/A rob->insertInst(inst); 11612292SN/A 11622292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 11632292SN/A 11642292SN/A youngestSeqNum[tid] = inst->seqNum; 11651061SN/A } else { 11662292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11671061SN/A "squashed, skipping.\n", 11682292SN/A inst->readPC(), inst->seqNum, tid); 11691061SN/A } 11701060SN/A } 11712965Sksewell@umich.edu} 11722965Sksewell@umich.edu 11732965Sksewell@umich.edutemplate <class Impl> 11742965Sksewell@umich.eduvoid 11752965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 11762965Sksewell@umich.edu{ 11772965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 11782965Sksewell@umich.edu "skidBuffer.\n"); 11792965Sksewell@umich.edu 11802965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 11812965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 11822965Sksewell@umich.edu 11832965Sksewell@umich.edu if (!inst->isSquashed()) { 11842965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 11853221Sktlim@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, 11863221Sktlim@umich.edu inst->threadNumber); 11872965Sksewell@umich.edu skidBuffer.push(inst); 11882965Sksewell@umich.edu } else { 11892965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11902965Sksewell@umich.edu "squashed, skipping.\n", 11913221Sktlim@umich.edu inst->readPC(), inst->seqNum, inst->threadNumber); 11922965Sksewell@umich.edu } 11932965Sksewell@umich.edu } 11941060SN/A} 11951060SN/A 11961061SN/Atemplate <class Impl> 11971060SN/Avoid 11982292SN/ADefaultCommit<Impl>::markCompletedInsts() 11991060SN/A{ 12001060SN/A // Grab completed insts out of the IEW instruction queue, and mark 12011060SN/A // instructions completed within the ROB. 12021060SN/A for (int inst_num = 0; 12031681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 12041060SN/A ++inst_num) 12051060SN/A { 12062292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12072316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 12082316SN/A "within ROB.\n", 12092292SN/A fromIEW->insts[inst_num]->threadNumber, 12102292SN/A fromIEW->insts[inst_num]->readPC(), 12112292SN/A fromIEW->insts[inst_num]->seqNum); 12121060SN/A 12132292SN/A // Mark the instruction as ready to commit. 12142292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12152292SN/A } 12161060SN/A } 12171060SN/A} 12181060SN/A 12191061SN/Atemplate <class Impl> 12202292SN/Abool 12212292SN/ADefaultCommit<Impl>::robDoneSquashing() 12221060SN/A{ 12236221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12246221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12252292SN/A 12263867Sbinkertn@umich.edu while (threads != end) { 12276221Snate@binkert.org ThreadID tid = *threads++; 12282292SN/A 12292292SN/A if (!rob->isDoneSquashing(tid)) 12302292SN/A return false; 12312292SN/A } 12322292SN/A 12332292SN/A return true; 12341060SN/A} 12352292SN/A 12362301SN/Atemplate <class Impl> 12372301SN/Avoid 12382301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 12392301SN/A{ 12406221Snate@binkert.org ThreadID tid = inst->threadNumber; 12412301SN/A 12422301SN/A // 12432301SN/A // Pick off the software prefetches 12442301SN/A // 12452301SN/A#ifdef TARGET_ALPHA 12462301SN/A if (inst->isDataPrefetch()) { 12476221Snate@binkert.org statComSwp[tid]++; 12482301SN/A } else { 12496221Snate@binkert.org statComInst[tid]++; 12502301SN/A } 12512301SN/A#else 12526221Snate@binkert.org statComInst[tid]++; 12532301SN/A#endif 12542301SN/A 12552301SN/A // 12562301SN/A // Control Instructions 12572301SN/A // 12582301SN/A if (inst->isControl()) 12596221Snate@binkert.org statComBranches[tid]++; 12602301SN/A 12612301SN/A // 12622301SN/A // Memory references 12632301SN/A // 12642301SN/A if (inst->isMemRef()) { 12656221Snate@binkert.org statComRefs[tid]++; 12662301SN/A 12672301SN/A if (inst->isLoad()) { 12686221Snate@binkert.org statComLoads[tid]++; 12692301SN/A } 12702301SN/A } 12712301SN/A 12722301SN/A if (inst->isMemBarrier()) { 12736221Snate@binkert.org statComMembars[tid]++; 12742301SN/A } 12752301SN/A} 12762301SN/A 12772292SN/A//////////////////////////////////////// 12782292SN/A// // 12792316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 12802292SN/A// // 12812292SN/A//////////////////////////////////////// 12822292SN/Atemplate <class Impl> 12836221Snate@binkert.orgThreadID 12842292SN/ADefaultCommit<Impl>::getCommittingThread() 12852292SN/A{ 12862292SN/A if (numThreads > 1) { 12872292SN/A switch (commitPolicy) { 12882292SN/A 12892292SN/A case Aggressive: 12902292SN/A //If Policy is Aggressive, commit will call 12912292SN/A //this function multiple times per 12922292SN/A //cycle 12932292SN/A return oldestReady(); 12942292SN/A 12952292SN/A case RoundRobin: 12962292SN/A return roundRobin(); 12972292SN/A 12982292SN/A case OldestReady: 12992292SN/A return oldestReady(); 13002292SN/A 13012292SN/A default: 13026221Snate@binkert.org return InvalidThreadID; 13032292SN/A } 13042292SN/A } else { 13053867Sbinkertn@umich.edu assert(!activeThreads->empty()); 13066221Snate@binkert.org ThreadID tid = activeThreads->front(); 13072292SN/A 13082292SN/A if (commitStatus[tid] == Running || 13092292SN/A commitStatus[tid] == Idle || 13102292SN/A commitStatus[tid] == FetchTrapPending) { 13112292SN/A return tid; 13122292SN/A } else { 13136221Snate@binkert.org return InvalidThreadID; 13142292SN/A } 13152292SN/A } 13162292SN/A} 13172292SN/A 13182292SN/Atemplate<class Impl> 13196221Snate@binkert.orgThreadID 13202292SN/ADefaultCommit<Impl>::roundRobin() 13212292SN/A{ 13226221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 13236221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 13242292SN/A 13252292SN/A while (pri_iter != end) { 13266221Snate@binkert.org ThreadID tid = *pri_iter; 13272292SN/A 13282292SN/A if (commitStatus[tid] == Running || 13292831Sksewell@umich.edu commitStatus[tid] == Idle || 13302831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 13312292SN/A 13322292SN/A if (rob->isHeadReady(tid)) { 13332292SN/A priority_list.erase(pri_iter); 13342292SN/A priority_list.push_back(tid); 13352292SN/A 13362292SN/A return tid; 13372292SN/A } 13382292SN/A } 13392292SN/A 13402292SN/A pri_iter++; 13412292SN/A } 13422292SN/A 13436221Snate@binkert.org return InvalidThreadID; 13442292SN/A} 13452292SN/A 13462292SN/Atemplate<class Impl> 13476221Snate@binkert.orgThreadID 13482292SN/ADefaultCommit<Impl>::oldestReady() 13492292SN/A{ 13502292SN/A unsigned oldest = 0; 13512292SN/A bool first = true; 13522292SN/A 13536221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 13546221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 13552292SN/A 13563867Sbinkertn@umich.edu while (threads != end) { 13576221Snate@binkert.org ThreadID tid = *threads++; 13582292SN/A 13592292SN/A if (!rob->isEmpty(tid) && 13602292SN/A (commitStatus[tid] == Running || 13612292SN/A commitStatus[tid] == Idle || 13622292SN/A commitStatus[tid] == FetchTrapPending)) { 13632292SN/A 13642292SN/A if (rob->isHeadReady(tid)) { 13652292SN/A 13662292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 13672292SN/A 13682292SN/A if (first) { 13692292SN/A oldest = tid; 13702292SN/A first = false; 13712292SN/A } else if (head_inst->seqNum < oldest) { 13722292SN/A oldest = tid; 13732292SN/A } 13742292SN/A } 13752292SN/A } 13762292SN/A } 13772292SN/A 13782292SN/A if (!first) { 13792292SN/A return oldest; 13802292SN/A } else { 13816221Snate@binkert.org return InvalidThreadID; 13822292SN/A } 13832292SN/A} 1384