commit_impl.hh revision 5704
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292965Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322733Sktlim@umich.edu#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 342733Sktlim@umich.edu 352292SN/A#include <algorithm> 362329SN/A#include <string> 372292SN/A 383577Sgblack@eecs.umich.edu#include "arch/utility.hh" 392292SN/A#include "base/loader/symtab.hh" 401060SN/A#include "base/timebuf.hh" 412292SN/A#include "cpu/exetrace.hh" 421717SN/A#include "cpu/o3/commit.hh" 432292SN/A#include "cpu/o3/thread_state.hh" 442292SN/A 452790Sktlim@umich.edu#if USE_CHECKER 462790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 472790Sktlim@umich.edu#endif 482790Sktlim@umich.edu 495529Snate@binkert.org#include "params/DerivO3CPU.hh" 505529Snate@binkert.org 511061SN/Atemplate <class Impl> 522292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 532292SN/A unsigned _tid) 545606Snate@binkert.org : Event(CPU_Tick_Pri), commit(_commit), tid(_tid) 551060SN/A{ 562292SN/A this->setFlags(Event::AutoDelete); 571060SN/A} 581060SN/A 591061SN/Atemplate <class Impl> 601060SN/Avoid 612292SN/ADefaultCommit<Impl>::TrapEvent::process() 621062SN/A{ 632316SN/A // This will get reset by commit if it was switched out at the 642316SN/A // time of this event processing. 652292SN/A commit->trapSquash[tid] = true; 662292SN/A} 672292SN/A 682292SN/Atemplate <class Impl> 692292SN/Aconst char * 705336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 712292SN/A{ 724873Sstever@eecs.umich.edu return "Trap"; 732292SN/A} 742292SN/A 752292SN/Atemplate <class Impl> 765529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 774329Sktlim@umich.edu : cpu(_cpu), 784329Sktlim@umich.edu squashCounter(0), 792292SN/A iewToCommitDelay(params->iewToCommitDelay), 802292SN/A commitToIEWDelay(params->commitToIEWDelay), 812292SN/A renameToROBDelay(params->renameToROBDelay), 822292SN/A fetchToCommitDelay(params->commitToFetchDelay), 832292SN/A renameWidth(params->renameWidth), 842292SN/A commitWidth(params->commitWidth), 855529Snate@binkert.org numThreads(params->numThreads), 862843Sktlim@umich.edu drainPending(false), 872316SN/A switchedOut(false), 882874Sktlim@umich.edu trapLatency(params->trapLatency) 892292SN/A{ 902292SN/A _status = Active; 912292SN/A _nextStatus = Inactive; 922980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 932292SN/A 942292SN/A //Convert string to lowercase 952292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 962292SN/A (int(*)(int)) tolower); 972292SN/A 982292SN/A //Assign commit policy 992292SN/A if (policy == "aggressive"){ 1002292SN/A commitPolicy = Aggressive; 1012292SN/A 1024329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive."); 1032292SN/A } else if (policy == "roundrobin"){ 1042292SN/A commitPolicy = RoundRobin; 1052292SN/A 1062292SN/A //Set-Up Priority List 1072292SN/A for (int tid=0; tid < numThreads; tid++) { 1082292SN/A priority_list.push_back(tid); 1092292SN/A } 1102292SN/A 1114329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 1122292SN/A } else if (policy == "oldestready"){ 1132292SN/A commitPolicy = OldestReady; 1142292SN/A 1154329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1162292SN/A } else { 1172292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1182292SN/A "RoundRobin,OldestReady}"); 1192292SN/A } 1202292SN/A 1212292SN/A for (int i=0; i < numThreads; i++) { 1222292SN/A commitStatus[i] = Idle; 1232292SN/A changedROBNumEntries[i] = false; 1244035Sktlim@umich.edu checkEmptyROB[i] = false; 1254035Sktlim@umich.edu trapInFlight[i] = false; 1264035Sktlim@umich.edu committedStores[i] = false; 1272292SN/A trapSquash[i] = false; 1282680Sktlim@umich.edu tcSquash[i] = false; 1294636Sgblack@eecs.umich.edu microPC[i] = nextMicroPC[i] = PC[i] = nextPC[i] = nextNPC[i] = 0; 1302292SN/A } 1313640Sktlim@umich.edu#if FULL_SYSTEM 1323640Sktlim@umich.edu interrupt = NoFault; 1333640Sktlim@umich.edu#endif 1342292SN/A} 1352292SN/A 1362292SN/Atemplate <class Impl> 1372292SN/Astd::string 1382292SN/ADefaultCommit<Impl>::name() const 1392292SN/A{ 1402292SN/A return cpu->name() + ".commit"; 1412292SN/A} 1422292SN/A 1432292SN/Atemplate <class Impl> 1442292SN/Avoid 1452292SN/ADefaultCommit<Impl>::regStats() 1462132SN/A{ 1472301SN/A using namespace Stats; 1481062SN/A commitCommittedInsts 1491062SN/A .name(name() + ".commitCommittedInsts") 1501062SN/A .desc("The number of committed instructions") 1511062SN/A .prereq(commitCommittedInsts); 1521062SN/A commitSquashedInsts 1531062SN/A .name(name() + ".commitSquashedInsts") 1541062SN/A .desc("The number of squashed insts skipped by commit") 1551062SN/A .prereq(commitSquashedInsts); 1561062SN/A commitSquashEvents 1571062SN/A .name(name() + ".commitSquashEvents") 1581062SN/A .desc("The number of times commit is told to squash") 1591062SN/A .prereq(commitSquashEvents); 1601062SN/A commitNonSpecStalls 1611062SN/A .name(name() + ".commitNonSpecStalls") 1621062SN/A .desc("The number of times commit has been forced to stall to " 1631062SN/A "communicate backwards") 1641062SN/A .prereq(commitNonSpecStalls); 1651062SN/A branchMispredicts 1661062SN/A .name(name() + ".branchMispredicts") 1671062SN/A .desc("The number of times a branch was mispredicted") 1681062SN/A .prereq(branchMispredicts); 1692292SN/A numCommittedDist 1701062SN/A .init(0,commitWidth,1) 1711062SN/A .name(name() + ".COM:committed_per_cycle") 1721062SN/A .desc("Number of insts commited each cycle") 1731062SN/A .flags(Stats::pdf) 1741062SN/A ; 1752301SN/A 1762316SN/A statComInst 1772301SN/A .init(cpu->number_of_threads) 1782301SN/A .name(name() + ".COM:count") 1792301SN/A .desc("Number of instructions committed") 1802301SN/A .flags(total) 1812301SN/A ; 1822301SN/A 1832316SN/A statComSwp 1842301SN/A .init(cpu->number_of_threads) 1852301SN/A .name(name() + ".COM:swp_count") 1862301SN/A .desc("Number of s/w prefetches committed") 1872301SN/A .flags(total) 1882301SN/A ; 1892301SN/A 1902316SN/A statComRefs 1912301SN/A .init(cpu->number_of_threads) 1922301SN/A .name(name() + ".COM:refs") 1932301SN/A .desc("Number of memory references committed") 1942301SN/A .flags(total) 1952301SN/A ; 1962301SN/A 1972316SN/A statComLoads 1982301SN/A .init(cpu->number_of_threads) 1992301SN/A .name(name() + ".COM:loads") 2002301SN/A .desc("Number of loads committed") 2012301SN/A .flags(total) 2022301SN/A ; 2032301SN/A 2042316SN/A statComMembars 2052301SN/A .init(cpu->number_of_threads) 2062301SN/A .name(name() + ".COM:membars") 2072301SN/A .desc("Number of memory barriers committed") 2082301SN/A .flags(total) 2092301SN/A ; 2102301SN/A 2112316SN/A statComBranches 2122301SN/A .init(cpu->number_of_threads) 2132301SN/A .name(name() + ".COM:branches") 2142301SN/A .desc("Number of branches committed") 2152301SN/A .flags(total) 2162301SN/A ; 2172301SN/A 2182316SN/A commitEligible 2192301SN/A .init(cpu->number_of_threads) 2202301SN/A .name(name() + ".COM:bw_limited") 2212301SN/A .desc("number of insts not committed due to BW limits") 2222301SN/A .flags(total) 2232301SN/A ; 2242301SN/A 2252316SN/A commitEligibleSamples 2262301SN/A .name(name() + ".COM:bw_lim_events") 2272301SN/A .desc("number cycles where commit BW limit reached") 2282301SN/A ; 2291062SN/A} 2301062SN/A 2311062SN/Atemplate <class Impl> 2321062SN/Avoid 2332980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2342292SN/A{ 2352292SN/A thread = threads; 2362292SN/A} 2372292SN/A 2382292SN/Atemplate <class Impl> 2392292SN/Avoid 2402292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2411060SN/A{ 2421060SN/A timeBuffer = tb_ptr; 2431060SN/A 2441060SN/A // Setup wire to send information back to IEW. 2451060SN/A toIEW = timeBuffer->getWire(0); 2461060SN/A 2471060SN/A // Setup wire to read data from IEW (for the ROB). 2481060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2491060SN/A} 2501060SN/A 2511061SN/Atemplate <class Impl> 2521060SN/Avoid 2532292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2542292SN/A{ 2552292SN/A fetchQueue = fq_ptr; 2562292SN/A 2572292SN/A // Setup wire to get instructions from rename (for the ROB). 2582292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2592292SN/A} 2602292SN/A 2612292SN/Atemplate <class Impl> 2622292SN/Avoid 2632292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2641060SN/A{ 2651060SN/A renameQueue = rq_ptr; 2661060SN/A 2671060SN/A // Setup wire to get instructions from rename (for the ROB). 2681060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2691060SN/A} 2701060SN/A 2711061SN/Atemplate <class Impl> 2721060SN/Avoid 2732292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2741060SN/A{ 2751060SN/A iewQueue = iq_ptr; 2761060SN/A 2771060SN/A // Setup wire to get instructions from IEW. 2781060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2791060SN/A} 2801060SN/A 2811061SN/Atemplate <class Impl> 2821060SN/Avoid 2832292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2842292SN/A{ 2852292SN/A iewStage = iew_stage; 2862292SN/A} 2872292SN/A 2882292SN/Atemplate<class Impl> 2892292SN/Avoid 2902980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2912292SN/A{ 2922292SN/A activeThreads = at_ptr; 2932292SN/A} 2942292SN/A 2952292SN/Atemplate <class Impl> 2962292SN/Avoid 2972292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 2982292SN/A{ 2992292SN/A for (int i=0; i < numThreads; i++) { 3002292SN/A renameMap[i] = &rm_ptr[i]; 3012292SN/A } 3022292SN/A} 3032292SN/A 3042292SN/Atemplate <class Impl> 3052292SN/Avoid 3062292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3071060SN/A{ 3081060SN/A rob = rob_ptr; 3091060SN/A} 3101060SN/A 3111061SN/Atemplate <class Impl> 3121060SN/Avoid 3132292SN/ADefaultCommit<Impl>::initStage() 3141060SN/A{ 3152292SN/A rob->setActiveThreads(activeThreads); 3162292SN/A rob->resetEntries(); 3171060SN/A 3182292SN/A // Broadcast the number of free entries. 3192292SN/A for (int i=0; i < numThreads; i++) { 3202292SN/A toIEW->commitInfo[i].usedROB = true; 3212292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3224035Sktlim@umich.edu toIEW->commitInfo[i].emptyROB = true; 3231060SN/A } 3241060SN/A 3254329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3264329Sktlim@umich.edu // start of the simulation, so it starts as active. 3274329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3284329Sktlim@umich.edu 3292292SN/A cpu->activityThisCycle(); 3305100Ssaidi@eecs.umich.edu trapLatency = cpu->ticks(trapLatency); 3311060SN/A} 3321060SN/A 3331061SN/Atemplate <class Impl> 3342863Sktlim@umich.edubool 3352843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3361060SN/A{ 3372843Sktlim@umich.edu drainPending = true; 3382863Sktlim@umich.edu 3392863Sktlim@umich.edu return false; 3402316SN/A} 3412316SN/A 3422316SN/Atemplate <class Impl> 3432316SN/Avoid 3442843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3452316SN/A{ 3462316SN/A switchedOut = true; 3472843Sktlim@umich.edu drainPending = false; 3482307SN/A rob->switchOut(); 3492307SN/A} 3502307SN/A 3512307SN/Atemplate <class Impl> 3522307SN/Avoid 3532843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3542843Sktlim@umich.edu{ 3552864Sktlim@umich.edu drainPending = false; 3562843Sktlim@umich.edu} 3572843Sktlim@umich.edu 3582843Sktlim@umich.edutemplate <class Impl> 3592843Sktlim@umich.eduvoid 3602307SN/ADefaultCommit<Impl>::takeOverFrom() 3612307SN/A{ 3622316SN/A switchedOut = false; 3632307SN/A _status = Active; 3642307SN/A _nextStatus = Inactive; 3652307SN/A for (int i=0; i < numThreads; i++) { 3662307SN/A commitStatus[i] = Idle; 3672307SN/A changedROBNumEntries[i] = false; 3682307SN/A trapSquash[i] = false; 3692680Sktlim@umich.edu tcSquash[i] = false; 3702307SN/A } 3712307SN/A squashCounter = 0; 3722307SN/A rob->takeOverFrom(); 3732307SN/A} 3742307SN/A 3752307SN/Atemplate <class Impl> 3762307SN/Avoid 3772292SN/ADefaultCommit<Impl>::updateStatus() 3782132SN/A{ 3792316SN/A // reset ROB changed variable 3803867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 3813867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 3823867Sbinkertn@umich.edu 3833867Sbinkertn@umich.edu while (threads != end) { 3842316SN/A unsigned tid = *threads++; 3853867Sbinkertn@umich.edu 3862316SN/A changedROBNumEntries[tid] = false; 3872316SN/A 3882316SN/A // Also check if any of the threads has a trap pending 3892316SN/A if (commitStatus[tid] == TrapPending || 3902316SN/A commitStatus[tid] == FetchTrapPending) { 3912316SN/A _nextStatus = Active; 3922316SN/A } 3932292SN/A } 3942292SN/A 3952292SN/A if (_nextStatus == Inactive && _status == Active) { 3962292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 3972733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 3982292SN/A } else if (_nextStatus == Active && _status == Inactive) { 3992292SN/A DPRINTF(Activity, "Activating stage.\n"); 4002733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4012292SN/A } 4022292SN/A 4032292SN/A _status = _nextStatus; 4042292SN/A} 4052292SN/A 4062292SN/Atemplate <class Impl> 4072292SN/Avoid 4082292SN/ADefaultCommit<Impl>::setNextStatus() 4092292SN/A{ 4102292SN/A int squashes = 0; 4112292SN/A 4123867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4133867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4142292SN/A 4153867Sbinkertn@umich.edu while (threads != end) { 4162292SN/A unsigned tid = *threads++; 4172292SN/A 4182292SN/A if (commitStatus[tid] == ROBSquashing) { 4192292SN/A squashes++; 4202292SN/A } 4212292SN/A } 4222292SN/A 4232702Sktlim@umich.edu squashCounter = squashes; 4242292SN/A 4252292SN/A // If commit is currently squashing, then it will have activity for the 4262292SN/A // next cycle. Set its next status as active. 4272292SN/A if (squashCounter) { 4282292SN/A _nextStatus = Active; 4292292SN/A } 4302292SN/A} 4312292SN/A 4322292SN/Atemplate <class Impl> 4332292SN/Abool 4342292SN/ADefaultCommit<Impl>::changedROBEntries() 4352292SN/A{ 4363867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4373867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4382292SN/A 4393867Sbinkertn@umich.edu while (threads != end) { 4402292SN/A unsigned tid = *threads++; 4412292SN/A 4422292SN/A if (changedROBNumEntries[tid]) { 4432292SN/A return true; 4442292SN/A } 4452292SN/A } 4462292SN/A 4472292SN/A return false; 4482292SN/A} 4492292SN/A 4502292SN/Atemplate <class Impl> 4512292SN/Aunsigned 4522292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4532292SN/A{ 4542292SN/A return rob->numFreeEntries(tid); 4552292SN/A} 4562292SN/A 4572292SN/Atemplate <class Impl> 4582292SN/Avoid 4592292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4602292SN/A{ 4612292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4622292SN/A 4632292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4642292SN/A 4655606Snate@binkert.org cpu->schedule(trap, curTick + trapLatency); 4664035Sktlim@umich.edu trapInFlight[tid] = true; 4672292SN/A} 4682292SN/A 4692292SN/Atemplate <class Impl> 4702292SN/Avoid 4712680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4722292SN/A{ 4734035Sktlim@umich.edu assert(!trapInFlight[tid]); 4742680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4752292SN/A 4762680Sktlim@umich.edu tcSquash[tid] = true; 4772292SN/A} 4782292SN/A 4792292SN/Atemplate <class Impl> 4802292SN/Avoid 4812316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4822292SN/A{ 4832292SN/A // If we want to include the squashing instruction in the squash, 4842292SN/A // then use one older sequence number. 4852292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4862292SN/A // all instructions of this thread. 4872292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 4884035Sktlim@umich.edu 0 : rob->readHeadInst(tid)->seqNum - 1; 4892292SN/A 4902292SN/A // All younger instructions will be squashed. Set the sequence 4912292SN/A // number as the youngest instruction in the ROB (0 in this case. 4922292SN/A // Hopefully nothing breaks.) 4932292SN/A youngestSeqNum[tid] = 0; 4942292SN/A 4952292SN/A rob->squash(squashed_inst, tid); 4962292SN/A changedROBNumEntries[tid] = true; 4972292SN/A 4982292SN/A // Send back the sequence number of the squashed instruction. 4992292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5002292SN/A 5012292SN/A // Send back the squash signal to tell stages that they should 5022292SN/A // squash. 5032292SN/A toIEW->commitInfo[tid].squash = true; 5042292SN/A 5052292SN/A // Send back the rob squashing signal so other stages know that 5062292SN/A // the ROB is in the process of squashing. 5072292SN/A toIEW->commitInfo[tid].robSquashing = true; 5082292SN/A 5092292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5102292SN/A 5112316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5123795Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextNPC = nextPC[tid]; 5134636Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid]; 5142316SN/A} 5152292SN/A 5162316SN/Atemplate <class Impl> 5172316SN/Avoid 5182316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5192316SN/A{ 5202316SN/A squashAll(tid); 5212316SN/A 5222316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5232316SN/A 5242316SN/A thread[tid]->trapPending = false; 5252316SN/A thread[tid]->inSyscall = false; 5264035Sktlim@umich.edu trapInFlight[tid] = false; 5272316SN/A 5282316SN/A trapSquash[tid] = false; 5292316SN/A 5302316SN/A commitStatus[tid] = ROBSquashing; 5312316SN/A cpu->activityThisCycle(); 5322316SN/A} 5332316SN/A 5342316SN/Atemplate <class Impl> 5352316SN/Avoid 5362680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5372316SN/A{ 5382316SN/A squashAll(tid); 5392292SN/A 5402680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5412292SN/A 5422292SN/A thread[tid]->inSyscall = false; 5432292SN/A assert(!thread[tid]->trapPending); 5442316SN/A 5452292SN/A commitStatus[tid] = ROBSquashing; 5462292SN/A cpu->activityThisCycle(); 5472292SN/A 5482680Sktlim@umich.edu tcSquash[tid] = false; 5492292SN/A} 5502292SN/A 5512292SN/Atemplate <class Impl> 5522292SN/Avoid 5532292SN/ADefaultCommit<Impl>::tick() 5542292SN/A{ 5552292SN/A wroteToTimeBuffer = false; 5562292SN/A _nextStatus = Inactive; 5572292SN/A 5582843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5592843Sktlim@umich.edu cpu->signalDrained(); 5602843Sktlim@umich.edu drainPending = false; 5612316SN/A return; 5622316SN/A } 5632316SN/A 5643867Sbinkertn@umich.edu if (activeThreads->empty()) 5652875Sksewell@umich.edu return; 5662875Sksewell@umich.edu 5673867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 5683867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 5692292SN/A 5702316SN/A // Check if any of the threads are done squashing. Change the 5712316SN/A // status if they are done. 5723867Sbinkertn@umich.edu while (threads != end) { 5732292SN/A unsigned tid = *threads++; 5742292SN/A 5754035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 5764035Sktlim@umich.edu // this cycle. 5774035Sktlim@umich.edu committedStores[tid] = false; 5784035Sktlim@umich.edu 5792292SN/A if (commitStatus[tid] == ROBSquashing) { 5802292SN/A 5812292SN/A if (rob->isDoneSquashing(tid)) { 5822292SN/A commitStatus[tid] = Running; 5832292SN/A } else { 5842292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5852877Sksewell@umich.edu " insts this cycle.\n", tid); 5862702Sktlim@umich.edu rob->doSquash(tid); 5872702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5882702Sktlim@umich.edu wroteToTimeBuffer = true; 5892292SN/A } 5902292SN/A } 5912292SN/A } 5922292SN/A 5932292SN/A commit(); 5942292SN/A 5952292SN/A markCompletedInsts(); 5962292SN/A 5973867Sbinkertn@umich.edu threads = activeThreads->begin(); 5982292SN/A 5993867Sbinkertn@umich.edu while (threads != end) { 6002292SN/A unsigned tid = *threads++; 6012292SN/A 6022292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6032292SN/A // The ROB has more instructions it can commit. Its next status 6042292SN/A // will be active. 6052292SN/A _nextStatus = Active; 6062292SN/A 6072292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6082292SN/A 6092292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6102292SN/A " ROB and ready to commit\n", 6112292SN/A tid, inst->seqNum, inst->readPC()); 6122292SN/A 6132292SN/A } else if (!rob->isEmpty(tid)) { 6142292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6152292SN/A 6162292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6172292SN/A "%#x is head of ROB and not ready\n", 6182292SN/A tid, inst->seqNum, inst->readPC()); 6192292SN/A } 6202292SN/A 6212292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6222292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6232292SN/A } 6242292SN/A 6252292SN/A 6262292SN/A if (wroteToTimeBuffer) { 6272316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6282292SN/A cpu->activityThisCycle(); 6292292SN/A } 6302292SN/A 6312292SN/A updateStatus(); 6322292SN/A} 6332292SN/A 6344035Sktlim@umich.edu#if FULL_SYSTEM 6352292SN/Atemplate <class Impl> 6362292SN/Avoid 6374035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 6382292SN/A{ 6393640Sktlim@umich.edu if (interrupt != NoFault) { 6402316SN/A // Wait until the ROB is empty and all stores have drained in 6412316SN/A // order to enter the interrupt. 6422292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6433633Sktlim@umich.edu // Squash or record that I need to squash this cycle if 6443633Sktlim@umich.edu // an interrupt needed to be handled. 6453633Sktlim@umich.edu DPRINTF(Commit, "Interrupt detected.\n"); 6463633Sktlim@umich.edu 6474035Sktlim@umich.edu // Clear the interrupt now that it's going to be handled 6484035Sktlim@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 6494035Sktlim@umich.edu 6502292SN/A assert(!thread[0]->inSyscall); 6512292SN/A thread[0]->inSyscall = true; 6522292SN/A 6533633Sktlim@umich.edu // CPU will handle interrupt. 6543640Sktlim@umich.edu cpu->processInterrupts(interrupt); 6552292SN/A 6563633Sktlim@umich.edu thread[0]->inSyscall = false; 6573633Sktlim@umich.edu 6582292SN/A commitStatus[0] = TrapPending; 6592292SN/A 6602292SN/A // Generate trap squash event. 6612292SN/A generateTrapEvent(0); 6622292SN/A 6633640Sktlim@umich.edu interrupt = NoFault; 6642292SN/A } else { 6652292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6662292SN/A } 6674035Sktlim@umich.edu } else if (commitStatus[0] != TrapPending && 6685704Snate@binkert.org cpu->checkInterrupts(cpu->tcBase(0)) && 6694035Sktlim@umich.edu !trapSquash[0] && 6704035Sktlim@umich.edu !tcSquash[0]) { 6713640Sktlim@umich.edu // Process interrupts if interrupts are enabled, not in PAL 6723640Sktlim@umich.edu // mode, and no other traps or external squashes are currently 6733640Sktlim@umich.edu // pending. 6743640Sktlim@umich.edu // @todo: Allow other threads to handle interrupts. 6753640Sktlim@umich.edu 6763640Sktlim@umich.edu // Get any interrupt that happened 6773640Sktlim@umich.edu interrupt = cpu->getInterrupts(); 6783640Sktlim@umich.edu 6793640Sktlim@umich.edu if (interrupt != NoFault) { 6803640Sktlim@umich.edu // Tell fetch that there is an interrupt pending. This 6813640Sktlim@umich.edu // will make fetch wait until it sees a non PAL-mode PC, 6823640Sktlim@umich.edu // at which point it stops fetching instructions. 6833640Sktlim@umich.edu toIEW->commitInfo[0].interruptPending = true; 6843640Sktlim@umich.edu } 6851060SN/A } 6864035Sktlim@umich.edu} 6874035Sktlim@umich.edu#endif // FULL_SYSTEM 6883634Sktlim@umich.edu 6894035Sktlim@umich.edutemplate <class Impl> 6904035Sktlim@umich.eduvoid 6914035Sktlim@umich.eduDefaultCommit<Impl>::commit() 6924035Sktlim@umich.edu{ 6934035Sktlim@umich.edu 6944035Sktlim@umich.edu#if FULL_SYSTEM 6954035Sktlim@umich.edu // Check for any interrupt, and start processing it. Or if we 6964035Sktlim@umich.edu // have an outstanding interrupt and are at a point when it is 6974035Sktlim@umich.edu // valid to take an interrupt, process it. 6985704Snate@binkert.org if (cpu->checkInterrupts(cpu->tcBase(0))) { 6994035Sktlim@umich.edu handleInterrupt(); 7004035Sktlim@umich.edu } 7011060SN/A#endif // FULL_SYSTEM 7021060SN/A 7031060SN/A //////////////////////////////////// 7042316SN/A // Check for any possible squashes, handle them first 7051060SN/A //////////////////////////////////// 7063867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7073867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7081060SN/A 7093867Sbinkertn@umich.edu while (threads != end) { 7102292SN/A unsigned tid = *threads++; 7111060SN/A 7122292SN/A // Not sure which one takes priority. I think if we have 7132292SN/A // both, that's a bad sign. 7142292SN/A if (trapSquash[tid] == true) { 7152680Sktlim@umich.edu assert(!tcSquash[tid]); 7162292SN/A squashFromTrap(tid); 7172680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7184035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 7192680Sktlim@umich.edu squashFromTC(tid); 7202292SN/A } 7211061SN/A 7222292SN/A // Squashed sequence number must be older than youngest valid 7232292SN/A // instruction in the ROB. This prevents squashes from younger 7242292SN/A // instructions overriding squashes from older instructions. 7252292SN/A if (fromIEW->squash[tid] && 7262292SN/A commitStatus[tid] != TrapPending && 7272292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7281061SN/A 7292292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7302292SN/A tid, 7312292SN/A fromIEW->mispredPC[tid], 7322292SN/A fromIEW->squashedSeqNum[tid]); 7331061SN/A 7342292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7352292SN/A tid, 7362292SN/A fromIEW->nextPC[tid]); 7371061SN/A 7382292SN/A commitStatus[tid] = ROBSquashing; 7391061SN/A 7402292SN/A // If we want to include the squashing instruction in the squash, 7412292SN/A // then use one older sequence number. 7422292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7431062SN/A 7442935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 7452292SN/A squashed_inst--; 7462935Sksewell@umich.edu } 7474035Sktlim@umich.edu 7482292SN/A // All younger instructions will be squashed. Set the sequence 7492292SN/A // number as the youngest instruction in the ROB. 7502292SN/A youngestSeqNum[tid] = squashed_inst; 7512292SN/A 7523093Sksewell@umich.edu rob->squash(squashed_inst, tid); 7532292SN/A changedROBNumEntries[tid] = true; 7542292SN/A 7552292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7562292SN/A 7572292SN/A toIEW->commitInfo[tid].squash = true; 7582292SN/A 7592292SN/A // Send back the rob squashing signal so other stages know that 7602292SN/A // the ROB is in the process of squashing. 7612292SN/A toIEW->commitInfo[tid].robSquashing = true; 7622292SN/A 7632292SN/A toIEW->commitInfo[tid].branchMispredict = 7642292SN/A fromIEW->branchMispredict[tid]; 7652292SN/A 7662292SN/A toIEW->commitInfo[tid].branchTaken = 7672292SN/A fromIEW->branchTaken[tid]; 7682292SN/A 7692292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7703795Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid]; 7714636Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid]; 7722292SN/A 7732316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7742292SN/A 7752292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7762292SN/A ++branchMispredicts; 7772292SN/A } 7781062SN/A } 7792292SN/A 7801060SN/A } 7811060SN/A 7822292SN/A setNextStatus(); 7832292SN/A 7842292SN/A if (squashCounter != numThreads) { 7851061SN/A // If we're not currently squashing, then get instructions. 7861060SN/A getInsts(); 7871060SN/A 7881061SN/A // Try to commit any instructions. 7891060SN/A commitInsts(); 7901060SN/A } 7911060SN/A 7922292SN/A //Check for any activity 7933867Sbinkertn@umich.edu threads = activeThreads->begin(); 7942292SN/A 7953867Sbinkertn@umich.edu while (threads != end) { 7962292SN/A unsigned tid = *threads++; 7972292SN/A 7982292SN/A if (changedROBNumEntries[tid]) { 7992292SN/A toIEW->commitInfo[tid].usedROB = true; 8002292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8012292SN/A 8022292SN/A wroteToTimeBuffer = true; 8032292SN/A changedROBNumEntries[tid] = false; 8044035Sktlim@umich.edu if (rob->isEmpty(tid)) 8054035Sktlim@umich.edu checkEmptyROB[tid] = true; 8062292SN/A } 8074035Sktlim@umich.edu 8084035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8094035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 8104035Sktlim@umich.edu // stage has received any information regarding stores that 8114035Sktlim@umich.edu // committed. 8124035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 8134035Sktlim@umich.edu // on the same cycle as when stores have been committed. 8144035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 8154035Sktlim@umich.edu // commit and IEW. 8164035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 8175557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 8184035Sktlim@umich.edu checkEmptyROB[tid] = false; 8194035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 8204035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 8214035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8224035Sktlim@umich.edu wroteToTimeBuffer = true; 8234035Sktlim@umich.edu } 8244035Sktlim@umich.edu 8251060SN/A } 8261060SN/A} 8271060SN/A 8281061SN/Atemplate <class Impl> 8291060SN/Avoid 8302292SN/ADefaultCommit<Impl>::commitInsts() 8311060SN/A{ 8321060SN/A //////////////////////////////////// 8331060SN/A // Handle commit 8342316SN/A // Note that commit will be handled prior to putting new 8352316SN/A // instructions in the ROB so that the ROB only tries to commit 8362316SN/A // instructions it has in this current cycle, and not instructions 8372316SN/A // it is writing in during this cycle. Can't commit and squash 8382316SN/A // things at the same time... 8391060SN/A //////////////////////////////////// 8401060SN/A 8412292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8421060SN/A 8431060SN/A unsigned num_committed = 0; 8441060SN/A 8452292SN/A DynInstPtr head_inst; 8462316SN/A 8471060SN/A // Commit as many instructions as possible until the commit bandwidth 8481060SN/A // limit is reached, or it becomes impossible to commit any more. 8492292SN/A while (num_committed < commitWidth) { 8502292SN/A int commit_thread = getCommittingThread(); 8511060SN/A 8522292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8532292SN/A break; 8542292SN/A 8552292SN/A head_inst = rob->readHeadInst(commit_thread); 8562292SN/A 8572292SN/A int tid = head_inst->threadNumber; 8582292SN/A 8592292SN/A assert(tid == commit_thread); 8602292SN/A 8612292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8622292SN/A head_inst->seqNum, tid); 8632132SN/A 8642316SN/A // If the head instruction is squashed, it is ready to retire 8652316SN/A // (be removed from the ROB) at any time. 8661060SN/A if (head_inst->isSquashed()) { 8671060SN/A 8682292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8691060SN/A "ROB.\n"); 8701060SN/A 8712292SN/A rob->retireHead(commit_thread); 8721060SN/A 8731062SN/A ++commitSquashedInsts; 8741062SN/A 8752292SN/A // Record that the number of ROB entries has changed. 8762292SN/A changedROBNumEntries[tid] = true; 8771060SN/A } else { 8782292SN/A PC[tid] = head_inst->readPC(); 8792292SN/A nextPC[tid] = head_inst->readNextPC(); 8802935Sksewell@umich.edu nextNPC[tid] = head_inst->readNextNPC(); 8814636Sgblack@eecs.umich.edu nextMicroPC[tid] = head_inst->readNextMicroPC(); 8822292SN/A 8831060SN/A // Increment the total number of non-speculative instructions 8841060SN/A // executed. 8851060SN/A // Hack for now: it really shouldn't happen until after the 8861061SN/A // commit is deemed to be successful, but this count is needed 8871061SN/A // for syscalls. 8882292SN/A thread[tid]->funcExeInst++; 8891060SN/A 8901060SN/A // Try to commit the head instruction. 8911060SN/A bool commit_success = commitHead(head_inst, num_committed); 8921060SN/A 8931062SN/A if (commit_success) { 8941060SN/A ++num_committed; 8951060SN/A 8962292SN/A changedROBNumEntries[tid] = true; 8972292SN/A 8982292SN/A // Set the doneSeqNum to the youngest committed instruction. 8992292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9001060SN/A 9011062SN/A ++commitCommittedInsts; 9021062SN/A 9032292SN/A // To match the old model, don't count nops and instruction 9042292SN/A // prefetches towards the total commit count. 9052292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9062292SN/A cpu->instDone(tid); 9071062SN/A } 9082292SN/A 9092292SN/A PC[tid] = nextPC[tid]; 9102935Sksewell@umich.edu nextPC[tid] = nextNPC[tid]; 9112935Sksewell@umich.edu nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 9124636Sgblack@eecs.umich.edu microPC[tid] = nextMicroPC[tid]; 9134636Sgblack@eecs.umich.edu nextMicroPC[tid] = microPC[tid] + 1; 9142935Sksewell@umich.edu 9152292SN/A int count = 0; 9162292SN/A Addr oldpc; 9175108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 9185108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 9195108Sgblack@eecs.umich.edu assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 9202292SN/A do { 9212292SN/A oldpc = PC[tid]; 9225108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 9232292SN/A count++; 9242292SN/A } while (oldpc != PC[tid]); 9252292SN/A if (count > 1) { 9265108Sgblack@eecs.umich.edu DPRINTF(Commit, 9275108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 9282292SN/A break; 9292292SN/A } 9301060SN/A } else { 9312292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9322292SN/A "[tid:%i] [sn:%i].\n", 9332292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9341060SN/A break; 9351060SN/A } 9361060SN/A } 9371060SN/A } 9381062SN/A 9391063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9402292SN/A numCommittedDist.sample(num_committed); 9412307SN/A 9422307SN/A if (num_committed == commitWidth) { 9432349SN/A commitEligibleSamples++; 9442307SN/A } 9451060SN/A} 9461060SN/A 9471061SN/Atemplate <class Impl> 9481060SN/Abool 9492292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9501060SN/A{ 9511060SN/A assert(head_inst); 9521060SN/A 9532292SN/A int tid = head_inst->threadNumber; 9542292SN/A 9552316SN/A // If the instruction is not executed yet, then it will need extra 9562316SN/A // handling. Signal backwards that it should be executed. 9571061SN/A if (!head_inst->isExecuted()) { 9581061SN/A // Keep this number correct. We have not yet actually executed 9591061SN/A // and committed this instruction. 9602292SN/A thread[tid]->funcExeInst--; 9611062SN/A 9622292SN/A if (head_inst->isNonSpeculative() || 9632348SN/A head_inst->isStoreConditional() || 9642292SN/A head_inst->isMemBarrier() || 9652292SN/A head_inst->isWriteBarrier()) { 9662316SN/A 9672316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9682316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9692316SN/A head_inst->seqNum, head_inst->readPC()); 9702316SN/A 9715557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 9722292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9732292SN/A return false; 9742292SN/A } 9752292SN/A 9762292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9771061SN/A 9781061SN/A // Change the instruction so it won't try to commit again until 9791061SN/A // it is executed. 9801061SN/A head_inst->clearCanCommit(); 9811061SN/A 9821062SN/A ++commitNonSpecStalls; 9831062SN/A 9841061SN/A return false; 9852292SN/A } else if (head_inst->isLoad()) { 9865557Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 9874035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9884035Sktlim@umich.edu return false; 9894035Sktlim@umich.edu } 9904035Sktlim@umich.edu 9914035Sktlim@umich.edu assert(head_inst->uncacheable()); 9922292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9932292SN/A head_inst->seqNum, head_inst->readPC()); 9942292SN/A 9952292SN/A // Send back the non-speculative instruction's sequence 9962316SN/A // number. Tell the lsq to re-execute the load. 9972292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9982292SN/A toIEW->commitInfo[tid].uncached = true; 9992292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10002292SN/A 10012292SN/A head_inst->clearCanCommit(); 10022292SN/A 10032292SN/A return false; 10041061SN/A } else { 10052292SN/A panic("Trying to commit un-executed instruction " 10061061SN/A "of unknown type!\n"); 10071061SN/A } 10081060SN/A } 10091060SN/A 10102316SN/A if (head_inst->isThreadSync()) { 10112292SN/A // Not handled for now. 10122316SN/A panic("Thread sync instructions are not handled yet.\n"); 10132132SN/A } 10142132SN/A 10154035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 10164035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 10174035Sktlim@umich.edu 10182316SN/A // Stores mark themselves as completed. 10194035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 10202310SN/A head_inst->setCompleted(); 10212310SN/A } 10222310SN/A 10232733Sktlim@umich.edu#if USE_CHECKER 10242316SN/A // Use checker prior to updating anything due to traps or PC 10252316SN/A // based events. 10262316SN/A if (cpu->checker) { 10272732Sktlim@umich.edu cpu->checker->verify(head_inst); 10281060SN/A } 10292733Sktlim@umich.edu#endif 10301060SN/A 10312918Sktlim@umich.edu // DTB will sometimes need the machine instruction for when 10322918Sktlim@umich.edu // faults happen. So we will set it here, prior to the DTB 10332918Sktlim@umich.edu // possibly needing it for its fault. 10342918Sktlim@umich.edu thread[tid]->setInst( 10352918Sktlim@umich.edu static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10362918Sktlim@umich.edu 10372112SN/A if (inst_fault != NoFault) { 10382316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10392316SN/A head_inst->seqNum, head_inst->readPC()); 10402292SN/A 10415557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 10422316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10432316SN/A return false; 10442316SN/A } 10452310SN/A 10464035Sktlim@umich.edu head_inst->setCompleted(); 10474035Sktlim@umich.edu 10482733Sktlim@umich.edu#if USE_CHECKER 10492316SN/A if (cpu->checker && head_inst->isStore()) { 10502732Sktlim@umich.edu cpu->checker->verify(head_inst); 10512316SN/A } 10522733Sktlim@umich.edu#endif 10532292SN/A 10542316SN/A assert(!thread[tid]->inSyscall); 10552292SN/A 10562316SN/A // Mark that we're in state update mode so that the trap's 10572316SN/A // execution doesn't generate extra squashes. 10582316SN/A thread[tid]->inSyscall = true; 10592292SN/A 10602316SN/A // Execute the trap. Although it's slightly unrealistic in 10612316SN/A // terms of timing (as it doesn't wait for the full timing of 10622316SN/A // the trap event to complete before updating state), it's 10632316SN/A // needed to update the state as soon as possible. This 10642316SN/A // prevents external agents from changing any specific state 10652316SN/A // that the trap need. 10662316SN/A cpu->trap(inst_fault, tid); 10672292SN/A 10682316SN/A // Exit state update mode to avoid accidental updating. 10692316SN/A thread[tid]->inSyscall = false; 10702292SN/A 10712316SN/A commitStatus[tid] = TrapPending; 10722292SN/A 10734035Sktlim@umich.edu if (head_inst->traceData) { 10744035Sktlim@umich.edu head_inst->traceData->setFetchSeq(head_inst->seqNum); 10754035Sktlim@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numInst); 10764288Sktlim@umich.edu head_inst->traceData->dump(); 10774288Sktlim@umich.edu delete head_inst->traceData; 10784035Sktlim@umich.edu head_inst->traceData = NULL; 10794035Sktlim@umich.edu } 10804035Sktlim@umich.edu 10812316SN/A // Generate trap squash event. 10822316SN/A generateTrapEvent(tid); 10832353SN/A// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 10842316SN/A return false; 10851060SN/A } 10861060SN/A 10872301SN/A updateComInstStats(head_inst); 10882132SN/A 10892362SN/A#if FULL_SYSTEM 10902362SN/A if (thread[tid]->profile) { 10913577Sgblack@eecs.umich.edu// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 10922362SN/A// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 10932362SN/A thread[tid]->profilePC = head_inst->readPC(); 10943126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 10952362SN/A head_inst->staticInst); 10962362SN/A 10972362SN/A if (node) 10982362SN/A thread[tid]->profileNode = node; 10992362SN/A } 11002362SN/A#endif 11012362SN/A 11022132SN/A if (head_inst->traceData) { 11032292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11042292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11054046Sbinkertn@umich.edu head_inst->traceData->dump(); 11064046Sbinkertn@umich.edu delete head_inst->traceData; 11072292SN/A head_inst->traceData = NULL; 11081060SN/A } 11091060SN/A 11102292SN/A // Update the commit rename map 11112292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11123771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 11132292SN/A head_inst->renamedDestRegIdx(i)); 11141060SN/A } 11151062SN/A 11162353SN/A if (head_inst->isCopy()) 11172353SN/A panic("Should not commit any copy instructions!"); 11182353SN/A 11192292SN/A // Finally clear the head ROB entry. 11202292SN/A rob->retireHead(tid); 11211060SN/A 11224035Sktlim@umich.edu // If this was a store, record it for this cycle. 11234035Sktlim@umich.edu if (head_inst->isStore()) 11244035Sktlim@umich.edu committedStores[tid] = true; 11254035Sktlim@umich.edu 11261060SN/A // Return true to indicate that we have committed an instruction. 11271060SN/A return true; 11281060SN/A} 11291060SN/A 11301061SN/Atemplate <class Impl> 11311060SN/Avoid 11322292SN/ADefaultCommit<Impl>::getInsts() 11331060SN/A{ 11342935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 11352935Sksewell@umich.edu 11363093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11373093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 11382965Sksewell@umich.edu 11392965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 11402965Sksewell@umich.edu DynInstPtr inst; 11412965Sksewell@umich.edu 11423093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 11432292SN/A int tid = inst->threadNumber; 11442292SN/A 11452292SN/A if (!inst->isSquashed() && 11464035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 11474035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 11482292SN/A changedROBNumEntries[tid] = true; 11492292SN/A 11502292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 11512292SN/A inst->readPC(), inst->seqNum, tid); 11522292SN/A 11532292SN/A rob->insertInst(inst); 11542292SN/A 11552292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 11562292SN/A 11572292SN/A youngestSeqNum[tid] = inst->seqNum; 11581061SN/A } else { 11592292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11601061SN/A "squashed, skipping.\n", 11612292SN/A inst->readPC(), inst->seqNum, tid); 11621061SN/A } 11631060SN/A } 11642965Sksewell@umich.edu} 11652965Sksewell@umich.edu 11662965Sksewell@umich.edutemplate <class Impl> 11672965Sksewell@umich.eduvoid 11682965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 11692965Sksewell@umich.edu{ 11702965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 11712965Sksewell@umich.edu "skidBuffer.\n"); 11722965Sksewell@umich.edu 11732965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 11742965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 11752965Sksewell@umich.edu 11762965Sksewell@umich.edu if (!inst->isSquashed()) { 11772965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 11783221Sktlim@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, 11793221Sktlim@umich.edu inst->threadNumber); 11802965Sksewell@umich.edu skidBuffer.push(inst); 11812965Sksewell@umich.edu } else { 11822965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11832965Sksewell@umich.edu "squashed, skipping.\n", 11843221Sktlim@umich.edu inst->readPC(), inst->seqNum, inst->threadNumber); 11852965Sksewell@umich.edu } 11862965Sksewell@umich.edu } 11871060SN/A} 11881060SN/A 11891061SN/Atemplate <class Impl> 11901060SN/Avoid 11912292SN/ADefaultCommit<Impl>::markCompletedInsts() 11921060SN/A{ 11931060SN/A // Grab completed insts out of the IEW instruction queue, and mark 11941060SN/A // instructions completed within the ROB. 11951060SN/A for (int inst_num = 0; 11961681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 11971060SN/A ++inst_num) 11981060SN/A { 11992292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12002316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 12012316SN/A "within ROB.\n", 12022292SN/A fromIEW->insts[inst_num]->threadNumber, 12032292SN/A fromIEW->insts[inst_num]->readPC(), 12042292SN/A fromIEW->insts[inst_num]->seqNum); 12051060SN/A 12062292SN/A // Mark the instruction as ready to commit. 12072292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12082292SN/A } 12091060SN/A } 12101060SN/A} 12111060SN/A 12121061SN/Atemplate <class Impl> 12132292SN/Abool 12142292SN/ADefaultCommit<Impl>::robDoneSquashing() 12151060SN/A{ 12163867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 12173867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 12182292SN/A 12193867Sbinkertn@umich.edu while (threads != end) { 12202292SN/A unsigned tid = *threads++; 12212292SN/A 12222292SN/A if (!rob->isDoneSquashing(tid)) 12232292SN/A return false; 12242292SN/A } 12252292SN/A 12262292SN/A return true; 12271060SN/A} 12282292SN/A 12292301SN/Atemplate <class Impl> 12302301SN/Avoid 12312301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 12322301SN/A{ 12332301SN/A unsigned thread = inst->threadNumber; 12342301SN/A 12352301SN/A // 12362301SN/A // Pick off the software prefetches 12372301SN/A // 12382301SN/A#ifdef TARGET_ALPHA 12392301SN/A if (inst->isDataPrefetch()) { 12402316SN/A statComSwp[thread]++; 12412301SN/A } else { 12422316SN/A statComInst[thread]++; 12432301SN/A } 12442301SN/A#else 12452316SN/A statComInst[thread]++; 12462301SN/A#endif 12472301SN/A 12482301SN/A // 12492301SN/A // Control Instructions 12502301SN/A // 12512301SN/A if (inst->isControl()) 12522316SN/A statComBranches[thread]++; 12532301SN/A 12542301SN/A // 12552301SN/A // Memory references 12562301SN/A // 12572301SN/A if (inst->isMemRef()) { 12582316SN/A statComRefs[thread]++; 12592301SN/A 12602301SN/A if (inst->isLoad()) { 12612316SN/A statComLoads[thread]++; 12622301SN/A } 12632301SN/A } 12642301SN/A 12652301SN/A if (inst->isMemBarrier()) { 12662316SN/A statComMembars[thread]++; 12672301SN/A } 12682301SN/A} 12692301SN/A 12702292SN/A//////////////////////////////////////// 12712292SN/A// // 12722316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 12732292SN/A// // 12742292SN/A//////////////////////////////////////// 12752292SN/Atemplate <class Impl> 12762292SN/Aint 12772292SN/ADefaultCommit<Impl>::getCommittingThread() 12782292SN/A{ 12792292SN/A if (numThreads > 1) { 12802292SN/A switch (commitPolicy) { 12812292SN/A 12822292SN/A case Aggressive: 12832292SN/A //If Policy is Aggressive, commit will call 12842292SN/A //this function multiple times per 12852292SN/A //cycle 12862292SN/A return oldestReady(); 12872292SN/A 12882292SN/A case RoundRobin: 12892292SN/A return roundRobin(); 12902292SN/A 12912292SN/A case OldestReady: 12922292SN/A return oldestReady(); 12932292SN/A 12942292SN/A default: 12952292SN/A return -1; 12962292SN/A } 12972292SN/A } else { 12983867Sbinkertn@umich.edu assert(!activeThreads->empty()); 12993867Sbinkertn@umich.edu int tid = activeThreads->front(); 13002292SN/A 13012292SN/A if (commitStatus[tid] == Running || 13022292SN/A commitStatus[tid] == Idle || 13032292SN/A commitStatus[tid] == FetchTrapPending) { 13042292SN/A return tid; 13052292SN/A } else { 13062292SN/A return -1; 13072292SN/A } 13082292SN/A } 13092292SN/A} 13102292SN/A 13112292SN/Atemplate<class Impl> 13122292SN/Aint 13132292SN/ADefaultCommit<Impl>::roundRobin() 13142292SN/A{ 13152980Sgblack@eecs.umich.edu std::list<unsigned>::iterator pri_iter = priority_list.begin(); 13162980Sgblack@eecs.umich.edu std::list<unsigned>::iterator end = priority_list.end(); 13172292SN/A 13182292SN/A while (pri_iter != end) { 13192292SN/A unsigned tid = *pri_iter; 13202292SN/A 13212292SN/A if (commitStatus[tid] == Running || 13222831Sksewell@umich.edu commitStatus[tid] == Idle || 13232831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 13242292SN/A 13252292SN/A if (rob->isHeadReady(tid)) { 13262292SN/A priority_list.erase(pri_iter); 13272292SN/A priority_list.push_back(tid); 13282292SN/A 13292292SN/A return tid; 13302292SN/A } 13312292SN/A } 13322292SN/A 13332292SN/A pri_iter++; 13342292SN/A } 13352292SN/A 13362292SN/A return -1; 13372292SN/A} 13382292SN/A 13392292SN/Atemplate<class Impl> 13402292SN/Aint 13412292SN/ADefaultCommit<Impl>::oldestReady() 13422292SN/A{ 13432292SN/A unsigned oldest = 0; 13442292SN/A bool first = true; 13452292SN/A 13463867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 13473867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 13482292SN/A 13493867Sbinkertn@umich.edu while (threads != end) { 13502292SN/A unsigned tid = *threads++; 13512292SN/A 13522292SN/A if (!rob->isEmpty(tid) && 13532292SN/A (commitStatus[tid] == Running || 13542292SN/A commitStatus[tid] == Idle || 13552292SN/A commitStatus[tid] == FetchTrapPending)) { 13562292SN/A 13572292SN/A if (rob->isHeadReady(tid)) { 13582292SN/A 13592292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 13602292SN/A 13612292SN/A if (first) { 13622292SN/A oldest = tid; 13632292SN/A first = false; 13642292SN/A } else if (head_inst->seqNum < oldest) { 13652292SN/A oldest = tid; 13662292SN/A } 13672292SN/A } 13682292SN/A } 13692292SN/A } 13702292SN/A 13712292SN/A if (!first) { 13722292SN/A return oldest; 13732292SN/A } else { 13742292SN/A return -1; 13752292SN/A } 13762292SN/A} 1377