commit_impl.hh revision 4636
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292965Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322733Sktlim@umich.edu#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 342733Sktlim@umich.edu 352292SN/A#include <algorithm> 362329SN/A#include <string> 372292SN/A 383577Sgblack@eecs.umich.edu#include "arch/utility.hh" 392292SN/A#include "base/loader/symtab.hh" 401060SN/A#include "base/timebuf.hh" 412292SN/A#include "cpu/exetrace.hh" 421717SN/A#include "cpu/o3/commit.hh" 432292SN/A#include "cpu/o3/thread_state.hh" 442292SN/A 452790Sktlim@umich.edu#if USE_CHECKER 462790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 472790Sktlim@umich.edu#endif 482790Sktlim@umich.edu 491061SN/Atemplate <class Impl> 502292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 512292SN/A unsigned _tid) 522292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 531060SN/A{ 542292SN/A this->setFlags(Event::AutoDelete); 551060SN/A} 561060SN/A 571061SN/Atemplate <class Impl> 581060SN/Avoid 592292SN/ADefaultCommit<Impl>::TrapEvent::process() 601062SN/A{ 612316SN/A // This will get reset by commit if it was switched out at the 622316SN/A // time of this event processing. 632292SN/A commit->trapSquash[tid] = true; 642292SN/A} 652292SN/A 662292SN/Atemplate <class Impl> 672292SN/Aconst char * 682292SN/ADefaultCommit<Impl>::TrapEvent::description() 692292SN/A{ 702292SN/A return "Trap event"; 712292SN/A} 722292SN/A 732292SN/Atemplate <class Impl> 744329Sktlim@umich.eduDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params) 754329Sktlim@umich.edu : cpu(_cpu), 764329Sktlim@umich.edu squashCounter(0), 772292SN/A iewToCommitDelay(params->iewToCommitDelay), 782292SN/A commitToIEWDelay(params->commitToIEWDelay), 792292SN/A renameToROBDelay(params->renameToROBDelay), 802292SN/A fetchToCommitDelay(params->commitToFetchDelay), 812292SN/A renameWidth(params->renameWidth), 822292SN/A commitWidth(params->commitWidth), 832307SN/A numThreads(params->numberOfThreads), 842843Sktlim@umich.edu drainPending(false), 852316SN/A switchedOut(false), 862874Sktlim@umich.edu trapLatency(params->trapLatency) 872292SN/A{ 882292SN/A _status = Active; 892292SN/A _nextStatus = Inactive; 902980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 912292SN/A 922292SN/A //Convert string to lowercase 932292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 942292SN/A (int(*)(int)) tolower); 952292SN/A 962292SN/A //Assign commit policy 972292SN/A if (policy == "aggressive"){ 982292SN/A commitPolicy = Aggressive; 992292SN/A 1004329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive."); 1012292SN/A } else if (policy == "roundrobin"){ 1022292SN/A commitPolicy = RoundRobin; 1032292SN/A 1042292SN/A //Set-Up Priority List 1052292SN/A for (int tid=0; tid < numThreads; tid++) { 1062292SN/A priority_list.push_back(tid); 1072292SN/A } 1082292SN/A 1094329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 1102292SN/A } else if (policy == "oldestready"){ 1112292SN/A commitPolicy = OldestReady; 1122292SN/A 1134329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1142292SN/A } else { 1152292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1162292SN/A "RoundRobin,OldestReady}"); 1172292SN/A } 1182292SN/A 1192292SN/A for (int i=0; i < numThreads; i++) { 1202292SN/A commitStatus[i] = Idle; 1212292SN/A changedROBNumEntries[i] = false; 1224035Sktlim@umich.edu checkEmptyROB[i] = false; 1234035Sktlim@umich.edu trapInFlight[i] = false; 1244035Sktlim@umich.edu committedStores[i] = false; 1252292SN/A trapSquash[i] = false; 1262680Sktlim@umich.edu tcSquash[i] = false; 1274636Sgblack@eecs.umich.edu microPC[i] = nextMicroPC[i] = PC[i] = nextPC[i] = nextNPC[i] = 0; 1282292SN/A } 1293640Sktlim@umich.edu#if FULL_SYSTEM 1303640Sktlim@umich.edu interrupt = NoFault; 1313640Sktlim@umich.edu#endif 1322292SN/A} 1332292SN/A 1342292SN/Atemplate <class Impl> 1352292SN/Astd::string 1362292SN/ADefaultCommit<Impl>::name() const 1372292SN/A{ 1382292SN/A return cpu->name() + ".commit"; 1392292SN/A} 1402292SN/A 1412292SN/Atemplate <class Impl> 1422292SN/Avoid 1432292SN/ADefaultCommit<Impl>::regStats() 1442132SN/A{ 1452301SN/A using namespace Stats; 1461062SN/A commitCommittedInsts 1471062SN/A .name(name() + ".commitCommittedInsts") 1481062SN/A .desc("The number of committed instructions") 1491062SN/A .prereq(commitCommittedInsts); 1501062SN/A commitSquashedInsts 1511062SN/A .name(name() + ".commitSquashedInsts") 1521062SN/A .desc("The number of squashed insts skipped by commit") 1531062SN/A .prereq(commitSquashedInsts); 1541062SN/A commitSquashEvents 1551062SN/A .name(name() + ".commitSquashEvents") 1561062SN/A .desc("The number of times commit is told to squash") 1571062SN/A .prereq(commitSquashEvents); 1581062SN/A commitNonSpecStalls 1591062SN/A .name(name() + ".commitNonSpecStalls") 1601062SN/A .desc("The number of times commit has been forced to stall to " 1611062SN/A "communicate backwards") 1621062SN/A .prereq(commitNonSpecStalls); 1631062SN/A branchMispredicts 1641062SN/A .name(name() + ".branchMispredicts") 1651062SN/A .desc("The number of times a branch was mispredicted") 1661062SN/A .prereq(branchMispredicts); 1672292SN/A numCommittedDist 1681062SN/A .init(0,commitWidth,1) 1691062SN/A .name(name() + ".COM:committed_per_cycle") 1701062SN/A .desc("Number of insts commited each cycle") 1711062SN/A .flags(Stats::pdf) 1721062SN/A ; 1732301SN/A 1742316SN/A statComInst 1752301SN/A .init(cpu->number_of_threads) 1762301SN/A .name(name() + ".COM:count") 1772301SN/A .desc("Number of instructions committed") 1782301SN/A .flags(total) 1792301SN/A ; 1802301SN/A 1812316SN/A statComSwp 1822301SN/A .init(cpu->number_of_threads) 1832301SN/A .name(name() + ".COM:swp_count") 1842301SN/A .desc("Number of s/w prefetches committed") 1852301SN/A .flags(total) 1862301SN/A ; 1872301SN/A 1882316SN/A statComRefs 1892301SN/A .init(cpu->number_of_threads) 1902301SN/A .name(name() + ".COM:refs") 1912301SN/A .desc("Number of memory references committed") 1922301SN/A .flags(total) 1932301SN/A ; 1942301SN/A 1952316SN/A statComLoads 1962301SN/A .init(cpu->number_of_threads) 1972301SN/A .name(name() + ".COM:loads") 1982301SN/A .desc("Number of loads committed") 1992301SN/A .flags(total) 2002301SN/A ; 2012301SN/A 2022316SN/A statComMembars 2032301SN/A .init(cpu->number_of_threads) 2042301SN/A .name(name() + ".COM:membars") 2052301SN/A .desc("Number of memory barriers committed") 2062301SN/A .flags(total) 2072301SN/A ; 2082301SN/A 2092316SN/A statComBranches 2102301SN/A .init(cpu->number_of_threads) 2112301SN/A .name(name() + ".COM:branches") 2122301SN/A .desc("Number of branches committed") 2132301SN/A .flags(total) 2142301SN/A ; 2152301SN/A 2162316SN/A commitEligible 2172301SN/A .init(cpu->number_of_threads) 2182301SN/A .name(name() + ".COM:bw_limited") 2192301SN/A .desc("number of insts not committed due to BW limits") 2202301SN/A .flags(total) 2212301SN/A ; 2222301SN/A 2232316SN/A commitEligibleSamples 2242301SN/A .name(name() + ".COM:bw_lim_events") 2252301SN/A .desc("number cycles where commit BW limit reached") 2262301SN/A ; 2271062SN/A} 2281062SN/A 2291062SN/Atemplate <class Impl> 2301062SN/Avoid 2312980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2322292SN/A{ 2332292SN/A thread = threads; 2342292SN/A} 2352292SN/A 2362292SN/Atemplate <class Impl> 2372292SN/Avoid 2382292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2391060SN/A{ 2401060SN/A timeBuffer = tb_ptr; 2411060SN/A 2421060SN/A // Setup wire to send information back to IEW. 2431060SN/A toIEW = timeBuffer->getWire(0); 2441060SN/A 2451060SN/A // Setup wire to read data from IEW (for the ROB). 2461060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2471060SN/A} 2481060SN/A 2491061SN/Atemplate <class Impl> 2501060SN/Avoid 2512292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2522292SN/A{ 2532292SN/A fetchQueue = fq_ptr; 2542292SN/A 2552292SN/A // Setup wire to get instructions from rename (for the ROB). 2562292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2572292SN/A} 2582292SN/A 2592292SN/Atemplate <class Impl> 2602292SN/Avoid 2612292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2621060SN/A{ 2631060SN/A renameQueue = rq_ptr; 2641060SN/A 2651060SN/A // Setup wire to get instructions from rename (for the ROB). 2661060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2671060SN/A} 2681060SN/A 2691061SN/Atemplate <class Impl> 2701060SN/Avoid 2712292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2721060SN/A{ 2731060SN/A iewQueue = iq_ptr; 2741060SN/A 2751060SN/A // Setup wire to get instructions from IEW. 2761060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2771060SN/A} 2781060SN/A 2791061SN/Atemplate <class Impl> 2801060SN/Avoid 2812292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2822292SN/A{ 2832292SN/A iewStage = iew_stage; 2842292SN/A} 2852292SN/A 2862292SN/Atemplate<class Impl> 2872292SN/Avoid 2882980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2892292SN/A{ 2902292SN/A activeThreads = at_ptr; 2912292SN/A} 2922292SN/A 2932292SN/Atemplate <class Impl> 2942292SN/Avoid 2952292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 2962292SN/A{ 2972292SN/A for (int i=0; i < numThreads; i++) { 2982292SN/A renameMap[i] = &rm_ptr[i]; 2992292SN/A } 3002292SN/A} 3012292SN/A 3022292SN/Atemplate <class Impl> 3032292SN/Avoid 3042292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3051060SN/A{ 3061060SN/A rob = rob_ptr; 3071060SN/A} 3081060SN/A 3091061SN/Atemplate <class Impl> 3101060SN/Avoid 3112292SN/ADefaultCommit<Impl>::initStage() 3121060SN/A{ 3132292SN/A rob->setActiveThreads(activeThreads); 3142292SN/A rob->resetEntries(); 3151060SN/A 3162292SN/A // Broadcast the number of free entries. 3172292SN/A for (int i=0; i < numThreads; i++) { 3182292SN/A toIEW->commitInfo[i].usedROB = true; 3192292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3204035Sktlim@umich.edu toIEW->commitInfo[i].emptyROB = true; 3211060SN/A } 3221060SN/A 3234329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3244329Sktlim@umich.edu // start of the simulation, so it starts as active. 3254329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3264329Sktlim@umich.edu 3272292SN/A cpu->activityThisCycle(); 3284329Sktlim@umich.edu trapLatency = cpu->cycles(trapLatency); 3291060SN/A} 3301060SN/A 3311061SN/Atemplate <class Impl> 3322863Sktlim@umich.edubool 3332843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3341060SN/A{ 3352843Sktlim@umich.edu drainPending = true; 3362863Sktlim@umich.edu 3372863Sktlim@umich.edu return false; 3382316SN/A} 3392316SN/A 3402316SN/Atemplate <class Impl> 3412316SN/Avoid 3422843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3432316SN/A{ 3442316SN/A switchedOut = true; 3452843Sktlim@umich.edu drainPending = false; 3462307SN/A rob->switchOut(); 3472307SN/A} 3482307SN/A 3492307SN/Atemplate <class Impl> 3502307SN/Avoid 3512843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3522843Sktlim@umich.edu{ 3532864Sktlim@umich.edu drainPending = false; 3542843Sktlim@umich.edu} 3552843Sktlim@umich.edu 3562843Sktlim@umich.edutemplate <class Impl> 3572843Sktlim@umich.eduvoid 3582307SN/ADefaultCommit<Impl>::takeOverFrom() 3592307SN/A{ 3602316SN/A switchedOut = false; 3612307SN/A _status = Active; 3622307SN/A _nextStatus = Inactive; 3632307SN/A for (int i=0; i < numThreads; i++) { 3642307SN/A commitStatus[i] = Idle; 3652307SN/A changedROBNumEntries[i] = false; 3662307SN/A trapSquash[i] = false; 3672680Sktlim@umich.edu tcSquash[i] = false; 3682307SN/A } 3692307SN/A squashCounter = 0; 3702307SN/A rob->takeOverFrom(); 3712307SN/A} 3722307SN/A 3732307SN/Atemplate <class Impl> 3742307SN/Avoid 3752292SN/ADefaultCommit<Impl>::updateStatus() 3762132SN/A{ 3772316SN/A // reset ROB changed variable 3783867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 3793867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 3803867Sbinkertn@umich.edu 3813867Sbinkertn@umich.edu while (threads != end) { 3822316SN/A unsigned tid = *threads++; 3833867Sbinkertn@umich.edu 3842316SN/A changedROBNumEntries[tid] = false; 3852316SN/A 3862316SN/A // Also check if any of the threads has a trap pending 3872316SN/A if (commitStatus[tid] == TrapPending || 3882316SN/A commitStatus[tid] == FetchTrapPending) { 3892316SN/A _nextStatus = Active; 3902316SN/A } 3912292SN/A } 3922292SN/A 3932292SN/A if (_nextStatus == Inactive && _status == Active) { 3942292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 3952733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 3962292SN/A } else if (_nextStatus == Active && _status == Inactive) { 3972292SN/A DPRINTF(Activity, "Activating stage.\n"); 3982733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3992292SN/A } 4002292SN/A 4012292SN/A _status = _nextStatus; 4022292SN/A} 4032292SN/A 4042292SN/Atemplate <class Impl> 4052292SN/Avoid 4062292SN/ADefaultCommit<Impl>::setNextStatus() 4072292SN/A{ 4082292SN/A int squashes = 0; 4092292SN/A 4103867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4113867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4122292SN/A 4133867Sbinkertn@umich.edu while (threads != end) { 4142292SN/A unsigned tid = *threads++; 4152292SN/A 4162292SN/A if (commitStatus[tid] == ROBSquashing) { 4172292SN/A squashes++; 4182292SN/A } 4192292SN/A } 4202292SN/A 4212702Sktlim@umich.edu squashCounter = squashes; 4222292SN/A 4232292SN/A // If commit is currently squashing, then it will have activity for the 4242292SN/A // next cycle. Set its next status as active. 4252292SN/A if (squashCounter) { 4262292SN/A _nextStatus = Active; 4272292SN/A } 4282292SN/A} 4292292SN/A 4302292SN/Atemplate <class Impl> 4312292SN/Abool 4322292SN/ADefaultCommit<Impl>::changedROBEntries() 4332292SN/A{ 4343867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4353867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4362292SN/A 4373867Sbinkertn@umich.edu while (threads != end) { 4382292SN/A unsigned tid = *threads++; 4392292SN/A 4402292SN/A if (changedROBNumEntries[tid]) { 4412292SN/A return true; 4422292SN/A } 4432292SN/A } 4442292SN/A 4452292SN/A return false; 4462292SN/A} 4472292SN/A 4482292SN/Atemplate <class Impl> 4492292SN/Aunsigned 4502292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4512292SN/A{ 4522292SN/A return rob->numFreeEntries(tid); 4532292SN/A} 4542292SN/A 4552292SN/Atemplate <class Impl> 4562292SN/Avoid 4572292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4582292SN/A{ 4592292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4602292SN/A 4612292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4622292SN/A 4632292SN/A trap->schedule(curTick + trapLatency); 4644035Sktlim@umich.edu trapInFlight[tid] = true; 4652292SN/A} 4662292SN/A 4672292SN/Atemplate <class Impl> 4682292SN/Avoid 4692680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4702292SN/A{ 4714035Sktlim@umich.edu assert(!trapInFlight[tid]); 4722680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4732292SN/A 4742680Sktlim@umich.edu tcSquash[tid] = true; 4752292SN/A} 4762292SN/A 4772292SN/Atemplate <class Impl> 4782292SN/Avoid 4792316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4802292SN/A{ 4812292SN/A // If we want to include the squashing instruction in the squash, 4822292SN/A // then use one older sequence number. 4832292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4842292SN/A // all instructions of this thread. 4852292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 4864035Sktlim@umich.edu 0 : rob->readHeadInst(tid)->seqNum - 1; 4872292SN/A 4882292SN/A // All younger instructions will be squashed. Set the sequence 4892292SN/A // number as the youngest instruction in the ROB (0 in this case. 4902292SN/A // Hopefully nothing breaks.) 4912292SN/A youngestSeqNum[tid] = 0; 4922292SN/A 4932292SN/A rob->squash(squashed_inst, tid); 4942292SN/A changedROBNumEntries[tid] = true; 4952292SN/A 4962292SN/A // Send back the sequence number of the squashed instruction. 4972292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 4982292SN/A 4992292SN/A // Send back the squash signal to tell stages that they should 5002292SN/A // squash. 5012292SN/A toIEW->commitInfo[tid].squash = true; 5022292SN/A 5032292SN/A // Send back the rob squashing signal so other stages know that 5042292SN/A // the ROB is in the process of squashing. 5052292SN/A toIEW->commitInfo[tid].robSquashing = true; 5062292SN/A 5072292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5082292SN/A 5092316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5103795Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextNPC = nextPC[tid]; 5114636Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid]; 5122316SN/A} 5132292SN/A 5142316SN/Atemplate <class Impl> 5152316SN/Avoid 5162316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5172316SN/A{ 5182316SN/A squashAll(tid); 5192316SN/A 5202316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5212316SN/A 5222316SN/A thread[tid]->trapPending = false; 5232316SN/A thread[tid]->inSyscall = false; 5244035Sktlim@umich.edu trapInFlight[tid] = false; 5252316SN/A 5262316SN/A trapSquash[tid] = false; 5272316SN/A 5282316SN/A commitStatus[tid] = ROBSquashing; 5292316SN/A cpu->activityThisCycle(); 5302316SN/A} 5312316SN/A 5322316SN/Atemplate <class Impl> 5332316SN/Avoid 5342680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5352316SN/A{ 5362316SN/A squashAll(tid); 5372292SN/A 5382680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5392292SN/A 5402292SN/A thread[tid]->inSyscall = false; 5412292SN/A assert(!thread[tid]->trapPending); 5422316SN/A 5432292SN/A commitStatus[tid] = ROBSquashing; 5442292SN/A cpu->activityThisCycle(); 5452292SN/A 5462680Sktlim@umich.edu tcSquash[tid] = false; 5472292SN/A} 5482292SN/A 5492292SN/Atemplate <class Impl> 5502292SN/Avoid 5512292SN/ADefaultCommit<Impl>::tick() 5522292SN/A{ 5532292SN/A wroteToTimeBuffer = false; 5542292SN/A _nextStatus = Inactive; 5552292SN/A 5562843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5572843Sktlim@umich.edu cpu->signalDrained(); 5582843Sktlim@umich.edu drainPending = false; 5592316SN/A return; 5602316SN/A } 5612316SN/A 5623867Sbinkertn@umich.edu if (activeThreads->empty()) 5632875Sksewell@umich.edu return; 5642875Sksewell@umich.edu 5653867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 5663867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 5672292SN/A 5682316SN/A // Check if any of the threads are done squashing. Change the 5692316SN/A // status if they are done. 5703867Sbinkertn@umich.edu while (threads != end) { 5712292SN/A unsigned tid = *threads++; 5722292SN/A 5734035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 5744035Sktlim@umich.edu // this cycle. 5754035Sktlim@umich.edu committedStores[tid] = false; 5764035Sktlim@umich.edu 5772292SN/A if (commitStatus[tid] == ROBSquashing) { 5782292SN/A 5792292SN/A if (rob->isDoneSquashing(tid)) { 5802292SN/A commitStatus[tid] = Running; 5812292SN/A } else { 5822292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5832877Sksewell@umich.edu " insts this cycle.\n", tid); 5842702Sktlim@umich.edu rob->doSquash(tid); 5852702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5862702Sktlim@umich.edu wroteToTimeBuffer = true; 5872292SN/A } 5882292SN/A } 5892292SN/A } 5902292SN/A 5912292SN/A commit(); 5922292SN/A 5932292SN/A markCompletedInsts(); 5942292SN/A 5953867Sbinkertn@umich.edu threads = activeThreads->begin(); 5962292SN/A 5973867Sbinkertn@umich.edu while (threads != end) { 5982292SN/A unsigned tid = *threads++; 5992292SN/A 6002292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6012292SN/A // The ROB has more instructions it can commit. Its next status 6022292SN/A // will be active. 6032292SN/A _nextStatus = Active; 6042292SN/A 6052292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6062292SN/A 6072292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6082292SN/A " ROB and ready to commit\n", 6092292SN/A tid, inst->seqNum, inst->readPC()); 6102292SN/A 6112292SN/A } else if (!rob->isEmpty(tid)) { 6122292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6132292SN/A 6142292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6152292SN/A "%#x is head of ROB and not ready\n", 6162292SN/A tid, inst->seqNum, inst->readPC()); 6172292SN/A } 6182292SN/A 6192292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6202292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6212292SN/A } 6222292SN/A 6232292SN/A 6242292SN/A if (wroteToTimeBuffer) { 6252316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6262292SN/A cpu->activityThisCycle(); 6272292SN/A } 6282292SN/A 6292292SN/A updateStatus(); 6302292SN/A} 6312292SN/A 6324035Sktlim@umich.edu#if FULL_SYSTEM 6332292SN/Atemplate <class Impl> 6342292SN/Avoid 6354035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 6362292SN/A{ 6373640Sktlim@umich.edu if (interrupt != NoFault) { 6382316SN/A // Wait until the ROB is empty and all stores have drained in 6392316SN/A // order to enter the interrupt. 6402292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6413633Sktlim@umich.edu // Squash or record that I need to squash this cycle if 6423633Sktlim@umich.edu // an interrupt needed to be handled. 6433633Sktlim@umich.edu DPRINTF(Commit, "Interrupt detected.\n"); 6443633Sktlim@umich.edu 6454035Sktlim@umich.edu Fault new_interrupt = cpu->getInterrupts(); 6464288Sktlim@umich.edu assert(new_interrupt != NoFault); 6474035Sktlim@umich.edu 6484035Sktlim@umich.edu // Clear the interrupt now that it's going to be handled 6494035Sktlim@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 6504035Sktlim@umich.edu 6512292SN/A assert(!thread[0]->inSyscall); 6522292SN/A thread[0]->inSyscall = true; 6532292SN/A 6543633Sktlim@umich.edu // CPU will handle interrupt. 6553640Sktlim@umich.edu cpu->processInterrupts(interrupt); 6562292SN/A 6573633Sktlim@umich.edu thread[0]->inSyscall = false; 6583633Sktlim@umich.edu 6592292SN/A commitStatus[0] = TrapPending; 6602292SN/A 6612292SN/A // Generate trap squash event. 6622292SN/A generateTrapEvent(0); 6632292SN/A 6643640Sktlim@umich.edu interrupt = NoFault; 6652292SN/A } else { 6662292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6672292SN/A } 6684035Sktlim@umich.edu } else if (commitStatus[0] != TrapPending && 6694035Sktlim@umich.edu cpu->check_interrupts(cpu->tcBase(0)) && 6704035Sktlim@umich.edu !trapSquash[0] && 6714035Sktlim@umich.edu !tcSquash[0]) { 6723640Sktlim@umich.edu // Process interrupts if interrupts are enabled, not in PAL 6733640Sktlim@umich.edu // mode, and no other traps or external squashes are currently 6743640Sktlim@umich.edu // pending. 6753640Sktlim@umich.edu // @todo: Allow other threads to handle interrupts. 6763640Sktlim@umich.edu 6773640Sktlim@umich.edu // Get any interrupt that happened 6783640Sktlim@umich.edu interrupt = cpu->getInterrupts(); 6793640Sktlim@umich.edu 6803640Sktlim@umich.edu if (interrupt != NoFault) { 6813640Sktlim@umich.edu // Tell fetch that there is an interrupt pending. This 6823640Sktlim@umich.edu // will make fetch wait until it sees a non PAL-mode PC, 6833640Sktlim@umich.edu // at which point it stops fetching instructions. 6843640Sktlim@umich.edu toIEW->commitInfo[0].interruptPending = true; 6853640Sktlim@umich.edu } 6861060SN/A } 6874035Sktlim@umich.edu} 6884035Sktlim@umich.edu#endif // FULL_SYSTEM 6893634Sktlim@umich.edu 6904035Sktlim@umich.edutemplate <class Impl> 6914035Sktlim@umich.eduvoid 6924035Sktlim@umich.eduDefaultCommit<Impl>::commit() 6934035Sktlim@umich.edu{ 6944035Sktlim@umich.edu 6954035Sktlim@umich.edu#if FULL_SYSTEM 6964035Sktlim@umich.edu // Check for any interrupt, and start processing it. Or if we 6974035Sktlim@umich.edu // have an outstanding interrupt and are at a point when it is 6984035Sktlim@umich.edu // valid to take an interrupt, process it. 6994035Sktlim@umich.edu if (cpu->check_interrupts(cpu->tcBase(0))) { 7004035Sktlim@umich.edu handleInterrupt(); 7014035Sktlim@umich.edu } 7021060SN/A#endif // FULL_SYSTEM 7031060SN/A 7041060SN/A //////////////////////////////////// 7052316SN/A // Check for any possible squashes, handle them first 7061060SN/A //////////////////////////////////// 7073867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7083867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7091060SN/A 7103867Sbinkertn@umich.edu while (threads != end) { 7112292SN/A unsigned tid = *threads++; 7121060SN/A 7132292SN/A // Not sure which one takes priority. I think if we have 7142292SN/A // both, that's a bad sign. 7152292SN/A if (trapSquash[tid] == true) { 7162680Sktlim@umich.edu assert(!tcSquash[tid]); 7172292SN/A squashFromTrap(tid); 7182680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7194035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 7202680Sktlim@umich.edu squashFromTC(tid); 7212292SN/A } 7221061SN/A 7232292SN/A // Squashed sequence number must be older than youngest valid 7242292SN/A // instruction in the ROB. This prevents squashes from younger 7252292SN/A // instructions overriding squashes from older instructions. 7262292SN/A if (fromIEW->squash[tid] && 7272292SN/A commitStatus[tid] != TrapPending && 7282292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7291061SN/A 7302292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7312292SN/A tid, 7322292SN/A fromIEW->mispredPC[tid], 7332292SN/A fromIEW->squashedSeqNum[tid]); 7341061SN/A 7352292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7362292SN/A tid, 7372292SN/A fromIEW->nextPC[tid]); 7381061SN/A 7392292SN/A commitStatus[tid] = ROBSquashing; 7401061SN/A 7412292SN/A // If we want to include the squashing instruction in the squash, 7422292SN/A // then use one older sequence number. 7432292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7441062SN/A 7452935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 7462292SN/A squashed_inst--; 7472935Sksewell@umich.edu } 7484035Sktlim@umich.edu 7492292SN/A // All younger instructions will be squashed. Set the sequence 7502292SN/A // number as the youngest instruction in the ROB. 7512292SN/A youngestSeqNum[tid] = squashed_inst; 7522292SN/A 7533093Sksewell@umich.edu rob->squash(squashed_inst, tid); 7542292SN/A changedROBNumEntries[tid] = true; 7552292SN/A 7562292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7572292SN/A 7582292SN/A toIEW->commitInfo[tid].squash = true; 7592292SN/A 7602292SN/A // Send back the rob squashing signal so other stages know that 7612292SN/A // the ROB is in the process of squashing. 7622292SN/A toIEW->commitInfo[tid].robSquashing = true; 7632292SN/A 7642292SN/A toIEW->commitInfo[tid].branchMispredict = 7652292SN/A fromIEW->branchMispredict[tid]; 7662292SN/A 7672292SN/A toIEW->commitInfo[tid].branchTaken = 7682292SN/A fromIEW->branchTaken[tid]; 7692292SN/A 7702292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7713795Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid]; 7724636Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid]; 7732292SN/A 7742316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7752292SN/A 7762292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7772292SN/A ++branchMispredicts; 7782292SN/A } 7791062SN/A } 7802292SN/A 7811060SN/A } 7821060SN/A 7832292SN/A setNextStatus(); 7842292SN/A 7852292SN/A if (squashCounter != numThreads) { 7861061SN/A // If we're not currently squashing, then get instructions. 7871060SN/A getInsts(); 7881060SN/A 7891061SN/A // Try to commit any instructions. 7901060SN/A commitInsts(); 7911060SN/A } 7921060SN/A 7932292SN/A //Check for any activity 7943867Sbinkertn@umich.edu threads = activeThreads->begin(); 7952292SN/A 7963867Sbinkertn@umich.edu while (threads != end) { 7972292SN/A unsigned tid = *threads++; 7982292SN/A 7992292SN/A if (changedROBNumEntries[tid]) { 8002292SN/A toIEW->commitInfo[tid].usedROB = true; 8012292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8022292SN/A 8032292SN/A wroteToTimeBuffer = true; 8042292SN/A changedROBNumEntries[tid] = false; 8054035Sktlim@umich.edu if (rob->isEmpty(tid)) 8064035Sktlim@umich.edu checkEmptyROB[tid] = true; 8072292SN/A } 8084035Sktlim@umich.edu 8094035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8104035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 8114035Sktlim@umich.edu // stage has received any information regarding stores that 8124035Sktlim@umich.edu // committed. 8134035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 8144035Sktlim@umich.edu // on the same cycle as when stores have been committed. 8154035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 8164035Sktlim@umich.edu // commit and IEW. 8174035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 8184035Sktlim@umich.edu !iewStage->hasStoresToWB() && !committedStores[tid]) { 8194035Sktlim@umich.edu checkEmptyROB[tid] = false; 8204035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 8214035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 8224035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8234035Sktlim@umich.edu wroteToTimeBuffer = true; 8244035Sktlim@umich.edu } 8254035Sktlim@umich.edu 8261060SN/A } 8271060SN/A} 8281060SN/A 8291061SN/Atemplate <class Impl> 8301060SN/Avoid 8312292SN/ADefaultCommit<Impl>::commitInsts() 8321060SN/A{ 8331060SN/A //////////////////////////////////// 8341060SN/A // Handle commit 8352316SN/A // Note that commit will be handled prior to putting new 8362316SN/A // instructions in the ROB so that the ROB only tries to commit 8372316SN/A // instructions it has in this current cycle, and not instructions 8382316SN/A // it is writing in during this cycle. Can't commit and squash 8392316SN/A // things at the same time... 8401060SN/A //////////////////////////////////// 8411060SN/A 8422292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8431060SN/A 8441060SN/A unsigned num_committed = 0; 8451060SN/A 8462292SN/A DynInstPtr head_inst; 8472316SN/A 8481060SN/A // Commit as many instructions as possible until the commit bandwidth 8491060SN/A // limit is reached, or it becomes impossible to commit any more. 8502292SN/A while (num_committed < commitWidth) { 8512292SN/A int commit_thread = getCommittingThread(); 8521060SN/A 8532292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8542292SN/A break; 8552292SN/A 8562292SN/A head_inst = rob->readHeadInst(commit_thread); 8572292SN/A 8582292SN/A int tid = head_inst->threadNumber; 8592292SN/A 8602292SN/A assert(tid == commit_thread); 8612292SN/A 8622292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8632292SN/A head_inst->seqNum, tid); 8642132SN/A 8652316SN/A // If the head instruction is squashed, it is ready to retire 8662316SN/A // (be removed from the ROB) at any time. 8671060SN/A if (head_inst->isSquashed()) { 8681060SN/A 8692292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8701060SN/A "ROB.\n"); 8711060SN/A 8722292SN/A rob->retireHead(commit_thread); 8731060SN/A 8741062SN/A ++commitSquashedInsts; 8751062SN/A 8762292SN/A // Record that the number of ROB entries has changed. 8772292SN/A changedROBNumEntries[tid] = true; 8781060SN/A } else { 8792292SN/A PC[tid] = head_inst->readPC(); 8802292SN/A nextPC[tid] = head_inst->readNextPC(); 8812935Sksewell@umich.edu nextNPC[tid] = head_inst->readNextNPC(); 8824636Sgblack@eecs.umich.edu nextMicroPC[tid] = head_inst->readNextMicroPC(); 8832292SN/A 8841060SN/A // Increment the total number of non-speculative instructions 8851060SN/A // executed. 8861060SN/A // Hack for now: it really shouldn't happen until after the 8871061SN/A // commit is deemed to be successful, but this count is needed 8881061SN/A // for syscalls. 8892292SN/A thread[tid]->funcExeInst++; 8901060SN/A 8911060SN/A // Try to commit the head instruction. 8921060SN/A bool commit_success = commitHead(head_inst, num_committed); 8931060SN/A 8941062SN/A if (commit_success) { 8951060SN/A ++num_committed; 8961060SN/A 8972292SN/A changedROBNumEntries[tid] = true; 8982292SN/A 8992292SN/A // Set the doneSeqNum to the youngest committed instruction. 9002292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9011060SN/A 9021062SN/A ++commitCommittedInsts; 9031062SN/A 9042292SN/A // To match the old model, don't count nops and instruction 9052292SN/A // prefetches towards the total commit count. 9062292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9072292SN/A cpu->instDone(tid); 9081062SN/A } 9092292SN/A 9102292SN/A PC[tid] = nextPC[tid]; 9112935Sksewell@umich.edu nextPC[tid] = nextNPC[tid]; 9122935Sksewell@umich.edu nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 9134636Sgblack@eecs.umich.edu microPC[tid] = nextMicroPC[tid]; 9144636Sgblack@eecs.umich.edu nextMicroPC[tid] = microPC[tid] + 1; 9152935Sksewell@umich.edu 9162292SN/A#if FULL_SYSTEM 9172292SN/A int count = 0; 9182292SN/A Addr oldpc; 9192292SN/A do { 9202316SN/A // Debug statement. Checks to make sure we're not 9212316SN/A // currently updating state while handling PC events. 9222292SN/A if (count == 0) 9232316SN/A assert(!thread[tid]->inSyscall && 9242316SN/A !thread[tid]->trapPending); 9252292SN/A oldpc = PC[tid]; 9262292SN/A cpu->system->pcEventQueue.service( 9272690Sktlim@umich.edu thread[tid]->getTC()); 9282292SN/A count++; 9292292SN/A } while (oldpc != PC[tid]); 9302292SN/A if (count > 1) { 9312292SN/A DPRINTF(Commit, "PC skip function event, stopping commit\n"); 9322292SN/A break; 9332292SN/A } 9342292SN/A#endif 9351060SN/A } else { 9362292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9372292SN/A "[tid:%i] [sn:%i].\n", 9382292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9391060SN/A break; 9401060SN/A } 9411060SN/A } 9421060SN/A } 9431062SN/A 9441063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9452292SN/A numCommittedDist.sample(num_committed); 9462307SN/A 9472307SN/A if (num_committed == commitWidth) { 9482349SN/A commitEligibleSamples++; 9492307SN/A } 9501060SN/A} 9511060SN/A 9521061SN/Atemplate <class Impl> 9531060SN/Abool 9542292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9551060SN/A{ 9561060SN/A assert(head_inst); 9571060SN/A 9582292SN/A int tid = head_inst->threadNumber; 9592292SN/A 9602316SN/A // If the instruction is not executed yet, then it will need extra 9612316SN/A // handling. Signal backwards that it should be executed. 9621061SN/A if (!head_inst->isExecuted()) { 9631061SN/A // Keep this number correct. We have not yet actually executed 9641061SN/A // and committed this instruction. 9652292SN/A thread[tid]->funcExeInst--; 9661062SN/A 9672292SN/A if (head_inst->isNonSpeculative() || 9682348SN/A head_inst->isStoreConditional() || 9692292SN/A head_inst->isMemBarrier() || 9702292SN/A head_inst->isWriteBarrier()) { 9712316SN/A 9722316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9732316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9742316SN/A head_inst->seqNum, head_inst->readPC()); 9752316SN/A 9764035Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB()) { 9772292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9782292SN/A return false; 9792292SN/A } 9802292SN/A 9812292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9821061SN/A 9831061SN/A // Change the instruction so it won't try to commit again until 9841061SN/A // it is executed. 9851061SN/A head_inst->clearCanCommit(); 9861061SN/A 9871062SN/A ++commitNonSpecStalls; 9881062SN/A 9891061SN/A return false; 9902292SN/A } else if (head_inst->isLoad()) { 9914035Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB()) { 9924035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9934035Sktlim@umich.edu return false; 9944035Sktlim@umich.edu } 9954035Sktlim@umich.edu 9964035Sktlim@umich.edu assert(head_inst->uncacheable()); 9972292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9982292SN/A head_inst->seqNum, head_inst->readPC()); 9992292SN/A 10002292SN/A // Send back the non-speculative instruction's sequence 10012316SN/A // number. Tell the lsq to re-execute the load. 10022292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10032292SN/A toIEW->commitInfo[tid].uncached = true; 10042292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10052292SN/A 10062292SN/A head_inst->clearCanCommit(); 10072292SN/A 10082292SN/A return false; 10091061SN/A } else { 10102292SN/A panic("Trying to commit un-executed instruction " 10111061SN/A "of unknown type!\n"); 10121061SN/A } 10131060SN/A } 10141060SN/A 10152316SN/A if (head_inst->isThreadSync()) { 10162292SN/A // Not handled for now. 10172316SN/A panic("Thread sync instructions are not handled yet.\n"); 10182132SN/A } 10192132SN/A 10204035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 10214035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 10224035Sktlim@umich.edu 10232316SN/A // Stores mark themselves as completed. 10244035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 10252310SN/A head_inst->setCompleted(); 10262310SN/A } 10272310SN/A 10282733Sktlim@umich.edu#if USE_CHECKER 10292316SN/A // Use checker prior to updating anything due to traps or PC 10302316SN/A // based events. 10312316SN/A if (cpu->checker) { 10322732Sktlim@umich.edu cpu->checker->verify(head_inst); 10331060SN/A } 10342733Sktlim@umich.edu#endif 10351060SN/A 10362918Sktlim@umich.edu // DTB will sometimes need the machine instruction for when 10372918Sktlim@umich.edu // faults happen. So we will set it here, prior to the DTB 10382918Sktlim@umich.edu // possibly needing it for its fault. 10392918Sktlim@umich.edu thread[tid]->setInst( 10402918Sktlim@umich.edu static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10412918Sktlim@umich.edu 10422112SN/A if (inst_fault != NoFault) { 10432316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10442316SN/A head_inst->seqNum, head_inst->readPC()); 10452292SN/A 10462316SN/A if (iewStage->hasStoresToWB() || inst_num > 0) { 10472316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10482316SN/A return false; 10492316SN/A } 10502310SN/A 10514035Sktlim@umich.edu head_inst->setCompleted(); 10524035Sktlim@umich.edu 10532733Sktlim@umich.edu#if USE_CHECKER 10542316SN/A if (cpu->checker && head_inst->isStore()) { 10552732Sktlim@umich.edu cpu->checker->verify(head_inst); 10562316SN/A } 10572733Sktlim@umich.edu#endif 10582292SN/A 10592316SN/A assert(!thread[tid]->inSyscall); 10602292SN/A 10612316SN/A // Mark that we're in state update mode so that the trap's 10622316SN/A // execution doesn't generate extra squashes. 10632316SN/A thread[tid]->inSyscall = true; 10642292SN/A 10652316SN/A // Execute the trap. Although it's slightly unrealistic in 10662316SN/A // terms of timing (as it doesn't wait for the full timing of 10672316SN/A // the trap event to complete before updating state), it's 10682316SN/A // needed to update the state as soon as possible. This 10692316SN/A // prevents external agents from changing any specific state 10702316SN/A // that the trap need. 10712316SN/A cpu->trap(inst_fault, tid); 10722292SN/A 10732316SN/A // Exit state update mode to avoid accidental updating. 10742316SN/A thread[tid]->inSyscall = false; 10752292SN/A 10762316SN/A commitStatus[tid] = TrapPending; 10772292SN/A 10784035Sktlim@umich.edu if (head_inst->traceData) { 10794035Sktlim@umich.edu head_inst->traceData->setFetchSeq(head_inst->seqNum); 10804035Sktlim@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numInst); 10814288Sktlim@umich.edu head_inst->traceData->dump(); 10824288Sktlim@umich.edu delete head_inst->traceData; 10834035Sktlim@umich.edu head_inst->traceData = NULL; 10844035Sktlim@umich.edu } 10854035Sktlim@umich.edu 10862316SN/A // Generate trap squash event. 10872316SN/A generateTrapEvent(tid); 10882353SN/A// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 10892316SN/A return false; 10901060SN/A } 10911060SN/A 10922301SN/A updateComInstStats(head_inst); 10932132SN/A 10942362SN/A#if FULL_SYSTEM 10952362SN/A if (thread[tid]->profile) { 10963577Sgblack@eecs.umich.edu// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 10972362SN/A// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 10982362SN/A thread[tid]->profilePC = head_inst->readPC(); 10993126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 11002362SN/A head_inst->staticInst); 11012362SN/A 11022362SN/A if (node) 11032362SN/A thread[tid]->profileNode = node; 11042362SN/A } 11052362SN/A#endif 11062362SN/A 11072132SN/A if (head_inst->traceData) { 11082292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11092292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11104046Sbinkertn@umich.edu head_inst->traceData->dump(); 11114046Sbinkertn@umich.edu delete head_inst->traceData; 11122292SN/A head_inst->traceData = NULL; 11131060SN/A } 11141060SN/A 11152292SN/A // Update the commit rename map 11162292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11173771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 11182292SN/A head_inst->renamedDestRegIdx(i)); 11191060SN/A } 11201062SN/A 11212353SN/A if (head_inst->isCopy()) 11222353SN/A panic("Should not commit any copy instructions!"); 11232353SN/A 11242292SN/A // Finally clear the head ROB entry. 11252292SN/A rob->retireHead(tid); 11261060SN/A 11274035Sktlim@umich.edu // If this was a store, record it for this cycle. 11284035Sktlim@umich.edu if (head_inst->isStore()) 11294035Sktlim@umich.edu committedStores[tid] = true; 11304035Sktlim@umich.edu 11311060SN/A // Return true to indicate that we have committed an instruction. 11321060SN/A return true; 11331060SN/A} 11341060SN/A 11351061SN/Atemplate <class Impl> 11361060SN/Avoid 11372292SN/ADefaultCommit<Impl>::getInsts() 11381060SN/A{ 11392935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 11402935Sksewell@umich.edu 11413093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11423093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 11432965Sksewell@umich.edu 11442965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 11452965Sksewell@umich.edu DynInstPtr inst; 11462965Sksewell@umich.edu 11473093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 11482292SN/A int tid = inst->threadNumber; 11492292SN/A 11502292SN/A if (!inst->isSquashed() && 11514035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 11524035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 11532292SN/A changedROBNumEntries[tid] = true; 11542292SN/A 11552292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 11562292SN/A inst->readPC(), inst->seqNum, tid); 11572292SN/A 11582292SN/A rob->insertInst(inst); 11592292SN/A 11602292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 11612292SN/A 11622292SN/A youngestSeqNum[tid] = inst->seqNum; 11631061SN/A } else { 11642292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11651061SN/A "squashed, skipping.\n", 11662292SN/A inst->readPC(), inst->seqNum, tid); 11671061SN/A } 11681060SN/A } 11692965Sksewell@umich.edu} 11702965Sksewell@umich.edu 11712965Sksewell@umich.edutemplate <class Impl> 11722965Sksewell@umich.eduvoid 11732965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 11742965Sksewell@umich.edu{ 11752965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 11762965Sksewell@umich.edu "skidBuffer.\n"); 11772965Sksewell@umich.edu 11782965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 11792965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 11802965Sksewell@umich.edu 11812965Sksewell@umich.edu if (!inst->isSquashed()) { 11822965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 11833221Sktlim@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, 11843221Sktlim@umich.edu inst->threadNumber); 11852965Sksewell@umich.edu skidBuffer.push(inst); 11862965Sksewell@umich.edu } else { 11872965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11882965Sksewell@umich.edu "squashed, skipping.\n", 11893221Sktlim@umich.edu inst->readPC(), inst->seqNum, inst->threadNumber); 11902965Sksewell@umich.edu } 11912965Sksewell@umich.edu } 11921060SN/A} 11931060SN/A 11941061SN/Atemplate <class Impl> 11951060SN/Avoid 11962292SN/ADefaultCommit<Impl>::markCompletedInsts() 11971060SN/A{ 11981060SN/A // Grab completed insts out of the IEW instruction queue, and mark 11991060SN/A // instructions completed within the ROB. 12001060SN/A for (int inst_num = 0; 12011681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 12021060SN/A ++inst_num) 12031060SN/A { 12042292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12052316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 12062316SN/A "within ROB.\n", 12072292SN/A fromIEW->insts[inst_num]->threadNumber, 12082292SN/A fromIEW->insts[inst_num]->readPC(), 12092292SN/A fromIEW->insts[inst_num]->seqNum); 12101060SN/A 12112292SN/A // Mark the instruction as ready to commit. 12122292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12132292SN/A } 12141060SN/A } 12151060SN/A} 12161060SN/A 12171061SN/Atemplate <class Impl> 12182292SN/Abool 12192292SN/ADefaultCommit<Impl>::robDoneSquashing() 12201060SN/A{ 12213867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 12223867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 12232292SN/A 12243867Sbinkertn@umich.edu while (threads != end) { 12252292SN/A unsigned tid = *threads++; 12262292SN/A 12272292SN/A if (!rob->isDoneSquashing(tid)) 12282292SN/A return false; 12292292SN/A } 12302292SN/A 12312292SN/A return true; 12321060SN/A} 12332292SN/A 12342301SN/Atemplate <class Impl> 12352301SN/Avoid 12362301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 12372301SN/A{ 12382301SN/A unsigned thread = inst->threadNumber; 12392301SN/A 12402301SN/A // 12412301SN/A // Pick off the software prefetches 12422301SN/A // 12432301SN/A#ifdef TARGET_ALPHA 12442301SN/A if (inst->isDataPrefetch()) { 12452316SN/A statComSwp[thread]++; 12462301SN/A } else { 12472316SN/A statComInst[thread]++; 12482301SN/A } 12492301SN/A#else 12502316SN/A statComInst[thread]++; 12512301SN/A#endif 12522301SN/A 12532301SN/A // 12542301SN/A // Control Instructions 12552301SN/A // 12562301SN/A if (inst->isControl()) 12572316SN/A statComBranches[thread]++; 12582301SN/A 12592301SN/A // 12602301SN/A // Memory references 12612301SN/A // 12622301SN/A if (inst->isMemRef()) { 12632316SN/A statComRefs[thread]++; 12642301SN/A 12652301SN/A if (inst->isLoad()) { 12662316SN/A statComLoads[thread]++; 12672301SN/A } 12682301SN/A } 12692301SN/A 12702301SN/A if (inst->isMemBarrier()) { 12712316SN/A statComMembars[thread]++; 12722301SN/A } 12732301SN/A} 12742301SN/A 12752292SN/A//////////////////////////////////////// 12762292SN/A// // 12772316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 12782292SN/A// // 12792292SN/A//////////////////////////////////////// 12802292SN/Atemplate <class Impl> 12812292SN/Aint 12822292SN/ADefaultCommit<Impl>::getCommittingThread() 12832292SN/A{ 12842292SN/A if (numThreads > 1) { 12852292SN/A switch (commitPolicy) { 12862292SN/A 12872292SN/A case Aggressive: 12882292SN/A //If Policy is Aggressive, commit will call 12892292SN/A //this function multiple times per 12902292SN/A //cycle 12912292SN/A return oldestReady(); 12922292SN/A 12932292SN/A case RoundRobin: 12942292SN/A return roundRobin(); 12952292SN/A 12962292SN/A case OldestReady: 12972292SN/A return oldestReady(); 12982292SN/A 12992292SN/A default: 13002292SN/A return -1; 13012292SN/A } 13022292SN/A } else { 13033867Sbinkertn@umich.edu assert(!activeThreads->empty()); 13043867Sbinkertn@umich.edu int tid = activeThreads->front(); 13052292SN/A 13062292SN/A if (commitStatus[tid] == Running || 13072292SN/A commitStatus[tid] == Idle || 13082292SN/A commitStatus[tid] == FetchTrapPending) { 13092292SN/A return tid; 13102292SN/A } else { 13112292SN/A return -1; 13122292SN/A } 13132292SN/A } 13142292SN/A} 13152292SN/A 13162292SN/Atemplate<class Impl> 13172292SN/Aint 13182292SN/ADefaultCommit<Impl>::roundRobin() 13192292SN/A{ 13202980Sgblack@eecs.umich.edu std::list<unsigned>::iterator pri_iter = priority_list.begin(); 13212980Sgblack@eecs.umich.edu std::list<unsigned>::iterator end = priority_list.end(); 13222292SN/A 13232292SN/A while (pri_iter != end) { 13242292SN/A unsigned tid = *pri_iter; 13252292SN/A 13262292SN/A if (commitStatus[tid] == Running || 13272831Sksewell@umich.edu commitStatus[tid] == Idle || 13282831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 13292292SN/A 13302292SN/A if (rob->isHeadReady(tid)) { 13312292SN/A priority_list.erase(pri_iter); 13322292SN/A priority_list.push_back(tid); 13332292SN/A 13342292SN/A return tid; 13352292SN/A } 13362292SN/A } 13372292SN/A 13382292SN/A pri_iter++; 13392292SN/A } 13402292SN/A 13412292SN/A return -1; 13422292SN/A} 13432292SN/A 13442292SN/Atemplate<class Impl> 13452292SN/Aint 13462292SN/ADefaultCommit<Impl>::oldestReady() 13472292SN/A{ 13482292SN/A unsigned oldest = 0; 13492292SN/A bool first = true; 13502292SN/A 13513867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 13523867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 13532292SN/A 13543867Sbinkertn@umich.edu while (threads != end) { 13552292SN/A unsigned tid = *threads++; 13562292SN/A 13572292SN/A if (!rob->isEmpty(tid) && 13582292SN/A (commitStatus[tid] == Running || 13592292SN/A commitStatus[tid] == Idle || 13602292SN/A commitStatus[tid] == FetchTrapPending)) { 13612292SN/A 13622292SN/A if (rob->isHeadReady(tid)) { 13632292SN/A 13642292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 13652292SN/A 13662292SN/A if (first) { 13672292SN/A oldest = tid; 13682292SN/A first = false; 13692292SN/A } else if (head_inst->seqNum < oldest) { 13702292SN/A oldest = tid; 13712292SN/A } 13722292SN/A } 13732292SN/A } 13742292SN/A } 13752292SN/A 13762292SN/A if (!first) { 13772292SN/A return oldest; 13782292SN/A } else { 13792292SN/A return -1; 13802292SN/A } 13812292SN/A} 1382