commit_impl.hh revision 4329
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292965Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322733Sktlim@umich.edu#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 342733Sktlim@umich.edu 352292SN/A#include <algorithm> 362329SN/A#include <string> 372292SN/A 383577Sgblack@eecs.umich.edu#include "arch/utility.hh" 392292SN/A#include "base/loader/symtab.hh" 401060SN/A#include "base/timebuf.hh" 412292SN/A#include "cpu/exetrace.hh" 421717SN/A#include "cpu/o3/commit.hh" 432292SN/A#include "cpu/o3/thread_state.hh" 442292SN/A 452790Sktlim@umich.edu#if USE_CHECKER 462790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 472790Sktlim@umich.edu#endif 482790Sktlim@umich.edu 491061SN/Atemplate <class Impl> 502292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 512292SN/A unsigned _tid) 522292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 531060SN/A{ 542292SN/A this->setFlags(Event::AutoDelete); 551060SN/A} 561060SN/A 571061SN/Atemplate <class Impl> 581060SN/Avoid 592292SN/ADefaultCommit<Impl>::TrapEvent::process() 601062SN/A{ 612316SN/A // This will get reset by commit if it was switched out at the 622316SN/A // time of this event processing. 632292SN/A commit->trapSquash[tid] = true; 642292SN/A} 652292SN/A 662292SN/Atemplate <class Impl> 672292SN/Aconst char * 682292SN/ADefaultCommit<Impl>::TrapEvent::description() 692292SN/A{ 702292SN/A return "Trap event"; 712292SN/A} 722292SN/A 732292SN/Atemplate <class Impl> 744329Sktlim@umich.eduDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params) 754329Sktlim@umich.edu : cpu(_cpu), 764329Sktlim@umich.edu squashCounter(0), 772292SN/A iewToCommitDelay(params->iewToCommitDelay), 782292SN/A commitToIEWDelay(params->commitToIEWDelay), 792292SN/A renameToROBDelay(params->renameToROBDelay), 802292SN/A fetchToCommitDelay(params->commitToFetchDelay), 812292SN/A renameWidth(params->renameWidth), 822292SN/A commitWidth(params->commitWidth), 832307SN/A numThreads(params->numberOfThreads), 842843Sktlim@umich.edu drainPending(false), 852316SN/A switchedOut(false), 862874Sktlim@umich.edu trapLatency(params->trapLatency) 872292SN/A{ 882292SN/A _status = Active; 892292SN/A _nextStatus = Inactive; 902980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 912292SN/A 922292SN/A //Convert string to lowercase 932292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 942292SN/A (int(*)(int)) tolower); 952292SN/A 962292SN/A //Assign commit policy 972292SN/A if (policy == "aggressive"){ 982292SN/A commitPolicy = Aggressive; 992292SN/A 1004329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive."); 1012292SN/A } else if (policy == "roundrobin"){ 1022292SN/A commitPolicy = RoundRobin; 1032292SN/A 1042292SN/A //Set-Up Priority List 1052292SN/A for (int tid=0; tid < numThreads; tid++) { 1062292SN/A priority_list.push_back(tid); 1072292SN/A } 1082292SN/A 1094329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 1102292SN/A } else if (policy == "oldestready"){ 1112292SN/A commitPolicy = OldestReady; 1122292SN/A 1134329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1142292SN/A } else { 1152292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1162292SN/A "RoundRobin,OldestReady}"); 1172292SN/A } 1182292SN/A 1192292SN/A for (int i=0; i < numThreads; i++) { 1202292SN/A commitStatus[i] = Idle; 1212292SN/A changedROBNumEntries[i] = false; 1224035Sktlim@umich.edu checkEmptyROB[i] = false; 1234035Sktlim@umich.edu trapInFlight[i] = false; 1244035Sktlim@umich.edu committedStores[i] = false; 1252292SN/A trapSquash[i] = false; 1262680Sktlim@umich.edu tcSquash[i] = false; 1272935Sksewell@umich.edu PC[i] = nextPC[i] = nextNPC[i] = 0; 1282292SN/A } 1293640Sktlim@umich.edu#if FULL_SYSTEM 1303640Sktlim@umich.edu interrupt = NoFault; 1313640Sktlim@umich.edu#endif 1322292SN/A} 1332292SN/A 1342292SN/Atemplate <class Impl> 1352292SN/Astd::string 1362292SN/ADefaultCommit<Impl>::name() const 1372292SN/A{ 1382292SN/A return cpu->name() + ".commit"; 1392292SN/A} 1402292SN/A 1412292SN/Atemplate <class Impl> 1422292SN/Avoid 1432292SN/ADefaultCommit<Impl>::regStats() 1442132SN/A{ 1452301SN/A using namespace Stats; 1461062SN/A commitCommittedInsts 1471062SN/A .name(name() + ".commitCommittedInsts") 1481062SN/A .desc("The number of committed instructions") 1491062SN/A .prereq(commitCommittedInsts); 1501062SN/A commitSquashedInsts 1511062SN/A .name(name() + ".commitSquashedInsts") 1521062SN/A .desc("The number of squashed insts skipped by commit") 1531062SN/A .prereq(commitSquashedInsts); 1541062SN/A commitSquashEvents 1551062SN/A .name(name() + ".commitSquashEvents") 1561062SN/A .desc("The number of times commit is told to squash") 1571062SN/A .prereq(commitSquashEvents); 1581062SN/A commitNonSpecStalls 1591062SN/A .name(name() + ".commitNonSpecStalls") 1601062SN/A .desc("The number of times commit has been forced to stall to " 1611062SN/A "communicate backwards") 1621062SN/A .prereq(commitNonSpecStalls); 1631062SN/A branchMispredicts 1641062SN/A .name(name() + ".branchMispredicts") 1651062SN/A .desc("The number of times a branch was mispredicted") 1661062SN/A .prereq(branchMispredicts); 1672292SN/A numCommittedDist 1681062SN/A .init(0,commitWidth,1) 1691062SN/A .name(name() + ".COM:committed_per_cycle") 1701062SN/A .desc("Number of insts commited each cycle") 1711062SN/A .flags(Stats::pdf) 1721062SN/A ; 1732301SN/A 1742316SN/A statComInst 1752301SN/A .init(cpu->number_of_threads) 1762301SN/A .name(name() + ".COM:count") 1772301SN/A .desc("Number of instructions committed") 1782301SN/A .flags(total) 1792301SN/A ; 1802301SN/A 1812316SN/A statComSwp 1822301SN/A .init(cpu->number_of_threads) 1832301SN/A .name(name() + ".COM:swp_count") 1842301SN/A .desc("Number of s/w prefetches committed") 1852301SN/A .flags(total) 1862301SN/A ; 1872301SN/A 1882316SN/A statComRefs 1892301SN/A .init(cpu->number_of_threads) 1902301SN/A .name(name() + ".COM:refs") 1912301SN/A .desc("Number of memory references committed") 1922301SN/A .flags(total) 1932301SN/A ; 1942301SN/A 1952316SN/A statComLoads 1962301SN/A .init(cpu->number_of_threads) 1972301SN/A .name(name() + ".COM:loads") 1982301SN/A .desc("Number of loads committed") 1992301SN/A .flags(total) 2002301SN/A ; 2012301SN/A 2022316SN/A statComMembars 2032301SN/A .init(cpu->number_of_threads) 2042301SN/A .name(name() + ".COM:membars") 2052301SN/A .desc("Number of memory barriers committed") 2062301SN/A .flags(total) 2072301SN/A ; 2082301SN/A 2092316SN/A statComBranches 2102301SN/A .init(cpu->number_of_threads) 2112301SN/A .name(name() + ".COM:branches") 2122301SN/A .desc("Number of branches committed") 2132301SN/A .flags(total) 2142301SN/A ; 2152301SN/A 2162316SN/A commitEligible 2172301SN/A .init(cpu->number_of_threads) 2182301SN/A .name(name() + ".COM:bw_limited") 2192301SN/A .desc("number of insts not committed due to BW limits") 2202301SN/A .flags(total) 2212301SN/A ; 2222301SN/A 2232316SN/A commitEligibleSamples 2242301SN/A .name(name() + ".COM:bw_lim_events") 2252301SN/A .desc("number cycles where commit BW limit reached") 2262301SN/A ; 2271062SN/A} 2281062SN/A 2291062SN/Atemplate <class Impl> 2301062SN/Avoid 2312980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2322292SN/A{ 2332292SN/A thread = threads; 2342292SN/A} 2352292SN/A 2362292SN/Atemplate <class Impl> 2372292SN/Avoid 2382292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2391060SN/A{ 2401060SN/A timeBuffer = tb_ptr; 2411060SN/A 2421060SN/A // Setup wire to send information back to IEW. 2431060SN/A toIEW = timeBuffer->getWire(0); 2441060SN/A 2451060SN/A // Setup wire to read data from IEW (for the ROB). 2461060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2471060SN/A} 2481060SN/A 2491061SN/Atemplate <class Impl> 2501060SN/Avoid 2512292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2522292SN/A{ 2532292SN/A fetchQueue = fq_ptr; 2542292SN/A 2552292SN/A // Setup wire to get instructions from rename (for the ROB). 2562292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2572292SN/A} 2582292SN/A 2592292SN/Atemplate <class Impl> 2602292SN/Avoid 2612292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2621060SN/A{ 2631060SN/A renameQueue = rq_ptr; 2641060SN/A 2651060SN/A // Setup wire to get instructions from rename (for the ROB). 2661060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2671060SN/A} 2681060SN/A 2691061SN/Atemplate <class Impl> 2701060SN/Avoid 2712292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2721060SN/A{ 2731060SN/A iewQueue = iq_ptr; 2741060SN/A 2751060SN/A // Setup wire to get instructions from IEW. 2761060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2771060SN/A} 2781060SN/A 2791061SN/Atemplate <class Impl> 2801060SN/Avoid 2812292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2822292SN/A{ 2832292SN/A iewStage = iew_stage; 2842292SN/A} 2852292SN/A 2862292SN/Atemplate<class Impl> 2872292SN/Avoid 2882980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2892292SN/A{ 2902292SN/A activeThreads = at_ptr; 2912292SN/A} 2922292SN/A 2932292SN/Atemplate <class Impl> 2942292SN/Avoid 2952292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 2962292SN/A{ 2972292SN/A for (int i=0; i < numThreads; i++) { 2982292SN/A renameMap[i] = &rm_ptr[i]; 2992292SN/A } 3002292SN/A} 3012292SN/A 3022292SN/Atemplate <class Impl> 3032292SN/Avoid 3042292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3051060SN/A{ 3061060SN/A rob = rob_ptr; 3071060SN/A} 3081060SN/A 3091061SN/Atemplate <class Impl> 3101060SN/Avoid 3112292SN/ADefaultCommit<Impl>::initStage() 3121060SN/A{ 3132292SN/A rob->setActiveThreads(activeThreads); 3142292SN/A rob->resetEntries(); 3151060SN/A 3162292SN/A // Broadcast the number of free entries. 3172292SN/A for (int i=0; i < numThreads; i++) { 3182292SN/A toIEW->commitInfo[i].usedROB = true; 3192292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3204035Sktlim@umich.edu toIEW->commitInfo[i].emptyROB = true; 3211060SN/A } 3221060SN/A 3234329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3244329Sktlim@umich.edu // start of the simulation, so it starts as active. 3254329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3264329Sktlim@umich.edu 3272292SN/A cpu->activityThisCycle(); 3284329Sktlim@umich.edu trapLatency = cpu->cycles(trapLatency); 3291060SN/A} 3301060SN/A 3311061SN/Atemplate <class Impl> 3322863Sktlim@umich.edubool 3332843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3341060SN/A{ 3352843Sktlim@umich.edu drainPending = true; 3362863Sktlim@umich.edu 3372863Sktlim@umich.edu return false; 3382316SN/A} 3392316SN/A 3402316SN/Atemplate <class Impl> 3412316SN/Avoid 3422843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3432316SN/A{ 3442316SN/A switchedOut = true; 3452843Sktlim@umich.edu drainPending = false; 3462307SN/A rob->switchOut(); 3472307SN/A} 3482307SN/A 3492307SN/Atemplate <class Impl> 3502307SN/Avoid 3512843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3522843Sktlim@umich.edu{ 3532864Sktlim@umich.edu drainPending = false; 3542843Sktlim@umich.edu} 3552843Sktlim@umich.edu 3562843Sktlim@umich.edutemplate <class Impl> 3572843Sktlim@umich.eduvoid 3582307SN/ADefaultCommit<Impl>::takeOverFrom() 3592307SN/A{ 3602316SN/A switchedOut = false; 3612307SN/A _status = Active; 3622307SN/A _nextStatus = Inactive; 3632307SN/A for (int i=0; i < numThreads; i++) { 3642307SN/A commitStatus[i] = Idle; 3652307SN/A changedROBNumEntries[i] = false; 3662307SN/A trapSquash[i] = false; 3672680Sktlim@umich.edu tcSquash[i] = false; 3682307SN/A } 3692307SN/A squashCounter = 0; 3702307SN/A rob->takeOverFrom(); 3712307SN/A} 3722307SN/A 3732307SN/Atemplate <class Impl> 3742307SN/Avoid 3752292SN/ADefaultCommit<Impl>::updateStatus() 3762132SN/A{ 3772316SN/A // reset ROB changed variable 3783867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 3793867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 3803867Sbinkertn@umich.edu 3813867Sbinkertn@umich.edu while (threads != end) { 3822316SN/A unsigned tid = *threads++; 3833867Sbinkertn@umich.edu 3842316SN/A changedROBNumEntries[tid] = false; 3852316SN/A 3862316SN/A // Also check if any of the threads has a trap pending 3872316SN/A if (commitStatus[tid] == TrapPending || 3882316SN/A commitStatus[tid] == FetchTrapPending) { 3892316SN/A _nextStatus = Active; 3902316SN/A } 3912292SN/A } 3922292SN/A 3932292SN/A if (_nextStatus == Inactive && _status == Active) { 3942292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 3952733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 3962292SN/A } else if (_nextStatus == Active && _status == Inactive) { 3972292SN/A DPRINTF(Activity, "Activating stage.\n"); 3982733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3992292SN/A } 4002292SN/A 4012292SN/A _status = _nextStatus; 4022292SN/A} 4032292SN/A 4042292SN/Atemplate <class Impl> 4052292SN/Avoid 4062292SN/ADefaultCommit<Impl>::setNextStatus() 4072292SN/A{ 4082292SN/A int squashes = 0; 4092292SN/A 4103867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4113867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4122292SN/A 4133867Sbinkertn@umich.edu while (threads != end) { 4142292SN/A unsigned tid = *threads++; 4152292SN/A 4162292SN/A if (commitStatus[tid] == ROBSquashing) { 4172292SN/A squashes++; 4182292SN/A } 4192292SN/A } 4202292SN/A 4212702Sktlim@umich.edu squashCounter = squashes; 4222292SN/A 4232292SN/A // If commit is currently squashing, then it will have activity for the 4242292SN/A // next cycle. Set its next status as active. 4252292SN/A if (squashCounter) { 4262292SN/A _nextStatus = Active; 4272292SN/A } 4282292SN/A} 4292292SN/A 4302292SN/Atemplate <class Impl> 4312292SN/Abool 4322292SN/ADefaultCommit<Impl>::changedROBEntries() 4332292SN/A{ 4343867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4353867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4362292SN/A 4373867Sbinkertn@umich.edu while (threads != end) { 4382292SN/A unsigned tid = *threads++; 4392292SN/A 4402292SN/A if (changedROBNumEntries[tid]) { 4412292SN/A return true; 4422292SN/A } 4432292SN/A } 4442292SN/A 4452292SN/A return false; 4462292SN/A} 4472292SN/A 4482292SN/Atemplate <class Impl> 4492292SN/Aunsigned 4502292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4512292SN/A{ 4522292SN/A return rob->numFreeEntries(tid); 4532292SN/A} 4542292SN/A 4552292SN/Atemplate <class Impl> 4562292SN/Avoid 4572292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4582292SN/A{ 4592292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4602292SN/A 4612292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4622292SN/A 4632292SN/A trap->schedule(curTick + trapLatency); 4644035Sktlim@umich.edu trapInFlight[tid] = true; 4652292SN/A} 4662292SN/A 4672292SN/Atemplate <class Impl> 4682292SN/Avoid 4692680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4702292SN/A{ 4714035Sktlim@umich.edu assert(!trapInFlight[tid]); 4722680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4732292SN/A 4742680Sktlim@umich.edu tcSquash[tid] = true; 4752292SN/A} 4762292SN/A 4772292SN/Atemplate <class Impl> 4782292SN/Avoid 4792316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4802292SN/A{ 4812292SN/A // If we want to include the squashing instruction in the squash, 4822292SN/A // then use one older sequence number. 4832292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4842292SN/A // all instructions of this thread. 4852292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 4864035Sktlim@umich.edu 0 : rob->readHeadInst(tid)->seqNum - 1; 4872292SN/A 4882292SN/A // All younger instructions will be squashed. Set the sequence 4892292SN/A // number as the youngest instruction in the ROB (0 in this case. 4902292SN/A // Hopefully nothing breaks.) 4912292SN/A youngestSeqNum[tid] = 0; 4922292SN/A 4932292SN/A rob->squash(squashed_inst, tid); 4942292SN/A changedROBNumEntries[tid] = true; 4952292SN/A 4962292SN/A // Send back the sequence number of the squashed instruction. 4972292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 4982292SN/A 4992292SN/A // Send back the squash signal to tell stages that they should 5002292SN/A // squash. 5012292SN/A toIEW->commitInfo[tid].squash = true; 5022292SN/A 5032292SN/A // Send back the rob squashing signal so other stages know that 5042292SN/A // the ROB is in the process of squashing. 5052292SN/A toIEW->commitInfo[tid].robSquashing = true; 5062292SN/A 5072292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5082292SN/A 5092316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5103795Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextNPC = nextPC[tid]; 5112316SN/A} 5122292SN/A 5132316SN/Atemplate <class Impl> 5142316SN/Avoid 5152316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5162316SN/A{ 5172316SN/A squashAll(tid); 5182316SN/A 5192316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5202316SN/A 5212316SN/A thread[tid]->trapPending = false; 5222316SN/A thread[tid]->inSyscall = false; 5234035Sktlim@umich.edu trapInFlight[tid] = false; 5242316SN/A 5252316SN/A trapSquash[tid] = false; 5262316SN/A 5272316SN/A commitStatus[tid] = ROBSquashing; 5282316SN/A cpu->activityThisCycle(); 5292316SN/A} 5302316SN/A 5312316SN/Atemplate <class Impl> 5322316SN/Avoid 5332680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5342316SN/A{ 5352316SN/A squashAll(tid); 5362292SN/A 5372680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5382292SN/A 5392292SN/A thread[tid]->inSyscall = false; 5402292SN/A assert(!thread[tid]->trapPending); 5412316SN/A 5422292SN/A commitStatus[tid] = ROBSquashing; 5432292SN/A cpu->activityThisCycle(); 5442292SN/A 5452680Sktlim@umich.edu tcSquash[tid] = false; 5462292SN/A} 5472292SN/A 5482292SN/Atemplate <class Impl> 5492292SN/Avoid 5502292SN/ADefaultCommit<Impl>::tick() 5512292SN/A{ 5522292SN/A wroteToTimeBuffer = false; 5532292SN/A _nextStatus = Inactive; 5542292SN/A 5552843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5562843Sktlim@umich.edu cpu->signalDrained(); 5572843Sktlim@umich.edu drainPending = false; 5582316SN/A return; 5592316SN/A } 5602316SN/A 5613867Sbinkertn@umich.edu if (activeThreads->empty()) 5622875Sksewell@umich.edu return; 5632875Sksewell@umich.edu 5643867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 5653867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 5662292SN/A 5672316SN/A // Check if any of the threads are done squashing. Change the 5682316SN/A // status if they are done. 5693867Sbinkertn@umich.edu while (threads != end) { 5702292SN/A unsigned tid = *threads++; 5712292SN/A 5724035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 5734035Sktlim@umich.edu // this cycle. 5744035Sktlim@umich.edu committedStores[tid] = false; 5754035Sktlim@umich.edu 5762292SN/A if (commitStatus[tid] == ROBSquashing) { 5772292SN/A 5782292SN/A if (rob->isDoneSquashing(tid)) { 5792292SN/A commitStatus[tid] = Running; 5802292SN/A } else { 5812292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5822877Sksewell@umich.edu " insts this cycle.\n", tid); 5832702Sktlim@umich.edu rob->doSquash(tid); 5842702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5852702Sktlim@umich.edu wroteToTimeBuffer = true; 5862292SN/A } 5872292SN/A } 5882292SN/A } 5892292SN/A 5902292SN/A commit(); 5912292SN/A 5922292SN/A markCompletedInsts(); 5932292SN/A 5943867Sbinkertn@umich.edu threads = activeThreads->begin(); 5952292SN/A 5963867Sbinkertn@umich.edu while (threads != end) { 5972292SN/A unsigned tid = *threads++; 5982292SN/A 5992292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6002292SN/A // The ROB has more instructions it can commit. Its next status 6012292SN/A // will be active. 6022292SN/A _nextStatus = Active; 6032292SN/A 6042292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6052292SN/A 6062292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6072292SN/A " ROB and ready to commit\n", 6082292SN/A tid, inst->seqNum, inst->readPC()); 6092292SN/A 6102292SN/A } else if (!rob->isEmpty(tid)) { 6112292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6122292SN/A 6132292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6142292SN/A "%#x is head of ROB and not ready\n", 6152292SN/A tid, inst->seqNum, inst->readPC()); 6162292SN/A } 6172292SN/A 6182292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6192292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6202292SN/A } 6212292SN/A 6222292SN/A 6232292SN/A if (wroteToTimeBuffer) { 6242316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6252292SN/A cpu->activityThisCycle(); 6262292SN/A } 6272292SN/A 6282292SN/A updateStatus(); 6292292SN/A} 6302292SN/A 6314035Sktlim@umich.edu#if FULL_SYSTEM 6322292SN/Atemplate <class Impl> 6332292SN/Avoid 6344035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 6352292SN/A{ 6363640Sktlim@umich.edu if (interrupt != NoFault) { 6372316SN/A // Wait until the ROB is empty and all stores have drained in 6382316SN/A // order to enter the interrupt. 6392292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6403633Sktlim@umich.edu // Squash or record that I need to squash this cycle if 6413633Sktlim@umich.edu // an interrupt needed to be handled. 6423633Sktlim@umich.edu DPRINTF(Commit, "Interrupt detected.\n"); 6433633Sktlim@umich.edu 6444035Sktlim@umich.edu Fault new_interrupt = cpu->getInterrupts(); 6454288Sktlim@umich.edu assert(new_interrupt != NoFault); 6464035Sktlim@umich.edu 6474035Sktlim@umich.edu // Clear the interrupt now that it's going to be handled 6484035Sktlim@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 6494035Sktlim@umich.edu 6502292SN/A assert(!thread[0]->inSyscall); 6512292SN/A thread[0]->inSyscall = true; 6522292SN/A 6533633Sktlim@umich.edu // CPU will handle interrupt. 6543640Sktlim@umich.edu cpu->processInterrupts(interrupt); 6552292SN/A 6563633Sktlim@umich.edu thread[0]->inSyscall = false; 6573633Sktlim@umich.edu 6582292SN/A commitStatus[0] = TrapPending; 6592292SN/A 6602292SN/A // Generate trap squash event. 6612292SN/A generateTrapEvent(0); 6622292SN/A 6633640Sktlim@umich.edu interrupt = NoFault; 6642292SN/A } else { 6652292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6662292SN/A } 6674035Sktlim@umich.edu } else if (commitStatus[0] != TrapPending && 6684035Sktlim@umich.edu cpu->check_interrupts(cpu->tcBase(0)) && 6694035Sktlim@umich.edu !trapSquash[0] && 6704035Sktlim@umich.edu !tcSquash[0]) { 6713640Sktlim@umich.edu // Process interrupts if interrupts are enabled, not in PAL 6723640Sktlim@umich.edu // mode, and no other traps or external squashes are currently 6733640Sktlim@umich.edu // pending. 6743640Sktlim@umich.edu // @todo: Allow other threads to handle interrupts. 6753640Sktlim@umich.edu 6763640Sktlim@umich.edu // Get any interrupt that happened 6773640Sktlim@umich.edu interrupt = cpu->getInterrupts(); 6783640Sktlim@umich.edu 6793640Sktlim@umich.edu if (interrupt != NoFault) { 6803640Sktlim@umich.edu // Tell fetch that there is an interrupt pending. This 6813640Sktlim@umich.edu // will make fetch wait until it sees a non PAL-mode PC, 6823640Sktlim@umich.edu // at which point it stops fetching instructions. 6833640Sktlim@umich.edu toIEW->commitInfo[0].interruptPending = true; 6843640Sktlim@umich.edu } 6851060SN/A } 6864035Sktlim@umich.edu} 6874035Sktlim@umich.edu#endif // FULL_SYSTEM 6883634Sktlim@umich.edu 6894035Sktlim@umich.edutemplate <class Impl> 6904035Sktlim@umich.eduvoid 6914035Sktlim@umich.eduDefaultCommit<Impl>::commit() 6924035Sktlim@umich.edu{ 6934035Sktlim@umich.edu 6944035Sktlim@umich.edu#if FULL_SYSTEM 6954035Sktlim@umich.edu // Check for any interrupt, and start processing it. Or if we 6964035Sktlim@umich.edu // have an outstanding interrupt and are at a point when it is 6974035Sktlim@umich.edu // valid to take an interrupt, process it. 6984035Sktlim@umich.edu if (cpu->check_interrupts(cpu->tcBase(0))) { 6994035Sktlim@umich.edu handleInterrupt(); 7004035Sktlim@umich.edu } 7011060SN/A#endif // FULL_SYSTEM 7021060SN/A 7031060SN/A //////////////////////////////////// 7042316SN/A // Check for any possible squashes, handle them first 7051060SN/A //////////////////////////////////// 7063867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 7073867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 7081060SN/A 7093867Sbinkertn@umich.edu while (threads != end) { 7102292SN/A unsigned tid = *threads++; 7111060SN/A 7122292SN/A // Not sure which one takes priority. I think if we have 7132292SN/A // both, that's a bad sign. 7142292SN/A if (trapSquash[tid] == true) { 7152680Sktlim@umich.edu assert(!tcSquash[tid]); 7162292SN/A squashFromTrap(tid); 7172680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7184035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 7192680Sktlim@umich.edu squashFromTC(tid); 7202292SN/A } 7211061SN/A 7222292SN/A // Squashed sequence number must be older than youngest valid 7232292SN/A // instruction in the ROB. This prevents squashes from younger 7242292SN/A // instructions overriding squashes from older instructions. 7252292SN/A if (fromIEW->squash[tid] && 7262292SN/A commitStatus[tid] != TrapPending && 7272292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7281061SN/A 7292292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7302292SN/A tid, 7312292SN/A fromIEW->mispredPC[tid], 7322292SN/A fromIEW->squashedSeqNum[tid]); 7331061SN/A 7342292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7352292SN/A tid, 7362292SN/A fromIEW->nextPC[tid]); 7371061SN/A 7382292SN/A commitStatus[tid] = ROBSquashing; 7391061SN/A 7402292SN/A // If we want to include the squashing instruction in the squash, 7412292SN/A // then use one older sequence number. 7422292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7431062SN/A 7443093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7453771Sgblack@eecs.umich.edu InstSeqNum bdelay_done_seq_num = squashed_inst; 7463771Sgblack@eecs.umich.edu bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid]; 7473957Sgblack@eecs.umich.edu bool branchMispredict = fromIEW->branchMispredict[tid]; 7482935Sksewell@umich.edu 7493957Sgblack@eecs.umich.edu // Squashing/not squashing the branch delay slot only makes 7503957Sgblack@eecs.umich.edu // sense when you're squashing from a branch, ie from a branch 7513957Sgblack@eecs.umich.edu // mispredict. 7523957Sgblack@eecs.umich.edu if (branchMispredict && !squash_bdelay_slot) { 7533771Sgblack@eecs.umich.edu bdelay_done_seq_num++; 7542935Sksewell@umich.edu } 7552935Sksewell@umich.edu#endif 7562935Sksewell@umich.edu 7572935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 7582292SN/A squashed_inst--; 7593093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7602935Sksewell@umich.edu bdelay_done_seq_num--; 7612935Sksewell@umich.edu#endif 7622935Sksewell@umich.edu } 7634035Sktlim@umich.edu 7642292SN/A // All younger instructions will be squashed. Set the sequence 7652292SN/A // number as the youngest instruction in the ROB. 7662292SN/A youngestSeqNum[tid] = squashed_inst; 7672292SN/A 7683093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7692935Sksewell@umich.edu rob->squash(bdelay_done_seq_num, tid); 7702935Sksewell@umich.edu toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 7712935Sksewell@umich.edu toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 7723093Sksewell@umich.edu#else 7733093Sksewell@umich.edu rob->squash(squashed_inst, tid); 7743093Sksewell@umich.edu toIEW->commitInfo[tid].squashDelaySlot = true; 7752935Sksewell@umich.edu#endif 7762292SN/A changedROBNumEntries[tid] = true; 7772292SN/A 7782292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7792292SN/A 7802292SN/A toIEW->commitInfo[tid].squash = true; 7812292SN/A 7822292SN/A // Send back the rob squashing signal so other stages know that 7832292SN/A // the ROB is in the process of squashing. 7842292SN/A toIEW->commitInfo[tid].robSquashing = true; 7852292SN/A 7862292SN/A toIEW->commitInfo[tid].branchMispredict = 7872292SN/A fromIEW->branchMispredict[tid]; 7882292SN/A 7892292SN/A toIEW->commitInfo[tid].branchTaken = 7902292SN/A fromIEW->branchTaken[tid]; 7912292SN/A 7922292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7933795Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid]; 7942292SN/A 7952316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7962292SN/A 7972292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7982292SN/A ++branchMispredicts; 7992292SN/A } 8001062SN/A } 8012292SN/A 8021060SN/A } 8031060SN/A 8042292SN/A setNextStatus(); 8052292SN/A 8062292SN/A if (squashCounter != numThreads) { 8071061SN/A // If we're not currently squashing, then get instructions. 8081060SN/A getInsts(); 8091060SN/A 8101061SN/A // Try to commit any instructions. 8111060SN/A commitInsts(); 8122965Sksewell@umich.edu } else { 8133093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 8142965Sksewell@umich.edu skidInsert(); 8152965Sksewell@umich.edu#endif 8161060SN/A } 8171060SN/A 8182292SN/A //Check for any activity 8193867Sbinkertn@umich.edu threads = activeThreads->begin(); 8202292SN/A 8213867Sbinkertn@umich.edu while (threads != end) { 8222292SN/A unsigned tid = *threads++; 8232292SN/A 8242292SN/A if (changedROBNumEntries[tid]) { 8252292SN/A toIEW->commitInfo[tid].usedROB = true; 8262292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8272292SN/A 8282292SN/A wroteToTimeBuffer = true; 8292292SN/A changedROBNumEntries[tid] = false; 8304035Sktlim@umich.edu if (rob->isEmpty(tid)) 8314035Sktlim@umich.edu checkEmptyROB[tid] = true; 8322292SN/A } 8334035Sktlim@umich.edu 8344035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8354035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 8364035Sktlim@umich.edu // stage has received any information regarding stores that 8374035Sktlim@umich.edu // committed. 8384035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 8394035Sktlim@umich.edu // on the same cycle as when stores have been committed. 8404035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 8414035Sktlim@umich.edu // commit and IEW. 8424035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 8434035Sktlim@umich.edu !iewStage->hasStoresToWB() && !committedStores[tid]) { 8444035Sktlim@umich.edu checkEmptyROB[tid] = false; 8454035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 8464035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 8474035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8484035Sktlim@umich.edu wroteToTimeBuffer = true; 8494035Sktlim@umich.edu } 8504035Sktlim@umich.edu 8511060SN/A } 8521060SN/A} 8531060SN/A 8541061SN/Atemplate <class Impl> 8551060SN/Avoid 8562292SN/ADefaultCommit<Impl>::commitInsts() 8571060SN/A{ 8581060SN/A //////////////////////////////////// 8591060SN/A // Handle commit 8602316SN/A // Note that commit will be handled prior to putting new 8612316SN/A // instructions in the ROB so that the ROB only tries to commit 8622316SN/A // instructions it has in this current cycle, and not instructions 8632316SN/A // it is writing in during this cycle. Can't commit and squash 8642316SN/A // things at the same time... 8651060SN/A //////////////////////////////////// 8661060SN/A 8672292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8681060SN/A 8691060SN/A unsigned num_committed = 0; 8701060SN/A 8712292SN/A DynInstPtr head_inst; 8722316SN/A 8731060SN/A // Commit as many instructions as possible until the commit bandwidth 8741060SN/A // limit is reached, or it becomes impossible to commit any more. 8752292SN/A while (num_committed < commitWidth) { 8762292SN/A int commit_thread = getCommittingThread(); 8771060SN/A 8782292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8792292SN/A break; 8802292SN/A 8812292SN/A head_inst = rob->readHeadInst(commit_thread); 8822292SN/A 8832292SN/A int tid = head_inst->threadNumber; 8842292SN/A 8852292SN/A assert(tid == commit_thread); 8862292SN/A 8872292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8882292SN/A head_inst->seqNum, tid); 8892132SN/A 8902316SN/A // If the head instruction is squashed, it is ready to retire 8912316SN/A // (be removed from the ROB) at any time. 8921060SN/A if (head_inst->isSquashed()) { 8931060SN/A 8942292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8951060SN/A "ROB.\n"); 8961060SN/A 8972292SN/A rob->retireHead(commit_thread); 8981060SN/A 8991062SN/A ++commitSquashedInsts; 9001062SN/A 9012292SN/A // Record that the number of ROB entries has changed. 9022292SN/A changedROBNumEntries[tid] = true; 9031060SN/A } else { 9042292SN/A PC[tid] = head_inst->readPC(); 9052292SN/A nextPC[tid] = head_inst->readNextPC(); 9062935Sksewell@umich.edu nextNPC[tid] = head_inst->readNextNPC(); 9072292SN/A 9081060SN/A // Increment the total number of non-speculative instructions 9091060SN/A // executed. 9101060SN/A // Hack for now: it really shouldn't happen until after the 9111061SN/A // commit is deemed to be successful, but this count is needed 9121061SN/A // for syscalls. 9132292SN/A thread[tid]->funcExeInst++; 9141060SN/A 9151060SN/A // Try to commit the head instruction. 9161060SN/A bool commit_success = commitHead(head_inst, num_committed); 9171060SN/A 9181062SN/A if (commit_success) { 9191060SN/A ++num_committed; 9201060SN/A 9212292SN/A changedROBNumEntries[tid] = true; 9222292SN/A 9232292SN/A // Set the doneSeqNum to the youngest committed instruction. 9242292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9251060SN/A 9261062SN/A ++commitCommittedInsts; 9271062SN/A 9282292SN/A // To match the old model, don't count nops and instruction 9292292SN/A // prefetches towards the total commit count. 9302292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9312292SN/A cpu->instDone(tid); 9321062SN/A } 9332292SN/A 9342292SN/A PC[tid] = nextPC[tid]; 9353093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 9362935Sksewell@umich.edu nextPC[tid] = nextNPC[tid]; 9372935Sksewell@umich.edu nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 9383093Sksewell@umich.edu#else 9393093Sksewell@umich.edu nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 9402935Sksewell@umich.edu#endif 9412935Sksewell@umich.edu 9422292SN/A#if FULL_SYSTEM 9432292SN/A int count = 0; 9442292SN/A Addr oldpc; 9452292SN/A do { 9462316SN/A // Debug statement. Checks to make sure we're not 9472316SN/A // currently updating state while handling PC events. 9482292SN/A if (count == 0) 9492316SN/A assert(!thread[tid]->inSyscall && 9502316SN/A !thread[tid]->trapPending); 9512292SN/A oldpc = PC[tid]; 9522292SN/A cpu->system->pcEventQueue.service( 9532690Sktlim@umich.edu thread[tid]->getTC()); 9542292SN/A count++; 9552292SN/A } while (oldpc != PC[tid]); 9562292SN/A if (count > 1) { 9572292SN/A DPRINTF(Commit, "PC skip function event, stopping commit\n"); 9582292SN/A break; 9592292SN/A } 9602292SN/A#endif 9611060SN/A } else { 9622292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9632292SN/A "[tid:%i] [sn:%i].\n", 9642292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9651060SN/A break; 9661060SN/A } 9671060SN/A } 9681060SN/A } 9691062SN/A 9701063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9712292SN/A numCommittedDist.sample(num_committed); 9722307SN/A 9732307SN/A if (num_committed == commitWidth) { 9742349SN/A commitEligibleSamples++; 9752307SN/A } 9761060SN/A} 9771060SN/A 9781061SN/Atemplate <class Impl> 9791060SN/Abool 9802292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9811060SN/A{ 9821060SN/A assert(head_inst); 9831060SN/A 9842292SN/A int tid = head_inst->threadNumber; 9852292SN/A 9862316SN/A // If the instruction is not executed yet, then it will need extra 9872316SN/A // handling. Signal backwards that it should be executed. 9881061SN/A if (!head_inst->isExecuted()) { 9891061SN/A // Keep this number correct. We have not yet actually executed 9901061SN/A // and committed this instruction. 9912292SN/A thread[tid]->funcExeInst--; 9921062SN/A 9932292SN/A if (head_inst->isNonSpeculative() || 9942348SN/A head_inst->isStoreConditional() || 9952292SN/A head_inst->isMemBarrier() || 9962292SN/A head_inst->isWriteBarrier()) { 9972316SN/A 9982316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9992316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 10002316SN/A head_inst->seqNum, head_inst->readPC()); 10012316SN/A 10024035Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB()) { 10032292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10042292SN/A return false; 10052292SN/A } 10062292SN/A 10072292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10081061SN/A 10091061SN/A // Change the instruction so it won't try to commit again until 10101061SN/A // it is executed. 10111061SN/A head_inst->clearCanCommit(); 10121061SN/A 10131062SN/A ++commitNonSpecStalls; 10141062SN/A 10151061SN/A return false; 10162292SN/A } else if (head_inst->isLoad()) { 10174035Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB()) { 10184035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10194035Sktlim@umich.edu return false; 10204035Sktlim@umich.edu } 10214035Sktlim@umich.edu 10224035Sktlim@umich.edu assert(head_inst->uncacheable()); 10232292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 10242292SN/A head_inst->seqNum, head_inst->readPC()); 10252292SN/A 10262292SN/A // Send back the non-speculative instruction's sequence 10272316SN/A // number. Tell the lsq to re-execute the load. 10282292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10292292SN/A toIEW->commitInfo[tid].uncached = true; 10302292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10312292SN/A 10322292SN/A head_inst->clearCanCommit(); 10332292SN/A 10342292SN/A return false; 10351061SN/A } else { 10362292SN/A panic("Trying to commit un-executed instruction " 10371061SN/A "of unknown type!\n"); 10381061SN/A } 10391060SN/A } 10401060SN/A 10412316SN/A if (head_inst->isThreadSync()) { 10422292SN/A // Not handled for now. 10432316SN/A panic("Thread sync instructions are not handled yet.\n"); 10442132SN/A } 10452132SN/A 10464035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 10474035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 10484035Sktlim@umich.edu 10492316SN/A // Stores mark themselves as completed. 10504035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 10512310SN/A head_inst->setCompleted(); 10522310SN/A } 10532310SN/A 10542733Sktlim@umich.edu#if USE_CHECKER 10552316SN/A // Use checker prior to updating anything due to traps or PC 10562316SN/A // based events. 10572316SN/A if (cpu->checker) { 10582732Sktlim@umich.edu cpu->checker->verify(head_inst); 10591060SN/A } 10602733Sktlim@umich.edu#endif 10611060SN/A 10622918Sktlim@umich.edu // DTB will sometimes need the machine instruction for when 10632918Sktlim@umich.edu // faults happen. So we will set it here, prior to the DTB 10642918Sktlim@umich.edu // possibly needing it for its fault. 10652918Sktlim@umich.edu thread[tid]->setInst( 10662918Sktlim@umich.edu static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10672918Sktlim@umich.edu 10682112SN/A if (inst_fault != NoFault) { 10692316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10702316SN/A head_inst->seqNum, head_inst->readPC()); 10712292SN/A 10722316SN/A if (iewStage->hasStoresToWB() || inst_num > 0) { 10732316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10742316SN/A return false; 10752316SN/A } 10762310SN/A 10774035Sktlim@umich.edu head_inst->setCompleted(); 10784035Sktlim@umich.edu 10792733Sktlim@umich.edu#if USE_CHECKER 10802316SN/A if (cpu->checker && head_inst->isStore()) { 10812732Sktlim@umich.edu cpu->checker->verify(head_inst); 10822316SN/A } 10832733Sktlim@umich.edu#endif 10842292SN/A 10852316SN/A assert(!thread[tid]->inSyscall); 10862292SN/A 10872316SN/A // Mark that we're in state update mode so that the trap's 10882316SN/A // execution doesn't generate extra squashes. 10892316SN/A thread[tid]->inSyscall = true; 10902292SN/A 10912316SN/A // Execute the trap. Although it's slightly unrealistic in 10922316SN/A // terms of timing (as it doesn't wait for the full timing of 10932316SN/A // the trap event to complete before updating state), it's 10942316SN/A // needed to update the state as soon as possible. This 10952316SN/A // prevents external agents from changing any specific state 10962316SN/A // that the trap need. 10972316SN/A cpu->trap(inst_fault, tid); 10982292SN/A 10992316SN/A // Exit state update mode to avoid accidental updating. 11002316SN/A thread[tid]->inSyscall = false; 11012292SN/A 11022316SN/A commitStatus[tid] = TrapPending; 11032292SN/A 11044035Sktlim@umich.edu if (head_inst->traceData) { 11054035Sktlim@umich.edu head_inst->traceData->setFetchSeq(head_inst->seqNum); 11064035Sktlim@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numInst); 11074288Sktlim@umich.edu head_inst->traceData->dump(); 11084288Sktlim@umich.edu delete head_inst->traceData; 11094035Sktlim@umich.edu head_inst->traceData = NULL; 11104035Sktlim@umich.edu } 11114035Sktlim@umich.edu 11122316SN/A // Generate trap squash event. 11132316SN/A generateTrapEvent(tid); 11142353SN/A// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 11152316SN/A return false; 11161060SN/A } 11171060SN/A 11182301SN/A updateComInstStats(head_inst); 11192132SN/A 11202362SN/A#if FULL_SYSTEM 11212362SN/A if (thread[tid]->profile) { 11223577Sgblack@eecs.umich.edu// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 11232362SN/A// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 11242362SN/A thread[tid]->profilePC = head_inst->readPC(); 11253126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 11262362SN/A head_inst->staticInst); 11272362SN/A 11282362SN/A if (node) 11292362SN/A thread[tid]->profileNode = node; 11302362SN/A } 11312362SN/A#endif 11322362SN/A 11332132SN/A if (head_inst->traceData) { 11342292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11352292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11364046Sbinkertn@umich.edu head_inst->traceData->dump(); 11374046Sbinkertn@umich.edu delete head_inst->traceData; 11382292SN/A head_inst->traceData = NULL; 11391060SN/A } 11401060SN/A 11412292SN/A // Update the commit rename map 11422292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11433771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 11442292SN/A head_inst->renamedDestRegIdx(i)); 11451060SN/A } 11461062SN/A 11472353SN/A if (head_inst->isCopy()) 11482353SN/A panic("Should not commit any copy instructions!"); 11492353SN/A 11502292SN/A // Finally clear the head ROB entry. 11512292SN/A rob->retireHead(tid); 11521060SN/A 11534035Sktlim@umich.edu // If this was a store, record it for this cycle. 11544035Sktlim@umich.edu if (head_inst->isStore()) 11554035Sktlim@umich.edu committedStores[tid] = true; 11564035Sktlim@umich.edu 11571060SN/A // Return true to indicate that we have committed an instruction. 11581060SN/A return true; 11591060SN/A} 11601060SN/A 11611061SN/Atemplate <class Impl> 11621060SN/Avoid 11632292SN/ADefaultCommit<Impl>::getInsts() 11641060SN/A{ 11652935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 11662935Sksewell@umich.edu 11673093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 11682965Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11692980Sgblack@eecs.umich.edu int insts_to_process = std::min((int)renameWidth, 11702965Sksewell@umich.edu (int)(fromRename->size + skidBuffer.size())); 11712965Sksewell@umich.edu int rename_idx = 0; 11721061SN/A 11732965Sksewell@umich.edu DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 11742965Sksewell@umich.edu "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 11752965Sksewell@umich.edu skidBuffer.size()); 11763093Sksewell@umich.edu#else 11773093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11783093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 11792965Sksewell@umich.edu#endif 11802965Sksewell@umich.edu 11812965Sksewell@umich.edu 11822965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 11832965Sksewell@umich.edu DynInstPtr inst; 11842965Sksewell@umich.edu 11853093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 11862965Sksewell@umich.edu // Get insts from skidBuffer or from Rename 11872965Sksewell@umich.edu if (skidBuffer.size() > 0) { 11882965Sksewell@umich.edu DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 11892965Sksewell@umich.edu inst = skidBuffer.front(); 11902965Sksewell@umich.edu skidBuffer.pop(); 11912965Sksewell@umich.edu } else { 11922965Sksewell@umich.edu DPRINTF(Commit, "Grabbing rename inst.\n"); 11932965Sksewell@umich.edu inst = fromRename->insts[rename_idx++]; 11942965Sksewell@umich.edu } 11953093Sksewell@umich.edu#else 11963093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 11972965Sksewell@umich.edu#endif 11982292SN/A int tid = inst->threadNumber; 11992292SN/A 12002292SN/A if (!inst->isSquashed() && 12014035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 12024035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 12032292SN/A changedROBNumEntries[tid] = true; 12042292SN/A 12052292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 12062292SN/A inst->readPC(), inst->seqNum, tid); 12072292SN/A 12082292SN/A rob->insertInst(inst); 12092292SN/A 12102292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 12112292SN/A 12122292SN/A youngestSeqNum[tid] = inst->seqNum; 12131061SN/A } else { 12142292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 12151061SN/A "squashed, skipping.\n", 12162292SN/A inst->readPC(), inst->seqNum, tid); 12171061SN/A } 12181060SN/A } 12192965Sksewell@umich.edu 12203093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 12212965Sksewell@umich.edu if (rename_idx < fromRename->size) { 12222965Sksewell@umich.edu DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 12232965Sksewell@umich.edu 12242965Sksewell@umich.edu for (; 12252965Sksewell@umich.edu rename_idx < fromRename->size; 12262965Sksewell@umich.edu rename_idx++) { 12272965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[rename_idx]; 12282965Sksewell@umich.edu 12292965Sksewell@umich.edu if (!inst->isSquashed()) { 12302965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 12313708Sktlim@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, 12323708Sktlim@umich.edu inst->threadNumber); 12332965Sksewell@umich.edu skidBuffer.push(inst); 12342965Sksewell@umich.edu } else { 12352965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 12362965Sksewell@umich.edu "squashed, skipping.\n", 12373708Sktlim@umich.edu inst->readPC(), inst->seqNum, inst->threadNumber); 12382965Sksewell@umich.edu } 12392965Sksewell@umich.edu } 12402965Sksewell@umich.edu } 12412965Sksewell@umich.edu#endif 12422965Sksewell@umich.edu 12432965Sksewell@umich.edu} 12442965Sksewell@umich.edu 12452965Sksewell@umich.edutemplate <class Impl> 12462965Sksewell@umich.eduvoid 12472965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 12482965Sksewell@umich.edu{ 12492965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 12502965Sksewell@umich.edu "skidBuffer.\n"); 12512965Sksewell@umich.edu 12522965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 12532965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 12542965Sksewell@umich.edu 12552965Sksewell@umich.edu if (!inst->isSquashed()) { 12562965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 12573221Sktlim@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, 12583221Sktlim@umich.edu inst->threadNumber); 12592965Sksewell@umich.edu skidBuffer.push(inst); 12602965Sksewell@umich.edu } else { 12612965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 12622965Sksewell@umich.edu "squashed, skipping.\n", 12633221Sktlim@umich.edu inst->readPC(), inst->seqNum, inst->threadNumber); 12642965Sksewell@umich.edu } 12652965Sksewell@umich.edu } 12661060SN/A} 12671060SN/A 12681061SN/Atemplate <class Impl> 12691060SN/Avoid 12702292SN/ADefaultCommit<Impl>::markCompletedInsts() 12711060SN/A{ 12721060SN/A // Grab completed insts out of the IEW instruction queue, and mark 12731060SN/A // instructions completed within the ROB. 12741060SN/A for (int inst_num = 0; 12751681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 12761060SN/A ++inst_num) 12771060SN/A { 12782292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12792316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 12802316SN/A "within ROB.\n", 12812292SN/A fromIEW->insts[inst_num]->threadNumber, 12822292SN/A fromIEW->insts[inst_num]->readPC(), 12832292SN/A fromIEW->insts[inst_num]->seqNum); 12841060SN/A 12852292SN/A // Mark the instruction as ready to commit. 12862292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12872292SN/A } 12881060SN/A } 12891060SN/A} 12901060SN/A 12911061SN/Atemplate <class Impl> 12922292SN/Abool 12932292SN/ADefaultCommit<Impl>::robDoneSquashing() 12941060SN/A{ 12953867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 12963867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 12972292SN/A 12983867Sbinkertn@umich.edu while (threads != end) { 12992292SN/A unsigned tid = *threads++; 13002292SN/A 13012292SN/A if (!rob->isDoneSquashing(tid)) 13022292SN/A return false; 13032292SN/A } 13042292SN/A 13052292SN/A return true; 13061060SN/A} 13072292SN/A 13082301SN/Atemplate <class Impl> 13092301SN/Avoid 13102301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 13112301SN/A{ 13122301SN/A unsigned thread = inst->threadNumber; 13132301SN/A 13142301SN/A // 13152301SN/A // Pick off the software prefetches 13162301SN/A // 13172301SN/A#ifdef TARGET_ALPHA 13182301SN/A if (inst->isDataPrefetch()) { 13192316SN/A statComSwp[thread]++; 13202301SN/A } else { 13212316SN/A statComInst[thread]++; 13222301SN/A } 13232301SN/A#else 13242316SN/A statComInst[thread]++; 13252301SN/A#endif 13262301SN/A 13272301SN/A // 13282301SN/A // Control Instructions 13292301SN/A // 13302301SN/A if (inst->isControl()) 13312316SN/A statComBranches[thread]++; 13322301SN/A 13332301SN/A // 13342301SN/A // Memory references 13352301SN/A // 13362301SN/A if (inst->isMemRef()) { 13372316SN/A statComRefs[thread]++; 13382301SN/A 13392301SN/A if (inst->isLoad()) { 13402316SN/A statComLoads[thread]++; 13412301SN/A } 13422301SN/A } 13432301SN/A 13442301SN/A if (inst->isMemBarrier()) { 13452316SN/A statComMembars[thread]++; 13462301SN/A } 13472301SN/A} 13482301SN/A 13492292SN/A//////////////////////////////////////// 13502292SN/A// // 13512316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 13522292SN/A// // 13532292SN/A//////////////////////////////////////// 13542292SN/Atemplate <class Impl> 13552292SN/Aint 13562292SN/ADefaultCommit<Impl>::getCommittingThread() 13572292SN/A{ 13582292SN/A if (numThreads > 1) { 13592292SN/A switch (commitPolicy) { 13602292SN/A 13612292SN/A case Aggressive: 13622292SN/A //If Policy is Aggressive, commit will call 13632292SN/A //this function multiple times per 13642292SN/A //cycle 13652292SN/A return oldestReady(); 13662292SN/A 13672292SN/A case RoundRobin: 13682292SN/A return roundRobin(); 13692292SN/A 13702292SN/A case OldestReady: 13712292SN/A return oldestReady(); 13722292SN/A 13732292SN/A default: 13742292SN/A return -1; 13752292SN/A } 13762292SN/A } else { 13773867Sbinkertn@umich.edu assert(!activeThreads->empty()); 13783867Sbinkertn@umich.edu int tid = activeThreads->front(); 13792292SN/A 13802292SN/A if (commitStatus[tid] == Running || 13812292SN/A commitStatus[tid] == Idle || 13822292SN/A commitStatus[tid] == FetchTrapPending) { 13832292SN/A return tid; 13842292SN/A } else { 13852292SN/A return -1; 13862292SN/A } 13872292SN/A } 13882292SN/A} 13892292SN/A 13902292SN/Atemplate<class Impl> 13912292SN/Aint 13922292SN/ADefaultCommit<Impl>::roundRobin() 13932292SN/A{ 13942980Sgblack@eecs.umich.edu std::list<unsigned>::iterator pri_iter = priority_list.begin(); 13952980Sgblack@eecs.umich.edu std::list<unsigned>::iterator end = priority_list.end(); 13962292SN/A 13972292SN/A while (pri_iter != end) { 13982292SN/A unsigned tid = *pri_iter; 13992292SN/A 14002292SN/A if (commitStatus[tid] == Running || 14012831Sksewell@umich.edu commitStatus[tid] == Idle || 14022831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 14032292SN/A 14042292SN/A if (rob->isHeadReady(tid)) { 14052292SN/A priority_list.erase(pri_iter); 14062292SN/A priority_list.push_back(tid); 14072292SN/A 14082292SN/A return tid; 14092292SN/A } 14102292SN/A } 14112292SN/A 14122292SN/A pri_iter++; 14132292SN/A } 14142292SN/A 14152292SN/A return -1; 14162292SN/A} 14172292SN/A 14182292SN/Atemplate<class Impl> 14192292SN/Aint 14202292SN/ADefaultCommit<Impl>::oldestReady() 14212292SN/A{ 14222292SN/A unsigned oldest = 0; 14232292SN/A bool first = true; 14242292SN/A 14253867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 14263867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 14272292SN/A 14283867Sbinkertn@umich.edu while (threads != end) { 14292292SN/A unsigned tid = *threads++; 14302292SN/A 14312292SN/A if (!rob->isEmpty(tid) && 14322292SN/A (commitStatus[tid] == Running || 14332292SN/A commitStatus[tid] == Idle || 14342292SN/A commitStatus[tid] == FetchTrapPending)) { 14352292SN/A 14362292SN/A if (rob->isHeadReady(tid)) { 14372292SN/A 14382292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 14392292SN/A 14402292SN/A if (first) { 14412292SN/A oldest = tid; 14422292SN/A first = false; 14432292SN/A } else if (head_inst->seqNum < oldest) { 14442292SN/A oldest = tid; 14452292SN/A } 14462292SN/A } 14472292SN/A } 14482292SN/A } 14492292SN/A 14502292SN/A if (!first) { 14512292SN/A return oldest; 14522292SN/A } else { 14532292SN/A return -1; 14542292SN/A } 14552292SN/A} 1456