commit_impl.hh revision 3867
112837Sgabeblack@google.com/* 212837Sgabeblack@google.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 312837Sgabeblack@google.com * All rights reserved. 412837Sgabeblack@google.com * 512837Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612837Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712837Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812837Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912837Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012837Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112837Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212837Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312837Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412837Sgabeblack@google.com * this software without specific prior written permission. 1512837Sgabeblack@google.com * 1612837Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712837Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812837Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912837Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012837Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112837Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212837Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312837Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412837Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512837Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612837Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712837Sgabeblack@google.com * 2812837Sgabeblack@google.com * Authors: Kevin Lim 2912837Sgabeblack@google.com * Korey Sewell 3012837Sgabeblack@google.com */ 3112837Sgabeblack@google.com 3212837Sgabeblack@google.com#include "config/full_system.hh" 3312837Sgabeblack@google.com#include "config/use_checker.hh" 3412837Sgabeblack@google.com 3512837Sgabeblack@google.com#include <algorithm> 3612837Sgabeblack@google.com#include <string> 3712837Sgabeblack@google.com 3812837Sgabeblack@google.com#include "arch/utility.hh" 3912837Sgabeblack@google.com#include "base/loader/symtab.hh" 4012837Sgabeblack@google.com#include "base/timebuf.hh" 4112837Sgabeblack@google.com#include "cpu/exetrace.hh" 4212837Sgabeblack@google.com#include "cpu/o3/commit.hh" 4312837Sgabeblack@google.com#include "cpu/o3/thread_state.hh" 4412837Sgabeblack@google.com 4512837Sgabeblack@google.com#if USE_CHECKER 4612837Sgabeblack@google.com#include "cpu/checker/cpu.hh" 4712837Sgabeblack@google.com#endif 4812837Sgabeblack@google.com 4912837Sgabeblack@google.comtemplate <class Impl> 5012837Sgabeblack@google.comDefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 5112837Sgabeblack@google.com unsigned _tid) 5212837Sgabeblack@google.com : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 5312837Sgabeblack@google.com{ 5412837Sgabeblack@google.com this->setFlags(Event::AutoDelete); 5512837Sgabeblack@google.com} 5612837Sgabeblack@google.com 5712837Sgabeblack@google.comtemplate <class Impl> 5812837Sgabeblack@google.comvoid 5912837Sgabeblack@google.comDefaultCommit<Impl>::TrapEvent::process() 6012837Sgabeblack@google.com{ 6112837Sgabeblack@google.com // This will get reset by commit if it was switched out at the 6212837Sgabeblack@google.com // time of this event processing. 6312837Sgabeblack@google.com commit->trapSquash[tid] = true; 6412837Sgabeblack@google.com} 6512837Sgabeblack@google.com 6612837Sgabeblack@google.comtemplate <class Impl> 6712837Sgabeblack@google.comconst char * 6812837Sgabeblack@google.comDefaultCommit<Impl>::TrapEvent::description() 6912837Sgabeblack@google.com{ 7012837Sgabeblack@google.com return "Trap event"; 7112837Sgabeblack@google.com} 7212837Sgabeblack@google.com 7312837Sgabeblack@google.comtemplate <class Impl> 7412837Sgabeblack@google.comDefaultCommit<Impl>::DefaultCommit(Params *params) 7512837Sgabeblack@google.com : squashCounter(0), 7612837Sgabeblack@google.com iewToCommitDelay(params->iewToCommitDelay), 7712837Sgabeblack@google.com commitToIEWDelay(params->commitToIEWDelay), 7812837Sgabeblack@google.com renameToROBDelay(params->renameToROBDelay), 7912837Sgabeblack@google.com fetchToCommitDelay(params->commitToFetchDelay), 8012837Sgabeblack@google.com renameWidth(params->renameWidth), 8112837Sgabeblack@google.com commitWidth(params->commitWidth), 8212837Sgabeblack@google.com numThreads(params->numberOfThreads), 8312837Sgabeblack@google.com drainPending(false), 8412837Sgabeblack@google.com switchedOut(false), 8512837Sgabeblack@google.com trapLatency(params->trapLatency) 8612837Sgabeblack@google.com{ 8712837Sgabeblack@google.com _status = Active; 8812837Sgabeblack@google.com _nextStatus = Inactive; 8912837Sgabeblack@google.com std::string policy = params->smtCommitPolicy; 9012837Sgabeblack@google.com 9112837Sgabeblack@google.com //Convert string to lowercase 9212837Sgabeblack@google.com std::transform(policy.begin(), policy.end(), policy.begin(), 9312837Sgabeblack@google.com (int(*)(int)) tolower); 9412837Sgabeblack@google.com 9512837Sgabeblack@google.com //Assign commit policy 9612837Sgabeblack@google.com if (policy == "aggressive"){ 9712837Sgabeblack@google.com commitPolicy = Aggressive; 9812837Sgabeblack@google.com 9912837Sgabeblack@google.com DPRINTF(Commit,"Commit Policy set to Aggressive."); 10012837Sgabeblack@google.com } else if (policy == "roundrobin"){ 10112837Sgabeblack@google.com commitPolicy = RoundRobin; 10212837Sgabeblack@google.com 10312837Sgabeblack@google.com //Set-Up Priority List 10412837Sgabeblack@google.com for (int tid=0; tid < numThreads; tid++) { 10512837Sgabeblack@google.com priority_list.push_back(tid); 10612837Sgabeblack@google.com } 10712837Sgabeblack@google.com 10812837Sgabeblack@google.com DPRINTF(Commit,"Commit Policy set to Round Robin."); 10912837Sgabeblack@google.com } else if (policy == "oldestready"){ 11012837Sgabeblack@google.com commitPolicy = OldestReady; 11112837Sgabeblack@google.com 11212837Sgabeblack@google.com DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 11312837Sgabeblack@google.com } else { 11412837Sgabeblack@google.com assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 11512837Sgabeblack@google.com "RoundRobin,OldestReady}"); 11612837Sgabeblack@google.com } 11712837Sgabeblack@google.com 11812837Sgabeblack@google.com for (int i=0; i < numThreads; i++) { 11912837Sgabeblack@google.com commitStatus[i] = Idle; 12012837Sgabeblack@google.com changedROBNumEntries[i] = false; 12112837Sgabeblack@google.com trapSquash[i] = false; 12212837Sgabeblack@google.com tcSquash[i] = false; 12312837Sgabeblack@google.com PC[i] = nextPC[i] = nextNPC[i] = 0; 12412837Sgabeblack@google.com } 12512837Sgabeblack@google.com#if FULL_SYSTEM 12612837Sgabeblack@google.com interrupt = NoFault; 12712837Sgabeblack@google.com#endif 12812837Sgabeblack@google.com} 12912837Sgabeblack@google.com 13012837Sgabeblack@google.comtemplate <class Impl> 13112837Sgabeblack@google.comstd::string 13212837Sgabeblack@google.comDefaultCommit<Impl>::name() const 13312837Sgabeblack@google.com{ 13412837Sgabeblack@google.com return cpu->name() + ".commit"; 13512837Sgabeblack@google.com} 13612837Sgabeblack@google.com 13712837Sgabeblack@google.comtemplate <class Impl> 13812837Sgabeblack@google.comvoid 13912837Sgabeblack@google.comDefaultCommit<Impl>::regStats() 14012837Sgabeblack@google.com{ 14112837Sgabeblack@google.com using namespace Stats; 14212837Sgabeblack@google.com commitCommittedInsts 14312837Sgabeblack@google.com .name(name() + ".commitCommittedInsts") 14412864Sgabeblack@google.com .desc("The number of committed instructions") 14512864Sgabeblack@google.com .prereq(commitCommittedInsts); 14612864Sgabeblack@google.com commitSquashedInsts 14712837Sgabeblack@google.com .name(name() + ".commitSquashedInsts") 14812837Sgabeblack@google.com .desc("The number of squashed insts skipped by commit") 14912837Sgabeblack@google.com .prereq(commitSquashedInsts); 15012837Sgabeblack@google.com commitSquashEvents 15112837Sgabeblack@google.com .name(name() + ".commitSquashEvents") 15212837Sgabeblack@google.com .desc("The number of times commit is told to squash") 15312837Sgabeblack@google.com .prereq(commitSquashEvents); 15412837Sgabeblack@google.com commitNonSpecStalls 15512837Sgabeblack@google.com .name(name() + ".commitNonSpecStalls") 15612837Sgabeblack@google.com .desc("The number of times commit has been forced to stall to " 15712837Sgabeblack@google.com "communicate backwards") 15812837Sgabeblack@google.com .prereq(commitNonSpecStalls); 15912837Sgabeblack@google.com branchMispredicts 16012837Sgabeblack@google.com .name(name() + ".branchMispredicts") 16112837Sgabeblack@google.com .desc("The number of times a branch was mispredicted") 16212837Sgabeblack@google.com .prereq(branchMispredicts); 16312837Sgabeblack@google.com numCommittedDist 16412837Sgabeblack@google.com .init(0,commitWidth,1) 16512837Sgabeblack@google.com .name(name() + ".COM:committed_per_cycle") 16612837Sgabeblack@google.com .desc("Number of insts commited each cycle") 16712837Sgabeblack@google.com .flags(Stats::pdf) 16812837Sgabeblack@google.com ; 16912837Sgabeblack@google.com 17012837Sgabeblack@google.com statComInst 17112837Sgabeblack@google.com .init(cpu->number_of_threads) 17212837Sgabeblack@google.com .name(name() + ".COM:count") 17312837Sgabeblack@google.com .desc("Number of instructions committed") 17412837Sgabeblack@google.com .flags(total) 17512837Sgabeblack@google.com ; 17612837Sgabeblack@google.com 17712837Sgabeblack@google.com statComSwp 17812837Sgabeblack@google.com .init(cpu->number_of_threads) 17912837Sgabeblack@google.com .name(name() + ".COM:swp_count") 18012837Sgabeblack@google.com .desc("Number of s/w prefetches committed") 18112837Sgabeblack@google.com .flags(total) 18212837Sgabeblack@google.com ; 18312837Sgabeblack@google.com 18412837Sgabeblack@google.com statComRefs 18512837Sgabeblack@google.com .init(cpu->number_of_threads) 18612837Sgabeblack@google.com .name(name() + ".COM:refs") 18712837Sgabeblack@google.com .desc("Number of memory references committed") 18812837Sgabeblack@google.com .flags(total) 18912909Sgabeblack@google.com ; 19012909Sgabeblack@google.com 19112837Sgabeblack@google.com statComLoads 19212837Sgabeblack@google.com .init(cpu->number_of_threads) 19312837Sgabeblack@google.com .name(name() + ".COM:loads") 19412837Sgabeblack@google.com .desc("Number of loads committed") 19512837Sgabeblack@google.com .flags(total) 19612837Sgabeblack@google.com ; 19712837Sgabeblack@google.com 19812837Sgabeblack@google.com statComMembars 19912837Sgabeblack@google.com .init(cpu->number_of_threads) 20012837Sgabeblack@google.com .name(name() + ".COM:membars") 20112837Sgabeblack@google.com .desc("Number of memory barriers committed") 20212837Sgabeblack@google.com .flags(total) 20312837Sgabeblack@google.com ; 20412837Sgabeblack@google.com 20512837Sgabeblack@google.com statComBranches 20612837Sgabeblack@google.com .init(cpu->number_of_threads) 20712837Sgabeblack@google.com .name(name() + ".COM:branches") 20812837Sgabeblack@google.com .desc("Number of branches committed") 20912837Sgabeblack@google.com .flags(total) 21012837Sgabeblack@google.com ; 21112837Sgabeblack@google.com 21212837Sgabeblack@google.com commitEligible 21312837Sgabeblack@google.com .init(cpu->number_of_threads) 21412837Sgabeblack@google.com .name(name() + ".COM:bw_limited") 21512837Sgabeblack@google.com .desc("number of insts not committed due to BW limits") 21612837Sgabeblack@google.com .flags(total) 21712837Sgabeblack@google.com ; 21812837Sgabeblack@google.com 21912837Sgabeblack@google.com commitEligibleSamples 22012837Sgabeblack@google.com .name(name() + ".COM:bw_lim_events") 22112837Sgabeblack@google.com .desc("number cycles where commit BW limit reached") 22212837Sgabeblack@google.com ; 22312837Sgabeblack@google.com} 22412837Sgabeblack@google.com 22512837Sgabeblack@google.comtemplate <class Impl> 22612837Sgabeblack@google.comvoid 22712837Sgabeblack@google.comDefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 22812837Sgabeblack@google.com{ 22912837Sgabeblack@google.com DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 23012837Sgabeblack@google.com cpu = cpu_ptr; 23112837Sgabeblack@google.com 23212837Sgabeblack@google.com // Commit must broadcast the number of free entries it has at the start of 23312837Sgabeblack@google.com // the simulation, so it starts as active. 23412837Sgabeblack@google.com cpu->activateStage(O3CPU::CommitIdx); 23512837Sgabeblack@google.com 23612837Sgabeblack@google.com trapLatency = cpu->cycles(trapLatency); 23712837Sgabeblack@google.com} 23812837Sgabeblack@google.com 23912837Sgabeblack@google.comtemplate <class Impl> 24012837Sgabeblack@google.comvoid 24112909Sgabeblack@google.comDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 24212909Sgabeblack@google.com{ 24312909Sgabeblack@google.com thread = threads; 24412909Sgabeblack@google.com} 24512909Sgabeblack@google.com 24612909Sgabeblack@google.comtemplate <class Impl> 24712837Sgabeblack@google.comvoid 24812837Sgabeblack@google.comDefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 24912837Sgabeblack@google.com{ 25012837Sgabeblack@google.com DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 25112837Sgabeblack@google.com timeBuffer = tb_ptr; 25212837Sgabeblack@google.com 25312837Sgabeblack@google.com // Setup wire to send information back to IEW. 25412837Sgabeblack@google.com toIEW = timeBuffer->getWire(0); 25512901Sgabeblack@google.com 25612901Sgabeblack@google.com // Setup wire to read data from IEW (for the ROB). 25712901Sgabeblack@google.com robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 25812901Sgabeblack@google.com} 25912901Sgabeblack@google.com 26012901Sgabeblack@google.comtemplate <class Impl> 26112907Sgabeblack@google.comvoid 26212907Sgabeblack@google.comDefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 26312907Sgabeblack@google.com{ 26412907Sgabeblack@google.com DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 26512907Sgabeblack@google.com fetchQueue = fq_ptr; 26612907Sgabeblack@google.com 26712907Sgabeblack@google.com // Setup wire to get instructions from rename (for the ROB). 26812907Sgabeblack@google.com fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 26912907Sgabeblack@google.com} 27012907Sgabeblack@google.com 27112907Sgabeblack@google.comtemplate <class Impl> 27212907Sgabeblack@google.comvoid 27312907Sgabeblack@google.comDefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 27412837Sgabeblack@google.com{ 27512837Sgabeblack@google.com DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 27612837Sgabeblack@google.com renameQueue = rq_ptr; 277 278 // Setup wire to get instructions from rename (for the ROB). 279 fromRename = renameQueue->getWire(-renameToROBDelay); 280} 281 282template <class Impl> 283void 284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 285{ 286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 287 iewQueue = iq_ptr; 288 289 // Setup wire to get instructions from IEW. 290 fromIEW = iewQueue->getWire(-iewToCommitDelay); 291} 292 293template <class Impl> 294void 295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 296{ 297 iewStage = iew_stage; 298} 299 300template<class Impl> 301void 302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 303{ 304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 305 activeThreads = at_ptr; 306} 307 308template <class Impl> 309void 310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 311{ 312 DPRINTF(Commit, "Setting rename map pointers.\n"); 313 314 for (int i=0; i < numThreads; i++) { 315 renameMap[i] = &rm_ptr[i]; 316 } 317} 318 319template <class Impl> 320void 321DefaultCommit<Impl>::setROB(ROB *rob_ptr) 322{ 323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 324 rob = rob_ptr; 325} 326 327template <class Impl> 328void 329DefaultCommit<Impl>::initStage() 330{ 331 rob->setActiveThreads(activeThreads); 332 rob->resetEntries(); 333 334 // Broadcast the number of free entries. 335 for (int i=0; i < numThreads; i++) { 336 toIEW->commitInfo[i].usedROB = true; 337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 338 } 339 340 cpu->activityThisCycle(); 341} 342 343template <class Impl> 344bool 345DefaultCommit<Impl>::drain() 346{ 347 drainPending = true; 348 349 return false; 350} 351 352template <class Impl> 353void 354DefaultCommit<Impl>::switchOut() 355{ 356 switchedOut = true; 357 drainPending = false; 358 rob->switchOut(); 359} 360 361template <class Impl> 362void 363DefaultCommit<Impl>::resume() 364{ 365 drainPending = false; 366} 367 368template <class Impl> 369void 370DefaultCommit<Impl>::takeOverFrom() 371{ 372 switchedOut = false; 373 _status = Active; 374 _nextStatus = Inactive; 375 for (int i=0; i < numThreads; i++) { 376 commitStatus[i] = Idle; 377 changedROBNumEntries[i] = false; 378 trapSquash[i] = false; 379 tcSquash[i] = false; 380 } 381 squashCounter = 0; 382 rob->takeOverFrom(); 383} 384 385template <class Impl> 386void 387DefaultCommit<Impl>::updateStatus() 388{ 389 // reset ROB changed variable 390 std::list<unsigned>::iterator threads = activeThreads->begin(); 391 std::list<unsigned>::iterator end = activeThreads->end(); 392 393 while (threads != end) { 394 unsigned tid = *threads++; 395 396 changedROBNumEntries[tid] = false; 397 398 // Also check if any of the threads has a trap pending 399 if (commitStatus[tid] == TrapPending || 400 commitStatus[tid] == FetchTrapPending) { 401 _nextStatus = Active; 402 } 403 } 404 405 if (_nextStatus == Inactive && _status == Active) { 406 DPRINTF(Activity, "Deactivating stage.\n"); 407 cpu->deactivateStage(O3CPU::CommitIdx); 408 } else if (_nextStatus == Active && _status == Inactive) { 409 DPRINTF(Activity, "Activating stage.\n"); 410 cpu->activateStage(O3CPU::CommitIdx); 411 } 412 413 _status = _nextStatus; 414} 415 416template <class Impl> 417void 418DefaultCommit<Impl>::setNextStatus() 419{ 420 int squashes = 0; 421 422 std::list<unsigned>::iterator threads = activeThreads->begin(); 423 std::list<unsigned>::iterator end = activeThreads->end(); 424 425 while (threads != end) { 426 unsigned tid = *threads++; 427 428 if (commitStatus[tid] == ROBSquashing) { 429 squashes++; 430 } 431 } 432 433 squashCounter = squashes; 434 435 // If commit is currently squashing, then it will have activity for the 436 // next cycle. Set its next status as active. 437 if (squashCounter) { 438 _nextStatus = Active; 439 } 440} 441 442template <class Impl> 443bool 444DefaultCommit<Impl>::changedROBEntries() 445{ 446 std::list<unsigned>::iterator threads = activeThreads->begin(); 447 std::list<unsigned>::iterator end = activeThreads->end(); 448 449 while (threads != end) { 450 unsigned tid = *threads++; 451 452 if (changedROBNumEntries[tid]) { 453 return true; 454 } 455 } 456 457 return false; 458} 459 460template <class Impl> 461unsigned 462DefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 463{ 464 return rob->numFreeEntries(tid); 465} 466 467template <class Impl> 468void 469DefaultCommit<Impl>::generateTrapEvent(unsigned tid) 470{ 471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 472 473 TrapEvent *trap = new TrapEvent(this, tid); 474 475 trap->schedule(curTick + trapLatency); 476 477 thread[tid]->trapPending = true; 478} 479 480template <class Impl> 481void 482DefaultCommit<Impl>::generateTCEvent(unsigned tid) 483{ 484 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 485 486 tcSquash[tid] = true; 487} 488 489template <class Impl> 490void 491DefaultCommit<Impl>::squashAll(unsigned tid) 492{ 493 // If we want to include the squashing instruction in the squash, 494 // then use one older sequence number. 495 // Hopefully this doesn't mess things up. Basically I want to squash 496 // all instructions of this thread. 497 InstSeqNum squashed_inst = rob->isEmpty() ? 498 0 : rob->readHeadInst(tid)->seqNum - 1;; 499 500 // All younger instructions will be squashed. Set the sequence 501 // number as the youngest instruction in the ROB (0 in this case. 502 // Hopefully nothing breaks.) 503 youngestSeqNum[tid] = 0; 504 505 rob->squash(squashed_inst, tid); 506 changedROBNumEntries[tid] = true; 507 508 // Send back the sequence number of the squashed instruction. 509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 510 511 // Send back the squash signal to tell stages that they should 512 // squash. 513 toIEW->commitInfo[tid].squash = true; 514 515 // Send back the rob squashing signal so other stages know that 516 // the ROB is in the process of squashing. 517 toIEW->commitInfo[tid].robSquashing = true; 518 519 toIEW->commitInfo[tid].branchMispredict = false; 520 521 toIEW->commitInfo[tid].nextPC = PC[tid]; 522} 523 524template <class Impl> 525void 526DefaultCommit<Impl>::squashFromTrap(unsigned tid) 527{ 528 squashAll(tid); 529 530 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 531 532 thread[tid]->trapPending = false; 533 thread[tid]->inSyscall = false; 534 535 trapSquash[tid] = false; 536 537 commitStatus[tid] = ROBSquashing; 538 cpu->activityThisCycle(); 539} 540 541template <class Impl> 542void 543DefaultCommit<Impl>::squashFromTC(unsigned tid) 544{ 545 squashAll(tid); 546 547 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 548 549 thread[tid]->inSyscall = false; 550 assert(!thread[tid]->trapPending); 551 552 commitStatus[tid] = ROBSquashing; 553 cpu->activityThisCycle(); 554 555 tcSquash[tid] = false; 556} 557 558template <class Impl> 559void 560DefaultCommit<Impl>::tick() 561{ 562 wroteToTimeBuffer = false; 563 _nextStatus = Inactive; 564 565 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 566 cpu->signalDrained(); 567 drainPending = false; 568 return; 569 } 570 571 if (activeThreads->empty()) 572 return; 573 574 std::list<unsigned>::iterator threads = activeThreads->begin(); 575 std::list<unsigned>::iterator end = activeThreads->end(); 576 577 // Check if any of the threads are done squashing. Change the 578 // status if they are done. 579 while (threads != end) { 580 unsigned tid = *threads++; 581 582 if (commitStatus[tid] == ROBSquashing) { 583 584 if (rob->isDoneSquashing(tid)) { 585 commitStatus[tid] = Running; 586 } else { 587 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 588 " insts this cycle.\n", tid); 589 rob->doSquash(tid); 590 toIEW->commitInfo[tid].robSquashing = true; 591 wroteToTimeBuffer = true; 592 } 593 } 594 } 595 596 commit(); 597 598 markCompletedInsts(); 599 600 threads = activeThreads->begin(); 601 602 while (threads != end) { 603 unsigned tid = *threads++; 604 605 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 606 // The ROB has more instructions it can commit. Its next status 607 // will be active. 608 _nextStatus = Active; 609 610 DynInstPtr inst = rob->readHeadInst(tid); 611 612 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 613 " ROB and ready to commit\n", 614 tid, inst->seqNum, inst->readPC()); 615 616 } else if (!rob->isEmpty(tid)) { 617 DynInstPtr inst = rob->readHeadInst(tid); 618 619 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 620 "%#x is head of ROB and not ready\n", 621 tid, inst->seqNum, inst->readPC()); 622 } 623 624 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 625 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 626 } 627 628 629 if (wroteToTimeBuffer) { 630 DPRINTF(Activity, "Activity This Cycle.\n"); 631 cpu->activityThisCycle(); 632 } 633 634 updateStatus(); 635} 636 637template <class Impl> 638void 639DefaultCommit<Impl>::commit() 640{ 641 642 ////////////////////////////////////// 643 // Check for interrupts 644 ////////////////////////////////////// 645 646#if FULL_SYSTEM 647 if (interrupt != NoFault) { 648 // Wait until the ROB is empty and all stores have drained in 649 // order to enter the interrupt. 650 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 651 // Squash or record that I need to squash this cycle if 652 // an interrupt needed to be handled. 653 DPRINTF(Commit, "Interrupt detected.\n"); 654 655 assert(!thread[0]->inSyscall); 656 thread[0]->inSyscall = true; 657 658 // CPU will handle interrupt. 659 cpu->processInterrupts(interrupt); 660 661 thread[0]->inSyscall = false; 662 663 commitStatus[0] = TrapPending; 664 665 // Generate trap squash event. 666 generateTrapEvent(0); 667 668 // Clear the interrupt now that it's been handled 669 toIEW->commitInfo[0].clearInterrupt = true; 670 interrupt = NoFault; 671 } else { 672 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 673 } 674 } else if (cpu->checkInterrupts && 675 cpu->check_interrupts(cpu->tcBase(0)) && 676 commitStatus[0] != TrapPending && 677 !trapSquash[0] && 678 !tcSquash[0]) { 679 // Process interrupts if interrupts are enabled, not in PAL 680 // mode, and no other traps or external squashes are currently 681 // pending. 682 // @todo: Allow other threads to handle interrupts. 683 684 // Get any interrupt that happened 685 interrupt = cpu->getInterrupts(); 686 687 if (interrupt != NoFault) { 688 // Tell fetch that there is an interrupt pending. This 689 // will make fetch wait until it sees a non PAL-mode PC, 690 // at which point it stops fetching instructions. 691 toIEW->commitInfo[0].interruptPending = true; 692 } 693 } 694 695#endif // FULL_SYSTEM 696 697 //////////////////////////////////// 698 // Check for any possible squashes, handle them first 699 //////////////////////////////////// 700 std::list<unsigned>::iterator threads = activeThreads->begin(); 701 std::list<unsigned>::iterator end = activeThreads->end(); 702 703 while (threads != end) { 704 unsigned tid = *threads++; 705 706 // Not sure which one takes priority. I think if we have 707 // both, that's a bad sign. 708 if (trapSquash[tid] == true) { 709 assert(!tcSquash[tid]); 710 squashFromTrap(tid); 711 } else if (tcSquash[tid] == true) { 712 squashFromTC(tid); 713 } 714 715 // Squashed sequence number must be older than youngest valid 716 // instruction in the ROB. This prevents squashes from younger 717 // instructions overriding squashes from older instructions. 718 if (fromIEW->squash[tid] && 719 commitStatus[tid] != TrapPending && 720 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 721 722 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 723 tid, 724 fromIEW->mispredPC[tid], 725 fromIEW->squashedSeqNum[tid]); 726 727 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 728 tid, 729 fromIEW->nextPC[tid]); 730 731 commitStatus[tid] = ROBSquashing; 732 733 // If we want to include the squashing instruction in the squash, 734 // then use one older sequence number. 735 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 736 737#if ISA_HAS_DELAY_SLOT 738 InstSeqNum bdelay_done_seq_num; 739 bool squash_bdelay_slot; 740 741 if (fromIEW->branchMispredict[tid]) { 742 if (fromIEW->branchTaken[tid] && 743 fromIEW->condDelaySlotBranch[tid]) { 744 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch" 745 "mispredicted as taken. Squashing after previous " 746 "inst, [sn:%i]\n", 747 tid, squashed_inst); 748 bdelay_done_seq_num = squashed_inst; 749 squash_bdelay_slot = true; 750 } else { 751 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing " 752 "after delay slot [sn:%i]\n", tid, squashed_inst+1); 753 bdelay_done_seq_num = squashed_inst + 1; 754 squash_bdelay_slot = false; 755 } 756 } else { 757 bdelay_done_seq_num = squashed_inst; 758 squash_bdelay_slot = true; 759 } 760#endif 761 762 if (fromIEW->includeSquashInst[tid] == true) { 763 squashed_inst--; 764#if ISA_HAS_DELAY_SLOT 765 bdelay_done_seq_num--; 766#endif 767 } 768 // All younger instructions will be squashed. Set the sequence 769 // number as the youngest instruction in the ROB. 770 youngestSeqNum[tid] = squashed_inst; 771 772#if ISA_HAS_DELAY_SLOT 773 rob->squash(bdelay_done_seq_num, tid); 774 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 775 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 776#else 777 rob->squash(squashed_inst, tid); 778 toIEW->commitInfo[tid].squashDelaySlot = true; 779#endif 780 changedROBNumEntries[tid] = true; 781 782 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 783 784 toIEW->commitInfo[tid].squash = true; 785 786 // Send back the rob squashing signal so other stages know that 787 // the ROB is in the process of squashing. 788 toIEW->commitInfo[tid].robSquashing = true; 789 790 toIEW->commitInfo[tid].branchMispredict = 791 fromIEW->branchMispredict[tid]; 792 793 toIEW->commitInfo[tid].branchTaken = 794 fromIEW->branchTaken[tid]; 795 796 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 797 798 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 799 800 if (toIEW->commitInfo[tid].branchMispredict) { 801 ++branchMispredicts; 802 } 803 } 804 805 } 806 807 setNextStatus(); 808 809 if (squashCounter != numThreads) { 810 // If we're not currently squashing, then get instructions. 811 getInsts(); 812 813 // Try to commit any instructions. 814 commitInsts(); 815 } else { 816#if ISA_HAS_DELAY_SLOT 817 skidInsert(); 818#endif 819 } 820 821 //Check for any activity 822 threads = activeThreads->begin(); 823 824 while (threads != end) { 825 unsigned tid = *threads++; 826 827 if (changedROBNumEntries[tid]) { 828 toIEW->commitInfo[tid].usedROB = true; 829 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 830 831 if (rob->isEmpty(tid)) { 832 toIEW->commitInfo[tid].emptyROB = true; 833 } 834 835 wroteToTimeBuffer = true; 836 changedROBNumEntries[tid] = false; 837 } 838 } 839} 840 841template <class Impl> 842void 843DefaultCommit<Impl>::commitInsts() 844{ 845 //////////////////////////////////// 846 // Handle commit 847 // Note that commit will be handled prior to putting new 848 // instructions in the ROB so that the ROB only tries to commit 849 // instructions it has in this current cycle, and not instructions 850 // it is writing in during this cycle. Can't commit and squash 851 // things at the same time... 852 //////////////////////////////////// 853 854 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 855 856 unsigned num_committed = 0; 857 858 DynInstPtr head_inst; 859 860 // Commit as many instructions as possible until the commit bandwidth 861 // limit is reached, or it becomes impossible to commit any more. 862 while (num_committed < commitWidth) { 863 int commit_thread = getCommittingThread(); 864 865 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 866 break; 867 868 head_inst = rob->readHeadInst(commit_thread); 869 870 int tid = head_inst->threadNumber; 871 872 assert(tid == commit_thread); 873 874 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 875 head_inst->seqNum, tid); 876 877 // If the head instruction is squashed, it is ready to retire 878 // (be removed from the ROB) at any time. 879 if (head_inst->isSquashed()) { 880 881 DPRINTF(Commit, "Retiring squashed instruction from " 882 "ROB.\n"); 883 884 rob->retireHead(commit_thread); 885 886 ++commitSquashedInsts; 887 888 // Record that the number of ROB entries has changed. 889 changedROBNumEntries[tid] = true; 890 } else { 891 PC[tid] = head_inst->readPC(); 892 nextPC[tid] = head_inst->readNextPC(); 893 nextNPC[tid] = head_inst->readNextNPC(); 894 895 // Increment the total number of non-speculative instructions 896 // executed. 897 // Hack for now: it really shouldn't happen until after the 898 // commit is deemed to be successful, but this count is needed 899 // for syscalls. 900 thread[tid]->funcExeInst++; 901 902 // Try to commit the head instruction. 903 bool commit_success = commitHead(head_inst, num_committed); 904 905 if (commit_success) { 906 ++num_committed; 907 908 changedROBNumEntries[tid] = true; 909 910 // Set the doneSeqNum to the youngest committed instruction. 911 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 912 913 ++commitCommittedInsts; 914 915 // To match the old model, don't count nops and instruction 916 // prefetches towards the total commit count. 917 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 918 cpu->instDone(tid); 919 } 920 921 PC[tid] = nextPC[tid]; 922#if ISA_HAS_DELAY_SLOT 923 nextPC[tid] = nextNPC[tid]; 924 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 925#else 926 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 927#endif 928 929#if FULL_SYSTEM 930 int count = 0; 931 Addr oldpc; 932 do { 933 // Debug statement. Checks to make sure we're not 934 // currently updating state while handling PC events. 935 if (count == 0) 936 assert(!thread[tid]->inSyscall && 937 !thread[tid]->trapPending); 938 oldpc = PC[tid]; 939 cpu->system->pcEventQueue.service( 940 thread[tid]->getTC()); 941 count++; 942 } while (oldpc != PC[tid]); 943 if (count > 1) { 944 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 945 break; 946 } 947#endif 948 } else { 949 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 950 "[tid:%i] [sn:%i].\n", 951 head_inst->readPC(), tid ,head_inst->seqNum); 952 break; 953 } 954 } 955 } 956 957 DPRINTF(CommitRate, "%i\n", num_committed); 958 numCommittedDist.sample(num_committed); 959 960 if (num_committed == commitWidth) { 961 commitEligibleSamples++; 962 } 963} 964 965template <class Impl> 966bool 967DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 968{ 969 assert(head_inst); 970 971 int tid = head_inst->threadNumber; 972 973 // If the instruction is not executed yet, then it will need extra 974 // handling. Signal backwards that it should be executed. 975 if (!head_inst->isExecuted()) { 976 // Keep this number correct. We have not yet actually executed 977 // and committed this instruction. 978 thread[tid]->funcExeInst--; 979 980 head_inst->setAtCommit(); 981 982 if (head_inst->isNonSpeculative() || 983 head_inst->isStoreConditional() || 984 head_inst->isMemBarrier() || 985 head_inst->isWriteBarrier()) { 986 987 DPRINTF(Commit, "Encountered a barrier or non-speculative " 988 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 989 head_inst->seqNum, head_inst->readPC()); 990 991#if !FULL_SYSTEM 992 // Hack to make sure syscalls/memory barriers/quiesces 993 // aren't executed until all stores write back their data. 994 // This direct communication shouldn't be used for 995 // anything other than this. 996 if (inst_num > 0 || iewStage->hasStoresToWB()) 997#else 998 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 999 head_inst->isQuiesce()) && 1000 iewStage->hasStoresToWB()) 1001#endif 1002 { 1003 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1004 return false; 1005 } 1006 1007 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1008 1009 // Change the instruction so it won't try to commit again until 1010 // it is executed. 1011 head_inst->clearCanCommit(); 1012 1013 ++commitNonSpecStalls; 1014 1015 return false; 1016 } else if (head_inst->isLoad()) { 1017 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 1018 head_inst->seqNum, head_inst->readPC()); 1019 1020 // Send back the non-speculative instruction's sequence 1021 // number. Tell the lsq to re-execute the load. 1022 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1023 toIEW->commitInfo[tid].uncached = true; 1024 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1025 1026 head_inst->clearCanCommit(); 1027 1028 return false; 1029 } else { 1030 panic("Trying to commit un-executed instruction " 1031 "of unknown type!\n"); 1032 } 1033 } 1034 1035 if (head_inst->isThreadSync()) { 1036 // Not handled for now. 1037 panic("Thread sync instructions are not handled yet.\n"); 1038 } 1039 1040 // Stores mark themselves as completed. 1041 if (!head_inst->isStore()) { 1042 head_inst->setCompleted(); 1043 } 1044 1045#if USE_CHECKER 1046 // Use checker prior to updating anything due to traps or PC 1047 // based events. 1048 if (cpu->checker) { 1049 cpu->checker->verify(head_inst); 1050 } 1051#endif 1052 1053 // Check if the instruction caused a fault. If so, trap. 1054 Fault inst_fault = head_inst->getFault(); 1055 1056 // DTB will sometimes need the machine instruction for when 1057 // faults happen. So we will set it here, prior to the DTB 1058 // possibly needing it for its fault. 1059 thread[tid]->setInst( 1060 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1061 1062 if (inst_fault != NoFault) { 1063 head_inst->setCompleted(); 1064 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1065 head_inst->seqNum, head_inst->readPC()); 1066 1067 if (iewStage->hasStoresToWB() || inst_num > 0) { 1068 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1069 return false; 1070 } 1071 1072#if USE_CHECKER 1073 if (cpu->checker && head_inst->isStore()) { 1074 cpu->checker->verify(head_inst); 1075 } 1076#endif 1077 1078 assert(!thread[tid]->inSyscall); 1079 1080 // Mark that we're in state update mode so that the trap's 1081 // execution doesn't generate extra squashes. 1082 thread[tid]->inSyscall = true; 1083 1084 // Execute the trap. Although it's slightly unrealistic in 1085 // terms of timing (as it doesn't wait for the full timing of 1086 // the trap event to complete before updating state), it's 1087 // needed to update the state as soon as possible. This 1088 // prevents external agents from changing any specific state 1089 // that the trap need. 1090 cpu->trap(inst_fault, tid); 1091 1092 // Exit state update mode to avoid accidental updating. 1093 thread[tid]->inSyscall = false; 1094 1095 commitStatus[tid] = TrapPending; 1096 1097 // Generate trap squash event. 1098 generateTrapEvent(tid); 1099// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 1100 return false; 1101 } 1102 1103 updateComInstStats(head_inst); 1104 1105#if FULL_SYSTEM 1106 if (thread[tid]->profile) { 1107// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 1108// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 1109 thread[tid]->profilePC = head_inst->readPC(); 1110 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1111 head_inst->staticInst); 1112 1113 if (node) 1114 thread[tid]->profileNode = node; 1115 } 1116#endif 1117 1118 if (head_inst->traceData) { 1119 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1120 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1121 head_inst->traceData->finalize(); 1122 head_inst->traceData = NULL; 1123 } 1124 1125 // Update the commit rename map 1126 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1127 renameMap[tid]->setEntry(head_inst->destRegIdx(i), 1128 head_inst->renamedDestRegIdx(i)); 1129 } 1130 1131 if (head_inst->isCopy()) 1132 panic("Should not commit any copy instructions!"); 1133 1134 // Finally clear the head ROB entry. 1135 rob->retireHead(tid); 1136 1137 // Return true to indicate that we have committed an instruction. 1138 return true; 1139} 1140 1141template <class Impl> 1142void 1143DefaultCommit<Impl>::getInsts() 1144{ 1145 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1146 1147#if ISA_HAS_DELAY_SLOT 1148 // Read any renamed instructions and place them into the ROB. 1149 int insts_to_process = std::min((int)renameWidth, 1150 (int)(fromRename->size + skidBuffer.size())); 1151 int rename_idx = 0; 1152 1153 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 1154 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 1155 skidBuffer.size()); 1156#else 1157 // Read any renamed instructions and place them into the ROB. 1158 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1159#endif 1160 1161 1162 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1163 DynInstPtr inst; 1164 1165#if ISA_HAS_DELAY_SLOT 1166 // Get insts from skidBuffer or from Rename 1167 if (skidBuffer.size() > 0) { 1168 DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 1169 inst = skidBuffer.front(); 1170 skidBuffer.pop(); 1171 } else { 1172 DPRINTF(Commit, "Grabbing rename inst.\n"); 1173 inst = fromRename->insts[rename_idx++]; 1174 } 1175#else 1176 inst = fromRename->insts[inst_num]; 1177#endif 1178 int tid = inst->threadNumber; 1179 1180 if (!inst->isSquashed() && 1181 commitStatus[tid] != ROBSquashing) { 1182 changedROBNumEntries[tid] = true; 1183 1184 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1185 inst->readPC(), inst->seqNum, tid); 1186 1187 rob->insertInst(inst); 1188 1189 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1190 1191 youngestSeqNum[tid] = inst->seqNum; 1192 } else { 1193 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1194 "squashed, skipping.\n", 1195 inst->readPC(), inst->seqNum, tid); 1196 } 1197 } 1198 1199#if ISA_HAS_DELAY_SLOT 1200 if (rename_idx < fromRename->size) { 1201 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 1202 1203 for (; 1204 rename_idx < fromRename->size; 1205 rename_idx++) { 1206 DynInstPtr inst = fromRename->insts[rename_idx]; 1207 1208 if (!inst->isSquashed()) { 1209 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1210 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1211 inst->threadNumber); 1212 skidBuffer.push(inst); 1213 } else { 1214 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1215 "squashed, skipping.\n", 1216 inst->readPC(), inst->seqNum, inst->threadNumber); 1217 } 1218 } 1219 } 1220#endif 1221 1222} 1223 1224template <class Impl> 1225void 1226DefaultCommit<Impl>::skidInsert() 1227{ 1228 DPRINTF(Commit, "Attempting to any instructions from rename into " 1229 "skidBuffer.\n"); 1230 1231 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1232 DynInstPtr inst = fromRename->insts[inst_num]; 1233 1234 if (!inst->isSquashed()) { 1235 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1236 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1237 inst->threadNumber); 1238 skidBuffer.push(inst); 1239 } else { 1240 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1241 "squashed, skipping.\n", 1242 inst->readPC(), inst->seqNum, inst->threadNumber); 1243 } 1244 } 1245} 1246 1247template <class Impl> 1248void 1249DefaultCommit<Impl>::markCompletedInsts() 1250{ 1251 // Grab completed insts out of the IEW instruction queue, and mark 1252 // instructions completed within the ROB. 1253 for (int inst_num = 0; 1254 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1255 ++inst_num) 1256 { 1257 if (!fromIEW->insts[inst_num]->isSquashed()) { 1258 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1259 "within ROB.\n", 1260 fromIEW->insts[inst_num]->threadNumber, 1261 fromIEW->insts[inst_num]->readPC(), 1262 fromIEW->insts[inst_num]->seqNum); 1263 1264 // Mark the instruction as ready to commit. 1265 fromIEW->insts[inst_num]->setCanCommit(); 1266 } 1267 } 1268} 1269 1270template <class Impl> 1271bool 1272DefaultCommit<Impl>::robDoneSquashing() 1273{ 1274 std::list<unsigned>::iterator threads = activeThreads->begin(); 1275 std::list<unsigned>::iterator end = activeThreads->end(); 1276 1277 while (threads != end) { 1278 unsigned tid = *threads++; 1279 1280 if (!rob->isDoneSquashing(tid)) 1281 return false; 1282 } 1283 1284 return true; 1285} 1286 1287template <class Impl> 1288void 1289DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1290{ 1291 unsigned thread = inst->threadNumber; 1292 1293 // 1294 // Pick off the software prefetches 1295 // 1296#ifdef TARGET_ALPHA 1297 if (inst->isDataPrefetch()) { 1298 statComSwp[thread]++; 1299 } else { 1300 statComInst[thread]++; 1301 } 1302#else 1303 statComInst[thread]++; 1304#endif 1305 1306 // 1307 // Control Instructions 1308 // 1309 if (inst->isControl()) 1310 statComBranches[thread]++; 1311 1312 // 1313 // Memory references 1314 // 1315 if (inst->isMemRef()) { 1316 statComRefs[thread]++; 1317 1318 if (inst->isLoad()) { 1319 statComLoads[thread]++; 1320 } 1321 } 1322 1323 if (inst->isMemBarrier()) { 1324 statComMembars[thread]++; 1325 } 1326} 1327 1328//////////////////////////////////////// 1329// // 1330// SMT COMMIT POLICY MAINTAINED HERE // 1331// // 1332//////////////////////////////////////// 1333template <class Impl> 1334int 1335DefaultCommit<Impl>::getCommittingThread() 1336{ 1337 if (numThreads > 1) { 1338 switch (commitPolicy) { 1339 1340 case Aggressive: 1341 //If Policy is Aggressive, commit will call 1342 //this function multiple times per 1343 //cycle 1344 return oldestReady(); 1345 1346 case RoundRobin: 1347 return roundRobin(); 1348 1349 case OldestReady: 1350 return oldestReady(); 1351 1352 default: 1353 return -1; 1354 } 1355 } else { 1356 assert(!activeThreads->empty()); 1357 int tid = activeThreads->front(); 1358 1359 if (commitStatus[tid] == Running || 1360 commitStatus[tid] == Idle || 1361 commitStatus[tid] == FetchTrapPending) { 1362 return tid; 1363 } else { 1364 return -1; 1365 } 1366 } 1367} 1368 1369template<class Impl> 1370int 1371DefaultCommit<Impl>::roundRobin() 1372{ 1373 std::list<unsigned>::iterator pri_iter = priority_list.begin(); 1374 std::list<unsigned>::iterator end = priority_list.end(); 1375 1376 while (pri_iter != end) { 1377 unsigned tid = *pri_iter; 1378 1379 if (commitStatus[tid] == Running || 1380 commitStatus[tid] == Idle || 1381 commitStatus[tid] == FetchTrapPending) { 1382 1383 if (rob->isHeadReady(tid)) { 1384 priority_list.erase(pri_iter); 1385 priority_list.push_back(tid); 1386 1387 return tid; 1388 } 1389 } 1390 1391 pri_iter++; 1392 } 1393 1394 return -1; 1395} 1396 1397template<class Impl> 1398int 1399DefaultCommit<Impl>::oldestReady() 1400{ 1401 unsigned oldest = 0; 1402 bool first = true; 1403 1404 std::list<unsigned>::iterator threads = activeThreads->begin(); 1405 std::list<unsigned>::iterator end = activeThreads->end(); 1406 1407 while (threads != end) { 1408 unsigned tid = *threads++; 1409 1410 if (!rob->isEmpty(tid) && 1411 (commitStatus[tid] == Running || 1412 commitStatus[tid] == Idle || 1413 commitStatus[tid] == FetchTrapPending)) { 1414 1415 if (rob->isHeadReady(tid)) { 1416 1417 DynInstPtr head_inst = rob->readHeadInst(tid); 1418 1419 if (first) { 1420 oldest = tid; 1421 first = false; 1422 } else if (head_inst->seqNum < oldest) { 1423 oldest = tid; 1424 } 1425 } 1426 } 1427 } 1428 1429 if (!first) { 1430 return oldest; 1431 } else { 1432 return -1; 1433 } 1434} 1435