commit_impl.hh revision 3221
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292965Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322733Sktlim@umich.edu#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 342733Sktlim@umich.edu 352292SN/A#include <algorithm> 362329SN/A#include <string> 372292SN/A 382292SN/A#include "base/loader/symtab.hh" 391060SN/A#include "base/timebuf.hh" 402292SN/A#include "cpu/exetrace.hh" 411717SN/A#include "cpu/o3/commit.hh" 422292SN/A#include "cpu/o3/thread_state.hh" 432292SN/A 442790Sktlim@umich.edu#if USE_CHECKER 452790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 462790Sktlim@umich.edu#endif 472790Sktlim@umich.edu 481061SN/Atemplate <class Impl> 492292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 502292SN/A unsigned _tid) 512292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 521060SN/A{ 532292SN/A this->setFlags(Event::AutoDelete); 541060SN/A} 551060SN/A 561061SN/Atemplate <class Impl> 571060SN/Avoid 582292SN/ADefaultCommit<Impl>::TrapEvent::process() 591062SN/A{ 602316SN/A // This will get reset by commit if it was switched out at the 612316SN/A // time of this event processing. 622292SN/A commit->trapSquash[tid] = true; 632292SN/A} 642292SN/A 652292SN/Atemplate <class Impl> 662292SN/Aconst char * 672292SN/ADefaultCommit<Impl>::TrapEvent::description() 682292SN/A{ 692292SN/A return "Trap event"; 702292SN/A} 712292SN/A 722292SN/Atemplate <class Impl> 732292SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 742669Sktlim@umich.edu : squashCounter(0), 752292SN/A iewToCommitDelay(params->iewToCommitDelay), 762292SN/A commitToIEWDelay(params->commitToIEWDelay), 772292SN/A renameToROBDelay(params->renameToROBDelay), 782292SN/A fetchToCommitDelay(params->commitToFetchDelay), 792292SN/A renameWidth(params->renameWidth), 802292SN/A commitWidth(params->commitWidth), 812307SN/A numThreads(params->numberOfThreads), 822843Sktlim@umich.edu drainPending(false), 832316SN/A switchedOut(false), 842874Sktlim@umich.edu trapLatency(params->trapLatency) 852292SN/A{ 862292SN/A _status = Active; 872292SN/A _nextStatus = Inactive; 882980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 892292SN/A 902292SN/A //Convert string to lowercase 912292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 922292SN/A (int(*)(int)) tolower); 932292SN/A 942292SN/A //Assign commit policy 952292SN/A if (policy == "aggressive"){ 962292SN/A commitPolicy = Aggressive; 972292SN/A 982292SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 992292SN/A } else if (policy == "roundrobin"){ 1002292SN/A commitPolicy = RoundRobin; 1012292SN/A 1022292SN/A //Set-Up Priority List 1032292SN/A for (int tid=0; tid < numThreads; tid++) { 1042292SN/A priority_list.push_back(tid); 1052292SN/A } 1062292SN/A 1072292SN/A DPRINTF(Commit,"Commit Policy set to Round Robin."); 1082292SN/A } else if (policy == "oldestready"){ 1092292SN/A commitPolicy = OldestReady; 1102292SN/A 1112292SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1122292SN/A } else { 1132292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1142292SN/A "RoundRobin,OldestReady}"); 1152292SN/A } 1162292SN/A 1172292SN/A for (int i=0; i < numThreads; i++) { 1182292SN/A commitStatus[i] = Idle; 1192292SN/A changedROBNumEntries[i] = false; 1202292SN/A trapSquash[i] = false; 1212680Sktlim@umich.edu tcSquash[i] = false; 1222935Sksewell@umich.edu PC[i] = nextPC[i] = nextNPC[i] = 0; 1232292SN/A } 1242292SN/A} 1252292SN/A 1262292SN/Atemplate <class Impl> 1272292SN/Astd::string 1282292SN/ADefaultCommit<Impl>::name() const 1292292SN/A{ 1302292SN/A return cpu->name() + ".commit"; 1312292SN/A} 1322292SN/A 1332292SN/Atemplate <class Impl> 1342292SN/Avoid 1352292SN/ADefaultCommit<Impl>::regStats() 1362132SN/A{ 1372301SN/A using namespace Stats; 1381062SN/A commitCommittedInsts 1391062SN/A .name(name() + ".commitCommittedInsts") 1401062SN/A .desc("The number of committed instructions") 1411062SN/A .prereq(commitCommittedInsts); 1421062SN/A commitSquashedInsts 1431062SN/A .name(name() + ".commitSquashedInsts") 1441062SN/A .desc("The number of squashed insts skipped by commit") 1451062SN/A .prereq(commitSquashedInsts); 1461062SN/A commitSquashEvents 1471062SN/A .name(name() + ".commitSquashEvents") 1481062SN/A .desc("The number of times commit is told to squash") 1491062SN/A .prereq(commitSquashEvents); 1501062SN/A commitNonSpecStalls 1511062SN/A .name(name() + ".commitNonSpecStalls") 1521062SN/A .desc("The number of times commit has been forced to stall to " 1531062SN/A "communicate backwards") 1541062SN/A .prereq(commitNonSpecStalls); 1551062SN/A branchMispredicts 1561062SN/A .name(name() + ".branchMispredicts") 1571062SN/A .desc("The number of times a branch was mispredicted") 1581062SN/A .prereq(branchMispredicts); 1592292SN/A numCommittedDist 1601062SN/A .init(0,commitWidth,1) 1611062SN/A .name(name() + ".COM:committed_per_cycle") 1621062SN/A .desc("Number of insts commited each cycle") 1631062SN/A .flags(Stats::pdf) 1641062SN/A ; 1652301SN/A 1662316SN/A statComInst 1672301SN/A .init(cpu->number_of_threads) 1682301SN/A .name(name() + ".COM:count") 1692301SN/A .desc("Number of instructions committed") 1702301SN/A .flags(total) 1712301SN/A ; 1722301SN/A 1732316SN/A statComSwp 1742301SN/A .init(cpu->number_of_threads) 1752301SN/A .name(name() + ".COM:swp_count") 1762301SN/A .desc("Number of s/w prefetches committed") 1772301SN/A .flags(total) 1782301SN/A ; 1792301SN/A 1802316SN/A statComRefs 1812301SN/A .init(cpu->number_of_threads) 1822301SN/A .name(name() + ".COM:refs") 1832301SN/A .desc("Number of memory references committed") 1842301SN/A .flags(total) 1852301SN/A ; 1862301SN/A 1872316SN/A statComLoads 1882301SN/A .init(cpu->number_of_threads) 1892301SN/A .name(name() + ".COM:loads") 1902301SN/A .desc("Number of loads committed") 1912301SN/A .flags(total) 1922301SN/A ; 1932301SN/A 1942316SN/A statComMembars 1952301SN/A .init(cpu->number_of_threads) 1962301SN/A .name(name() + ".COM:membars") 1972301SN/A .desc("Number of memory barriers committed") 1982301SN/A .flags(total) 1992301SN/A ; 2002301SN/A 2012316SN/A statComBranches 2022301SN/A .init(cpu->number_of_threads) 2032301SN/A .name(name() + ".COM:branches") 2042301SN/A .desc("Number of branches committed") 2052301SN/A .flags(total) 2062301SN/A ; 2072301SN/A 2082316SN/A commitEligible 2092301SN/A .init(cpu->number_of_threads) 2102301SN/A .name(name() + ".COM:bw_limited") 2112301SN/A .desc("number of insts not committed due to BW limits") 2122301SN/A .flags(total) 2132301SN/A ; 2142301SN/A 2152316SN/A commitEligibleSamples 2162301SN/A .name(name() + ".COM:bw_lim_events") 2172301SN/A .desc("number cycles where commit BW limit reached") 2182301SN/A ; 2191062SN/A} 2201062SN/A 2211062SN/Atemplate <class Impl> 2221062SN/Avoid 2232733Sktlim@umich.eduDefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 2241060SN/A{ 2251060SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2261060SN/A cpu = cpu_ptr; 2272292SN/A 2282292SN/A // Commit must broadcast the number of free entries it has at the start of 2292292SN/A // the simulation, so it starts as active. 2302733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 2312307SN/A 2322316SN/A trapLatency = cpu->cycles(trapLatency); 2331060SN/A} 2341060SN/A 2351061SN/Atemplate <class Impl> 2361060SN/Avoid 2372980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2382292SN/A{ 2392292SN/A thread = threads; 2402292SN/A} 2412292SN/A 2422292SN/Atemplate <class Impl> 2432292SN/Avoid 2442292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2451060SN/A{ 2461060SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2471060SN/A timeBuffer = tb_ptr; 2481060SN/A 2491060SN/A // Setup wire to send information back to IEW. 2501060SN/A toIEW = timeBuffer->getWire(0); 2511060SN/A 2521060SN/A // Setup wire to read data from IEW (for the ROB). 2531060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2541060SN/A} 2551060SN/A 2561061SN/Atemplate <class Impl> 2571060SN/Avoid 2582292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2592292SN/A{ 2602292SN/A DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2612292SN/A fetchQueue = fq_ptr; 2622292SN/A 2632292SN/A // Setup wire to get instructions from rename (for the ROB). 2642292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2652292SN/A} 2662292SN/A 2672292SN/Atemplate <class Impl> 2682292SN/Avoid 2692292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2701060SN/A{ 2711060SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2721060SN/A renameQueue = rq_ptr; 2731060SN/A 2741060SN/A // Setup wire to get instructions from rename (for the ROB). 2751060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2761060SN/A} 2771060SN/A 2781061SN/Atemplate <class Impl> 2791060SN/Avoid 2802292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2811060SN/A{ 2821060SN/A DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2831060SN/A iewQueue = iq_ptr; 2841060SN/A 2851060SN/A // Setup wire to get instructions from IEW. 2861060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2871060SN/A} 2881060SN/A 2891061SN/Atemplate <class Impl> 2901060SN/Avoid 2912292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2922292SN/A{ 2932292SN/A iewStage = iew_stage; 2942292SN/A} 2952292SN/A 2962292SN/Atemplate<class Impl> 2972292SN/Avoid 2982980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2992292SN/A{ 3002292SN/A DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3012292SN/A activeThreads = at_ptr; 3022292SN/A} 3032292SN/A 3042292SN/Atemplate <class Impl> 3052292SN/Avoid 3062292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3072292SN/A{ 3082292SN/A DPRINTF(Commit, "Setting rename map pointers.\n"); 3092292SN/A 3102292SN/A for (int i=0; i < numThreads; i++) { 3112292SN/A renameMap[i] = &rm_ptr[i]; 3122292SN/A } 3132292SN/A} 3142292SN/A 3152292SN/Atemplate <class Impl> 3162292SN/Avoid 3172292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3181060SN/A{ 3191060SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3201060SN/A rob = rob_ptr; 3211060SN/A} 3221060SN/A 3231061SN/Atemplate <class Impl> 3241060SN/Avoid 3252292SN/ADefaultCommit<Impl>::initStage() 3261060SN/A{ 3272292SN/A rob->setActiveThreads(activeThreads); 3282292SN/A rob->resetEntries(); 3291060SN/A 3302292SN/A // Broadcast the number of free entries. 3312292SN/A for (int i=0; i < numThreads; i++) { 3322292SN/A toIEW->commitInfo[i].usedROB = true; 3332292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3341060SN/A } 3351060SN/A 3362292SN/A cpu->activityThisCycle(); 3371060SN/A} 3381060SN/A 3391061SN/Atemplate <class Impl> 3402863Sktlim@umich.edubool 3412843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3421060SN/A{ 3432843Sktlim@umich.edu drainPending = true; 3442863Sktlim@umich.edu 3452863Sktlim@umich.edu return false; 3462316SN/A} 3472316SN/A 3482316SN/Atemplate <class Impl> 3492316SN/Avoid 3502843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3512316SN/A{ 3522316SN/A switchedOut = true; 3532843Sktlim@umich.edu drainPending = false; 3542307SN/A rob->switchOut(); 3552307SN/A} 3562307SN/A 3572307SN/Atemplate <class Impl> 3582307SN/Avoid 3592843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3602843Sktlim@umich.edu{ 3612864Sktlim@umich.edu drainPending = false; 3622843Sktlim@umich.edu} 3632843Sktlim@umich.edu 3642843Sktlim@umich.edutemplate <class Impl> 3652843Sktlim@umich.eduvoid 3662307SN/ADefaultCommit<Impl>::takeOverFrom() 3672307SN/A{ 3682316SN/A switchedOut = false; 3692307SN/A _status = Active; 3702307SN/A _nextStatus = Inactive; 3712307SN/A for (int i=0; i < numThreads; i++) { 3722307SN/A commitStatus[i] = Idle; 3732307SN/A changedROBNumEntries[i] = false; 3742307SN/A trapSquash[i] = false; 3752680Sktlim@umich.edu tcSquash[i] = false; 3762307SN/A } 3772307SN/A squashCounter = 0; 3782307SN/A rob->takeOverFrom(); 3792307SN/A} 3802307SN/A 3812307SN/Atemplate <class Impl> 3822307SN/Avoid 3832292SN/ADefaultCommit<Impl>::updateStatus() 3842132SN/A{ 3852316SN/A // reset ROB changed variable 3862980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 3872316SN/A while (threads != (*activeThreads).end()) { 3882316SN/A unsigned tid = *threads++; 3892316SN/A changedROBNumEntries[tid] = false; 3902316SN/A 3912316SN/A // Also check if any of the threads has a trap pending 3922316SN/A if (commitStatus[tid] == TrapPending || 3932316SN/A commitStatus[tid] == FetchTrapPending) { 3942316SN/A _nextStatus = Active; 3952316SN/A } 3962292SN/A } 3972292SN/A 3982292SN/A if (_nextStatus == Inactive && _status == Active) { 3992292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4002733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4012292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4022292SN/A DPRINTF(Activity, "Activating stage.\n"); 4032733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4042292SN/A } 4052292SN/A 4062292SN/A _status = _nextStatus; 4072292SN/A} 4082292SN/A 4092292SN/Atemplate <class Impl> 4102292SN/Avoid 4112292SN/ADefaultCommit<Impl>::setNextStatus() 4122292SN/A{ 4132292SN/A int squashes = 0; 4142292SN/A 4152980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4162292SN/A 4172292SN/A while (threads != (*activeThreads).end()) { 4182292SN/A unsigned tid = *threads++; 4192292SN/A 4202292SN/A if (commitStatus[tid] == ROBSquashing) { 4212292SN/A squashes++; 4222292SN/A } 4232292SN/A } 4242292SN/A 4252702Sktlim@umich.edu squashCounter = squashes; 4262292SN/A 4272292SN/A // If commit is currently squashing, then it will have activity for the 4282292SN/A // next cycle. Set its next status as active. 4292292SN/A if (squashCounter) { 4302292SN/A _nextStatus = Active; 4312292SN/A } 4322292SN/A} 4332292SN/A 4342292SN/Atemplate <class Impl> 4352292SN/Abool 4362292SN/ADefaultCommit<Impl>::changedROBEntries() 4372292SN/A{ 4382980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4392292SN/A 4402292SN/A while (threads != (*activeThreads).end()) { 4412292SN/A unsigned tid = *threads++; 4422292SN/A 4432292SN/A if (changedROBNumEntries[tid]) { 4442292SN/A return true; 4452292SN/A } 4462292SN/A } 4472292SN/A 4482292SN/A return false; 4492292SN/A} 4502292SN/A 4512292SN/Atemplate <class Impl> 4522292SN/Aunsigned 4532292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4542292SN/A{ 4552292SN/A return rob->numFreeEntries(tid); 4562292SN/A} 4572292SN/A 4582292SN/Atemplate <class Impl> 4592292SN/Avoid 4602292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4612292SN/A{ 4622292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4632292SN/A 4642292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4652292SN/A 4662292SN/A trap->schedule(curTick + trapLatency); 4672292SN/A 4682292SN/A thread[tid]->trapPending = true; 4692292SN/A} 4702292SN/A 4712292SN/Atemplate <class Impl> 4722292SN/Avoid 4732680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4742292SN/A{ 4752680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4762292SN/A 4772680Sktlim@umich.edu tcSquash[tid] = true; 4782292SN/A} 4792292SN/A 4802292SN/Atemplate <class Impl> 4812292SN/Avoid 4822316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4832292SN/A{ 4842292SN/A // If we want to include the squashing instruction in the squash, 4852292SN/A // then use one older sequence number. 4862292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4872292SN/A // all instructions of this thread. 4882292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 4892292SN/A 0 : rob->readHeadInst(tid)->seqNum - 1;; 4902292SN/A 4912292SN/A // All younger instructions will be squashed. Set the sequence 4922292SN/A // number as the youngest instruction in the ROB (0 in this case. 4932292SN/A // Hopefully nothing breaks.) 4942292SN/A youngestSeqNum[tid] = 0; 4952292SN/A 4962292SN/A rob->squash(squashed_inst, tid); 4972292SN/A changedROBNumEntries[tid] = true; 4982292SN/A 4992292SN/A // Send back the sequence number of the squashed instruction. 5002292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5012292SN/A 5022292SN/A // Send back the squash signal to tell stages that they should 5032292SN/A // squash. 5042292SN/A toIEW->commitInfo[tid].squash = true; 5052292SN/A 5062292SN/A // Send back the rob squashing signal so other stages know that 5072292SN/A // the ROB is in the process of squashing. 5082292SN/A toIEW->commitInfo[tid].robSquashing = true; 5092292SN/A 5102292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5112292SN/A 5122316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5132316SN/A} 5142292SN/A 5152316SN/Atemplate <class Impl> 5162316SN/Avoid 5172316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5182316SN/A{ 5192316SN/A squashAll(tid); 5202316SN/A 5212316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5222316SN/A 5232316SN/A thread[tid]->trapPending = false; 5242316SN/A thread[tid]->inSyscall = false; 5252316SN/A 5262316SN/A trapSquash[tid] = false; 5272316SN/A 5282316SN/A commitStatus[tid] = ROBSquashing; 5292316SN/A cpu->activityThisCycle(); 5302316SN/A} 5312316SN/A 5322316SN/Atemplate <class Impl> 5332316SN/Avoid 5342680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5352316SN/A{ 5362316SN/A squashAll(tid); 5372292SN/A 5382680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5392292SN/A 5402292SN/A thread[tid]->inSyscall = false; 5412292SN/A assert(!thread[tid]->trapPending); 5422316SN/A 5432292SN/A commitStatus[tid] = ROBSquashing; 5442292SN/A cpu->activityThisCycle(); 5452292SN/A 5462680Sktlim@umich.edu tcSquash[tid] = false; 5472292SN/A} 5482292SN/A 5492292SN/Atemplate <class Impl> 5502292SN/Avoid 5512292SN/ADefaultCommit<Impl>::tick() 5522292SN/A{ 5532292SN/A wroteToTimeBuffer = false; 5542292SN/A _nextStatus = Inactive; 5552292SN/A 5562843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5572843Sktlim@umich.edu cpu->signalDrained(); 5582843Sktlim@umich.edu drainPending = false; 5592316SN/A return; 5602316SN/A } 5612316SN/A 5622875Sksewell@umich.edu if ((*activeThreads).size() <= 0) 5632875Sksewell@umich.edu return; 5642875Sksewell@umich.edu 5652980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 5662292SN/A 5672316SN/A // Check if any of the threads are done squashing. Change the 5682316SN/A // status if they are done. 5692292SN/A while (threads != (*activeThreads).end()) { 5702292SN/A unsigned tid = *threads++; 5712292SN/A 5722292SN/A if (commitStatus[tid] == ROBSquashing) { 5732292SN/A 5742292SN/A if (rob->isDoneSquashing(tid)) { 5752292SN/A commitStatus[tid] = Running; 5762292SN/A } else { 5772292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5782877Sksewell@umich.edu " insts this cycle.\n", tid); 5792702Sktlim@umich.edu rob->doSquash(tid); 5802702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5812702Sktlim@umich.edu wroteToTimeBuffer = true; 5822292SN/A } 5832292SN/A } 5842292SN/A } 5852292SN/A 5862292SN/A commit(); 5872292SN/A 5882292SN/A markCompletedInsts(); 5892292SN/A 5902292SN/A threads = (*activeThreads).begin(); 5912292SN/A 5922292SN/A while (threads != (*activeThreads).end()) { 5932292SN/A unsigned tid = *threads++; 5942292SN/A 5952292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 5962292SN/A // The ROB has more instructions it can commit. Its next status 5972292SN/A // will be active. 5982292SN/A _nextStatus = Active; 5992292SN/A 6002292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6012292SN/A 6022292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6032292SN/A " ROB and ready to commit\n", 6042292SN/A tid, inst->seqNum, inst->readPC()); 6052292SN/A 6062292SN/A } else if (!rob->isEmpty(tid)) { 6072292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6082292SN/A 6092292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6102292SN/A "%#x is head of ROB and not ready\n", 6112292SN/A tid, inst->seqNum, inst->readPC()); 6122292SN/A } 6132292SN/A 6142292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6152292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6162292SN/A } 6172292SN/A 6182292SN/A 6192292SN/A if (wroteToTimeBuffer) { 6202316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6212292SN/A cpu->activityThisCycle(); 6222292SN/A } 6232292SN/A 6242292SN/A updateStatus(); 6252292SN/A} 6262292SN/A 6272292SN/Atemplate <class Impl> 6282292SN/Avoid 6292292SN/ADefaultCommit<Impl>::commit() 6302292SN/A{ 6312292SN/A 6321060SN/A ////////////////////////////////////// 6331060SN/A // Check for interrupts 6341060SN/A ////////////////////////////////////// 6351060SN/A 6361858SN/A#if FULL_SYSTEM 6372316SN/A // Process interrupts if interrupts are enabled, not in PAL mode, 6382316SN/A // and no other traps or external squashes are currently pending. 6392316SN/A // @todo: Allow other threads to handle interrupts. 6402292SN/A if (cpu->checkInterrupts && 6411060SN/A cpu->check_interrupts() && 6422292SN/A !cpu->inPalMode(readPC()) && 6432292SN/A !trapSquash[0] && 6442680Sktlim@umich.edu !tcSquash[0]) { 6452316SN/A // Tell fetch that there is an interrupt pending. This will 6462316SN/A // make fetch wait until it sees a non PAL-mode PC, at which 6472316SN/A // point it stops fetching instructions. 6482292SN/A toIEW->commitInfo[0].interruptPending = true; 6491060SN/A 6502316SN/A // Wait until the ROB is empty and all stores have drained in 6512316SN/A // order to enter the interrupt. 6522292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6532292SN/A // Not sure which thread should be the one to interrupt. For now 6542292SN/A // always do thread 0. 6552292SN/A assert(!thread[0]->inSyscall); 6562292SN/A thread[0]->inSyscall = true; 6572292SN/A 6582292SN/A // CPU will handle implementation of the interrupt. 6592292SN/A cpu->processInterrupts(); 6602292SN/A 6612292SN/A // Now squash or record that I need to squash this cycle. 6622292SN/A commitStatus[0] = TrapPending; 6632292SN/A 6642292SN/A // Exit state update mode to avoid accidental updating. 6652292SN/A thread[0]->inSyscall = false; 6662292SN/A 6672292SN/A // Generate trap squash event. 6682292SN/A generateTrapEvent(0); 6692292SN/A 6702292SN/A toIEW->commitInfo[0].clearInterrupt = true; 6712292SN/A 6722292SN/A DPRINTF(Commit, "Interrupt detected.\n"); 6732292SN/A } else { 6742292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6752292SN/A } 6761060SN/A } 6771060SN/A#endif // FULL_SYSTEM 6781060SN/A 6791060SN/A //////////////////////////////////// 6802316SN/A // Check for any possible squashes, handle them first 6811060SN/A //////////////////////////////////// 6821060SN/A 6832980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 6841060SN/A 6852292SN/A while (threads != (*activeThreads).end()) { 6862292SN/A unsigned tid = *threads++; 6871060SN/A 6882292SN/A // Not sure which one takes priority. I think if we have 6892292SN/A // both, that's a bad sign. 6902292SN/A if (trapSquash[tid] == true) { 6912680Sktlim@umich.edu assert(!tcSquash[tid]); 6922292SN/A squashFromTrap(tid); 6932680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 6942680Sktlim@umich.edu squashFromTC(tid); 6952292SN/A } 6961061SN/A 6972292SN/A // Squashed sequence number must be older than youngest valid 6982292SN/A // instruction in the ROB. This prevents squashes from younger 6992292SN/A // instructions overriding squashes from older instructions. 7002292SN/A if (fromIEW->squash[tid] && 7012292SN/A commitStatus[tid] != TrapPending && 7022292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7031061SN/A 7042292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7052292SN/A tid, 7062292SN/A fromIEW->mispredPC[tid], 7072292SN/A fromIEW->squashedSeqNum[tid]); 7081061SN/A 7092292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7102292SN/A tid, 7112292SN/A fromIEW->nextPC[tid]); 7121061SN/A 7132292SN/A commitStatus[tid] = ROBSquashing; 7141061SN/A 7152292SN/A // If we want to include the squashing instruction in the squash, 7162292SN/A // then use one older sequence number. 7172292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7181062SN/A 7193093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7202935Sksewell@umich.edu InstSeqNum bdelay_done_seq_num; 7212935Sksewell@umich.edu bool squash_bdelay_slot; 7222935Sksewell@umich.edu 7232935Sksewell@umich.edu if (fromIEW->branchMispredict[tid]) { 7242935Sksewell@umich.edu if (fromIEW->branchTaken[tid] && 7252935Sksewell@umich.edu fromIEW->condDelaySlotBranch[tid]) { 7262935Sksewell@umich.edu DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch" 7272935Sksewell@umich.edu "mispredicted as taken. Squashing after previous " 7282935Sksewell@umich.edu "inst, [sn:%i]\n", 7292935Sksewell@umich.edu tid, squashed_inst); 7302935Sksewell@umich.edu bdelay_done_seq_num = squashed_inst; 7312935Sksewell@umich.edu squash_bdelay_slot = true; 7322935Sksewell@umich.edu } else { 7332935Sksewell@umich.edu DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing " 7342935Sksewell@umich.edu "after delay slot [sn:%i]\n", tid, squashed_inst+1); 7352935Sksewell@umich.edu bdelay_done_seq_num = squashed_inst + 1; 7362935Sksewell@umich.edu squash_bdelay_slot = false; 7372935Sksewell@umich.edu } 7382935Sksewell@umich.edu } else { 7392935Sksewell@umich.edu bdelay_done_seq_num = squashed_inst; 7402935Sksewell@umich.edu } 7412935Sksewell@umich.edu#endif 7422935Sksewell@umich.edu 7432935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 7442292SN/A squashed_inst--; 7453093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7462935Sksewell@umich.edu bdelay_done_seq_num--; 7472935Sksewell@umich.edu#endif 7482935Sksewell@umich.edu } 7492292SN/A // All younger instructions will be squashed. Set the sequence 7502292SN/A // number as the youngest instruction in the ROB. 7512292SN/A youngestSeqNum[tid] = squashed_inst; 7522292SN/A 7533093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7542935Sksewell@umich.edu rob->squash(bdelay_done_seq_num, tid); 7552935Sksewell@umich.edu toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 7562935Sksewell@umich.edu toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 7573093Sksewell@umich.edu#else 7583093Sksewell@umich.edu rob->squash(squashed_inst, tid); 7593093Sksewell@umich.edu toIEW->commitInfo[tid].squashDelaySlot = true; 7602935Sksewell@umich.edu#endif 7612292SN/A changedROBNumEntries[tid] = true; 7622292SN/A 7632292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7642292SN/A 7652292SN/A toIEW->commitInfo[tid].squash = true; 7662292SN/A 7672292SN/A // Send back the rob squashing signal so other stages know that 7682292SN/A // the ROB is in the process of squashing. 7692292SN/A toIEW->commitInfo[tid].robSquashing = true; 7702292SN/A 7712292SN/A toIEW->commitInfo[tid].branchMispredict = 7722292SN/A fromIEW->branchMispredict[tid]; 7732292SN/A 7742292SN/A toIEW->commitInfo[tid].branchTaken = 7752292SN/A fromIEW->branchTaken[tid]; 7762292SN/A 7772292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7782292SN/A 7792316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7802292SN/A 7812292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7822292SN/A ++branchMispredicts; 7832292SN/A } 7841062SN/A } 7852292SN/A 7861060SN/A } 7871060SN/A 7882292SN/A setNextStatus(); 7892292SN/A 7902292SN/A if (squashCounter != numThreads) { 7911061SN/A // If we're not currently squashing, then get instructions. 7921060SN/A getInsts(); 7931060SN/A 7941061SN/A // Try to commit any instructions. 7951060SN/A commitInsts(); 7962965Sksewell@umich.edu } else { 7973093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7982965Sksewell@umich.edu skidInsert(); 7992965Sksewell@umich.edu#endif 8001060SN/A } 8011060SN/A 8022292SN/A //Check for any activity 8032292SN/A threads = (*activeThreads).begin(); 8042292SN/A 8052292SN/A while (threads != (*activeThreads).end()) { 8062292SN/A unsigned tid = *threads++; 8072292SN/A 8082292SN/A if (changedROBNumEntries[tid]) { 8092292SN/A toIEW->commitInfo[tid].usedROB = true; 8102292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8112292SN/A 8122292SN/A if (rob->isEmpty(tid)) { 8132292SN/A toIEW->commitInfo[tid].emptyROB = true; 8142292SN/A } 8152292SN/A 8162292SN/A wroteToTimeBuffer = true; 8172292SN/A changedROBNumEntries[tid] = false; 8182292SN/A } 8191060SN/A } 8201060SN/A} 8211060SN/A 8221061SN/Atemplate <class Impl> 8231060SN/Avoid 8242292SN/ADefaultCommit<Impl>::commitInsts() 8251060SN/A{ 8261060SN/A //////////////////////////////////// 8271060SN/A // Handle commit 8282316SN/A // Note that commit will be handled prior to putting new 8292316SN/A // instructions in the ROB so that the ROB only tries to commit 8302316SN/A // instructions it has in this current cycle, and not instructions 8312316SN/A // it is writing in during this cycle. Can't commit and squash 8322316SN/A // things at the same time... 8331060SN/A //////////////////////////////////// 8341060SN/A 8352292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8361060SN/A 8371060SN/A unsigned num_committed = 0; 8381060SN/A 8392292SN/A DynInstPtr head_inst; 8402316SN/A 8411060SN/A // Commit as many instructions as possible until the commit bandwidth 8421060SN/A // limit is reached, or it becomes impossible to commit any more. 8432292SN/A while (num_committed < commitWidth) { 8442292SN/A int commit_thread = getCommittingThread(); 8451060SN/A 8462292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8472292SN/A break; 8482292SN/A 8492292SN/A head_inst = rob->readHeadInst(commit_thread); 8502292SN/A 8512292SN/A int tid = head_inst->threadNumber; 8522292SN/A 8532292SN/A assert(tid == commit_thread); 8542292SN/A 8552292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8562292SN/A head_inst->seqNum, tid); 8572132SN/A 8582316SN/A // If the head instruction is squashed, it is ready to retire 8592316SN/A // (be removed from the ROB) at any time. 8601060SN/A if (head_inst->isSquashed()) { 8611060SN/A 8622292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8631060SN/A "ROB.\n"); 8641060SN/A 8652292SN/A rob->retireHead(commit_thread); 8661060SN/A 8671062SN/A ++commitSquashedInsts; 8681062SN/A 8692292SN/A // Record that the number of ROB entries has changed. 8702292SN/A changedROBNumEntries[tid] = true; 8711060SN/A } else { 8722292SN/A PC[tid] = head_inst->readPC(); 8732292SN/A nextPC[tid] = head_inst->readNextPC(); 8742935Sksewell@umich.edu nextNPC[tid] = head_inst->readNextNPC(); 8752292SN/A 8761060SN/A // Increment the total number of non-speculative instructions 8771060SN/A // executed. 8781060SN/A // Hack for now: it really shouldn't happen until after the 8791061SN/A // commit is deemed to be successful, but this count is needed 8801061SN/A // for syscalls. 8812292SN/A thread[tid]->funcExeInst++; 8821060SN/A 8831060SN/A // Try to commit the head instruction. 8841060SN/A bool commit_success = commitHead(head_inst, num_committed); 8851060SN/A 8861062SN/A if (commit_success) { 8871060SN/A ++num_committed; 8881060SN/A 8892292SN/A changedROBNumEntries[tid] = true; 8902292SN/A 8912292SN/A // Set the doneSeqNum to the youngest committed instruction. 8922292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 8931060SN/A 8941062SN/A ++commitCommittedInsts; 8951062SN/A 8962292SN/A // To match the old model, don't count nops and instruction 8972292SN/A // prefetches towards the total commit count. 8982292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 8992292SN/A cpu->instDone(tid); 9001062SN/A } 9012292SN/A 9022292SN/A PC[tid] = nextPC[tid]; 9033093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 9042935Sksewell@umich.edu nextPC[tid] = nextNPC[tid]; 9052935Sksewell@umich.edu nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 9063093Sksewell@umich.edu#else 9073093Sksewell@umich.edu nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 9082935Sksewell@umich.edu#endif 9092935Sksewell@umich.edu 9102292SN/A#if FULL_SYSTEM 9112292SN/A int count = 0; 9122292SN/A Addr oldpc; 9132292SN/A do { 9142316SN/A // Debug statement. Checks to make sure we're not 9152316SN/A // currently updating state while handling PC events. 9162292SN/A if (count == 0) 9172316SN/A assert(!thread[tid]->inSyscall && 9182316SN/A !thread[tid]->trapPending); 9192292SN/A oldpc = PC[tid]; 9202292SN/A cpu->system->pcEventQueue.service( 9212690Sktlim@umich.edu thread[tid]->getTC()); 9222292SN/A count++; 9232292SN/A } while (oldpc != PC[tid]); 9242292SN/A if (count > 1) { 9252292SN/A DPRINTF(Commit, "PC skip function event, stopping commit\n"); 9262292SN/A break; 9272292SN/A } 9282292SN/A#endif 9291060SN/A } else { 9302292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9312292SN/A "[tid:%i] [sn:%i].\n", 9322292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9331060SN/A break; 9341060SN/A } 9351060SN/A } 9361060SN/A } 9371062SN/A 9381063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9392292SN/A numCommittedDist.sample(num_committed); 9402307SN/A 9412307SN/A if (num_committed == commitWidth) { 9422349SN/A commitEligibleSamples++; 9432307SN/A } 9441060SN/A} 9451060SN/A 9461061SN/Atemplate <class Impl> 9471060SN/Abool 9482292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9491060SN/A{ 9501060SN/A assert(head_inst); 9511060SN/A 9522292SN/A int tid = head_inst->threadNumber; 9532292SN/A 9542316SN/A // If the instruction is not executed yet, then it will need extra 9552316SN/A // handling. Signal backwards that it should be executed. 9561061SN/A if (!head_inst->isExecuted()) { 9571061SN/A // Keep this number correct. We have not yet actually executed 9581061SN/A // and committed this instruction. 9592292SN/A thread[tid]->funcExeInst--; 9601062SN/A 9612731Sktlim@umich.edu head_inst->setAtCommit(); 9621060SN/A 9632292SN/A if (head_inst->isNonSpeculative() || 9642348SN/A head_inst->isStoreConditional() || 9652292SN/A head_inst->isMemBarrier() || 9662292SN/A head_inst->isWriteBarrier()) { 9672316SN/A 9682316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9692316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9702316SN/A head_inst->seqNum, head_inst->readPC()); 9712316SN/A 9722292SN/A#if !FULL_SYSTEM 9732316SN/A // Hack to make sure syscalls/memory barriers/quiesces 9742316SN/A // aren't executed until all stores write back their data. 9752316SN/A // This direct communication shouldn't be used for 9762316SN/A // anything other than this. 9772292SN/A if (inst_num > 0 || iewStage->hasStoresToWB()) 9782292SN/A#else 9792292SN/A if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 9802292SN/A head_inst->isQuiesce()) && 9812292SN/A iewStage->hasStoresToWB()) 9822292SN/A#endif 9832292SN/A { 9842292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9852292SN/A return false; 9862292SN/A } 9872292SN/A 9882292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9891061SN/A 9901061SN/A // Change the instruction so it won't try to commit again until 9911061SN/A // it is executed. 9921061SN/A head_inst->clearCanCommit(); 9931061SN/A 9941062SN/A ++commitNonSpecStalls; 9951062SN/A 9961061SN/A return false; 9972292SN/A } else if (head_inst->isLoad()) { 9982292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9992292SN/A head_inst->seqNum, head_inst->readPC()); 10002292SN/A 10012292SN/A // Send back the non-speculative instruction's sequence 10022316SN/A // number. Tell the lsq to re-execute the load. 10032292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10042292SN/A toIEW->commitInfo[tid].uncached = true; 10052292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10062292SN/A 10072292SN/A head_inst->clearCanCommit(); 10082292SN/A 10092292SN/A return false; 10101061SN/A } else { 10112292SN/A panic("Trying to commit un-executed instruction " 10121061SN/A "of unknown type!\n"); 10131061SN/A } 10141060SN/A } 10151060SN/A 10162316SN/A if (head_inst->isThreadSync()) { 10172292SN/A // Not handled for now. 10182316SN/A panic("Thread sync instructions are not handled yet.\n"); 10192132SN/A } 10202132SN/A 10212316SN/A // Stores mark themselves as completed. 10222310SN/A if (!head_inst->isStore()) { 10232310SN/A head_inst->setCompleted(); 10242310SN/A } 10252310SN/A 10262733Sktlim@umich.edu#if USE_CHECKER 10272316SN/A // Use checker prior to updating anything due to traps or PC 10282316SN/A // based events. 10292316SN/A if (cpu->checker) { 10302732Sktlim@umich.edu cpu->checker->verify(head_inst); 10311060SN/A } 10322733Sktlim@umich.edu#endif 10331060SN/A 10341060SN/A // Check if the instruction caused a fault. If so, trap. 10352132SN/A Fault inst_fault = head_inst->getFault(); 10361681SN/A 10372918Sktlim@umich.edu // DTB will sometimes need the machine instruction for when 10382918Sktlim@umich.edu // faults happen. So we will set it here, prior to the DTB 10392918Sktlim@umich.edu // possibly needing it for its fault. 10402918Sktlim@umich.edu thread[tid]->setInst( 10412918Sktlim@umich.edu static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10422918Sktlim@umich.edu 10432112SN/A if (inst_fault != NoFault) { 10442316SN/A head_inst->setCompleted(); 10452316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10462316SN/A head_inst->seqNum, head_inst->readPC()); 10472292SN/A 10482316SN/A if (iewStage->hasStoresToWB() || inst_num > 0) { 10492316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10502316SN/A return false; 10512316SN/A } 10522310SN/A 10532733Sktlim@umich.edu#if USE_CHECKER 10542316SN/A if (cpu->checker && head_inst->isStore()) { 10552732Sktlim@umich.edu cpu->checker->verify(head_inst); 10562316SN/A } 10572733Sktlim@umich.edu#endif 10582292SN/A 10592316SN/A assert(!thread[tid]->inSyscall); 10602292SN/A 10612316SN/A // Mark that we're in state update mode so that the trap's 10622316SN/A // execution doesn't generate extra squashes. 10632316SN/A thread[tid]->inSyscall = true; 10642292SN/A 10652316SN/A // Execute the trap. Although it's slightly unrealistic in 10662316SN/A // terms of timing (as it doesn't wait for the full timing of 10672316SN/A // the trap event to complete before updating state), it's 10682316SN/A // needed to update the state as soon as possible. This 10692316SN/A // prevents external agents from changing any specific state 10702316SN/A // that the trap need. 10712316SN/A cpu->trap(inst_fault, tid); 10722292SN/A 10732316SN/A // Exit state update mode to avoid accidental updating. 10742316SN/A thread[tid]->inSyscall = false; 10752292SN/A 10762316SN/A commitStatus[tid] = TrapPending; 10772292SN/A 10782316SN/A // Generate trap squash event. 10792316SN/A generateTrapEvent(tid); 10802353SN/A// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 10812316SN/A return false; 10821060SN/A } 10831060SN/A 10842301SN/A updateComInstStats(head_inst); 10852132SN/A 10862362SN/A#if FULL_SYSTEM 10872362SN/A if (thread[tid]->profile) { 10882362SN/A// bool usermode = 10892362SN/A// (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0; 10902362SN/A// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 10912362SN/A thread[tid]->profilePC = head_inst->readPC(); 10923126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 10932362SN/A head_inst->staticInst); 10942362SN/A 10952362SN/A if (node) 10962362SN/A thread[tid]->profileNode = node; 10972362SN/A } 10982362SN/A#endif 10992362SN/A 11002132SN/A if (head_inst->traceData) { 11012292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11022292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11032132SN/A head_inst->traceData->finalize(); 11042292SN/A head_inst->traceData = NULL; 11051060SN/A } 11061060SN/A 11072292SN/A // Update the commit rename map 11082292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11092292SN/A renameMap[tid]->setEntry(head_inst->destRegIdx(i), 11102292SN/A head_inst->renamedDestRegIdx(i)); 11111060SN/A } 11121062SN/A 11132353SN/A if (head_inst->isCopy()) 11142353SN/A panic("Should not commit any copy instructions!"); 11152353SN/A 11162292SN/A // Finally clear the head ROB entry. 11172292SN/A rob->retireHead(tid); 11181060SN/A 11191060SN/A // Return true to indicate that we have committed an instruction. 11201060SN/A return true; 11211060SN/A} 11221060SN/A 11231061SN/Atemplate <class Impl> 11241060SN/Avoid 11252292SN/ADefaultCommit<Impl>::getInsts() 11261060SN/A{ 11272935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 11282935Sksewell@umich.edu 11293093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 11302965Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11312980Sgblack@eecs.umich.edu int insts_to_process = std::min((int)renameWidth, 11322965Sksewell@umich.edu (int)(fromRename->size + skidBuffer.size())); 11332965Sksewell@umich.edu int rename_idx = 0; 11341061SN/A 11352965Sksewell@umich.edu DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 11362965Sksewell@umich.edu "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 11372965Sksewell@umich.edu skidBuffer.size()); 11383093Sksewell@umich.edu#else 11393093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11403093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 11412965Sksewell@umich.edu#endif 11422965Sksewell@umich.edu 11432965Sksewell@umich.edu 11442965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 11452965Sksewell@umich.edu DynInstPtr inst; 11462965Sksewell@umich.edu 11473093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 11482965Sksewell@umich.edu // Get insts from skidBuffer or from Rename 11492965Sksewell@umich.edu if (skidBuffer.size() > 0) { 11502965Sksewell@umich.edu DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 11512965Sksewell@umich.edu inst = skidBuffer.front(); 11522965Sksewell@umich.edu skidBuffer.pop(); 11532965Sksewell@umich.edu } else { 11542965Sksewell@umich.edu DPRINTF(Commit, "Grabbing rename inst.\n"); 11552965Sksewell@umich.edu inst = fromRename->insts[rename_idx++]; 11562965Sksewell@umich.edu } 11573093Sksewell@umich.edu#else 11583093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 11592965Sksewell@umich.edu#endif 11602292SN/A int tid = inst->threadNumber; 11612292SN/A 11622292SN/A if (!inst->isSquashed() && 11632292SN/A commitStatus[tid] != ROBSquashing) { 11642292SN/A changedROBNumEntries[tid] = true; 11652292SN/A 11662292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 11672292SN/A inst->readPC(), inst->seqNum, tid); 11682292SN/A 11692292SN/A rob->insertInst(inst); 11702292SN/A 11712292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 11722292SN/A 11732292SN/A youngestSeqNum[tid] = inst->seqNum; 11741061SN/A } else { 11752292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11761061SN/A "squashed, skipping.\n", 11772292SN/A inst->readPC(), inst->seqNum, tid); 11781061SN/A } 11791060SN/A } 11802965Sksewell@umich.edu 11813093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 11822965Sksewell@umich.edu if (rename_idx < fromRename->size) { 11832965Sksewell@umich.edu DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 11842965Sksewell@umich.edu 11852965Sksewell@umich.edu for (; 11862965Sksewell@umich.edu rename_idx < fromRename->size; 11872965Sksewell@umich.edu rename_idx++) { 11882965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[rename_idx]; 11892965Sksewell@umich.edu int tid = inst->threadNumber; 11902965Sksewell@umich.edu 11912965Sksewell@umich.edu if (!inst->isSquashed()) { 11922965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 11932965Sksewell@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, tid); 11942965Sksewell@umich.edu skidBuffer.push(inst); 11952965Sksewell@umich.edu } else { 11962965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11972965Sksewell@umich.edu "squashed, skipping.\n", 11982965Sksewell@umich.edu inst->readPC(), inst->seqNum, tid); 11992965Sksewell@umich.edu } 12002965Sksewell@umich.edu } 12012965Sksewell@umich.edu } 12022965Sksewell@umich.edu#endif 12032965Sksewell@umich.edu 12042965Sksewell@umich.edu} 12052965Sksewell@umich.edu 12062965Sksewell@umich.edutemplate <class Impl> 12072965Sksewell@umich.eduvoid 12082965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 12092965Sksewell@umich.edu{ 12102965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 12112965Sksewell@umich.edu "skidBuffer.\n"); 12122965Sksewell@umich.edu 12132965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 12142965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 12152965Sksewell@umich.edu 12162965Sksewell@umich.edu if (!inst->isSquashed()) { 12172965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 12183221Sktlim@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, 12193221Sktlim@umich.edu inst->threadNumber); 12202965Sksewell@umich.edu skidBuffer.push(inst); 12212965Sksewell@umich.edu } else { 12222965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 12232965Sksewell@umich.edu "squashed, skipping.\n", 12243221Sktlim@umich.edu inst->readPC(), inst->seqNum, inst->threadNumber); 12252965Sksewell@umich.edu } 12262965Sksewell@umich.edu } 12271060SN/A} 12281060SN/A 12291061SN/Atemplate <class Impl> 12301060SN/Avoid 12312292SN/ADefaultCommit<Impl>::markCompletedInsts() 12321060SN/A{ 12331060SN/A // Grab completed insts out of the IEW instruction queue, and mark 12341060SN/A // instructions completed within the ROB. 12351060SN/A for (int inst_num = 0; 12361681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 12371060SN/A ++inst_num) 12381060SN/A { 12392292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12402316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 12412316SN/A "within ROB.\n", 12422292SN/A fromIEW->insts[inst_num]->threadNumber, 12432292SN/A fromIEW->insts[inst_num]->readPC(), 12442292SN/A fromIEW->insts[inst_num]->seqNum); 12451060SN/A 12462292SN/A // Mark the instruction as ready to commit. 12472292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12482292SN/A } 12491060SN/A } 12501060SN/A} 12511060SN/A 12521061SN/Atemplate <class Impl> 12532292SN/Abool 12542292SN/ADefaultCommit<Impl>::robDoneSquashing() 12551060SN/A{ 12562980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 12572292SN/A 12582292SN/A while (threads != (*activeThreads).end()) { 12592292SN/A unsigned tid = *threads++; 12602292SN/A 12612292SN/A if (!rob->isDoneSquashing(tid)) 12622292SN/A return false; 12632292SN/A } 12642292SN/A 12652292SN/A return true; 12661060SN/A} 12672292SN/A 12682301SN/Atemplate <class Impl> 12692301SN/Avoid 12702301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 12712301SN/A{ 12722301SN/A unsigned thread = inst->threadNumber; 12732301SN/A 12742301SN/A // 12752301SN/A // Pick off the software prefetches 12762301SN/A // 12772301SN/A#ifdef TARGET_ALPHA 12782301SN/A if (inst->isDataPrefetch()) { 12792316SN/A statComSwp[thread]++; 12802301SN/A } else { 12812316SN/A statComInst[thread]++; 12822301SN/A } 12832301SN/A#else 12842316SN/A statComInst[thread]++; 12852301SN/A#endif 12862301SN/A 12872301SN/A // 12882301SN/A // Control Instructions 12892301SN/A // 12902301SN/A if (inst->isControl()) 12912316SN/A statComBranches[thread]++; 12922301SN/A 12932301SN/A // 12942301SN/A // Memory references 12952301SN/A // 12962301SN/A if (inst->isMemRef()) { 12972316SN/A statComRefs[thread]++; 12982301SN/A 12992301SN/A if (inst->isLoad()) { 13002316SN/A statComLoads[thread]++; 13012301SN/A } 13022301SN/A } 13032301SN/A 13042301SN/A if (inst->isMemBarrier()) { 13052316SN/A statComMembars[thread]++; 13062301SN/A } 13072301SN/A} 13082301SN/A 13092292SN/A//////////////////////////////////////// 13102292SN/A// // 13112316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 13122292SN/A// // 13132292SN/A//////////////////////////////////////// 13142292SN/Atemplate <class Impl> 13152292SN/Aint 13162292SN/ADefaultCommit<Impl>::getCommittingThread() 13172292SN/A{ 13182292SN/A if (numThreads > 1) { 13192292SN/A switch (commitPolicy) { 13202292SN/A 13212292SN/A case Aggressive: 13222292SN/A //If Policy is Aggressive, commit will call 13232292SN/A //this function multiple times per 13242292SN/A //cycle 13252292SN/A return oldestReady(); 13262292SN/A 13272292SN/A case RoundRobin: 13282292SN/A return roundRobin(); 13292292SN/A 13302292SN/A case OldestReady: 13312292SN/A return oldestReady(); 13322292SN/A 13332292SN/A default: 13342292SN/A return -1; 13352292SN/A } 13362292SN/A } else { 13372292SN/A int tid = (*activeThreads).front(); 13382292SN/A 13392292SN/A if (commitStatus[tid] == Running || 13402292SN/A commitStatus[tid] == Idle || 13412292SN/A commitStatus[tid] == FetchTrapPending) { 13422292SN/A return tid; 13432292SN/A } else { 13442292SN/A return -1; 13452292SN/A } 13462292SN/A } 13472292SN/A} 13482292SN/A 13492292SN/Atemplate<class Impl> 13502292SN/Aint 13512292SN/ADefaultCommit<Impl>::roundRobin() 13522292SN/A{ 13532980Sgblack@eecs.umich.edu std::list<unsigned>::iterator pri_iter = priority_list.begin(); 13542980Sgblack@eecs.umich.edu std::list<unsigned>::iterator end = priority_list.end(); 13552292SN/A 13562292SN/A while (pri_iter != end) { 13572292SN/A unsigned tid = *pri_iter; 13582292SN/A 13592292SN/A if (commitStatus[tid] == Running || 13602831Sksewell@umich.edu commitStatus[tid] == Idle || 13612831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 13622292SN/A 13632292SN/A if (rob->isHeadReady(tid)) { 13642292SN/A priority_list.erase(pri_iter); 13652292SN/A priority_list.push_back(tid); 13662292SN/A 13672292SN/A return tid; 13682292SN/A } 13692292SN/A } 13702292SN/A 13712292SN/A pri_iter++; 13722292SN/A } 13732292SN/A 13742292SN/A return -1; 13752292SN/A} 13762292SN/A 13772292SN/Atemplate<class Impl> 13782292SN/Aint 13792292SN/ADefaultCommit<Impl>::oldestReady() 13802292SN/A{ 13812292SN/A unsigned oldest = 0; 13822292SN/A bool first = true; 13832292SN/A 13842980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 13852292SN/A 13862292SN/A while (threads != (*activeThreads).end()) { 13872292SN/A unsigned tid = *threads++; 13882292SN/A 13892292SN/A if (!rob->isEmpty(tid) && 13902292SN/A (commitStatus[tid] == Running || 13912292SN/A commitStatus[tid] == Idle || 13922292SN/A commitStatus[tid] == FetchTrapPending)) { 13932292SN/A 13942292SN/A if (rob->isHeadReady(tid)) { 13952292SN/A 13962292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 13972292SN/A 13982292SN/A if (first) { 13992292SN/A oldest = tid; 14002292SN/A first = false; 14012292SN/A } else if (head_inst->seqNum < oldest) { 14022292SN/A oldest = tid; 14032292SN/A } 14042292SN/A } 14052292SN/A } 14062292SN/A } 14072292SN/A 14082292SN/A if (!first) { 14092292SN/A return oldest; 14102292SN/A } else { 14112292SN/A return -1; 14122292SN/A } 14132292SN/A} 1414