commit_impl.hh revision 2918
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312733Sktlim@umich.edu#include "config/full_system.hh" 322733Sktlim@umich.edu#include "config/use_checker.hh" 332733Sktlim@umich.edu 342292SN/A#include <algorithm> 352329SN/A#include <string> 362292SN/A 372292SN/A#include "base/loader/symtab.hh" 381060SN/A#include "base/timebuf.hh" 392292SN/A#include "cpu/exetrace.hh" 401717SN/A#include "cpu/o3/commit.hh" 412292SN/A#include "cpu/o3/thread_state.hh" 422292SN/A 432790Sktlim@umich.edu#if USE_CHECKER 442790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 452790Sktlim@umich.edu#endif 462790Sktlim@umich.edu 472292SN/Ausing namespace std; 481060SN/A 491061SN/Atemplate <class Impl> 502292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 512292SN/A unsigned _tid) 522292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 531060SN/A{ 542292SN/A this->setFlags(Event::AutoDelete); 551060SN/A} 561060SN/A 571061SN/Atemplate <class Impl> 581060SN/Avoid 592292SN/ADefaultCommit<Impl>::TrapEvent::process() 601062SN/A{ 612316SN/A // This will get reset by commit if it was switched out at the 622316SN/A // time of this event processing. 632292SN/A commit->trapSquash[tid] = true; 642292SN/A} 652292SN/A 662292SN/Atemplate <class Impl> 672292SN/Aconst char * 682292SN/ADefaultCommit<Impl>::TrapEvent::description() 692292SN/A{ 702292SN/A return "Trap event"; 712292SN/A} 722292SN/A 732292SN/Atemplate <class Impl> 742292SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 752669Sktlim@umich.edu : squashCounter(0), 762292SN/A iewToCommitDelay(params->iewToCommitDelay), 772292SN/A commitToIEWDelay(params->commitToIEWDelay), 782292SN/A renameToROBDelay(params->renameToROBDelay), 792292SN/A fetchToCommitDelay(params->commitToFetchDelay), 802292SN/A renameWidth(params->renameWidth), 812292SN/A commitWidth(params->commitWidth), 822307SN/A numThreads(params->numberOfThreads), 832843Sktlim@umich.edu drainPending(false), 842316SN/A switchedOut(false), 852874Sktlim@umich.edu trapLatency(params->trapLatency) 862292SN/A{ 872292SN/A _status = Active; 882292SN/A _nextStatus = Inactive; 892292SN/A string policy = params->smtCommitPolicy; 902292SN/A 912292SN/A //Convert string to lowercase 922292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 932292SN/A (int(*)(int)) tolower); 942292SN/A 952292SN/A //Assign commit policy 962292SN/A if (policy == "aggressive"){ 972292SN/A commitPolicy = Aggressive; 982292SN/A 992292SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 1002292SN/A } else if (policy == "roundrobin"){ 1012292SN/A commitPolicy = RoundRobin; 1022292SN/A 1032292SN/A //Set-Up Priority List 1042292SN/A for (int tid=0; tid < numThreads; tid++) { 1052292SN/A priority_list.push_back(tid); 1062292SN/A } 1072292SN/A 1082292SN/A DPRINTF(Commit,"Commit Policy set to Round Robin."); 1092292SN/A } else if (policy == "oldestready"){ 1102292SN/A commitPolicy = OldestReady; 1112292SN/A 1122292SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1132292SN/A } else { 1142292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1152292SN/A "RoundRobin,OldestReady}"); 1162292SN/A } 1172292SN/A 1182292SN/A for (int i=0; i < numThreads; i++) { 1192292SN/A commitStatus[i] = Idle; 1202292SN/A changedROBNumEntries[i] = false; 1212292SN/A trapSquash[i] = false; 1222680Sktlim@umich.edu tcSquash[i] = false; 1232678Sktlim@umich.edu PC[i] = nextPC[i] = 0; 1242292SN/A } 1252292SN/A} 1262292SN/A 1272292SN/Atemplate <class Impl> 1282292SN/Astd::string 1292292SN/ADefaultCommit<Impl>::name() const 1302292SN/A{ 1312292SN/A return cpu->name() + ".commit"; 1322292SN/A} 1332292SN/A 1342292SN/Atemplate <class Impl> 1352292SN/Avoid 1362292SN/ADefaultCommit<Impl>::regStats() 1372132SN/A{ 1382301SN/A using namespace Stats; 1391062SN/A commitCommittedInsts 1401062SN/A .name(name() + ".commitCommittedInsts") 1411062SN/A .desc("The number of committed instructions") 1421062SN/A .prereq(commitCommittedInsts); 1431062SN/A commitSquashedInsts 1441062SN/A .name(name() + ".commitSquashedInsts") 1451062SN/A .desc("The number of squashed insts skipped by commit") 1461062SN/A .prereq(commitSquashedInsts); 1471062SN/A commitSquashEvents 1481062SN/A .name(name() + ".commitSquashEvents") 1491062SN/A .desc("The number of times commit is told to squash") 1501062SN/A .prereq(commitSquashEvents); 1511062SN/A commitNonSpecStalls 1521062SN/A .name(name() + ".commitNonSpecStalls") 1531062SN/A .desc("The number of times commit has been forced to stall to " 1541062SN/A "communicate backwards") 1551062SN/A .prereq(commitNonSpecStalls); 1561062SN/A branchMispredicts 1571062SN/A .name(name() + ".branchMispredicts") 1581062SN/A .desc("The number of times a branch was mispredicted") 1591062SN/A .prereq(branchMispredicts); 1602292SN/A numCommittedDist 1611062SN/A .init(0,commitWidth,1) 1621062SN/A .name(name() + ".COM:committed_per_cycle") 1631062SN/A .desc("Number of insts commited each cycle") 1641062SN/A .flags(Stats::pdf) 1651062SN/A ; 1662301SN/A 1672316SN/A statComInst 1682301SN/A .init(cpu->number_of_threads) 1692301SN/A .name(name() + ".COM:count") 1702301SN/A .desc("Number of instructions committed") 1712301SN/A .flags(total) 1722301SN/A ; 1732301SN/A 1742316SN/A statComSwp 1752301SN/A .init(cpu->number_of_threads) 1762301SN/A .name(name() + ".COM:swp_count") 1772301SN/A .desc("Number of s/w prefetches committed") 1782301SN/A .flags(total) 1792301SN/A ; 1802301SN/A 1812316SN/A statComRefs 1822301SN/A .init(cpu->number_of_threads) 1832301SN/A .name(name() + ".COM:refs") 1842301SN/A .desc("Number of memory references committed") 1852301SN/A .flags(total) 1862301SN/A ; 1872301SN/A 1882316SN/A statComLoads 1892301SN/A .init(cpu->number_of_threads) 1902301SN/A .name(name() + ".COM:loads") 1912301SN/A .desc("Number of loads committed") 1922301SN/A .flags(total) 1932301SN/A ; 1942301SN/A 1952316SN/A statComMembars 1962301SN/A .init(cpu->number_of_threads) 1972301SN/A .name(name() + ".COM:membars") 1982301SN/A .desc("Number of memory barriers committed") 1992301SN/A .flags(total) 2002301SN/A ; 2012301SN/A 2022316SN/A statComBranches 2032301SN/A .init(cpu->number_of_threads) 2042301SN/A .name(name() + ".COM:branches") 2052301SN/A .desc("Number of branches committed") 2062301SN/A .flags(total) 2072301SN/A ; 2082301SN/A 2092316SN/A commitEligible 2102301SN/A .init(cpu->number_of_threads) 2112301SN/A .name(name() + ".COM:bw_limited") 2122301SN/A .desc("number of insts not committed due to BW limits") 2132301SN/A .flags(total) 2142301SN/A ; 2152301SN/A 2162316SN/A commitEligibleSamples 2172301SN/A .name(name() + ".COM:bw_lim_events") 2182301SN/A .desc("number cycles where commit BW limit reached") 2192301SN/A ; 2201062SN/A} 2211062SN/A 2221062SN/Atemplate <class Impl> 2231062SN/Avoid 2242733Sktlim@umich.eduDefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 2251060SN/A{ 2261060SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2271060SN/A cpu = cpu_ptr; 2282292SN/A 2292292SN/A // Commit must broadcast the number of free entries it has at the start of 2302292SN/A // the simulation, so it starts as active. 2312733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 2322307SN/A 2332316SN/A trapLatency = cpu->cycles(trapLatency); 2341060SN/A} 2351060SN/A 2361061SN/Atemplate <class Impl> 2371060SN/Avoid 2382292SN/ADefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 2392292SN/A{ 2402292SN/A thread = threads; 2412292SN/A} 2422292SN/A 2432292SN/Atemplate <class Impl> 2442292SN/Avoid 2452292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2461060SN/A{ 2471060SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2481060SN/A timeBuffer = tb_ptr; 2491060SN/A 2501060SN/A // Setup wire to send information back to IEW. 2511060SN/A toIEW = timeBuffer->getWire(0); 2521060SN/A 2531060SN/A // Setup wire to read data from IEW (for the ROB). 2541060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2551060SN/A} 2561060SN/A 2571061SN/Atemplate <class Impl> 2581060SN/Avoid 2592292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2602292SN/A{ 2612292SN/A DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2622292SN/A fetchQueue = fq_ptr; 2632292SN/A 2642292SN/A // Setup wire to get instructions from rename (for the ROB). 2652292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2662292SN/A} 2672292SN/A 2682292SN/Atemplate <class Impl> 2692292SN/Avoid 2702292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2711060SN/A{ 2721060SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2731060SN/A renameQueue = rq_ptr; 2741060SN/A 2751060SN/A // Setup wire to get instructions from rename (for the ROB). 2761060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2771060SN/A} 2781060SN/A 2791061SN/Atemplate <class Impl> 2801060SN/Avoid 2812292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2821060SN/A{ 2831060SN/A DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2841060SN/A iewQueue = iq_ptr; 2851060SN/A 2861060SN/A // Setup wire to get instructions from IEW. 2871060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2881060SN/A} 2891060SN/A 2901061SN/Atemplate <class Impl> 2911060SN/Avoid 2922292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2932292SN/A{ 2942292SN/A iewStage = iew_stage; 2952292SN/A} 2962292SN/A 2972292SN/Atemplate<class Impl> 2982292SN/Avoid 2992292SN/ADefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3002292SN/A{ 3012292SN/A DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3022292SN/A activeThreads = at_ptr; 3032292SN/A} 3042292SN/A 3052292SN/Atemplate <class Impl> 3062292SN/Avoid 3072292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3082292SN/A{ 3092292SN/A DPRINTF(Commit, "Setting rename map pointers.\n"); 3102292SN/A 3112292SN/A for (int i=0; i < numThreads; i++) { 3122292SN/A renameMap[i] = &rm_ptr[i]; 3132292SN/A } 3142292SN/A} 3152292SN/A 3162292SN/Atemplate <class Impl> 3172292SN/Avoid 3182292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3191060SN/A{ 3201060SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3211060SN/A rob = rob_ptr; 3221060SN/A} 3231060SN/A 3241061SN/Atemplate <class Impl> 3251060SN/Avoid 3262292SN/ADefaultCommit<Impl>::initStage() 3271060SN/A{ 3282292SN/A rob->setActiveThreads(activeThreads); 3292292SN/A rob->resetEntries(); 3301060SN/A 3312292SN/A // Broadcast the number of free entries. 3322292SN/A for (int i=0; i < numThreads; i++) { 3332292SN/A toIEW->commitInfo[i].usedROB = true; 3342292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3351060SN/A } 3361060SN/A 3372292SN/A cpu->activityThisCycle(); 3381060SN/A} 3391060SN/A 3401061SN/Atemplate <class Impl> 3412863Sktlim@umich.edubool 3422843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3431060SN/A{ 3442843Sktlim@umich.edu drainPending = true; 3452863Sktlim@umich.edu 3462863Sktlim@umich.edu // If it's already drained, return true. 3472863Sktlim@umich.edu if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 3482863Sktlim@umich.edu cpu->signalDrained(); 3492863Sktlim@umich.edu return true; 3502863Sktlim@umich.edu } 3512863Sktlim@umich.edu 3522863Sktlim@umich.edu return false; 3532316SN/A} 3542316SN/A 3552316SN/Atemplate <class Impl> 3562316SN/Avoid 3572843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3582316SN/A{ 3592316SN/A switchedOut = true; 3602843Sktlim@umich.edu drainPending = false; 3612307SN/A rob->switchOut(); 3622307SN/A} 3632307SN/A 3642307SN/Atemplate <class Impl> 3652307SN/Avoid 3662843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3672843Sktlim@umich.edu{ 3682864Sktlim@umich.edu drainPending = false; 3692843Sktlim@umich.edu} 3702843Sktlim@umich.edu 3712843Sktlim@umich.edutemplate <class Impl> 3722843Sktlim@umich.eduvoid 3732307SN/ADefaultCommit<Impl>::takeOverFrom() 3742307SN/A{ 3752316SN/A switchedOut = false; 3762307SN/A _status = Active; 3772307SN/A _nextStatus = Inactive; 3782307SN/A for (int i=0; i < numThreads; i++) { 3792307SN/A commitStatus[i] = Idle; 3802307SN/A changedROBNumEntries[i] = false; 3812307SN/A trapSquash[i] = false; 3822680Sktlim@umich.edu tcSquash[i] = false; 3832307SN/A } 3842307SN/A squashCounter = 0; 3852307SN/A rob->takeOverFrom(); 3862307SN/A} 3872307SN/A 3882307SN/Atemplate <class Impl> 3892307SN/Avoid 3902292SN/ADefaultCommit<Impl>::updateStatus() 3912132SN/A{ 3922316SN/A // reset ROB changed variable 3932316SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 3942316SN/A while (threads != (*activeThreads).end()) { 3952316SN/A unsigned tid = *threads++; 3962316SN/A changedROBNumEntries[tid] = false; 3972316SN/A 3982316SN/A // Also check if any of the threads has a trap pending 3992316SN/A if (commitStatus[tid] == TrapPending || 4002316SN/A commitStatus[tid] == FetchTrapPending) { 4012316SN/A _nextStatus = Active; 4022316SN/A } 4032292SN/A } 4042292SN/A 4052292SN/A if (_nextStatus == Inactive && _status == Active) { 4062292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4072733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4082292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4092292SN/A DPRINTF(Activity, "Activating stage.\n"); 4102733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4112292SN/A } 4122292SN/A 4132292SN/A _status = _nextStatus; 4142292SN/A} 4152292SN/A 4162292SN/Atemplate <class Impl> 4172292SN/Avoid 4182292SN/ADefaultCommit<Impl>::setNextStatus() 4192292SN/A{ 4202292SN/A int squashes = 0; 4212292SN/A 4222292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4232292SN/A 4242292SN/A while (threads != (*activeThreads).end()) { 4252292SN/A unsigned tid = *threads++; 4262292SN/A 4272292SN/A if (commitStatus[tid] == ROBSquashing) { 4282292SN/A squashes++; 4292292SN/A } 4302292SN/A } 4312292SN/A 4322702Sktlim@umich.edu squashCounter = squashes; 4332292SN/A 4342292SN/A // If commit is currently squashing, then it will have activity for the 4352292SN/A // next cycle. Set its next status as active. 4362292SN/A if (squashCounter) { 4372292SN/A _nextStatus = Active; 4382292SN/A } 4392292SN/A} 4402292SN/A 4412292SN/Atemplate <class Impl> 4422292SN/Abool 4432292SN/ADefaultCommit<Impl>::changedROBEntries() 4442292SN/A{ 4452292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4462292SN/A 4472292SN/A while (threads != (*activeThreads).end()) { 4482292SN/A unsigned tid = *threads++; 4492292SN/A 4502292SN/A if (changedROBNumEntries[tid]) { 4512292SN/A return true; 4522292SN/A } 4532292SN/A } 4542292SN/A 4552292SN/A return false; 4562292SN/A} 4572292SN/A 4582292SN/Atemplate <class Impl> 4592292SN/Aunsigned 4602292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4612292SN/A{ 4622292SN/A return rob->numFreeEntries(tid); 4632292SN/A} 4642292SN/A 4652292SN/Atemplate <class Impl> 4662292SN/Avoid 4672292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4682292SN/A{ 4692292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4702292SN/A 4712292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4722292SN/A 4732292SN/A trap->schedule(curTick + trapLatency); 4742292SN/A 4752292SN/A thread[tid]->trapPending = true; 4762292SN/A} 4772292SN/A 4782292SN/Atemplate <class Impl> 4792292SN/Avoid 4802680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4812292SN/A{ 4822680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4832292SN/A 4842680Sktlim@umich.edu tcSquash[tid] = true; 4852292SN/A} 4862292SN/A 4872292SN/Atemplate <class Impl> 4882292SN/Avoid 4892316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4902292SN/A{ 4912292SN/A // If we want to include the squashing instruction in the squash, 4922292SN/A // then use one older sequence number. 4932292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4942292SN/A // all instructions of this thread. 4952292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 4962292SN/A 0 : rob->readHeadInst(tid)->seqNum - 1;; 4972292SN/A 4982292SN/A // All younger instructions will be squashed. Set the sequence 4992292SN/A // number as the youngest instruction in the ROB (0 in this case. 5002292SN/A // Hopefully nothing breaks.) 5012292SN/A youngestSeqNum[tid] = 0; 5022292SN/A 5032292SN/A rob->squash(squashed_inst, tid); 5042292SN/A changedROBNumEntries[tid] = true; 5052292SN/A 5062292SN/A // Send back the sequence number of the squashed instruction. 5072292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5082292SN/A 5092292SN/A // Send back the squash signal to tell stages that they should 5102292SN/A // squash. 5112292SN/A toIEW->commitInfo[tid].squash = true; 5122292SN/A 5132292SN/A // Send back the rob squashing signal so other stages know that 5142292SN/A // the ROB is in the process of squashing. 5152292SN/A toIEW->commitInfo[tid].robSquashing = true; 5162292SN/A 5172292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5182292SN/A 5192316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5202316SN/A} 5212292SN/A 5222316SN/Atemplate <class Impl> 5232316SN/Avoid 5242316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5252316SN/A{ 5262316SN/A squashAll(tid); 5272316SN/A 5282316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5292316SN/A 5302316SN/A thread[tid]->trapPending = false; 5312316SN/A thread[tid]->inSyscall = false; 5322316SN/A 5332316SN/A trapSquash[tid] = false; 5342316SN/A 5352316SN/A commitStatus[tid] = ROBSquashing; 5362316SN/A cpu->activityThisCycle(); 5372316SN/A} 5382316SN/A 5392316SN/Atemplate <class Impl> 5402316SN/Avoid 5412680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5422316SN/A{ 5432316SN/A squashAll(tid); 5442292SN/A 5452680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5462292SN/A 5472292SN/A thread[tid]->inSyscall = false; 5482292SN/A assert(!thread[tid]->trapPending); 5492316SN/A 5502292SN/A commitStatus[tid] = ROBSquashing; 5512292SN/A cpu->activityThisCycle(); 5522292SN/A 5532680Sktlim@umich.edu tcSquash[tid] = false; 5542292SN/A} 5552292SN/A 5562292SN/Atemplate <class Impl> 5572292SN/Avoid 5582292SN/ADefaultCommit<Impl>::tick() 5592292SN/A{ 5602292SN/A wroteToTimeBuffer = false; 5612292SN/A _nextStatus = Inactive; 5622292SN/A 5632843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5642843Sktlim@umich.edu cpu->signalDrained(); 5652843Sktlim@umich.edu drainPending = false; 5662316SN/A return; 5672316SN/A } 5682316SN/A 5692875Sksewell@umich.edu if ((*activeThreads).size() <= 0) 5702875Sksewell@umich.edu return; 5712875Sksewell@umich.edu 5722292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 5732292SN/A 5742316SN/A // Check if any of the threads are done squashing. Change the 5752316SN/A // status if they are done. 5762292SN/A while (threads != (*activeThreads).end()) { 5772292SN/A unsigned tid = *threads++; 5782292SN/A 5792292SN/A if (commitStatus[tid] == ROBSquashing) { 5802292SN/A 5812292SN/A if (rob->isDoneSquashing(tid)) { 5822292SN/A commitStatus[tid] = Running; 5832292SN/A } else { 5842292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5852877Sksewell@umich.edu " insts this cycle.\n", tid); 5862702Sktlim@umich.edu rob->doSquash(tid); 5872702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5882702Sktlim@umich.edu wroteToTimeBuffer = true; 5892292SN/A } 5902292SN/A } 5912292SN/A } 5922292SN/A 5932292SN/A commit(); 5942292SN/A 5952292SN/A markCompletedInsts(); 5962292SN/A 5972292SN/A threads = (*activeThreads).begin(); 5982292SN/A 5992292SN/A while (threads != (*activeThreads).end()) { 6002292SN/A unsigned tid = *threads++; 6012292SN/A 6022292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6032292SN/A // The ROB has more instructions it can commit. Its next status 6042292SN/A // will be active. 6052292SN/A _nextStatus = Active; 6062292SN/A 6072292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6082292SN/A 6092292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6102292SN/A " ROB and ready to commit\n", 6112292SN/A tid, inst->seqNum, inst->readPC()); 6122292SN/A 6132292SN/A } else if (!rob->isEmpty(tid)) { 6142292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6152292SN/A 6162292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6172292SN/A "%#x is head of ROB and not ready\n", 6182292SN/A tid, inst->seqNum, inst->readPC()); 6192292SN/A } 6202292SN/A 6212292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6222292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6232292SN/A } 6242292SN/A 6252292SN/A 6262292SN/A if (wroteToTimeBuffer) { 6272316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6282292SN/A cpu->activityThisCycle(); 6292292SN/A } 6302292SN/A 6312292SN/A updateStatus(); 6322292SN/A} 6332292SN/A 6342292SN/Atemplate <class Impl> 6352292SN/Avoid 6362292SN/ADefaultCommit<Impl>::commit() 6372292SN/A{ 6382292SN/A 6391060SN/A ////////////////////////////////////// 6401060SN/A // Check for interrupts 6411060SN/A ////////////////////////////////////// 6421060SN/A 6431858SN/A#if FULL_SYSTEM 6442316SN/A // Process interrupts if interrupts are enabled, not in PAL mode, 6452316SN/A // and no other traps or external squashes are currently pending. 6462316SN/A // @todo: Allow other threads to handle interrupts. 6472292SN/A if (cpu->checkInterrupts && 6481060SN/A cpu->check_interrupts() && 6492292SN/A !cpu->inPalMode(readPC()) && 6502292SN/A !trapSquash[0] && 6512680Sktlim@umich.edu !tcSquash[0]) { 6522316SN/A // Tell fetch that there is an interrupt pending. This will 6532316SN/A // make fetch wait until it sees a non PAL-mode PC, at which 6542316SN/A // point it stops fetching instructions. 6552292SN/A toIEW->commitInfo[0].interruptPending = true; 6561060SN/A 6572316SN/A // Wait until the ROB is empty and all stores have drained in 6582316SN/A // order to enter the interrupt. 6592292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6602292SN/A // Not sure which thread should be the one to interrupt. For now 6612292SN/A // always do thread 0. 6622292SN/A assert(!thread[0]->inSyscall); 6632292SN/A thread[0]->inSyscall = true; 6642292SN/A 6652292SN/A // CPU will handle implementation of the interrupt. 6662292SN/A cpu->processInterrupts(); 6672292SN/A 6682292SN/A // Now squash or record that I need to squash this cycle. 6692292SN/A commitStatus[0] = TrapPending; 6702292SN/A 6712292SN/A // Exit state update mode to avoid accidental updating. 6722292SN/A thread[0]->inSyscall = false; 6732292SN/A 6742292SN/A // Generate trap squash event. 6752292SN/A generateTrapEvent(0); 6762292SN/A 6772292SN/A toIEW->commitInfo[0].clearInterrupt = true; 6782292SN/A 6792292SN/A DPRINTF(Commit, "Interrupt detected.\n"); 6802292SN/A } else { 6812292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6822292SN/A } 6831060SN/A } 6841060SN/A#endif // FULL_SYSTEM 6851060SN/A 6861060SN/A //////////////////////////////////// 6872316SN/A // Check for any possible squashes, handle them first 6881060SN/A //////////////////////////////////// 6891060SN/A 6902292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6911060SN/A 6922292SN/A while (threads != (*activeThreads).end()) { 6932292SN/A unsigned tid = *threads++; 6941060SN/A 6952292SN/A // Not sure which one takes priority. I think if we have 6962292SN/A // both, that's a bad sign. 6972292SN/A if (trapSquash[tid] == true) { 6982680Sktlim@umich.edu assert(!tcSquash[tid]); 6992292SN/A squashFromTrap(tid); 7002680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7012680Sktlim@umich.edu squashFromTC(tid); 7022292SN/A } 7031061SN/A 7042292SN/A // Squashed sequence number must be older than youngest valid 7052292SN/A // instruction in the ROB. This prevents squashes from younger 7062292SN/A // instructions overriding squashes from older instructions. 7072292SN/A if (fromIEW->squash[tid] && 7082292SN/A commitStatus[tid] != TrapPending && 7092292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7101061SN/A 7112292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7122292SN/A tid, 7132292SN/A fromIEW->mispredPC[tid], 7142292SN/A fromIEW->squashedSeqNum[tid]); 7151061SN/A 7162292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7172292SN/A tid, 7182292SN/A fromIEW->nextPC[tid]); 7191061SN/A 7202292SN/A commitStatus[tid] = ROBSquashing; 7211061SN/A 7222292SN/A // If we want to include the squashing instruction in the squash, 7232292SN/A // then use one older sequence number. 7242292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7251062SN/A 7262292SN/A if (fromIEW->includeSquashInst[tid] == true) 7272292SN/A squashed_inst--; 7282292SN/A 7292292SN/A // All younger instructions will be squashed. Set the sequence 7302292SN/A // number as the youngest instruction in the ROB. 7312292SN/A youngestSeqNum[tid] = squashed_inst; 7322292SN/A 7332292SN/A rob->squash(squashed_inst, tid); 7342292SN/A changedROBNumEntries[tid] = true; 7352292SN/A 7362292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7372292SN/A 7382292SN/A toIEW->commitInfo[tid].squash = true; 7392292SN/A 7402292SN/A // Send back the rob squashing signal so other stages know that 7412292SN/A // the ROB is in the process of squashing. 7422292SN/A toIEW->commitInfo[tid].robSquashing = true; 7432292SN/A 7442292SN/A toIEW->commitInfo[tid].branchMispredict = 7452292SN/A fromIEW->branchMispredict[tid]; 7462292SN/A 7472292SN/A toIEW->commitInfo[tid].branchTaken = 7482292SN/A fromIEW->branchTaken[tid]; 7492292SN/A 7502292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7512292SN/A 7522316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7532292SN/A 7542292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7552292SN/A ++branchMispredicts; 7562292SN/A } 7571062SN/A } 7582292SN/A 7591060SN/A } 7601060SN/A 7612292SN/A setNextStatus(); 7622292SN/A 7632292SN/A if (squashCounter != numThreads) { 7641061SN/A // If we're not currently squashing, then get instructions. 7651060SN/A getInsts(); 7661060SN/A 7671061SN/A // Try to commit any instructions. 7681060SN/A commitInsts(); 7691060SN/A } 7701060SN/A 7712292SN/A //Check for any activity 7722292SN/A threads = (*activeThreads).begin(); 7732292SN/A 7742292SN/A while (threads != (*activeThreads).end()) { 7752292SN/A unsigned tid = *threads++; 7762292SN/A 7772292SN/A if (changedROBNumEntries[tid]) { 7782292SN/A toIEW->commitInfo[tid].usedROB = true; 7792292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 7802292SN/A 7812292SN/A if (rob->isEmpty(tid)) { 7822292SN/A toIEW->commitInfo[tid].emptyROB = true; 7832292SN/A } 7842292SN/A 7852292SN/A wroteToTimeBuffer = true; 7862292SN/A changedROBNumEntries[tid] = false; 7872292SN/A } 7881060SN/A } 7891060SN/A} 7901060SN/A 7911061SN/Atemplate <class Impl> 7921060SN/Avoid 7932292SN/ADefaultCommit<Impl>::commitInsts() 7941060SN/A{ 7951060SN/A //////////////////////////////////// 7961060SN/A // Handle commit 7972316SN/A // Note that commit will be handled prior to putting new 7982316SN/A // instructions in the ROB so that the ROB only tries to commit 7992316SN/A // instructions it has in this current cycle, and not instructions 8002316SN/A // it is writing in during this cycle. Can't commit and squash 8012316SN/A // things at the same time... 8021060SN/A //////////////////////////////////// 8031060SN/A 8042292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8051060SN/A 8061060SN/A unsigned num_committed = 0; 8071060SN/A 8082292SN/A DynInstPtr head_inst; 8092316SN/A 8101060SN/A // Commit as many instructions as possible until the commit bandwidth 8111060SN/A // limit is reached, or it becomes impossible to commit any more. 8122292SN/A while (num_committed < commitWidth) { 8132292SN/A int commit_thread = getCommittingThread(); 8141060SN/A 8152292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8162292SN/A break; 8172292SN/A 8182292SN/A head_inst = rob->readHeadInst(commit_thread); 8192292SN/A 8202292SN/A int tid = head_inst->threadNumber; 8212292SN/A 8222292SN/A assert(tid == commit_thread); 8232292SN/A 8242292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8252292SN/A head_inst->seqNum, tid); 8262132SN/A 8272316SN/A // If the head instruction is squashed, it is ready to retire 8282316SN/A // (be removed from the ROB) at any time. 8291060SN/A if (head_inst->isSquashed()) { 8301060SN/A 8312292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8321060SN/A "ROB.\n"); 8331060SN/A 8342292SN/A rob->retireHead(commit_thread); 8351060SN/A 8361062SN/A ++commitSquashedInsts; 8371062SN/A 8382292SN/A // Record that the number of ROB entries has changed. 8392292SN/A changedROBNumEntries[tid] = true; 8401060SN/A } else { 8412292SN/A PC[tid] = head_inst->readPC(); 8422292SN/A nextPC[tid] = head_inst->readNextPC(); 8432292SN/A 8441060SN/A // Increment the total number of non-speculative instructions 8451060SN/A // executed. 8461060SN/A // Hack for now: it really shouldn't happen until after the 8471061SN/A // commit is deemed to be successful, but this count is needed 8481061SN/A // for syscalls. 8492292SN/A thread[tid]->funcExeInst++; 8501060SN/A 8511060SN/A // Try to commit the head instruction. 8521060SN/A bool commit_success = commitHead(head_inst, num_committed); 8531060SN/A 8541062SN/A if (commit_success) { 8551060SN/A ++num_committed; 8561060SN/A 8572292SN/A changedROBNumEntries[tid] = true; 8582292SN/A 8592292SN/A // Set the doneSeqNum to the youngest committed instruction. 8602292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 8611060SN/A 8621062SN/A ++commitCommittedInsts; 8631062SN/A 8642292SN/A // To match the old model, don't count nops and instruction 8652292SN/A // prefetches towards the total commit count. 8662292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 8672292SN/A cpu->instDone(tid); 8681062SN/A } 8692292SN/A 8702292SN/A PC[tid] = nextPC[tid]; 8712307SN/A nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 8722292SN/A#if FULL_SYSTEM 8732292SN/A int count = 0; 8742292SN/A Addr oldpc; 8752292SN/A do { 8762316SN/A // Debug statement. Checks to make sure we're not 8772316SN/A // currently updating state while handling PC events. 8782292SN/A if (count == 0) 8792316SN/A assert(!thread[tid]->inSyscall && 8802316SN/A !thread[tid]->trapPending); 8812292SN/A oldpc = PC[tid]; 8822292SN/A cpu->system->pcEventQueue.service( 8832690Sktlim@umich.edu thread[tid]->getTC()); 8842292SN/A count++; 8852292SN/A } while (oldpc != PC[tid]); 8862292SN/A if (count > 1) { 8872292SN/A DPRINTF(Commit, "PC skip function event, stopping commit\n"); 8882292SN/A break; 8892292SN/A } 8902292SN/A#endif 8911060SN/A } else { 8922292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 8932292SN/A "[tid:%i] [sn:%i].\n", 8942292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 8951060SN/A break; 8961060SN/A } 8971060SN/A } 8981060SN/A } 8991062SN/A 9001063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9012292SN/A numCommittedDist.sample(num_committed); 9022307SN/A 9032307SN/A if (num_committed == commitWidth) { 9042349SN/A commitEligibleSamples++; 9052307SN/A } 9061060SN/A} 9071060SN/A 9081061SN/Atemplate <class Impl> 9091060SN/Abool 9102292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9111060SN/A{ 9121060SN/A assert(head_inst); 9131060SN/A 9142292SN/A int tid = head_inst->threadNumber; 9152292SN/A 9162316SN/A // If the instruction is not executed yet, then it will need extra 9172316SN/A // handling. Signal backwards that it should be executed. 9181061SN/A if (!head_inst->isExecuted()) { 9191061SN/A // Keep this number correct. We have not yet actually executed 9201061SN/A // and committed this instruction. 9212292SN/A thread[tid]->funcExeInst--; 9221062SN/A 9232731Sktlim@umich.edu head_inst->setAtCommit(); 9241060SN/A 9252292SN/A if (head_inst->isNonSpeculative() || 9262348SN/A head_inst->isStoreConditional() || 9272292SN/A head_inst->isMemBarrier() || 9282292SN/A head_inst->isWriteBarrier()) { 9292316SN/A 9302316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9312316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9322316SN/A head_inst->seqNum, head_inst->readPC()); 9332316SN/A 9342292SN/A#if !FULL_SYSTEM 9352316SN/A // Hack to make sure syscalls/memory barriers/quiesces 9362316SN/A // aren't executed until all stores write back their data. 9372316SN/A // This direct communication shouldn't be used for 9382316SN/A // anything other than this. 9392292SN/A if (inst_num > 0 || iewStage->hasStoresToWB()) 9402292SN/A#else 9412292SN/A if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 9422292SN/A head_inst->isQuiesce()) && 9432292SN/A iewStage->hasStoresToWB()) 9442292SN/A#endif 9452292SN/A { 9462292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9472292SN/A return false; 9482292SN/A } 9492292SN/A 9502292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9511061SN/A 9521061SN/A // Change the instruction so it won't try to commit again until 9531061SN/A // it is executed. 9541061SN/A head_inst->clearCanCommit(); 9551061SN/A 9561062SN/A ++commitNonSpecStalls; 9571062SN/A 9581061SN/A return false; 9592292SN/A } else if (head_inst->isLoad()) { 9602292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9612292SN/A head_inst->seqNum, head_inst->readPC()); 9622292SN/A 9632292SN/A // Send back the non-speculative instruction's sequence 9642316SN/A // number. Tell the lsq to re-execute the load. 9652292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9662292SN/A toIEW->commitInfo[tid].uncached = true; 9672292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 9682292SN/A 9692292SN/A head_inst->clearCanCommit(); 9702292SN/A 9712292SN/A return false; 9721061SN/A } else { 9732292SN/A panic("Trying to commit un-executed instruction " 9741061SN/A "of unknown type!\n"); 9751061SN/A } 9761060SN/A } 9771060SN/A 9782316SN/A if (head_inst->isThreadSync()) { 9792292SN/A // Not handled for now. 9802316SN/A panic("Thread sync instructions are not handled yet.\n"); 9812132SN/A } 9822132SN/A 9832316SN/A // Stores mark themselves as completed. 9842310SN/A if (!head_inst->isStore()) { 9852310SN/A head_inst->setCompleted(); 9862310SN/A } 9872310SN/A 9882733Sktlim@umich.edu#if USE_CHECKER 9892316SN/A // Use checker prior to updating anything due to traps or PC 9902316SN/A // based events. 9912316SN/A if (cpu->checker) { 9922732Sktlim@umich.edu cpu->checker->verify(head_inst); 9931060SN/A } 9942733Sktlim@umich.edu#endif 9951060SN/A 9961060SN/A // Check if the instruction caused a fault. If so, trap. 9972132SN/A Fault inst_fault = head_inst->getFault(); 9981681SN/A 9992918Sktlim@umich.edu // DTB will sometimes need the machine instruction for when 10002918Sktlim@umich.edu // faults happen. So we will set it here, prior to the DTB 10012918Sktlim@umich.edu // possibly needing it for its fault. 10022918Sktlim@umich.edu thread[tid]->setInst( 10032918Sktlim@umich.edu static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10042918Sktlim@umich.edu 10052112SN/A if (inst_fault != NoFault) { 10062316SN/A head_inst->setCompleted(); 10072316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10082316SN/A head_inst->seqNum, head_inst->readPC()); 10092292SN/A 10102316SN/A if (iewStage->hasStoresToWB() || inst_num > 0) { 10112316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10122316SN/A return false; 10132316SN/A } 10142310SN/A 10152733Sktlim@umich.edu#if USE_CHECKER 10162316SN/A if (cpu->checker && head_inst->isStore()) { 10172732Sktlim@umich.edu cpu->checker->verify(head_inst); 10182316SN/A } 10192733Sktlim@umich.edu#endif 10202292SN/A 10212316SN/A assert(!thread[tid]->inSyscall); 10222292SN/A 10232316SN/A // Mark that we're in state update mode so that the trap's 10242316SN/A // execution doesn't generate extra squashes. 10252316SN/A thread[tid]->inSyscall = true; 10262292SN/A 10272316SN/A // Execute the trap. Although it's slightly unrealistic in 10282316SN/A // terms of timing (as it doesn't wait for the full timing of 10292316SN/A // the trap event to complete before updating state), it's 10302316SN/A // needed to update the state as soon as possible. This 10312316SN/A // prevents external agents from changing any specific state 10322316SN/A // that the trap need. 10332316SN/A cpu->trap(inst_fault, tid); 10342292SN/A 10352316SN/A // Exit state update mode to avoid accidental updating. 10362316SN/A thread[tid]->inSyscall = false; 10372292SN/A 10382316SN/A commitStatus[tid] = TrapPending; 10392292SN/A 10402316SN/A // Generate trap squash event. 10412316SN/A generateTrapEvent(tid); 10422316SN/A 10432316SN/A return false; 10441060SN/A } 10451060SN/A 10462301SN/A updateComInstStats(head_inst); 10472132SN/A 10482132SN/A if (head_inst->traceData) { 10492292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 10502292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 10512132SN/A head_inst->traceData->finalize(); 10522292SN/A head_inst->traceData = NULL; 10531060SN/A } 10541060SN/A 10552292SN/A // Update the commit rename map 10562292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 10572292SN/A renameMap[tid]->setEntry(head_inst->destRegIdx(i), 10582292SN/A head_inst->renamedDestRegIdx(i)); 10591060SN/A } 10601062SN/A 10612292SN/A // Finally clear the head ROB entry. 10622292SN/A rob->retireHead(tid); 10631060SN/A 10641060SN/A // Return true to indicate that we have committed an instruction. 10651060SN/A return true; 10661060SN/A} 10671060SN/A 10681061SN/Atemplate <class Impl> 10691060SN/Avoid 10702292SN/ADefaultCommit<Impl>::getInsts() 10711060SN/A{ 10722316SN/A // Read any renamed instructions and place them into the ROB. 10731061SN/A int insts_to_process = min((int)renameWidth, fromRename->size); 10741061SN/A 10752292SN/A for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 10761060SN/A { 10772292SN/A DynInstPtr inst = fromRename->insts[inst_num]; 10782292SN/A int tid = inst->threadNumber; 10792292SN/A 10802292SN/A if (!inst->isSquashed() && 10812292SN/A commitStatus[tid] != ROBSquashing) { 10822292SN/A changedROBNumEntries[tid] = true; 10832292SN/A 10842292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 10852292SN/A inst->readPC(), inst->seqNum, tid); 10862292SN/A 10872292SN/A rob->insertInst(inst); 10882292SN/A 10892292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 10902292SN/A 10912292SN/A youngestSeqNum[tid] = inst->seqNum; 10921061SN/A } else { 10932292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 10941061SN/A "squashed, skipping.\n", 10952292SN/A inst->readPC(), inst->seqNum, tid); 10961061SN/A } 10971060SN/A } 10981060SN/A} 10991060SN/A 11001061SN/Atemplate <class Impl> 11011060SN/Avoid 11022292SN/ADefaultCommit<Impl>::markCompletedInsts() 11031060SN/A{ 11041060SN/A // Grab completed insts out of the IEW instruction queue, and mark 11051060SN/A // instructions completed within the ROB. 11061060SN/A for (int inst_num = 0; 11071681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 11081060SN/A ++inst_num) 11091060SN/A { 11102292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 11112316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 11122316SN/A "within ROB.\n", 11132292SN/A fromIEW->insts[inst_num]->threadNumber, 11142292SN/A fromIEW->insts[inst_num]->readPC(), 11152292SN/A fromIEW->insts[inst_num]->seqNum); 11161060SN/A 11172292SN/A // Mark the instruction as ready to commit. 11182292SN/A fromIEW->insts[inst_num]->setCanCommit(); 11192292SN/A } 11201060SN/A } 11211060SN/A} 11221060SN/A 11231061SN/Atemplate <class Impl> 11242292SN/Abool 11252292SN/ADefaultCommit<Impl>::robDoneSquashing() 11261060SN/A{ 11272292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11282292SN/A 11292292SN/A while (threads != (*activeThreads).end()) { 11302292SN/A unsigned tid = *threads++; 11312292SN/A 11322292SN/A if (!rob->isDoneSquashing(tid)) 11332292SN/A return false; 11342292SN/A } 11352292SN/A 11362292SN/A return true; 11371060SN/A} 11382292SN/A 11392301SN/Atemplate <class Impl> 11402301SN/Avoid 11412301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 11422301SN/A{ 11432301SN/A unsigned thread = inst->threadNumber; 11442301SN/A 11452301SN/A // 11462301SN/A // Pick off the software prefetches 11472301SN/A // 11482301SN/A#ifdef TARGET_ALPHA 11492301SN/A if (inst->isDataPrefetch()) { 11502316SN/A statComSwp[thread]++; 11512301SN/A } else { 11522316SN/A statComInst[thread]++; 11532301SN/A } 11542301SN/A#else 11552316SN/A statComInst[thread]++; 11562301SN/A#endif 11572301SN/A 11582301SN/A // 11592301SN/A // Control Instructions 11602301SN/A // 11612301SN/A if (inst->isControl()) 11622316SN/A statComBranches[thread]++; 11632301SN/A 11642301SN/A // 11652301SN/A // Memory references 11662301SN/A // 11672301SN/A if (inst->isMemRef()) { 11682316SN/A statComRefs[thread]++; 11692301SN/A 11702301SN/A if (inst->isLoad()) { 11712316SN/A statComLoads[thread]++; 11722301SN/A } 11732301SN/A } 11742301SN/A 11752301SN/A if (inst->isMemBarrier()) { 11762316SN/A statComMembars[thread]++; 11772301SN/A } 11782301SN/A} 11792301SN/A 11802292SN/A//////////////////////////////////////// 11812292SN/A// // 11822316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 11832292SN/A// // 11842292SN/A//////////////////////////////////////// 11852292SN/Atemplate <class Impl> 11862292SN/Aint 11872292SN/ADefaultCommit<Impl>::getCommittingThread() 11882292SN/A{ 11892292SN/A if (numThreads > 1) { 11902292SN/A switch (commitPolicy) { 11912292SN/A 11922292SN/A case Aggressive: 11932292SN/A //If Policy is Aggressive, commit will call 11942292SN/A //this function multiple times per 11952292SN/A //cycle 11962292SN/A return oldestReady(); 11972292SN/A 11982292SN/A case RoundRobin: 11992292SN/A return roundRobin(); 12002292SN/A 12012292SN/A case OldestReady: 12022292SN/A return oldestReady(); 12032292SN/A 12042292SN/A default: 12052292SN/A return -1; 12062292SN/A } 12072292SN/A } else { 12082292SN/A int tid = (*activeThreads).front(); 12092292SN/A 12102292SN/A if (commitStatus[tid] == Running || 12112292SN/A commitStatus[tid] == Idle || 12122292SN/A commitStatus[tid] == FetchTrapPending) { 12132292SN/A return tid; 12142292SN/A } else { 12152292SN/A return -1; 12162292SN/A } 12172292SN/A } 12182292SN/A} 12192292SN/A 12202292SN/Atemplate<class Impl> 12212292SN/Aint 12222292SN/ADefaultCommit<Impl>::roundRobin() 12232292SN/A{ 12242292SN/A list<unsigned>::iterator pri_iter = priority_list.begin(); 12252292SN/A list<unsigned>::iterator end = priority_list.end(); 12262292SN/A 12272292SN/A while (pri_iter != end) { 12282292SN/A unsigned tid = *pri_iter; 12292292SN/A 12302292SN/A if (commitStatus[tid] == Running || 12312831Sksewell@umich.edu commitStatus[tid] == Idle || 12322831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 12332292SN/A 12342292SN/A if (rob->isHeadReady(tid)) { 12352292SN/A priority_list.erase(pri_iter); 12362292SN/A priority_list.push_back(tid); 12372292SN/A 12382292SN/A return tid; 12392292SN/A } 12402292SN/A } 12412292SN/A 12422292SN/A pri_iter++; 12432292SN/A } 12442292SN/A 12452292SN/A return -1; 12462292SN/A} 12472292SN/A 12482292SN/Atemplate<class Impl> 12492292SN/Aint 12502292SN/ADefaultCommit<Impl>::oldestReady() 12512292SN/A{ 12522292SN/A unsigned oldest = 0; 12532292SN/A bool first = true; 12542292SN/A 12552292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 12562292SN/A 12572292SN/A while (threads != (*activeThreads).end()) { 12582292SN/A unsigned tid = *threads++; 12592292SN/A 12602292SN/A if (!rob->isEmpty(tid) && 12612292SN/A (commitStatus[tid] == Running || 12622292SN/A commitStatus[tid] == Idle || 12632292SN/A commitStatus[tid] == FetchTrapPending)) { 12642292SN/A 12652292SN/A if (rob->isHeadReady(tid)) { 12662292SN/A 12672292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 12682292SN/A 12692292SN/A if (first) { 12702292SN/A oldest = tid; 12712292SN/A first = false; 12722292SN/A } else if (head_inst->seqNum < oldest) { 12732292SN/A oldest = tid; 12742292SN/A } 12752292SN/A } 12762292SN/A } 12772292SN/A } 12782292SN/A 12792292SN/A if (!first) { 12802292SN/A return oldest; 12812292SN/A } else { 12822292SN/A return -1; 12832292SN/A } 12842292SN/A} 1285