commit_impl.hh revision 2863
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312733Sktlim@umich.edu#include "config/full_system.hh" 322733Sktlim@umich.edu#include "config/use_checker.hh" 332733Sktlim@umich.edu 342292SN/A#include <algorithm> 352329SN/A#include <string> 362292SN/A 372292SN/A#include "base/loader/symtab.hh" 381060SN/A#include "base/timebuf.hh" 392292SN/A#include "cpu/exetrace.hh" 401717SN/A#include "cpu/o3/commit.hh" 412292SN/A#include "cpu/o3/thread_state.hh" 422292SN/A 432790Sktlim@umich.edu#if USE_CHECKER 442790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 452790Sktlim@umich.edu#endif 462790Sktlim@umich.edu 472292SN/Ausing namespace std; 481060SN/A 491061SN/Atemplate <class Impl> 502292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 512292SN/A unsigned _tid) 522292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 531060SN/A{ 542292SN/A this->setFlags(Event::AutoDelete); 551060SN/A} 561060SN/A 571061SN/Atemplate <class Impl> 581060SN/Avoid 592292SN/ADefaultCommit<Impl>::TrapEvent::process() 601062SN/A{ 612316SN/A // This will get reset by commit if it was switched out at the 622316SN/A // time of this event processing. 632292SN/A commit->trapSquash[tid] = true; 642292SN/A} 652292SN/A 662292SN/Atemplate <class Impl> 672292SN/Aconst char * 682292SN/ADefaultCommit<Impl>::TrapEvent::description() 692292SN/A{ 702292SN/A return "Trap event"; 712292SN/A} 722292SN/A 732292SN/Atemplate <class Impl> 742292SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 752669Sktlim@umich.edu : squashCounter(0), 762292SN/A iewToCommitDelay(params->iewToCommitDelay), 772292SN/A commitToIEWDelay(params->commitToIEWDelay), 782292SN/A renameToROBDelay(params->renameToROBDelay), 792292SN/A fetchToCommitDelay(params->commitToFetchDelay), 802292SN/A renameWidth(params->renameWidth), 812292SN/A commitWidth(params->commitWidth), 822307SN/A numThreads(params->numberOfThreads), 832843Sktlim@umich.edu drainPending(false), 842316SN/A switchedOut(false), 852316SN/A trapLatency(params->trapLatency), 862316SN/A fetchTrapLatency(params->fetchTrapLatency) 872292SN/A{ 882292SN/A _status = Active; 892292SN/A _nextStatus = Inactive; 902292SN/A string policy = params->smtCommitPolicy; 912292SN/A 922292SN/A //Convert string to lowercase 932292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 942292SN/A (int(*)(int)) tolower); 952292SN/A 962292SN/A //Assign commit policy 972292SN/A if (policy == "aggressive"){ 982292SN/A commitPolicy = Aggressive; 992292SN/A 1002292SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 1012292SN/A } else if (policy == "roundrobin"){ 1022292SN/A commitPolicy = RoundRobin; 1032292SN/A 1042292SN/A //Set-Up Priority List 1052292SN/A for (int tid=0; tid < numThreads; tid++) { 1062292SN/A priority_list.push_back(tid); 1072292SN/A } 1082292SN/A 1092292SN/A DPRINTF(Commit,"Commit Policy set to Round Robin."); 1102292SN/A } else if (policy == "oldestready"){ 1112292SN/A commitPolicy = OldestReady; 1122292SN/A 1132292SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1142292SN/A } else { 1152292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1162292SN/A "RoundRobin,OldestReady}"); 1172292SN/A } 1182292SN/A 1192292SN/A for (int i=0; i < numThreads; i++) { 1202292SN/A commitStatus[i] = Idle; 1212292SN/A changedROBNumEntries[i] = false; 1222292SN/A trapSquash[i] = false; 1232680Sktlim@umich.edu tcSquash[i] = false; 1242678Sktlim@umich.edu PC[i] = nextPC[i] = 0; 1252292SN/A } 1262292SN/A 1272292SN/A fetchFaultTick = 0; 1282292SN/A fetchTrapWait = 0; 1292292SN/A} 1302292SN/A 1312292SN/Atemplate <class Impl> 1322292SN/Astd::string 1332292SN/ADefaultCommit<Impl>::name() const 1342292SN/A{ 1352292SN/A return cpu->name() + ".commit"; 1362292SN/A} 1372292SN/A 1382292SN/Atemplate <class Impl> 1392292SN/Avoid 1402292SN/ADefaultCommit<Impl>::regStats() 1412132SN/A{ 1422301SN/A using namespace Stats; 1431062SN/A commitCommittedInsts 1441062SN/A .name(name() + ".commitCommittedInsts") 1451062SN/A .desc("The number of committed instructions") 1461062SN/A .prereq(commitCommittedInsts); 1471062SN/A commitSquashedInsts 1481062SN/A .name(name() + ".commitSquashedInsts") 1491062SN/A .desc("The number of squashed insts skipped by commit") 1501062SN/A .prereq(commitSquashedInsts); 1511062SN/A commitSquashEvents 1521062SN/A .name(name() + ".commitSquashEvents") 1531062SN/A .desc("The number of times commit is told to squash") 1541062SN/A .prereq(commitSquashEvents); 1551062SN/A commitNonSpecStalls 1561062SN/A .name(name() + ".commitNonSpecStalls") 1571062SN/A .desc("The number of times commit has been forced to stall to " 1581062SN/A "communicate backwards") 1591062SN/A .prereq(commitNonSpecStalls); 1601062SN/A branchMispredicts 1611062SN/A .name(name() + ".branchMispredicts") 1621062SN/A .desc("The number of times a branch was mispredicted") 1631062SN/A .prereq(branchMispredicts); 1642292SN/A numCommittedDist 1651062SN/A .init(0,commitWidth,1) 1661062SN/A .name(name() + ".COM:committed_per_cycle") 1671062SN/A .desc("Number of insts commited each cycle") 1681062SN/A .flags(Stats::pdf) 1691062SN/A ; 1702301SN/A 1712316SN/A statComInst 1722301SN/A .init(cpu->number_of_threads) 1732301SN/A .name(name() + ".COM:count") 1742301SN/A .desc("Number of instructions committed") 1752301SN/A .flags(total) 1762301SN/A ; 1772301SN/A 1782316SN/A statComSwp 1792301SN/A .init(cpu->number_of_threads) 1802301SN/A .name(name() + ".COM:swp_count") 1812301SN/A .desc("Number of s/w prefetches committed") 1822301SN/A .flags(total) 1832301SN/A ; 1842301SN/A 1852316SN/A statComRefs 1862301SN/A .init(cpu->number_of_threads) 1872301SN/A .name(name() + ".COM:refs") 1882301SN/A .desc("Number of memory references committed") 1892301SN/A .flags(total) 1902301SN/A ; 1912301SN/A 1922316SN/A statComLoads 1932301SN/A .init(cpu->number_of_threads) 1942301SN/A .name(name() + ".COM:loads") 1952301SN/A .desc("Number of loads committed") 1962301SN/A .flags(total) 1972301SN/A ; 1982301SN/A 1992316SN/A statComMembars 2002301SN/A .init(cpu->number_of_threads) 2012301SN/A .name(name() + ".COM:membars") 2022301SN/A .desc("Number of memory barriers committed") 2032301SN/A .flags(total) 2042301SN/A ; 2052301SN/A 2062316SN/A statComBranches 2072301SN/A .init(cpu->number_of_threads) 2082301SN/A .name(name() + ".COM:branches") 2092301SN/A .desc("Number of branches committed") 2102301SN/A .flags(total) 2112301SN/A ; 2122301SN/A 2132316SN/A commitEligible 2142301SN/A .init(cpu->number_of_threads) 2152301SN/A .name(name() + ".COM:bw_limited") 2162301SN/A .desc("number of insts not committed due to BW limits") 2172301SN/A .flags(total) 2182301SN/A ; 2192301SN/A 2202316SN/A commitEligibleSamples 2212301SN/A .name(name() + ".COM:bw_lim_events") 2222301SN/A .desc("number cycles where commit BW limit reached") 2232301SN/A ; 2241062SN/A} 2251062SN/A 2261062SN/Atemplate <class Impl> 2271062SN/Avoid 2282733Sktlim@umich.eduDefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 2291060SN/A{ 2301060SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2311060SN/A cpu = cpu_ptr; 2322292SN/A 2332292SN/A // Commit must broadcast the number of free entries it has at the start of 2342292SN/A // the simulation, so it starts as active. 2352733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 2362307SN/A 2372316SN/A trapLatency = cpu->cycles(trapLatency); 2382316SN/A fetchTrapLatency = cpu->cycles(fetchTrapLatency); 2391060SN/A} 2401060SN/A 2411061SN/Atemplate <class Impl> 2421060SN/Avoid 2432292SN/ADefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 2442292SN/A{ 2452292SN/A thread = threads; 2462292SN/A} 2472292SN/A 2482292SN/Atemplate <class Impl> 2492292SN/Avoid 2502292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2511060SN/A{ 2521060SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2531060SN/A timeBuffer = tb_ptr; 2541060SN/A 2551060SN/A // Setup wire to send information back to IEW. 2561060SN/A toIEW = timeBuffer->getWire(0); 2571060SN/A 2581060SN/A // Setup wire to read data from IEW (for the ROB). 2591060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2601060SN/A} 2611060SN/A 2621061SN/Atemplate <class Impl> 2631060SN/Avoid 2642292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2652292SN/A{ 2662292SN/A DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2672292SN/A fetchQueue = fq_ptr; 2682292SN/A 2692292SN/A // Setup wire to get instructions from rename (for the ROB). 2702292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2712292SN/A} 2722292SN/A 2732292SN/Atemplate <class Impl> 2742292SN/Avoid 2752292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2761060SN/A{ 2771060SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2781060SN/A renameQueue = rq_ptr; 2791060SN/A 2801060SN/A // Setup wire to get instructions from rename (for the ROB). 2811060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2821060SN/A} 2831060SN/A 2841061SN/Atemplate <class Impl> 2851060SN/Avoid 2862292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2871060SN/A{ 2881060SN/A DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2891060SN/A iewQueue = iq_ptr; 2901060SN/A 2911060SN/A // Setup wire to get instructions from IEW. 2921060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2931060SN/A} 2941060SN/A 2951061SN/Atemplate <class Impl> 2961060SN/Avoid 2972316SN/ADefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 2982316SN/A{ 2992316SN/A fetchStage = fetch_stage; 3002316SN/A} 3012316SN/A 3022316SN/Atemplate <class Impl> 3032316SN/Avoid 3042292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3052292SN/A{ 3062292SN/A iewStage = iew_stage; 3072292SN/A} 3082292SN/A 3092292SN/Atemplate<class Impl> 3102292SN/Avoid 3112292SN/ADefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3122292SN/A{ 3132292SN/A DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3142292SN/A activeThreads = at_ptr; 3152292SN/A} 3162292SN/A 3172292SN/Atemplate <class Impl> 3182292SN/Avoid 3192292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3202292SN/A{ 3212292SN/A DPRINTF(Commit, "Setting rename map pointers.\n"); 3222292SN/A 3232292SN/A for (int i=0; i < numThreads; i++) { 3242292SN/A renameMap[i] = &rm_ptr[i]; 3252292SN/A } 3262292SN/A} 3272292SN/A 3282292SN/Atemplate <class Impl> 3292292SN/Avoid 3302292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3311060SN/A{ 3321060SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3331060SN/A rob = rob_ptr; 3341060SN/A} 3351060SN/A 3361061SN/Atemplate <class Impl> 3371060SN/Avoid 3382292SN/ADefaultCommit<Impl>::initStage() 3391060SN/A{ 3402292SN/A rob->setActiveThreads(activeThreads); 3412292SN/A rob->resetEntries(); 3421060SN/A 3432292SN/A // Broadcast the number of free entries. 3442292SN/A for (int i=0; i < numThreads; i++) { 3452292SN/A toIEW->commitInfo[i].usedROB = true; 3462292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3471060SN/A } 3481060SN/A 3492292SN/A cpu->activityThisCycle(); 3501060SN/A} 3511060SN/A 3521061SN/Atemplate <class Impl> 3532863Sktlim@umich.edubool 3542843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3551060SN/A{ 3562843Sktlim@umich.edu drainPending = true; 3572863Sktlim@umich.edu 3582863Sktlim@umich.edu // If it's already drained, return true. 3592863Sktlim@umich.edu if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 3602863Sktlim@umich.edu cpu->signalDrained(); 3612863Sktlim@umich.edu return true; 3622863Sktlim@umich.edu } 3632863Sktlim@umich.edu 3642863Sktlim@umich.edu return false; 3652316SN/A} 3662316SN/A 3672316SN/Atemplate <class Impl> 3682316SN/Avoid 3692843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3702316SN/A{ 3712316SN/A switchedOut = true; 3722843Sktlim@umich.edu drainPending = false; 3732307SN/A rob->switchOut(); 3742307SN/A} 3752307SN/A 3762307SN/Atemplate <class Impl> 3772307SN/Avoid 3782843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3792843Sktlim@umich.edu{ 3802843Sktlim@umich.edu} 3812843Sktlim@umich.edu 3822843Sktlim@umich.edutemplate <class Impl> 3832843Sktlim@umich.eduvoid 3842307SN/ADefaultCommit<Impl>::takeOverFrom() 3852307SN/A{ 3862316SN/A switchedOut = false; 3872307SN/A _status = Active; 3882307SN/A _nextStatus = Inactive; 3892307SN/A for (int i=0; i < numThreads; i++) { 3902307SN/A commitStatus[i] = Idle; 3912307SN/A changedROBNumEntries[i] = false; 3922307SN/A trapSquash[i] = false; 3932680Sktlim@umich.edu tcSquash[i] = false; 3942307SN/A } 3952307SN/A squashCounter = 0; 3962307SN/A rob->takeOverFrom(); 3972307SN/A} 3982307SN/A 3992307SN/Atemplate <class Impl> 4002307SN/Avoid 4012292SN/ADefaultCommit<Impl>::updateStatus() 4022132SN/A{ 4032316SN/A // reset ROB changed variable 4042316SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4052316SN/A while (threads != (*activeThreads).end()) { 4062316SN/A unsigned tid = *threads++; 4072316SN/A changedROBNumEntries[tid] = false; 4082316SN/A 4092316SN/A // Also check if any of the threads has a trap pending 4102316SN/A if (commitStatus[tid] == TrapPending || 4112316SN/A commitStatus[tid] == FetchTrapPending) { 4122316SN/A _nextStatus = Active; 4132316SN/A } 4142292SN/A } 4152292SN/A 4162292SN/A if (_nextStatus == Inactive && _status == Active) { 4172292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4182733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4192292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4202292SN/A DPRINTF(Activity, "Activating stage.\n"); 4212733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4222292SN/A } 4232292SN/A 4242292SN/A _status = _nextStatus; 4252292SN/A} 4262292SN/A 4272292SN/Atemplate <class Impl> 4282292SN/Avoid 4292292SN/ADefaultCommit<Impl>::setNextStatus() 4302292SN/A{ 4312292SN/A int squashes = 0; 4322292SN/A 4332292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4342292SN/A 4352292SN/A while (threads != (*activeThreads).end()) { 4362292SN/A unsigned tid = *threads++; 4372292SN/A 4382292SN/A if (commitStatus[tid] == ROBSquashing) { 4392292SN/A squashes++; 4402292SN/A } 4412292SN/A } 4422292SN/A 4432702Sktlim@umich.edu squashCounter = squashes; 4442292SN/A 4452292SN/A // If commit is currently squashing, then it will have activity for the 4462292SN/A // next cycle. Set its next status as active. 4472292SN/A if (squashCounter) { 4482292SN/A _nextStatus = Active; 4492292SN/A } 4502292SN/A} 4512292SN/A 4522292SN/Atemplate <class Impl> 4532292SN/Abool 4542292SN/ADefaultCommit<Impl>::changedROBEntries() 4552292SN/A{ 4562292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4572292SN/A 4582292SN/A while (threads != (*activeThreads).end()) { 4592292SN/A unsigned tid = *threads++; 4602292SN/A 4612292SN/A if (changedROBNumEntries[tid]) { 4622292SN/A return true; 4632292SN/A } 4642292SN/A } 4652292SN/A 4662292SN/A return false; 4672292SN/A} 4682292SN/A 4692292SN/Atemplate <class Impl> 4702292SN/Aunsigned 4712292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4722292SN/A{ 4732292SN/A return rob->numFreeEntries(tid); 4742292SN/A} 4752292SN/A 4762292SN/Atemplate <class Impl> 4772292SN/Avoid 4782292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4792292SN/A{ 4802292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4812292SN/A 4822292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4832292SN/A 4842292SN/A trap->schedule(curTick + trapLatency); 4852292SN/A 4862292SN/A thread[tid]->trapPending = true; 4872292SN/A} 4882292SN/A 4892292SN/Atemplate <class Impl> 4902292SN/Avoid 4912680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4922292SN/A{ 4932680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4942292SN/A 4952680Sktlim@umich.edu tcSquash[tid] = true; 4962292SN/A} 4972292SN/A 4982292SN/Atemplate <class Impl> 4992292SN/Avoid 5002316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 5012292SN/A{ 5022292SN/A // If we want to include the squashing instruction in the squash, 5032292SN/A // then use one older sequence number. 5042292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5052292SN/A // all instructions of this thread. 5062292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5072292SN/A 0 : rob->readHeadInst(tid)->seqNum - 1;; 5082292SN/A 5092292SN/A // All younger instructions will be squashed. Set the sequence 5102292SN/A // number as the youngest instruction in the ROB (0 in this case. 5112292SN/A // Hopefully nothing breaks.) 5122292SN/A youngestSeqNum[tid] = 0; 5132292SN/A 5142292SN/A rob->squash(squashed_inst, tid); 5152292SN/A changedROBNumEntries[tid] = true; 5162292SN/A 5172292SN/A // Send back the sequence number of the squashed instruction. 5182292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5192292SN/A 5202292SN/A // Send back the squash signal to tell stages that they should 5212292SN/A // squash. 5222292SN/A toIEW->commitInfo[tid].squash = true; 5232292SN/A 5242292SN/A // Send back the rob squashing signal so other stages know that 5252292SN/A // the ROB is in the process of squashing. 5262292SN/A toIEW->commitInfo[tid].robSquashing = true; 5272292SN/A 5282292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5292292SN/A 5302316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5312316SN/A} 5322292SN/A 5332316SN/Atemplate <class Impl> 5342316SN/Avoid 5352316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5362316SN/A{ 5372316SN/A squashAll(tid); 5382316SN/A 5392316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5402316SN/A 5412316SN/A thread[tid]->trapPending = false; 5422316SN/A thread[tid]->inSyscall = false; 5432316SN/A 5442316SN/A trapSquash[tid] = false; 5452316SN/A 5462316SN/A commitStatus[tid] = ROBSquashing; 5472316SN/A cpu->activityThisCycle(); 5482316SN/A} 5492316SN/A 5502316SN/Atemplate <class Impl> 5512316SN/Avoid 5522680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5532316SN/A{ 5542316SN/A squashAll(tid); 5552292SN/A 5562680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5572292SN/A 5582292SN/A thread[tid]->inSyscall = false; 5592292SN/A assert(!thread[tid]->trapPending); 5602316SN/A 5612292SN/A commitStatus[tid] = ROBSquashing; 5622292SN/A cpu->activityThisCycle(); 5632292SN/A 5642680Sktlim@umich.edu tcSquash[tid] = false; 5652292SN/A} 5662292SN/A 5672292SN/Atemplate <class Impl> 5682292SN/Avoid 5692292SN/ADefaultCommit<Impl>::tick() 5702292SN/A{ 5712292SN/A wroteToTimeBuffer = false; 5722292SN/A _nextStatus = Inactive; 5732292SN/A 5742843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5752843Sktlim@umich.edu cpu->signalDrained(); 5762843Sktlim@umich.edu drainPending = false; 5772316SN/A return; 5782316SN/A } 5792316SN/A 5802292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 5812292SN/A 5822316SN/A // Check if any of the threads are done squashing. Change the 5832316SN/A // status if they are done. 5842292SN/A while (threads != (*activeThreads).end()) { 5852292SN/A unsigned tid = *threads++; 5862292SN/A 5872292SN/A if (commitStatus[tid] == ROBSquashing) { 5882292SN/A 5892292SN/A if (rob->isDoneSquashing(tid)) { 5902292SN/A commitStatus[tid] = Running; 5912292SN/A } else { 5922292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5932292SN/A "insts this cycle.\n", tid); 5942702Sktlim@umich.edu rob->doSquash(tid); 5952702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5962702Sktlim@umich.edu wroteToTimeBuffer = true; 5972292SN/A } 5982292SN/A } 5992292SN/A } 6002292SN/A 6012292SN/A commit(); 6022292SN/A 6032292SN/A markCompletedInsts(); 6042292SN/A 6052292SN/A threads = (*activeThreads).begin(); 6062292SN/A 6072292SN/A while (threads != (*activeThreads).end()) { 6082292SN/A unsigned tid = *threads++; 6092292SN/A 6102292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6112292SN/A // The ROB has more instructions it can commit. Its next status 6122292SN/A // will be active. 6132292SN/A _nextStatus = Active; 6142292SN/A 6152292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6162292SN/A 6172292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6182292SN/A " ROB and ready to commit\n", 6192292SN/A tid, inst->seqNum, inst->readPC()); 6202292SN/A 6212292SN/A } else if (!rob->isEmpty(tid)) { 6222292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6232292SN/A 6242292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6252292SN/A "%#x is head of ROB and not ready\n", 6262292SN/A tid, inst->seqNum, inst->readPC()); 6272292SN/A } 6282292SN/A 6292292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6302292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6312292SN/A } 6322292SN/A 6332292SN/A 6342292SN/A if (wroteToTimeBuffer) { 6352316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6362292SN/A cpu->activityThisCycle(); 6372292SN/A } 6382292SN/A 6392292SN/A updateStatus(); 6402292SN/A} 6412292SN/A 6422292SN/Atemplate <class Impl> 6432292SN/Avoid 6442292SN/ADefaultCommit<Impl>::commit() 6452292SN/A{ 6462292SN/A 6471060SN/A ////////////////////////////////////// 6481060SN/A // Check for interrupts 6491060SN/A ////////////////////////////////////// 6501060SN/A 6511858SN/A#if FULL_SYSTEM 6522316SN/A // Process interrupts if interrupts are enabled, not in PAL mode, 6532316SN/A // and no other traps or external squashes are currently pending. 6542316SN/A // @todo: Allow other threads to handle interrupts. 6552292SN/A if (cpu->checkInterrupts && 6561060SN/A cpu->check_interrupts() && 6572292SN/A !cpu->inPalMode(readPC()) && 6582292SN/A !trapSquash[0] && 6592680Sktlim@umich.edu !tcSquash[0]) { 6602316SN/A // Tell fetch that there is an interrupt pending. This will 6612316SN/A // make fetch wait until it sees a non PAL-mode PC, at which 6622316SN/A // point it stops fetching instructions. 6632292SN/A toIEW->commitInfo[0].interruptPending = true; 6641060SN/A 6652316SN/A // Wait until the ROB is empty and all stores have drained in 6662316SN/A // order to enter the interrupt. 6672292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6682292SN/A // Not sure which thread should be the one to interrupt. For now 6692292SN/A // always do thread 0. 6702292SN/A assert(!thread[0]->inSyscall); 6712292SN/A thread[0]->inSyscall = true; 6722292SN/A 6732292SN/A // CPU will handle implementation of the interrupt. 6742292SN/A cpu->processInterrupts(); 6752292SN/A 6762292SN/A // Now squash or record that I need to squash this cycle. 6772292SN/A commitStatus[0] = TrapPending; 6782292SN/A 6792292SN/A // Exit state update mode to avoid accidental updating. 6802292SN/A thread[0]->inSyscall = false; 6812292SN/A 6822292SN/A // Generate trap squash event. 6832292SN/A generateTrapEvent(0); 6842292SN/A 6852292SN/A toIEW->commitInfo[0].clearInterrupt = true; 6862292SN/A 6872292SN/A DPRINTF(Commit, "Interrupt detected.\n"); 6882292SN/A } else { 6892292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6902292SN/A } 6911060SN/A } 6921060SN/A#endif // FULL_SYSTEM 6931060SN/A 6941060SN/A //////////////////////////////////// 6952316SN/A // Check for any possible squashes, handle them first 6961060SN/A //////////////////////////////////// 6971060SN/A 6982292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6991060SN/A 7002292SN/A while (threads != (*activeThreads).end()) { 7012292SN/A unsigned tid = *threads++; 7021060SN/A 7032292SN/A // Not sure which one takes priority. I think if we have 7042292SN/A // both, that's a bad sign. 7052292SN/A if (trapSquash[tid] == true) { 7062680Sktlim@umich.edu assert(!tcSquash[tid]); 7072292SN/A squashFromTrap(tid); 7082680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7092680Sktlim@umich.edu squashFromTC(tid); 7102292SN/A } 7111061SN/A 7122292SN/A // Squashed sequence number must be older than youngest valid 7132292SN/A // instruction in the ROB. This prevents squashes from younger 7142292SN/A // instructions overriding squashes from older instructions. 7152292SN/A if (fromIEW->squash[tid] && 7162292SN/A commitStatus[tid] != TrapPending && 7172292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7181061SN/A 7192292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7202292SN/A tid, 7212292SN/A fromIEW->mispredPC[tid], 7222292SN/A fromIEW->squashedSeqNum[tid]); 7231061SN/A 7242292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7252292SN/A tid, 7262292SN/A fromIEW->nextPC[tid]); 7271061SN/A 7282292SN/A commitStatus[tid] = ROBSquashing; 7291061SN/A 7302292SN/A // If we want to include the squashing instruction in the squash, 7312292SN/A // then use one older sequence number. 7322292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7331062SN/A 7342292SN/A if (fromIEW->includeSquashInst[tid] == true) 7352292SN/A squashed_inst--; 7362292SN/A 7372292SN/A // All younger instructions will be squashed. Set the sequence 7382292SN/A // number as the youngest instruction in the ROB. 7392292SN/A youngestSeqNum[tid] = squashed_inst; 7402292SN/A 7412292SN/A rob->squash(squashed_inst, tid); 7422292SN/A changedROBNumEntries[tid] = true; 7432292SN/A 7442292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7452292SN/A 7462292SN/A toIEW->commitInfo[tid].squash = true; 7472292SN/A 7482292SN/A // Send back the rob squashing signal so other stages know that 7492292SN/A // the ROB is in the process of squashing. 7502292SN/A toIEW->commitInfo[tid].robSquashing = true; 7512292SN/A 7522292SN/A toIEW->commitInfo[tid].branchMispredict = 7532292SN/A fromIEW->branchMispredict[tid]; 7542292SN/A 7552292SN/A toIEW->commitInfo[tid].branchTaken = 7562292SN/A fromIEW->branchTaken[tid]; 7572292SN/A 7582292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7592292SN/A 7602316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7612292SN/A 7622292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7632292SN/A ++branchMispredicts; 7642292SN/A } 7651062SN/A } 7662292SN/A 7671060SN/A } 7681060SN/A 7692292SN/A setNextStatus(); 7702292SN/A 7712292SN/A if (squashCounter != numThreads) { 7721061SN/A // If we're not currently squashing, then get instructions. 7731060SN/A getInsts(); 7741060SN/A 7751061SN/A // Try to commit any instructions. 7761060SN/A commitInsts(); 7771060SN/A } 7781060SN/A 7792292SN/A //Check for any activity 7802292SN/A threads = (*activeThreads).begin(); 7812292SN/A 7822292SN/A while (threads != (*activeThreads).end()) { 7832292SN/A unsigned tid = *threads++; 7842292SN/A 7852292SN/A if (changedROBNumEntries[tid]) { 7862292SN/A toIEW->commitInfo[tid].usedROB = true; 7872292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 7882292SN/A 7892292SN/A if (rob->isEmpty(tid)) { 7902292SN/A toIEW->commitInfo[tid].emptyROB = true; 7912292SN/A } 7922292SN/A 7932292SN/A wroteToTimeBuffer = true; 7942292SN/A changedROBNumEntries[tid] = false; 7952292SN/A } 7961060SN/A } 7971060SN/A} 7981060SN/A 7991061SN/Atemplate <class Impl> 8001060SN/Avoid 8012292SN/ADefaultCommit<Impl>::commitInsts() 8021060SN/A{ 8031060SN/A //////////////////////////////////// 8041060SN/A // Handle commit 8052316SN/A // Note that commit will be handled prior to putting new 8062316SN/A // instructions in the ROB so that the ROB only tries to commit 8072316SN/A // instructions it has in this current cycle, and not instructions 8082316SN/A // it is writing in during this cycle. Can't commit and squash 8092316SN/A // things at the same time... 8101060SN/A //////////////////////////////////// 8111060SN/A 8122292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8131060SN/A 8141060SN/A unsigned num_committed = 0; 8151060SN/A 8162292SN/A DynInstPtr head_inst; 8172316SN/A 8181060SN/A // Commit as many instructions as possible until the commit bandwidth 8191060SN/A // limit is reached, or it becomes impossible to commit any more. 8202292SN/A while (num_committed < commitWidth) { 8212292SN/A int commit_thread = getCommittingThread(); 8221060SN/A 8232292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8242292SN/A break; 8252292SN/A 8262292SN/A head_inst = rob->readHeadInst(commit_thread); 8272292SN/A 8282292SN/A int tid = head_inst->threadNumber; 8292292SN/A 8302292SN/A assert(tid == commit_thread); 8312292SN/A 8322292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8332292SN/A head_inst->seqNum, tid); 8342132SN/A 8352316SN/A // If the head instruction is squashed, it is ready to retire 8362316SN/A // (be removed from the ROB) at any time. 8371060SN/A if (head_inst->isSquashed()) { 8381060SN/A 8392292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8401060SN/A "ROB.\n"); 8411060SN/A 8422292SN/A rob->retireHead(commit_thread); 8431060SN/A 8441062SN/A ++commitSquashedInsts; 8451062SN/A 8462292SN/A // Record that the number of ROB entries has changed. 8472292SN/A changedROBNumEntries[tid] = true; 8481060SN/A } else { 8492292SN/A PC[tid] = head_inst->readPC(); 8502292SN/A nextPC[tid] = head_inst->readNextPC(); 8512292SN/A 8521060SN/A // Increment the total number of non-speculative instructions 8531060SN/A // executed. 8541060SN/A // Hack for now: it really shouldn't happen until after the 8551061SN/A // commit is deemed to be successful, but this count is needed 8561061SN/A // for syscalls. 8572292SN/A thread[tid]->funcExeInst++; 8581060SN/A 8591060SN/A // Try to commit the head instruction. 8601060SN/A bool commit_success = commitHead(head_inst, num_committed); 8611060SN/A 8621062SN/A if (commit_success) { 8631060SN/A ++num_committed; 8641060SN/A 8652292SN/A changedROBNumEntries[tid] = true; 8662292SN/A 8672292SN/A // Set the doneSeqNum to the youngest committed instruction. 8682292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 8691060SN/A 8701062SN/A ++commitCommittedInsts; 8711062SN/A 8722292SN/A // To match the old model, don't count nops and instruction 8732292SN/A // prefetches towards the total commit count. 8742292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 8752292SN/A cpu->instDone(tid); 8761062SN/A } 8772292SN/A 8782292SN/A PC[tid] = nextPC[tid]; 8792307SN/A nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 8802292SN/A#if FULL_SYSTEM 8812292SN/A int count = 0; 8822292SN/A Addr oldpc; 8832292SN/A do { 8842316SN/A // Debug statement. Checks to make sure we're not 8852316SN/A // currently updating state while handling PC events. 8862292SN/A if (count == 0) 8872316SN/A assert(!thread[tid]->inSyscall && 8882316SN/A !thread[tid]->trapPending); 8892292SN/A oldpc = PC[tid]; 8902292SN/A cpu->system->pcEventQueue.service( 8912690Sktlim@umich.edu thread[tid]->getTC()); 8922292SN/A count++; 8932292SN/A } while (oldpc != PC[tid]); 8942292SN/A if (count > 1) { 8952292SN/A DPRINTF(Commit, "PC skip function event, stopping commit\n"); 8962292SN/A break; 8972292SN/A } 8982292SN/A#endif 8991060SN/A } else { 9002292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9012292SN/A "[tid:%i] [sn:%i].\n", 9022292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9031060SN/A break; 9041060SN/A } 9051060SN/A } 9061060SN/A } 9071062SN/A 9081063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9092292SN/A numCommittedDist.sample(num_committed); 9102307SN/A 9112307SN/A if (num_committed == commitWidth) { 9122349SN/A commitEligibleSamples++; 9132307SN/A } 9141060SN/A} 9151060SN/A 9161061SN/Atemplate <class Impl> 9171060SN/Abool 9182292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9191060SN/A{ 9201060SN/A assert(head_inst); 9211060SN/A 9222292SN/A int tid = head_inst->threadNumber; 9232292SN/A 9242316SN/A // If the instruction is not executed yet, then it will need extra 9252316SN/A // handling. Signal backwards that it should be executed. 9261061SN/A if (!head_inst->isExecuted()) { 9271061SN/A // Keep this number correct. We have not yet actually executed 9281061SN/A // and committed this instruction. 9292292SN/A thread[tid]->funcExeInst--; 9301062SN/A 9312731Sktlim@umich.edu head_inst->setAtCommit(); 9321060SN/A 9332292SN/A if (head_inst->isNonSpeculative() || 9342348SN/A head_inst->isStoreConditional() || 9352292SN/A head_inst->isMemBarrier() || 9362292SN/A head_inst->isWriteBarrier()) { 9372316SN/A 9382316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9392316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9402316SN/A head_inst->seqNum, head_inst->readPC()); 9412316SN/A 9422292SN/A#if !FULL_SYSTEM 9432316SN/A // Hack to make sure syscalls/memory barriers/quiesces 9442316SN/A // aren't executed until all stores write back their data. 9452316SN/A // This direct communication shouldn't be used for 9462316SN/A // anything other than this. 9472292SN/A if (inst_num > 0 || iewStage->hasStoresToWB()) 9482292SN/A#else 9492292SN/A if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 9502292SN/A head_inst->isQuiesce()) && 9512292SN/A iewStage->hasStoresToWB()) 9522292SN/A#endif 9532292SN/A { 9542292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9552292SN/A return false; 9562292SN/A } 9572292SN/A 9582292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9591061SN/A 9601061SN/A // Change the instruction so it won't try to commit again until 9611061SN/A // it is executed. 9621061SN/A head_inst->clearCanCommit(); 9631061SN/A 9641062SN/A ++commitNonSpecStalls; 9651062SN/A 9661061SN/A return false; 9672292SN/A } else if (head_inst->isLoad()) { 9682292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9692292SN/A head_inst->seqNum, head_inst->readPC()); 9702292SN/A 9712292SN/A // Send back the non-speculative instruction's sequence 9722316SN/A // number. Tell the lsq to re-execute the load. 9732292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9742292SN/A toIEW->commitInfo[tid].uncached = true; 9752292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 9762292SN/A 9772292SN/A head_inst->clearCanCommit(); 9782292SN/A 9792292SN/A return false; 9801061SN/A } else { 9812292SN/A panic("Trying to commit un-executed instruction " 9821061SN/A "of unknown type!\n"); 9831061SN/A } 9841060SN/A } 9851060SN/A 9862316SN/A if (head_inst->isThreadSync()) { 9872292SN/A // Not handled for now. 9882316SN/A panic("Thread sync instructions are not handled yet.\n"); 9892132SN/A } 9902132SN/A 9912316SN/A // Stores mark themselves as completed. 9922310SN/A if (!head_inst->isStore()) { 9932310SN/A head_inst->setCompleted(); 9942310SN/A } 9952310SN/A 9962733Sktlim@umich.edu#if USE_CHECKER 9972316SN/A // Use checker prior to updating anything due to traps or PC 9982316SN/A // based events. 9992316SN/A if (cpu->checker) { 10002732Sktlim@umich.edu cpu->checker->verify(head_inst); 10011060SN/A } 10022733Sktlim@umich.edu#endif 10031060SN/A 10041060SN/A // Check if the instruction caused a fault. If so, trap. 10052132SN/A Fault inst_fault = head_inst->getFault(); 10061681SN/A 10072112SN/A if (inst_fault != NoFault) { 10082316SN/A head_inst->setCompleted(); 10092316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10102316SN/A head_inst->seqNum, head_inst->readPC()); 10112292SN/A 10122316SN/A if (iewStage->hasStoresToWB() || inst_num > 0) { 10132316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10142316SN/A return false; 10152316SN/A } 10162310SN/A 10172733Sktlim@umich.edu#if USE_CHECKER 10182316SN/A if (cpu->checker && head_inst->isStore()) { 10192732Sktlim@umich.edu cpu->checker->verify(head_inst); 10202316SN/A } 10212733Sktlim@umich.edu#endif 10222292SN/A 10232316SN/A assert(!thread[tid]->inSyscall); 10242292SN/A 10252316SN/A // Mark that we're in state update mode so that the trap's 10262316SN/A // execution doesn't generate extra squashes. 10272316SN/A thread[tid]->inSyscall = true; 10282292SN/A 10292316SN/A // DTB will sometimes need the machine instruction for when 10302316SN/A // faults happen. So we will set it here, prior to the DTB 10312316SN/A // possibly needing it for its fault. 10322316SN/A thread[tid]->setInst( 10332316SN/A static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10342292SN/A 10352316SN/A // Execute the trap. Although it's slightly unrealistic in 10362316SN/A // terms of timing (as it doesn't wait for the full timing of 10372316SN/A // the trap event to complete before updating state), it's 10382316SN/A // needed to update the state as soon as possible. This 10392316SN/A // prevents external agents from changing any specific state 10402316SN/A // that the trap need. 10412316SN/A cpu->trap(inst_fault, tid); 10422292SN/A 10432316SN/A // Exit state update mode to avoid accidental updating. 10442316SN/A thread[tid]->inSyscall = false; 10452292SN/A 10462316SN/A commitStatus[tid] = TrapPending; 10472292SN/A 10482316SN/A // Generate trap squash event. 10492316SN/A generateTrapEvent(tid); 10502316SN/A 10512316SN/A return false; 10521060SN/A } 10531060SN/A 10542301SN/A updateComInstStats(head_inst); 10552132SN/A 10562132SN/A if (head_inst->traceData) { 10572292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 10582292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 10592132SN/A head_inst->traceData->finalize(); 10602292SN/A head_inst->traceData = NULL; 10611060SN/A } 10621060SN/A 10632292SN/A // Update the commit rename map 10642292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 10652292SN/A renameMap[tid]->setEntry(head_inst->destRegIdx(i), 10662292SN/A head_inst->renamedDestRegIdx(i)); 10671060SN/A } 10681062SN/A 10692292SN/A // Finally clear the head ROB entry. 10702292SN/A rob->retireHead(tid); 10711060SN/A 10721060SN/A // Return true to indicate that we have committed an instruction. 10731060SN/A return true; 10741060SN/A} 10751060SN/A 10761061SN/Atemplate <class Impl> 10771060SN/Avoid 10782292SN/ADefaultCommit<Impl>::getInsts() 10791060SN/A{ 10802316SN/A // Read any renamed instructions and place them into the ROB. 10811061SN/A int insts_to_process = min((int)renameWidth, fromRename->size); 10821061SN/A 10832292SN/A for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 10841060SN/A { 10852292SN/A DynInstPtr inst = fromRename->insts[inst_num]; 10862292SN/A int tid = inst->threadNumber; 10872292SN/A 10882292SN/A if (!inst->isSquashed() && 10892292SN/A commitStatus[tid] != ROBSquashing) { 10902292SN/A changedROBNumEntries[tid] = true; 10912292SN/A 10922292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 10932292SN/A inst->readPC(), inst->seqNum, tid); 10942292SN/A 10952292SN/A rob->insertInst(inst); 10962292SN/A 10972292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 10982292SN/A 10992292SN/A youngestSeqNum[tid] = inst->seqNum; 11001061SN/A } else { 11012292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11021061SN/A "squashed, skipping.\n", 11032292SN/A inst->readPC(), inst->seqNum, tid); 11041061SN/A } 11051060SN/A } 11061060SN/A} 11071060SN/A 11081061SN/Atemplate <class Impl> 11091060SN/Avoid 11102292SN/ADefaultCommit<Impl>::markCompletedInsts() 11111060SN/A{ 11121060SN/A // Grab completed insts out of the IEW instruction queue, and mark 11131060SN/A // instructions completed within the ROB. 11141060SN/A for (int inst_num = 0; 11151681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 11161060SN/A ++inst_num) 11171060SN/A { 11182292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 11192316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 11202316SN/A "within ROB.\n", 11212292SN/A fromIEW->insts[inst_num]->threadNumber, 11222292SN/A fromIEW->insts[inst_num]->readPC(), 11232292SN/A fromIEW->insts[inst_num]->seqNum); 11241060SN/A 11252292SN/A // Mark the instruction as ready to commit. 11262292SN/A fromIEW->insts[inst_num]->setCanCommit(); 11272292SN/A } 11281060SN/A } 11291060SN/A} 11301060SN/A 11311061SN/Atemplate <class Impl> 11322292SN/Abool 11332292SN/ADefaultCommit<Impl>::robDoneSquashing() 11341060SN/A{ 11352292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11362292SN/A 11372292SN/A while (threads != (*activeThreads).end()) { 11382292SN/A unsigned tid = *threads++; 11392292SN/A 11402292SN/A if (!rob->isDoneSquashing(tid)) 11412292SN/A return false; 11422292SN/A } 11432292SN/A 11442292SN/A return true; 11451060SN/A} 11462292SN/A 11472301SN/Atemplate <class Impl> 11482301SN/Avoid 11492301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 11502301SN/A{ 11512301SN/A unsigned thread = inst->threadNumber; 11522301SN/A 11532301SN/A // 11542301SN/A // Pick off the software prefetches 11552301SN/A // 11562301SN/A#ifdef TARGET_ALPHA 11572301SN/A if (inst->isDataPrefetch()) { 11582316SN/A statComSwp[thread]++; 11592301SN/A } else { 11602316SN/A statComInst[thread]++; 11612301SN/A } 11622301SN/A#else 11632316SN/A statComInst[thread]++; 11642301SN/A#endif 11652301SN/A 11662301SN/A // 11672301SN/A // Control Instructions 11682301SN/A // 11692301SN/A if (inst->isControl()) 11702316SN/A statComBranches[thread]++; 11712301SN/A 11722301SN/A // 11732301SN/A // Memory references 11742301SN/A // 11752301SN/A if (inst->isMemRef()) { 11762316SN/A statComRefs[thread]++; 11772301SN/A 11782301SN/A if (inst->isLoad()) { 11792316SN/A statComLoads[thread]++; 11802301SN/A } 11812301SN/A } 11822301SN/A 11832301SN/A if (inst->isMemBarrier()) { 11842316SN/A statComMembars[thread]++; 11852301SN/A } 11862301SN/A} 11872301SN/A 11882292SN/A//////////////////////////////////////// 11892292SN/A// // 11902316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 11912292SN/A// // 11922292SN/A//////////////////////////////////////// 11932292SN/Atemplate <class Impl> 11942292SN/Aint 11952292SN/ADefaultCommit<Impl>::getCommittingThread() 11962292SN/A{ 11972292SN/A if (numThreads > 1) { 11982292SN/A switch (commitPolicy) { 11992292SN/A 12002292SN/A case Aggressive: 12012292SN/A //If Policy is Aggressive, commit will call 12022292SN/A //this function multiple times per 12032292SN/A //cycle 12042292SN/A return oldestReady(); 12052292SN/A 12062292SN/A case RoundRobin: 12072292SN/A return roundRobin(); 12082292SN/A 12092292SN/A case OldestReady: 12102292SN/A return oldestReady(); 12112292SN/A 12122292SN/A default: 12132292SN/A return -1; 12142292SN/A } 12152292SN/A } else { 12162292SN/A int tid = (*activeThreads).front(); 12172292SN/A 12182292SN/A if (commitStatus[tid] == Running || 12192292SN/A commitStatus[tid] == Idle || 12202292SN/A commitStatus[tid] == FetchTrapPending) { 12212292SN/A return tid; 12222292SN/A } else { 12232292SN/A return -1; 12242292SN/A } 12252292SN/A } 12262292SN/A} 12272292SN/A 12282292SN/Atemplate<class Impl> 12292292SN/Aint 12302292SN/ADefaultCommit<Impl>::roundRobin() 12312292SN/A{ 12322292SN/A list<unsigned>::iterator pri_iter = priority_list.begin(); 12332292SN/A list<unsigned>::iterator end = priority_list.end(); 12342292SN/A 12352292SN/A while (pri_iter != end) { 12362292SN/A unsigned tid = *pri_iter; 12372292SN/A 12382292SN/A if (commitStatus[tid] == Running || 12392831Sksewell@umich.edu commitStatus[tid] == Idle || 12402831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 12412292SN/A 12422292SN/A if (rob->isHeadReady(tid)) { 12432292SN/A priority_list.erase(pri_iter); 12442292SN/A priority_list.push_back(tid); 12452292SN/A 12462292SN/A return tid; 12472292SN/A } 12482292SN/A } 12492292SN/A 12502292SN/A pri_iter++; 12512292SN/A } 12522292SN/A 12532292SN/A return -1; 12542292SN/A} 12552292SN/A 12562292SN/Atemplate<class Impl> 12572292SN/Aint 12582292SN/ADefaultCommit<Impl>::oldestReady() 12592292SN/A{ 12602292SN/A unsigned oldest = 0; 12612292SN/A bool first = true; 12622292SN/A 12632292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 12642292SN/A 12652292SN/A while (threads != (*activeThreads).end()) { 12662292SN/A unsigned tid = *threads++; 12672292SN/A 12682292SN/A if (!rob->isEmpty(tid) && 12692292SN/A (commitStatus[tid] == Running || 12702292SN/A commitStatus[tid] == Idle || 12712292SN/A commitStatus[tid] == FetchTrapPending)) { 12722292SN/A 12732292SN/A if (rob->isHeadReady(tid)) { 12742292SN/A 12752292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 12762292SN/A 12772292SN/A if (first) { 12782292SN/A oldest = tid; 12792292SN/A first = false; 12802292SN/A } else if (head_inst->seqNum < oldest) { 12812292SN/A oldest = tid; 12822292SN/A } 12832292SN/A } 12842292SN/A } 12852292SN/A } 12862292SN/A 12872292SN/A if (!first) { 12882292SN/A return oldest; 12892292SN/A } else { 12902292SN/A return -1; 12912292SN/A } 12922292SN/A} 1293