commit_impl.hh revision 2731
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312292SN/A#include <algorithm> 322329SN/A#include <string> 332292SN/A 342292SN/A#include "base/loader/symtab.hh" 351060SN/A#include "base/timebuf.hh" 362316SN/A#include "cpu/checker/cpu.hh" 372292SN/A#include "cpu/exetrace.hh" 381717SN/A#include "cpu/o3/commit.hh" 392292SN/A#include "cpu/o3/thread_state.hh" 402292SN/A 412292SN/Ausing namespace std; 421060SN/A 431061SN/Atemplate <class Impl> 442292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 452292SN/A unsigned _tid) 462292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 471060SN/A{ 482292SN/A this->setFlags(Event::AutoDelete); 491060SN/A} 501060SN/A 511061SN/Atemplate <class Impl> 521060SN/Avoid 532292SN/ADefaultCommit<Impl>::TrapEvent::process() 541062SN/A{ 552316SN/A // This will get reset by commit if it was switched out at the 562316SN/A // time of this event processing. 572292SN/A commit->trapSquash[tid] = true; 582292SN/A} 592292SN/A 602292SN/Atemplate <class Impl> 612292SN/Aconst char * 622292SN/ADefaultCommit<Impl>::TrapEvent::description() 632292SN/A{ 642292SN/A return "Trap event"; 652292SN/A} 662292SN/A 672292SN/Atemplate <class Impl> 682292SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 692669Sktlim@umich.edu : squashCounter(0), 702292SN/A iewToCommitDelay(params->iewToCommitDelay), 712292SN/A commitToIEWDelay(params->commitToIEWDelay), 722292SN/A renameToROBDelay(params->renameToROBDelay), 732292SN/A fetchToCommitDelay(params->commitToFetchDelay), 742292SN/A renameWidth(params->renameWidth), 752292SN/A commitWidth(params->commitWidth), 762307SN/A numThreads(params->numberOfThreads), 772678Sktlim@umich.edu switchPending(false), 782316SN/A switchedOut(false), 792316SN/A trapLatency(params->trapLatency), 802316SN/A fetchTrapLatency(params->fetchTrapLatency) 812292SN/A{ 822292SN/A _status = Active; 832292SN/A _nextStatus = Inactive; 842292SN/A string policy = params->smtCommitPolicy; 852292SN/A 862292SN/A //Convert string to lowercase 872292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 882292SN/A (int(*)(int)) tolower); 892292SN/A 902292SN/A //Assign commit policy 912292SN/A if (policy == "aggressive"){ 922292SN/A commitPolicy = Aggressive; 932292SN/A 942292SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 952292SN/A } else if (policy == "roundrobin"){ 962292SN/A commitPolicy = RoundRobin; 972292SN/A 982292SN/A //Set-Up Priority List 992292SN/A for (int tid=0; tid < numThreads; tid++) { 1002292SN/A priority_list.push_back(tid); 1012292SN/A } 1022292SN/A 1032292SN/A DPRINTF(Commit,"Commit Policy set to Round Robin."); 1042292SN/A } else if (policy == "oldestready"){ 1052292SN/A commitPolicy = OldestReady; 1062292SN/A 1072292SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1082292SN/A } else { 1092292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1102292SN/A "RoundRobin,OldestReady}"); 1112292SN/A } 1122292SN/A 1132292SN/A for (int i=0; i < numThreads; i++) { 1142292SN/A commitStatus[i] = Idle; 1152292SN/A changedROBNumEntries[i] = false; 1162292SN/A trapSquash[i] = false; 1172680Sktlim@umich.edu tcSquash[i] = false; 1182678Sktlim@umich.edu PC[i] = nextPC[i] = 0; 1192292SN/A } 1202292SN/A 1212292SN/A fetchFaultTick = 0; 1222292SN/A fetchTrapWait = 0; 1232292SN/A} 1242292SN/A 1252292SN/Atemplate <class Impl> 1262292SN/Astd::string 1272292SN/ADefaultCommit<Impl>::name() const 1282292SN/A{ 1292292SN/A return cpu->name() + ".commit"; 1302292SN/A} 1312292SN/A 1322292SN/Atemplate <class Impl> 1332292SN/Avoid 1342292SN/ADefaultCommit<Impl>::regStats() 1352132SN/A{ 1362301SN/A using namespace Stats; 1371062SN/A commitCommittedInsts 1381062SN/A .name(name() + ".commitCommittedInsts") 1391062SN/A .desc("The number of committed instructions") 1401062SN/A .prereq(commitCommittedInsts); 1411062SN/A commitSquashedInsts 1421062SN/A .name(name() + ".commitSquashedInsts") 1431062SN/A .desc("The number of squashed insts skipped by commit") 1441062SN/A .prereq(commitSquashedInsts); 1451062SN/A commitSquashEvents 1461062SN/A .name(name() + ".commitSquashEvents") 1471062SN/A .desc("The number of times commit is told to squash") 1481062SN/A .prereq(commitSquashEvents); 1491062SN/A commitNonSpecStalls 1501062SN/A .name(name() + ".commitNonSpecStalls") 1511062SN/A .desc("The number of times commit has been forced to stall to " 1521062SN/A "communicate backwards") 1531062SN/A .prereq(commitNonSpecStalls); 1541062SN/A branchMispredicts 1551062SN/A .name(name() + ".branchMispredicts") 1561062SN/A .desc("The number of times a branch was mispredicted") 1571062SN/A .prereq(branchMispredicts); 1582292SN/A numCommittedDist 1591062SN/A .init(0,commitWidth,1) 1601062SN/A .name(name() + ".COM:committed_per_cycle") 1611062SN/A .desc("Number of insts commited each cycle") 1621062SN/A .flags(Stats::pdf) 1631062SN/A ; 1642301SN/A 1652316SN/A statComInst 1662301SN/A .init(cpu->number_of_threads) 1672301SN/A .name(name() + ".COM:count") 1682301SN/A .desc("Number of instructions committed") 1692301SN/A .flags(total) 1702301SN/A ; 1712301SN/A 1722316SN/A statComSwp 1732301SN/A .init(cpu->number_of_threads) 1742301SN/A .name(name() + ".COM:swp_count") 1752301SN/A .desc("Number of s/w prefetches committed") 1762301SN/A .flags(total) 1772301SN/A ; 1782301SN/A 1792316SN/A statComRefs 1802301SN/A .init(cpu->number_of_threads) 1812301SN/A .name(name() + ".COM:refs") 1822301SN/A .desc("Number of memory references committed") 1832301SN/A .flags(total) 1842301SN/A ; 1852301SN/A 1862316SN/A statComLoads 1872301SN/A .init(cpu->number_of_threads) 1882301SN/A .name(name() + ".COM:loads") 1892301SN/A .desc("Number of loads committed") 1902301SN/A .flags(total) 1912301SN/A ; 1922301SN/A 1932316SN/A statComMembars 1942301SN/A .init(cpu->number_of_threads) 1952301SN/A .name(name() + ".COM:membars") 1962301SN/A .desc("Number of memory barriers committed") 1972301SN/A .flags(total) 1982301SN/A ; 1992301SN/A 2002316SN/A statComBranches 2012301SN/A .init(cpu->number_of_threads) 2022301SN/A .name(name() + ".COM:branches") 2032301SN/A .desc("Number of branches committed") 2042301SN/A .flags(total) 2052301SN/A ; 2062301SN/A 2072316SN/A commitEligible 2082301SN/A .init(cpu->number_of_threads) 2092301SN/A .name(name() + ".COM:bw_limited") 2102301SN/A .desc("number of insts not committed due to BW limits") 2112301SN/A .flags(total) 2122301SN/A ; 2132301SN/A 2142316SN/A commitEligibleSamples 2152301SN/A .name(name() + ".COM:bw_lim_events") 2162301SN/A .desc("number cycles where commit BW limit reached") 2172301SN/A ; 2181062SN/A} 2191062SN/A 2201062SN/Atemplate <class Impl> 2211062SN/Avoid 2222292SN/ADefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr) 2231060SN/A{ 2241060SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2251060SN/A cpu = cpu_ptr; 2262292SN/A 2272292SN/A // Commit must broadcast the number of free entries it has at the start of 2282292SN/A // the simulation, so it starts as active. 2292292SN/A cpu->activateStage(FullCPU::CommitIdx); 2302307SN/A 2312316SN/A trapLatency = cpu->cycles(trapLatency); 2322316SN/A fetchTrapLatency = cpu->cycles(fetchTrapLatency); 2331060SN/A} 2341060SN/A 2351061SN/Atemplate <class Impl> 2361060SN/Avoid 2372292SN/ADefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 2382292SN/A{ 2392292SN/A thread = threads; 2402292SN/A} 2412292SN/A 2422292SN/Atemplate <class Impl> 2432292SN/Avoid 2442292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2451060SN/A{ 2461060SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2471060SN/A timeBuffer = tb_ptr; 2481060SN/A 2491060SN/A // Setup wire to send information back to IEW. 2501060SN/A toIEW = timeBuffer->getWire(0); 2511060SN/A 2521060SN/A // Setup wire to read data from IEW (for the ROB). 2531060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2541060SN/A} 2551060SN/A 2561061SN/Atemplate <class Impl> 2571060SN/Avoid 2582292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2592292SN/A{ 2602292SN/A DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2612292SN/A fetchQueue = fq_ptr; 2622292SN/A 2632292SN/A // Setup wire to get instructions from rename (for the ROB). 2642292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2652292SN/A} 2662292SN/A 2672292SN/Atemplate <class Impl> 2682292SN/Avoid 2692292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2701060SN/A{ 2711060SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2721060SN/A renameQueue = rq_ptr; 2731060SN/A 2741060SN/A // Setup wire to get instructions from rename (for the ROB). 2751060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2761060SN/A} 2771060SN/A 2781061SN/Atemplate <class Impl> 2791060SN/Avoid 2802292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2811060SN/A{ 2821060SN/A DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2831060SN/A iewQueue = iq_ptr; 2841060SN/A 2851060SN/A // Setup wire to get instructions from IEW. 2861060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2871060SN/A} 2881060SN/A 2891061SN/Atemplate <class Impl> 2901060SN/Avoid 2912316SN/ADefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 2922316SN/A{ 2932316SN/A fetchStage = fetch_stage; 2942316SN/A} 2952316SN/A 2962316SN/Atemplate <class Impl> 2972316SN/Avoid 2982292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2992292SN/A{ 3002292SN/A iewStage = iew_stage; 3012292SN/A} 3022292SN/A 3032292SN/Atemplate<class Impl> 3042292SN/Avoid 3052292SN/ADefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3062292SN/A{ 3072292SN/A DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3082292SN/A activeThreads = at_ptr; 3092292SN/A} 3102292SN/A 3112292SN/Atemplate <class Impl> 3122292SN/Avoid 3132292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3142292SN/A{ 3152292SN/A DPRINTF(Commit, "Setting rename map pointers.\n"); 3162292SN/A 3172292SN/A for (int i=0; i < numThreads; i++) { 3182292SN/A renameMap[i] = &rm_ptr[i]; 3192292SN/A } 3202292SN/A} 3212292SN/A 3222292SN/Atemplate <class Impl> 3232292SN/Avoid 3242292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3251060SN/A{ 3261060SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3271060SN/A rob = rob_ptr; 3281060SN/A} 3291060SN/A 3301061SN/Atemplate <class Impl> 3311060SN/Avoid 3322292SN/ADefaultCommit<Impl>::initStage() 3331060SN/A{ 3342292SN/A rob->setActiveThreads(activeThreads); 3352292SN/A rob->resetEntries(); 3361060SN/A 3372292SN/A // Broadcast the number of free entries. 3382292SN/A for (int i=0; i < numThreads; i++) { 3392292SN/A toIEW->commitInfo[i].usedROB = true; 3402292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3411060SN/A } 3421060SN/A 3432292SN/A cpu->activityThisCycle(); 3441060SN/A} 3451060SN/A 3461061SN/Atemplate <class Impl> 3471060SN/Avoid 3482307SN/ADefaultCommit<Impl>::switchOut() 3491060SN/A{ 3502316SN/A switchPending = true; 3512316SN/A} 3522316SN/A 3532316SN/Atemplate <class Impl> 3542316SN/Avoid 3552316SN/ADefaultCommit<Impl>::doSwitchOut() 3562316SN/A{ 3572316SN/A switchedOut = true; 3582316SN/A switchPending = false; 3592307SN/A rob->switchOut(); 3602307SN/A} 3612307SN/A 3622307SN/Atemplate <class Impl> 3632307SN/Avoid 3642307SN/ADefaultCommit<Impl>::takeOverFrom() 3652307SN/A{ 3662316SN/A switchedOut = false; 3672307SN/A _status = Active; 3682307SN/A _nextStatus = Inactive; 3692307SN/A for (int i=0; i < numThreads; i++) { 3702307SN/A commitStatus[i] = Idle; 3712307SN/A changedROBNumEntries[i] = false; 3722307SN/A trapSquash[i] = false; 3732680Sktlim@umich.edu tcSquash[i] = false; 3742307SN/A } 3752307SN/A squashCounter = 0; 3762307SN/A rob->takeOverFrom(); 3772307SN/A} 3782307SN/A 3792307SN/Atemplate <class Impl> 3802307SN/Avoid 3812292SN/ADefaultCommit<Impl>::updateStatus() 3822132SN/A{ 3832316SN/A // reset ROB changed variable 3842316SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 3852316SN/A while (threads != (*activeThreads).end()) { 3862316SN/A unsigned tid = *threads++; 3872316SN/A changedROBNumEntries[tid] = false; 3882316SN/A 3892316SN/A // Also check if any of the threads has a trap pending 3902316SN/A if (commitStatus[tid] == TrapPending || 3912316SN/A commitStatus[tid] == FetchTrapPending) { 3922316SN/A _nextStatus = Active; 3932316SN/A } 3942292SN/A } 3952292SN/A 3962292SN/A if (_nextStatus == Inactive && _status == Active) { 3972292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 3982292SN/A cpu->deactivateStage(FullCPU::CommitIdx); 3992292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4002292SN/A DPRINTF(Activity, "Activating stage.\n"); 4012292SN/A cpu->activateStage(FullCPU::CommitIdx); 4022292SN/A } 4032292SN/A 4042292SN/A _status = _nextStatus; 4052292SN/A} 4062292SN/A 4072292SN/Atemplate <class Impl> 4082292SN/Avoid 4092292SN/ADefaultCommit<Impl>::setNextStatus() 4102292SN/A{ 4112292SN/A int squashes = 0; 4122292SN/A 4132292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4142292SN/A 4152292SN/A while (threads != (*activeThreads).end()) { 4162292SN/A unsigned tid = *threads++; 4172292SN/A 4182292SN/A if (commitStatus[tid] == ROBSquashing) { 4192292SN/A squashes++; 4202292SN/A } 4212292SN/A } 4222292SN/A 4232702Sktlim@umich.edu squashCounter = squashes; 4242292SN/A 4252292SN/A // If commit is currently squashing, then it will have activity for the 4262292SN/A // next cycle. Set its next status as active. 4272292SN/A if (squashCounter) { 4282292SN/A _nextStatus = Active; 4292292SN/A } 4302292SN/A} 4312292SN/A 4322292SN/Atemplate <class Impl> 4332292SN/Abool 4342292SN/ADefaultCommit<Impl>::changedROBEntries() 4352292SN/A{ 4362292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4372292SN/A 4382292SN/A while (threads != (*activeThreads).end()) { 4392292SN/A unsigned tid = *threads++; 4402292SN/A 4412292SN/A if (changedROBNumEntries[tid]) { 4422292SN/A return true; 4432292SN/A } 4442292SN/A } 4452292SN/A 4462292SN/A return false; 4472292SN/A} 4482292SN/A 4492292SN/Atemplate <class Impl> 4502292SN/Aunsigned 4512292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4522292SN/A{ 4532292SN/A return rob->numFreeEntries(tid); 4542292SN/A} 4552292SN/A 4562292SN/Atemplate <class Impl> 4572292SN/Avoid 4582292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4592292SN/A{ 4602292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4612292SN/A 4622292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4632292SN/A 4642292SN/A trap->schedule(curTick + trapLatency); 4652292SN/A 4662292SN/A thread[tid]->trapPending = true; 4672292SN/A} 4682292SN/A 4692292SN/Atemplate <class Impl> 4702292SN/Avoid 4712680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4722292SN/A{ 4732680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4742292SN/A 4752680Sktlim@umich.edu tcSquash[tid] = true; 4762292SN/A} 4772292SN/A 4782292SN/Atemplate <class Impl> 4792292SN/Avoid 4802316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4812292SN/A{ 4822292SN/A // If we want to include the squashing instruction in the squash, 4832292SN/A // then use one older sequence number. 4842292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4852292SN/A // all instructions of this thread. 4862292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 4872292SN/A 0 : rob->readHeadInst(tid)->seqNum - 1;; 4882292SN/A 4892292SN/A // All younger instructions will be squashed. Set the sequence 4902292SN/A // number as the youngest instruction in the ROB (0 in this case. 4912292SN/A // Hopefully nothing breaks.) 4922292SN/A youngestSeqNum[tid] = 0; 4932292SN/A 4942292SN/A rob->squash(squashed_inst, tid); 4952292SN/A changedROBNumEntries[tid] = true; 4962292SN/A 4972292SN/A // Send back the sequence number of the squashed instruction. 4982292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 4992292SN/A 5002292SN/A // Send back the squash signal to tell stages that they should 5012292SN/A // squash. 5022292SN/A toIEW->commitInfo[tid].squash = true; 5032292SN/A 5042292SN/A // Send back the rob squashing signal so other stages know that 5052292SN/A // the ROB is in the process of squashing. 5062292SN/A toIEW->commitInfo[tid].robSquashing = true; 5072292SN/A 5082292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5092292SN/A 5102316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5112316SN/A} 5122292SN/A 5132316SN/Atemplate <class Impl> 5142316SN/Avoid 5152316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5162316SN/A{ 5172316SN/A squashAll(tid); 5182316SN/A 5192316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5202316SN/A 5212316SN/A thread[tid]->trapPending = false; 5222316SN/A thread[tid]->inSyscall = false; 5232316SN/A 5242316SN/A trapSquash[tid] = false; 5252316SN/A 5262316SN/A commitStatus[tid] = ROBSquashing; 5272316SN/A cpu->activityThisCycle(); 5282316SN/A} 5292316SN/A 5302316SN/Atemplate <class Impl> 5312316SN/Avoid 5322680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5332316SN/A{ 5342316SN/A squashAll(tid); 5352292SN/A 5362680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5372292SN/A 5382292SN/A thread[tid]->inSyscall = false; 5392292SN/A assert(!thread[tid]->trapPending); 5402316SN/A 5412292SN/A commitStatus[tid] = ROBSquashing; 5422292SN/A cpu->activityThisCycle(); 5432292SN/A 5442680Sktlim@umich.edu tcSquash[tid] = false; 5452292SN/A} 5462292SN/A 5472292SN/Atemplate <class Impl> 5482292SN/Avoid 5492292SN/ADefaultCommit<Impl>::tick() 5502292SN/A{ 5512292SN/A wroteToTimeBuffer = false; 5522292SN/A _nextStatus = Inactive; 5532292SN/A 5542316SN/A if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5552316SN/A cpu->signalSwitched(); 5562316SN/A return; 5572316SN/A } 5582316SN/A 5592292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 5602292SN/A 5612316SN/A // Check if any of the threads are done squashing. Change the 5622316SN/A // status if they are done. 5632292SN/A while (threads != (*activeThreads).end()) { 5642292SN/A unsigned tid = *threads++; 5652292SN/A 5662292SN/A if (commitStatus[tid] == ROBSquashing) { 5672292SN/A 5682292SN/A if (rob->isDoneSquashing(tid)) { 5692292SN/A commitStatus[tid] = Running; 5702292SN/A } else { 5712292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5722292SN/A "insts this cycle.\n", tid); 5732702Sktlim@umich.edu rob->doSquash(tid); 5742702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5752702Sktlim@umich.edu wroteToTimeBuffer = true; 5762292SN/A } 5772292SN/A } 5782292SN/A } 5792292SN/A 5802292SN/A commit(); 5812292SN/A 5822292SN/A markCompletedInsts(); 5832292SN/A 5842292SN/A threads = (*activeThreads).begin(); 5852292SN/A 5862292SN/A while (threads != (*activeThreads).end()) { 5872292SN/A unsigned tid = *threads++; 5882292SN/A 5892292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 5902292SN/A // The ROB has more instructions it can commit. Its next status 5912292SN/A // will be active. 5922292SN/A _nextStatus = Active; 5932292SN/A 5942292SN/A DynInstPtr inst = rob->readHeadInst(tid); 5952292SN/A 5962292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 5972292SN/A " ROB and ready to commit\n", 5982292SN/A tid, inst->seqNum, inst->readPC()); 5992292SN/A 6002292SN/A } else if (!rob->isEmpty(tid)) { 6012292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6022292SN/A 6032292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6042292SN/A "%#x is head of ROB and not ready\n", 6052292SN/A tid, inst->seqNum, inst->readPC()); 6062292SN/A } 6072292SN/A 6082292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6092292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6102292SN/A } 6112292SN/A 6122292SN/A 6132292SN/A if (wroteToTimeBuffer) { 6142316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6152292SN/A cpu->activityThisCycle(); 6162292SN/A } 6172292SN/A 6182292SN/A updateStatus(); 6192292SN/A} 6202292SN/A 6212292SN/Atemplate <class Impl> 6222292SN/Avoid 6232292SN/ADefaultCommit<Impl>::commit() 6242292SN/A{ 6252292SN/A 6261060SN/A ////////////////////////////////////// 6271060SN/A // Check for interrupts 6281060SN/A ////////////////////////////////////// 6291060SN/A 6301858SN/A#if FULL_SYSTEM 6312316SN/A // Process interrupts if interrupts are enabled, not in PAL mode, 6322316SN/A // and no other traps or external squashes are currently pending. 6332316SN/A // @todo: Allow other threads to handle interrupts. 6342292SN/A if (cpu->checkInterrupts && 6351060SN/A cpu->check_interrupts() && 6362292SN/A !cpu->inPalMode(readPC()) && 6372292SN/A !trapSquash[0] && 6382680Sktlim@umich.edu !tcSquash[0]) { 6392316SN/A // Tell fetch that there is an interrupt pending. This will 6402316SN/A // make fetch wait until it sees a non PAL-mode PC, at which 6412316SN/A // point it stops fetching instructions. 6422292SN/A toIEW->commitInfo[0].interruptPending = true; 6431060SN/A 6442316SN/A // Wait until the ROB is empty and all stores have drained in 6452316SN/A // order to enter the interrupt. 6462292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6472292SN/A // Not sure which thread should be the one to interrupt. For now 6482292SN/A // always do thread 0. 6492292SN/A assert(!thread[0]->inSyscall); 6502292SN/A thread[0]->inSyscall = true; 6512292SN/A 6522292SN/A // CPU will handle implementation of the interrupt. 6532292SN/A cpu->processInterrupts(); 6542292SN/A 6552292SN/A // Now squash or record that I need to squash this cycle. 6562292SN/A commitStatus[0] = TrapPending; 6572292SN/A 6582292SN/A // Exit state update mode to avoid accidental updating. 6592292SN/A thread[0]->inSyscall = false; 6602292SN/A 6612292SN/A // Generate trap squash event. 6622292SN/A generateTrapEvent(0); 6632292SN/A 6642292SN/A toIEW->commitInfo[0].clearInterrupt = true; 6652292SN/A 6662292SN/A DPRINTF(Commit, "Interrupt detected.\n"); 6672292SN/A } else { 6682292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6692292SN/A } 6701060SN/A } 6711060SN/A#endif // FULL_SYSTEM 6721060SN/A 6731060SN/A //////////////////////////////////// 6742316SN/A // Check for any possible squashes, handle them first 6751060SN/A //////////////////////////////////// 6761060SN/A 6772292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6781060SN/A 6792292SN/A while (threads != (*activeThreads).end()) { 6802292SN/A unsigned tid = *threads++; 6811060SN/A 6822292SN/A // Not sure which one takes priority. I think if we have 6832292SN/A // both, that's a bad sign. 6842292SN/A if (trapSquash[tid] == true) { 6852680Sktlim@umich.edu assert(!tcSquash[tid]); 6862292SN/A squashFromTrap(tid); 6872680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 6882680Sktlim@umich.edu squashFromTC(tid); 6892292SN/A } 6901061SN/A 6912292SN/A // Squashed sequence number must be older than youngest valid 6922292SN/A // instruction in the ROB. This prevents squashes from younger 6932292SN/A // instructions overriding squashes from older instructions. 6942292SN/A if (fromIEW->squash[tid] && 6952292SN/A commitStatus[tid] != TrapPending && 6962292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 6971061SN/A 6982292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 6992292SN/A tid, 7002292SN/A fromIEW->mispredPC[tid], 7012292SN/A fromIEW->squashedSeqNum[tid]); 7021061SN/A 7032292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7042292SN/A tid, 7052292SN/A fromIEW->nextPC[tid]); 7061061SN/A 7072292SN/A commitStatus[tid] = ROBSquashing; 7081061SN/A 7092292SN/A // If we want to include the squashing instruction in the squash, 7102292SN/A // then use one older sequence number. 7112292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7121062SN/A 7132292SN/A if (fromIEW->includeSquashInst[tid] == true) 7142292SN/A squashed_inst--; 7152292SN/A 7162292SN/A // All younger instructions will be squashed. Set the sequence 7172292SN/A // number as the youngest instruction in the ROB. 7182292SN/A youngestSeqNum[tid] = squashed_inst; 7192292SN/A 7202292SN/A rob->squash(squashed_inst, tid); 7212292SN/A changedROBNumEntries[tid] = true; 7222292SN/A 7232292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7242292SN/A 7252292SN/A toIEW->commitInfo[tid].squash = true; 7262292SN/A 7272292SN/A // Send back the rob squashing signal so other stages know that 7282292SN/A // the ROB is in the process of squashing. 7292292SN/A toIEW->commitInfo[tid].robSquashing = true; 7302292SN/A 7312292SN/A toIEW->commitInfo[tid].branchMispredict = 7322292SN/A fromIEW->branchMispredict[tid]; 7332292SN/A 7342292SN/A toIEW->commitInfo[tid].branchTaken = 7352292SN/A fromIEW->branchTaken[tid]; 7362292SN/A 7372292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7382292SN/A 7392316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7402292SN/A 7412292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7422292SN/A ++branchMispredicts; 7432292SN/A } 7441062SN/A } 7452292SN/A 7461060SN/A } 7471060SN/A 7482292SN/A setNextStatus(); 7492292SN/A 7502292SN/A if (squashCounter != numThreads) { 7511061SN/A // If we're not currently squashing, then get instructions. 7521060SN/A getInsts(); 7531060SN/A 7541061SN/A // Try to commit any instructions. 7551060SN/A commitInsts(); 7561060SN/A } 7571060SN/A 7582292SN/A //Check for any activity 7592292SN/A threads = (*activeThreads).begin(); 7602292SN/A 7612292SN/A while (threads != (*activeThreads).end()) { 7622292SN/A unsigned tid = *threads++; 7632292SN/A 7642292SN/A if (changedROBNumEntries[tid]) { 7652292SN/A toIEW->commitInfo[tid].usedROB = true; 7662292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 7672292SN/A 7682292SN/A if (rob->isEmpty(tid)) { 7692292SN/A toIEW->commitInfo[tid].emptyROB = true; 7702292SN/A } 7712292SN/A 7722292SN/A wroteToTimeBuffer = true; 7732292SN/A changedROBNumEntries[tid] = false; 7742292SN/A } 7751060SN/A } 7761060SN/A} 7771060SN/A 7781061SN/Atemplate <class Impl> 7791060SN/Avoid 7802292SN/ADefaultCommit<Impl>::commitInsts() 7811060SN/A{ 7821060SN/A //////////////////////////////////// 7831060SN/A // Handle commit 7842316SN/A // Note that commit will be handled prior to putting new 7852316SN/A // instructions in the ROB so that the ROB only tries to commit 7862316SN/A // instructions it has in this current cycle, and not instructions 7872316SN/A // it is writing in during this cycle. Can't commit and squash 7882316SN/A // things at the same time... 7891060SN/A //////////////////////////////////// 7901060SN/A 7912292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 7921060SN/A 7931060SN/A unsigned num_committed = 0; 7941060SN/A 7952292SN/A DynInstPtr head_inst; 7962316SN/A 7971060SN/A // Commit as many instructions as possible until the commit bandwidth 7981060SN/A // limit is reached, or it becomes impossible to commit any more. 7992292SN/A while (num_committed < commitWidth) { 8002292SN/A int commit_thread = getCommittingThread(); 8011060SN/A 8022292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8032292SN/A break; 8042292SN/A 8052292SN/A head_inst = rob->readHeadInst(commit_thread); 8062292SN/A 8072292SN/A int tid = head_inst->threadNumber; 8082292SN/A 8092292SN/A assert(tid == commit_thread); 8102292SN/A 8112292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8122292SN/A head_inst->seqNum, tid); 8132132SN/A 8142316SN/A // If the head instruction is squashed, it is ready to retire 8152316SN/A // (be removed from the ROB) at any time. 8161060SN/A if (head_inst->isSquashed()) { 8171060SN/A 8182292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8191060SN/A "ROB.\n"); 8201060SN/A 8212292SN/A rob->retireHead(commit_thread); 8221060SN/A 8231062SN/A ++commitSquashedInsts; 8241062SN/A 8252292SN/A // Record that the number of ROB entries has changed. 8262292SN/A changedROBNumEntries[tid] = true; 8271060SN/A } else { 8282292SN/A PC[tid] = head_inst->readPC(); 8292292SN/A nextPC[tid] = head_inst->readNextPC(); 8302292SN/A 8311060SN/A // Increment the total number of non-speculative instructions 8321060SN/A // executed. 8331060SN/A // Hack for now: it really shouldn't happen until after the 8341061SN/A // commit is deemed to be successful, but this count is needed 8351061SN/A // for syscalls. 8362292SN/A thread[tid]->funcExeInst++; 8371060SN/A 8381060SN/A // Try to commit the head instruction. 8391060SN/A bool commit_success = commitHead(head_inst, num_committed); 8401060SN/A 8411062SN/A if (commit_success) { 8421060SN/A ++num_committed; 8431060SN/A 8442292SN/A changedROBNumEntries[tid] = true; 8452292SN/A 8462292SN/A // Set the doneSeqNum to the youngest committed instruction. 8472292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 8481060SN/A 8491062SN/A ++commitCommittedInsts; 8501062SN/A 8512292SN/A // To match the old model, don't count nops and instruction 8522292SN/A // prefetches towards the total commit count. 8532292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 8542292SN/A cpu->instDone(tid); 8551062SN/A } 8562292SN/A 8572292SN/A PC[tid] = nextPC[tid]; 8582307SN/A nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 8592292SN/A#if FULL_SYSTEM 8602292SN/A int count = 0; 8612292SN/A Addr oldpc; 8622292SN/A do { 8632316SN/A // Debug statement. Checks to make sure we're not 8642316SN/A // currently updating state while handling PC events. 8652292SN/A if (count == 0) 8662316SN/A assert(!thread[tid]->inSyscall && 8672316SN/A !thread[tid]->trapPending); 8682292SN/A oldpc = PC[tid]; 8692292SN/A cpu->system->pcEventQueue.service( 8702690Sktlim@umich.edu thread[tid]->getTC()); 8712292SN/A count++; 8722292SN/A } while (oldpc != PC[tid]); 8732292SN/A if (count > 1) { 8742292SN/A DPRINTF(Commit, "PC skip function event, stopping commit\n"); 8752292SN/A break; 8762292SN/A } 8772292SN/A#endif 8781060SN/A } else { 8792292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 8802292SN/A "[tid:%i] [sn:%i].\n", 8812292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 8821060SN/A break; 8831060SN/A } 8841060SN/A } 8851060SN/A } 8861062SN/A 8871063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 8882292SN/A numCommittedDist.sample(num_committed); 8892307SN/A 8902307SN/A if (num_committed == commitWidth) { 8912349SN/A commitEligibleSamples++; 8922307SN/A } 8931060SN/A} 8941060SN/A 8951061SN/Atemplate <class Impl> 8961060SN/Abool 8972292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 8981060SN/A{ 8991060SN/A assert(head_inst); 9001060SN/A 9012292SN/A int tid = head_inst->threadNumber; 9022292SN/A 9032316SN/A // If the instruction is not executed yet, then it will need extra 9042316SN/A // handling. Signal backwards that it should be executed. 9051061SN/A if (!head_inst->isExecuted()) { 9061061SN/A // Keep this number correct. We have not yet actually executed 9071061SN/A // and committed this instruction. 9082292SN/A thread[tid]->funcExeInst--; 9091062SN/A 9102731Sktlim@umich.edu head_inst->setAtCommit(); 9111060SN/A 9122292SN/A if (head_inst->isNonSpeculative() || 9132348SN/A head_inst->isStoreConditional() || 9142292SN/A head_inst->isMemBarrier() || 9152292SN/A head_inst->isWriteBarrier()) { 9162316SN/A 9172316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9182316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9192316SN/A head_inst->seqNum, head_inst->readPC()); 9202316SN/A 9212292SN/A#if !FULL_SYSTEM 9222316SN/A // Hack to make sure syscalls/memory barriers/quiesces 9232316SN/A // aren't executed until all stores write back their data. 9242316SN/A // This direct communication shouldn't be used for 9252316SN/A // anything other than this. 9262292SN/A if (inst_num > 0 || iewStage->hasStoresToWB()) 9272292SN/A#else 9282292SN/A if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 9292292SN/A head_inst->isQuiesce()) && 9302292SN/A iewStage->hasStoresToWB()) 9312292SN/A#endif 9322292SN/A { 9332292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9342292SN/A return false; 9352292SN/A } 9362292SN/A 9372292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9381061SN/A 9391061SN/A // Change the instruction so it won't try to commit again until 9401061SN/A // it is executed. 9411061SN/A head_inst->clearCanCommit(); 9421061SN/A 9431062SN/A ++commitNonSpecStalls; 9441062SN/A 9451061SN/A return false; 9462292SN/A } else if (head_inst->isLoad()) { 9472292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9482292SN/A head_inst->seqNum, head_inst->readPC()); 9492292SN/A 9502292SN/A // Send back the non-speculative instruction's sequence 9512316SN/A // number. Tell the lsq to re-execute the load. 9522292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9532292SN/A toIEW->commitInfo[tid].uncached = true; 9542292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 9552292SN/A 9562292SN/A head_inst->clearCanCommit(); 9572292SN/A 9582292SN/A return false; 9591061SN/A } else { 9602292SN/A panic("Trying to commit un-executed instruction " 9611061SN/A "of unknown type!\n"); 9621061SN/A } 9631060SN/A } 9641060SN/A 9652316SN/A if (head_inst->isThreadSync()) { 9662292SN/A // Not handled for now. 9672316SN/A panic("Thread sync instructions are not handled yet.\n"); 9682132SN/A } 9692132SN/A 9702316SN/A // Stores mark themselves as completed. 9712310SN/A if (!head_inst->isStore()) { 9722310SN/A head_inst->setCompleted(); 9732310SN/A } 9742310SN/A 9752316SN/A // Use checker prior to updating anything due to traps or PC 9762316SN/A // based events. 9772316SN/A if (cpu->checker) { 9782316SN/A cpu->checker->tick(head_inst); 9791060SN/A } 9801060SN/A 9811060SN/A // Check if the instruction caused a fault. If so, trap. 9822132SN/A Fault inst_fault = head_inst->getFault(); 9831681SN/A 9842112SN/A if (inst_fault != NoFault) { 9852316SN/A head_inst->setCompleted(); 9861858SN/A#if FULL_SYSTEM 9872316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 9882316SN/A head_inst->seqNum, head_inst->readPC()); 9892292SN/A 9902316SN/A if (iewStage->hasStoresToWB() || inst_num > 0) { 9912316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 9922316SN/A return false; 9932316SN/A } 9942310SN/A 9952316SN/A if (cpu->checker && head_inst->isStore()) { 9962316SN/A cpu->checker->tick(head_inst); 9972316SN/A } 9982292SN/A 9992316SN/A assert(!thread[tid]->inSyscall); 10002292SN/A 10012316SN/A // Mark that we're in state update mode so that the trap's 10022316SN/A // execution doesn't generate extra squashes. 10032316SN/A thread[tid]->inSyscall = true; 10042292SN/A 10052316SN/A // DTB will sometimes need the machine instruction for when 10062316SN/A // faults happen. So we will set it here, prior to the DTB 10072316SN/A // possibly needing it for its fault. 10082316SN/A thread[tid]->setInst( 10092316SN/A static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10102292SN/A 10112316SN/A // Execute the trap. Although it's slightly unrealistic in 10122316SN/A // terms of timing (as it doesn't wait for the full timing of 10132316SN/A // the trap event to complete before updating state), it's 10142316SN/A // needed to update the state as soon as possible. This 10152316SN/A // prevents external agents from changing any specific state 10162316SN/A // that the trap need. 10172316SN/A cpu->trap(inst_fault, tid); 10182292SN/A 10192316SN/A // Exit state update mode to avoid accidental updating. 10202316SN/A thread[tid]->inSyscall = false; 10212292SN/A 10222316SN/A commitStatus[tid] = TrapPending; 10232292SN/A 10242316SN/A // Generate trap squash event. 10252316SN/A generateTrapEvent(tid); 10262316SN/A 10272316SN/A return false; 10281060SN/A#else // !FULL_SYSTEM 10292316SN/A panic("fault (%d) detected @ PC %08p", inst_fault, 10302316SN/A head_inst->PC); 10311062SN/A#endif // FULL_SYSTEM 10321060SN/A } 10331060SN/A 10342301SN/A updateComInstStats(head_inst); 10352132SN/A 10362132SN/A if (head_inst->traceData) { 10372292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 10382292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 10392132SN/A head_inst->traceData->finalize(); 10402292SN/A head_inst->traceData = NULL; 10411060SN/A } 10421060SN/A 10432292SN/A // Update the commit rename map 10442292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 10452292SN/A renameMap[tid]->setEntry(head_inst->destRegIdx(i), 10462292SN/A head_inst->renamedDestRegIdx(i)); 10471060SN/A } 10481062SN/A 10492292SN/A // Finally clear the head ROB entry. 10502292SN/A rob->retireHead(tid); 10511060SN/A 10521060SN/A // Return true to indicate that we have committed an instruction. 10531060SN/A return true; 10541060SN/A} 10551060SN/A 10561061SN/Atemplate <class Impl> 10571060SN/Avoid 10582292SN/ADefaultCommit<Impl>::getInsts() 10591060SN/A{ 10602316SN/A // Read any renamed instructions and place them into the ROB. 10611061SN/A int insts_to_process = min((int)renameWidth, fromRename->size); 10621061SN/A 10632292SN/A for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 10641060SN/A { 10652292SN/A DynInstPtr inst = fromRename->insts[inst_num]; 10662292SN/A int tid = inst->threadNumber; 10672292SN/A 10682292SN/A if (!inst->isSquashed() && 10692292SN/A commitStatus[tid] != ROBSquashing) { 10702292SN/A changedROBNumEntries[tid] = true; 10712292SN/A 10722292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 10732292SN/A inst->readPC(), inst->seqNum, tid); 10742292SN/A 10752292SN/A rob->insertInst(inst); 10762292SN/A 10772292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 10782292SN/A 10792292SN/A youngestSeqNum[tid] = inst->seqNum; 10801061SN/A } else { 10812292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 10821061SN/A "squashed, skipping.\n", 10832292SN/A inst->readPC(), inst->seqNum, tid); 10841061SN/A } 10851060SN/A } 10861060SN/A} 10871060SN/A 10881061SN/Atemplate <class Impl> 10891060SN/Avoid 10902292SN/ADefaultCommit<Impl>::markCompletedInsts() 10911060SN/A{ 10921060SN/A // Grab completed insts out of the IEW instruction queue, and mark 10931060SN/A // instructions completed within the ROB. 10941060SN/A for (int inst_num = 0; 10951681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 10961060SN/A ++inst_num) 10971060SN/A { 10982292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 10992316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 11002316SN/A "within ROB.\n", 11012292SN/A fromIEW->insts[inst_num]->threadNumber, 11022292SN/A fromIEW->insts[inst_num]->readPC(), 11032292SN/A fromIEW->insts[inst_num]->seqNum); 11041060SN/A 11052292SN/A // Mark the instruction as ready to commit. 11062292SN/A fromIEW->insts[inst_num]->setCanCommit(); 11072292SN/A } 11081060SN/A } 11091060SN/A} 11101060SN/A 11111061SN/Atemplate <class Impl> 11122292SN/Abool 11132292SN/ADefaultCommit<Impl>::robDoneSquashing() 11141060SN/A{ 11152292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11162292SN/A 11172292SN/A while (threads != (*activeThreads).end()) { 11182292SN/A unsigned tid = *threads++; 11192292SN/A 11202292SN/A if (!rob->isDoneSquashing(tid)) 11212292SN/A return false; 11222292SN/A } 11232292SN/A 11242292SN/A return true; 11251060SN/A} 11262292SN/A 11272301SN/Atemplate <class Impl> 11282301SN/Avoid 11292301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 11302301SN/A{ 11312301SN/A unsigned thread = inst->threadNumber; 11322301SN/A 11332301SN/A // 11342301SN/A // Pick off the software prefetches 11352301SN/A // 11362301SN/A#ifdef TARGET_ALPHA 11372301SN/A if (inst->isDataPrefetch()) { 11382316SN/A statComSwp[thread]++; 11392301SN/A } else { 11402316SN/A statComInst[thread]++; 11412301SN/A } 11422301SN/A#else 11432316SN/A statComInst[thread]++; 11442301SN/A#endif 11452301SN/A 11462301SN/A // 11472301SN/A // Control Instructions 11482301SN/A // 11492301SN/A if (inst->isControl()) 11502316SN/A statComBranches[thread]++; 11512301SN/A 11522301SN/A // 11532301SN/A // Memory references 11542301SN/A // 11552301SN/A if (inst->isMemRef()) { 11562316SN/A statComRefs[thread]++; 11572301SN/A 11582301SN/A if (inst->isLoad()) { 11592316SN/A statComLoads[thread]++; 11602301SN/A } 11612301SN/A } 11622301SN/A 11632301SN/A if (inst->isMemBarrier()) { 11642316SN/A statComMembars[thread]++; 11652301SN/A } 11662301SN/A} 11672301SN/A 11682292SN/A//////////////////////////////////////// 11692292SN/A// // 11702316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 11712292SN/A// // 11722292SN/A//////////////////////////////////////// 11732292SN/Atemplate <class Impl> 11742292SN/Aint 11752292SN/ADefaultCommit<Impl>::getCommittingThread() 11762292SN/A{ 11772292SN/A if (numThreads > 1) { 11782292SN/A switch (commitPolicy) { 11792292SN/A 11802292SN/A case Aggressive: 11812292SN/A //If Policy is Aggressive, commit will call 11822292SN/A //this function multiple times per 11832292SN/A //cycle 11842292SN/A return oldestReady(); 11852292SN/A 11862292SN/A case RoundRobin: 11872292SN/A return roundRobin(); 11882292SN/A 11892292SN/A case OldestReady: 11902292SN/A return oldestReady(); 11912292SN/A 11922292SN/A default: 11932292SN/A return -1; 11942292SN/A } 11952292SN/A } else { 11962292SN/A int tid = (*activeThreads).front(); 11972292SN/A 11982292SN/A if (commitStatus[tid] == Running || 11992292SN/A commitStatus[tid] == Idle || 12002292SN/A commitStatus[tid] == FetchTrapPending) { 12012292SN/A return tid; 12022292SN/A } else { 12032292SN/A return -1; 12042292SN/A } 12052292SN/A } 12062292SN/A} 12072292SN/A 12082292SN/Atemplate<class Impl> 12092292SN/Aint 12102292SN/ADefaultCommit<Impl>::roundRobin() 12112292SN/A{ 12122292SN/A list<unsigned>::iterator pri_iter = priority_list.begin(); 12132292SN/A list<unsigned>::iterator end = priority_list.end(); 12142292SN/A 12152292SN/A while (pri_iter != end) { 12162292SN/A unsigned tid = *pri_iter; 12172292SN/A 12182292SN/A if (commitStatus[tid] == Running || 12192292SN/A commitStatus[tid] == Idle) { 12202292SN/A 12212292SN/A if (rob->isHeadReady(tid)) { 12222292SN/A priority_list.erase(pri_iter); 12232292SN/A priority_list.push_back(tid); 12242292SN/A 12252292SN/A return tid; 12262292SN/A } 12272292SN/A } 12282292SN/A 12292292SN/A pri_iter++; 12302292SN/A } 12312292SN/A 12322292SN/A return -1; 12332292SN/A} 12342292SN/A 12352292SN/Atemplate<class Impl> 12362292SN/Aint 12372292SN/ADefaultCommit<Impl>::oldestReady() 12382292SN/A{ 12392292SN/A unsigned oldest = 0; 12402292SN/A bool first = true; 12412292SN/A 12422292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 12432292SN/A 12442292SN/A while (threads != (*activeThreads).end()) { 12452292SN/A unsigned tid = *threads++; 12462292SN/A 12472292SN/A if (!rob->isEmpty(tid) && 12482292SN/A (commitStatus[tid] == Running || 12492292SN/A commitStatus[tid] == Idle || 12502292SN/A commitStatus[tid] == FetchTrapPending)) { 12512292SN/A 12522292SN/A if (rob->isHeadReady(tid)) { 12532292SN/A 12542292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 12552292SN/A 12562292SN/A if (first) { 12572292SN/A oldest = tid; 12582292SN/A first = false; 12592292SN/A } else if (head_inst->seqNum < oldest) { 12602292SN/A oldest = tid; 12612292SN/A } 12622292SN/A } 12632292SN/A } 12642292SN/A } 12652292SN/A 12662292SN/A if (!first) { 12672292SN/A return oldest; 12682292SN/A } else { 12692292SN/A return -1; 12702292SN/A } 12712292SN/A} 1272