commit_impl.hh revision 2680
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312292SN/A#include <algorithm> 322329SN/A#include <string> 332292SN/A 342292SN/A#include "base/loader/symtab.hh" 351060SN/A#include "base/timebuf.hh" 362316SN/A#include "cpu/checker/cpu.hh" 372292SN/A#include "cpu/exetrace.hh" 381717SN/A#include "cpu/o3/commit.hh" 392292SN/A#include "cpu/o3/thread_state.hh" 402292SN/A 412292SN/Ausing namespace std; 421060SN/A 431061SN/Atemplate <class Impl> 442292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 452292SN/A unsigned _tid) 462292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 471060SN/A{ 482292SN/A this->setFlags(Event::AutoDelete); 491060SN/A} 501060SN/A 511061SN/Atemplate <class Impl> 521060SN/Avoid 532292SN/ADefaultCommit<Impl>::TrapEvent::process() 541062SN/A{ 552316SN/A // This will get reset by commit if it was switched out at the 562316SN/A // time of this event processing. 572292SN/A commit->trapSquash[tid] = true; 582292SN/A} 592292SN/A 602292SN/Atemplate <class Impl> 612292SN/Aconst char * 622292SN/ADefaultCommit<Impl>::TrapEvent::description() 632292SN/A{ 642292SN/A return "Trap event"; 652292SN/A} 662292SN/A 672292SN/Atemplate <class Impl> 682292SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 692669Sktlim@umich.edu : squashCounter(0), 702292SN/A iewToCommitDelay(params->iewToCommitDelay), 712292SN/A commitToIEWDelay(params->commitToIEWDelay), 722292SN/A renameToROBDelay(params->renameToROBDelay), 732292SN/A fetchToCommitDelay(params->commitToFetchDelay), 742292SN/A renameWidth(params->renameWidth), 752292SN/A iewWidth(params->executeWidth), 762292SN/A commitWidth(params->commitWidth), 772307SN/A numThreads(params->numberOfThreads), 782678Sktlim@umich.edu switchPending(false), 792316SN/A switchedOut(false), 802316SN/A trapLatency(params->trapLatency), 812316SN/A fetchTrapLatency(params->fetchTrapLatency) 822292SN/A{ 832292SN/A _status = Active; 842292SN/A _nextStatus = Inactive; 852292SN/A string policy = params->smtCommitPolicy; 862292SN/A 872292SN/A //Convert string to lowercase 882292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 892292SN/A (int(*)(int)) tolower); 902292SN/A 912292SN/A //Assign commit policy 922292SN/A if (policy == "aggressive"){ 932292SN/A commitPolicy = Aggressive; 942292SN/A 952292SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 962292SN/A } else if (policy == "roundrobin"){ 972292SN/A commitPolicy = RoundRobin; 982292SN/A 992292SN/A //Set-Up Priority List 1002292SN/A for (int tid=0; tid < numThreads; tid++) { 1012292SN/A priority_list.push_back(tid); 1022292SN/A } 1032292SN/A 1042292SN/A DPRINTF(Commit,"Commit Policy set to Round Robin."); 1052292SN/A } else if (policy == "oldestready"){ 1062292SN/A commitPolicy = OldestReady; 1072292SN/A 1082292SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1092292SN/A } else { 1102292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1112292SN/A "RoundRobin,OldestReady}"); 1122292SN/A } 1132292SN/A 1142292SN/A for (int i=0; i < numThreads; i++) { 1152292SN/A commitStatus[i] = Idle; 1162292SN/A changedROBNumEntries[i] = false; 1172292SN/A trapSquash[i] = false; 1182680Sktlim@umich.edu tcSquash[i] = false; 1192678Sktlim@umich.edu PC[i] = nextPC[i] = 0; 1202292SN/A } 1212292SN/A 1222292SN/A fetchFaultTick = 0; 1232292SN/A fetchTrapWait = 0; 1242292SN/A} 1252292SN/A 1262292SN/Atemplate <class Impl> 1272292SN/Astd::string 1282292SN/ADefaultCommit<Impl>::name() const 1292292SN/A{ 1302292SN/A return cpu->name() + ".commit"; 1312292SN/A} 1322292SN/A 1332292SN/Atemplate <class Impl> 1342292SN/Avoid 1352292SN/ADefaultCommit<Impl>::regStats() 1362132SN/A{ 1372301SN/A using namespace Stats; 1381062SN/A commitCommittedInsts 1391062SN/A .name(name() + ".commitCommittedInsts") 1401062SN/A .desc("The number of committed instructions") 1411062SN/A .prereq(commitCommittedInsts); 1421062SN/A commitSquashedInsts 1431062SN/A .name(name() + ".commitSquashedInsts") 1441062SN/A .desc("The number of squashed insts skipped by commit") 1451062SN/A .prereq(commitSquashedInsts); 1461062SN/A commitSquashEvents 1471062SN/A .name(name() + ".commitSquashEvents") 1481062SN/A .desc("The number of times commit is told to squash") 1491062SN/A .prereq(commitSquashEvents); 1501062SN/A commitNonSpecStalls 1511062SN/A .name(name() + ".commitNonSpecStalls") 1521062SN/A .desc("The number of times commit has been forced to stall to " 1531062SN/A "communicate backwards") 1541062SN/A .prereq(commitNonSpecStalls); 1551062SN/A branchMispredicts 1561062SN/A .name(name() + ".branchMispredicts") 1571062SN/A .desc("The number of times a branch was mispredicted") 1581062SN/A .prereq(branchMispredicts); 1592292SN/A numCommittedDist 1601062SN/A .init(0,commitWidth,1) 1611062SN/A .name(name() + ".COM:committed_per_cycle") 1621062SN/A .desc("Number of insts commited each cycle") 1631062SN/A .flags(Stats::pdf) 1641062SN/A ; 1652301SN/A 1662316SN/A statComInst 1672301SN/A .init(cpu->number_of_threads) 1682301SN/A .name(name() + ".COM:count") 1692301SN/A .desc("Number of instructions committed") 1702301SN/A .flags(total) 1712301SN/A ; 1722301SN/A 1732316SN/A statComSwp 1742301SN/A .init(cpu->number_of_threads) 1752301SN/A .name(name() + ".COM:swp_count") 1762301SN/A .desc("Number of s/w prefetches committed") 1772301SN/A .flags(total) 1782301SN/A ; 1792301SN/A 1802316SN/A statComRefs 1812301SN/A .init(cpu->number_of_threads) 1822301SN/A .name(name() + ".COM:refs") 1832301SN/A .desc("Number of memory references committed") 1842301SN/A .flags(total) 1852301SN/A ; 1862301SN/A 1872316SN/A statComLoads 1882301SN/A .init(cpu->number_of_threads) 1892301SN/A .name(name() + ".COM:loads") 1902301SN/A .desc("Number of loads committed") 1912301SN/A .flags(total) 1922301SN/A ; 1932301SN/A 1942316SN/A statComMembars 1952301SN/A .init(cpu->number_of_threads) 1962301SN/A .name(name() + ".COM:membars") 1972301SN/A .desc("Number of memory barriers committed") 1982301SN/A .flags(total) 1992301SN/A ; 2002301SN/A 2012316SN/A statComBranches 2022301SN/A .init(cpu->number_of_threads) 2032301SN/A .name(name() + ".COM:branches") 2042301SN/A .desc("Number of branches committed") 2052301SN/A .flags(total) 2062301SN/A ; 2072301SN/A 2082301SN/A // 2092301SN/A // Commit-Eligible instructions... 2102301SN/A // 2112301SN/A // -> The number of instructions eligible to commit in those 2122301SN/A // cycles where we reached our commit BW limit (less the number 2132301SN/A // actually committed) 2142301SN/A // 2152301SN/A // -> The average value is computed over ALL CYCLES... not just 2162301SN/A // the BW limited cycles 2172301SN/A // 2182301SN/A // -> The standard deviation is computed only over cycles where 2192301SN/A // we reached the BW limit 2202301SN/A // 2212316SN/A commitEligible 2222301SN/A .init(cpu->number_of_threads) 2232301SN/A .name(name() + ".COM:bw_limited") 2242301SN/A .desc("number of insts not committed due to BW limits") 2252301SN/A .flags(total) 2262301SN/A ; 2272301SN/A 2282316SN/A commitEligibleSamples 2292301SN/A .name(name() + ".COM:bw_lim_events") 2302301SN/A .desc("number cycles where commit BW limit reached") 2312301SN/A ; 2321062SN/A} 2331062SN/A 2341062SN/Atemplate <class Impl> 2351062SN/Avoid 2362292SN/ADefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr) 2371060SN/A{ 2381060SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2391060SN/A cpu = cpu_ptr; 2402292SN/A 2412292SN/A // Commit must broadcast the number of free entries it has at the start of 2422292SN/A // the simulation, so it starts as active. 2432292SN/A cpu->activateStage(FullCPU::CommitIdx); 2442307SN/A 2452316SN/A trapLatency = cpu->cycles(trapLatency); 2462316SN/A fetchTrapLatency = cpu->cycles(fetchTrapLatency); 2471060SN/A} 2481060SN/A 2491061SN/Atemplate <class Impl> 2501060SN/Avoid 2512292SN/ADefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 2522292SN/A{ 2532292SN/A thread = threads; 2542292SN/A} 2552292SN/A 2562292SN/Atemplate <class Impl> 2572292SN/Avoid 2582292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2591060SN/A{ 2601060SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2611060SN/A timeBuffer = tb_ptr; 2621060SN/A 2631060SN/A // Setup wire to send information back to IEW. 2641060SN/A toIEW = timeBuffer->getWire(0); 2651060SN/A 2661060SN/A // Setup wire to read data from IEW (for the ROB). 2671060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2681060SN/A} 2691060SN/A 2701061SN/Atemplate <class Impl> 2711060SN/Avoid 2722292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2732292SN/A{ 2742292SN/A DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2752292SN/A fetchQueue = fq_ptr; 2762292SN/A 2772292SN/A // Setup wire to get instructions from rename (for the ROB). 2782292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2792292SN/A} 2802292SN/A 2812292SN/Atemplate <class Impl> 2822292SN/Avoid 2832292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2841060SN/A{ 2851060SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2861060SN/A renameQueue = rq_ptr; 2871060SN/A 2881060SN/A // Setup wire to get instructions from rename (for the ROB). 2891060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2901060SN/A} 2911060SN/A 2921061SN/Atemplate <class Impl> 2931060SN/Avoid 2942292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2951060SN/A{ 2961060SN/A DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2971060SN/A iewQueue = iq_ptr; 2981060SN/A 2991060SN/A // Setup wire to get instructions from IEW. 3001060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3011060SN/A} 3021060SN/A 3031061SN/Atemplate <class Impl> 3041060SN/Avoid 3052316SN/ADefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 3062316SN/A{ 3072316SN/A fetchStage = fetch_stage; 3082316SN/A} 3092316SN/A 3102316SN/Atemplate <class Impl> 3112316SN/Avoid 3122292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3132292SN/A{ 3142292SN/A iewStage = iew_stage; 3152292SN/A} 3162292SN/A 3172292SN/Atemplate<class Impl> 3182292SN/Avoid 3192292SN/ADefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3202292SN/A{ 3212292SN/A DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3222292SN/A activeThreads = at_ptr; 3232292SN/A} 3242292SN/A 3252292SN/Atemplate <class Impl> 3262292SN/Avoid 3272292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3282292SN/A{ 3292292SN/A DPRINTF(Commit, "Setting rename map pointers.\n"); 3302292SN/A 3312292SN/A for (int i=0; i < numThreads; i++) { 3322292SN/A renameMap[i] = &rm_ptr[i]; 3332292SN/A } 3342292SN/A} 3352292SN/A 3362292SN/Atemplate <class Impl> 3372292SN/Avoid 3382292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3391060SN/A{ 3401060SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3411060SN/A rob = rob_ptr; 3421060SN/A} 3431060SN/A 3441061SN/Atemplate <class Impl> 3451060SN/Avoid 3462292SN/ADefaultCommit<Impl>::initStage() 3471060SN/A{ 3482292SN/A rob->setActiveThreads(activeThreads); 3492292SN/A rob->resetEntries(); 3501060SN/A 3512292SN/A // Broadcast the number of free entries. 3522292SN/A for (int i=0; i < numThreads; i++) { 3532292SN/A toIEW->commitInfo[i].usedROB = true; 3542292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3551060SN/A } 3561060SN/A 3572292SN/A cpu->activityThisCycle(); 3581060SN/A} 3591060SN/A 3601061SN/Atemplate <class Impl> 3611060SN/Avoid 3622307SN/ADefaultCommit<Impl>::switchOut() 3631060SN/A{ 3642316SN/A switchPending = true; 3652316SN/A} 3662316SN/A 3672316SN/Atemplate <class Impl> 3682316SN/Avoid 3692316SN/ADefaultCommit<Impl>::doSwitchOut() 3702316SN/A{ 3712316SN/A switchedOut = true; 3722316SN/A switchPending = false; 3732307SN/A rob->switchOut(); 3742307SN/A} 3752307SN/A 3762307SN/Atemplate <class Impl> 3772307SN/Avoid 3782307SN/ADefaultCommit<Impl>::takeOverFrom() 3792307SN/A{ 3802316SN/A switchedOut = false; 3812307SN/A _status = Active; 3822307SN/A _nextStatus = Inactive; 3832307SN/A for (int i=0; i < numThreads; i++) { 3842307SN/A commitStatus[i] = Idle; 3852307SN/A changedROBNumEntries[i] = false; 3862307SN/A trapSquash[i] = false; 3872680Sktlim@umich.edu tcSquash[i] = false; 3882307SN/A } 3892307SN/A squashCounter = 0; 3902307SN/A rob->takeOverFrom(); 3912307SN/A} 3922307SN/A 3932307SN/Atemplate <class Impl> 3942307SN/Avoid 3952292SN/ADefaultCommit<Impl>::updateStatus() 3962132SN/A{ 3972316SN/A // reset ROB changed variable 3982316SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 3992316SN/A while (threads != (*activeThreads).end()) { 4002316SN/A unsigned tid = *threads++; 4012316SN/A changedROBNumEntries[tid] = false; 4022316SN/A 4032316SN/A // Also check if any of the threads has a trap pending 4042316SN/A if (commitStatus[tid] == TrapPending || 4052316SN/A commitStatus[tid] == FetchTrapPending) { 4062316SN/A _nextStatus = Active; 4072316SN/A } 4082292SN/A } 4092292SN/A 4102292SN/A if (_nextStatus == Inactive && _status == Active) { 4112292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4122292SN/A cpu->deactivateStage(FullCPU::CommitIdx); 4132292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4142292SN/A DPRINTF(Activity, "Activating stage.\n"); 4152292SN/A cpu->activateStage(FullCPU::CommitIdx); 4162292SN/A } 4172292SN/A 4182292SN/A _status = _nextStatus; 4192292SN/A} 4202292SN/A 4212292SN/Atemplate <class Impl> 4222292SN/Avoid 4232292SN/ADefaultCommit<Impl>::setNextStatus() 4242292SN/A{ 4252292SN/A int squashes = 0; 4262292SN/A 4272292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4282292SN/A 4292292SN/A while (threads != (*activeThreads).end()) { 4302292SN/A unsigned tid = *threads++; 4312292SN/A 4322292SN/A if (commitStatus[tid] == ROBSquashing) { 4332292SN/A squashes++; 4342292SN/A } 4352292SN/A } 4362292SN/A 4372292SN/A assert(squashes == squashCounter); 4382292SN/A 4392292SN/A // If commit is currently squashing, then it will have activity for the 4402292SN/A // next cycle. Set its next status as active. 4412292SN/A if (squashCounter) { 4422292SN/A _nextStatus = Active; 4432292SN/A } 4442292SN/A} 4452292SN/A 4462292SN/Atemplate <class Impl> 4472292SN/Abool 4482292SN/ADefaultCommit<Impl>::changedROBEntries() 4492292SN/A{ 4502292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4512292SN/A 4522292SN/A while (threads != (*activeThreads).end()) { 4532292SN/A unsigned tid = *threads++; 4542292SN/A 4552292SN/A if (changedROBNumEntries[tid]) { 4562292SN/A return true; 4572292SN/A } 4582292SN/A } 4592292SN/A 4602292SN/A return false; 4612292SN/A} 4622292SN/A 4632292SN/Atemplate <class Impl> 4642292SN/Aunsigned 4652292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4662292SN/A{ 4672292SN/A return rob->numFreeEntries(tid); 4682292SN/A} 4692292SN/A 4702292SN/Atemplate <class Impl> 4712292SN/Avoid 4722292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4732292SN/A{ 4742292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4752292SN/A 4762292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4772292SN/A 4782292SN/A trap->schedule(curTick + trapLatency); 4792292SN/A 4802292SN/A thread[tid]->trapPending = true; 4812292SN/A} 4822292SN/A 4832292SN/Atemplate <class Impl> 4842292SN/Avoid 4852680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4862292SN/A{ 4872680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4882292SN/A 4892680Sktlim@umich.edu tcSquash[tid] = true; 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4932292SN/Avoid 4942316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4952292SN/A{ 4962292SN/A // If we want to include the squashing instruction in the squash, 4972292SN/A // then use one older sequence number. 4982292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4992292SN/A // all instructions of this thread. 5002292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5012292SN/A 0 : rob->readHeadInst(tid)->seqNum - 1;; 5022292SN/A 5032292SN/A // All younger instructions will be squashed. Set the sequence 5042292SN/A // number as the youngest instruction in the ROB (0 in this case. 5052292SN/A // Hopefully nothing breaks.) 5062292SN/A youngestSeqNum[tid] = 0; 5072292SN/A 5082292SN/A rob->squash(squashed_inst, tid); 5092292SN/A changedROBNumEntries[tid] = true; 5102292SN/A 5112292SN/A // Send back the sequence number of the squashed instruction. 5122292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5132292SN/A 5142292SN/A // Send back the squash signal to tell stages that they should 5152292SN/A // squash. 5162292SN/A toIEW->commitInfo[tid].squash = true; 5172292SN/A 5182292SN/A // Send back the rob squashing signal so other stages know that 5192292SN/A // the ROB is in the process of squashing. 5202292SN/A toIEW->commitInfo[tid].robSquashing = true; 5212292SN/A 5222292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5232292SN/A 5242316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5252316SN/A} 5262292SN/A 5272316SN/Atemplate <class Impl> 5282316SN/Avoid 5292316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5302316SN/A{ 5312316SN/A squashAll(tid); 5322316SN/A 5332316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5342316SN/A 5352316SN/A thread[tid]->trapPending = false; 5362316SN/A thread[tid]->inSyscall = false; 5372316SN/A 5382316SN/A trapSquash[tid] = false; 5392316SN/A 5402316SN/A commitStatus[tid] = ROBSquashing; 5412316SN/A cpu->activityThisCycle(); 5422316SN/A 5432316SN/A ++squashCounter; 5442316SN/A} 5452316SN/A 5462316SN/Atemplate <class Impl> 5472316SN/Avoid 5482680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5492316SN/A{ 5502316SN/A squashAll(tid); 5512292SN/A 5522680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5532292SN/A 5542292SN/A thread[tid]->inSyscall = false; 5552292SN/A assert(!thread[tid]->trapPending); 5562316SN/A 5572292SN/A commitStatus[tid] = ROBSquashing; 5582292SN/A cpu->activityThisCycle(); 5592292SN/A 5602680Sktlim@umich.edu tcSquash[tid] = false; 5612292SN/A 5622292SN/A ++squashCounter; 5632292SN/A} 5642292SN/A 5652292SN/Atemplate <class Impl> 5662292SN/Avoid 5672292SN/ADefaultCommit<Impl>::tick() 5682292SN/A{ 5692292SN/A wroteToTimeBuffer = false; 5702292SN/A _nextStatus = Inactive; 5712292SN/A 5722316SN/A if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5732316SN/A cpu->signalSwitched(); 5742316SN/A return; 5752316SN/A } 5762316SN/A 5772292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 5782292SN/A 5792316SN/A // Check if any of the threads are done squashing. Change the 5802316SN/A // status if they are done. 5812292SN/A while (threads != (*activeThreads).end()) { 5822292SN/A unsigned tid = *threads++; 5832292SN/A 5842292SN/A if (commitStatus[tid] == ROBSquashing) { 5852292SN/A 5862292SN/A if (rob->isDoneSquashing(tid)) { 5872292SN/A commitStatus[tid] = Running; 5882292SN/A --squashCounter; 5892292SN/A } else { 5902292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5912292SN/A "insts this cycle.\n", tid); 5922292SN/A } 5932292SN/A } 5942292SN/A } 5952292SN/A 5962292SN/A commit(); 5972292SN/A 5982292SN/A markCompletedInsts(); 5992292SN/A 6002292SN/A threads = (*activeThreads).begin(); 6012292SN/A 6022292SN/A while (threads != (*activeThreads).end()) { 6032292SN/A unsigned tid = *threads++; 6042292SN/A 6052292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6062292SN/A // The ROB has more instructions it can commit. Its next status 6072292SN/A // will be active. 6082292SN/A _nextStatus = Active; 6092292SN/A 6102292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6112292SN/A 6122292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6132292SN/A " ROB and ready to commit\n", 6142292SN/A tid, inst->seqNum, inst->readPC()); 6152292SN/A 6162292SN/A } else if (!rob->isEmpty(tid)) { 6172292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6182292SN/A 6192292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6202292SN/A "%#x is head of ROB and not ready\n", 6212292SN/A tid, inst->seqNum, inst->readPC()); 6222292SN/A } 6232292SN/A 6242292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6252292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6262292SN/A } 6272292SN/A 6282292SN/A 6292292SN/A if (wroteToTimeBuffer) { 6302316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6312292SN/A cpu->activityThisCycle(); 6322292SN/A } 6332292SN/A 6342292SN/A updateStatus(); 6352292SN/A} 6362292SN/A 6372292SN/Atemplate <class Impl> 6382292SN/Avoid 6392292SN/ADefaultCommit<Impl>::commit() 6402292SN/A{ 6412292SN/A 6421060SN/A ////////////////////////////////////// 6431060SN/A // Check for interrupts 6441060SN/A ////////////////////////////////////// 6451060SN/A 6461858SN/A#if FULL_SYSTEM 6472316SN/A // Process interrupts if interrupts are enabled, not in PAL mode, 6482316SN/A // and no other traps or external squashes are currently pending. 6492316SN/A // @todo: Allow other threads to handle interrupts. 6502292SN/A if (cpu->checkInterrupts && 6511060SN/A cpu->check_interrupts() && 6522292SN/A !cpu->inPalMode(readPC()) && 6532292SN/A !trapSquash[0] && 6542680Sktlim@umich.edu !tcSquash[0]) { 6552316SN/A // Tell fetch that there is an interrupt pending. This will 6562316SN/A // make fetch wait until it sees a non PAL-mode PC, at which 6572316SN/A // point it stops fetching instructions. 6582292SN/A toIEW->commitInfo[0].interruptPending = true; 6591060SN/A 6602316SN/A // Wait until the ROB is empty and all stores have drained in 6612316SN/A // order to enter the interrupt. 6622292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6632292SN/A // Not sure which thread should be the one to interrupt. For now 6642292SN/A // always do thread 0. 6652292SN/A assert(!thread[0]->inSyscall); 6662292SN/A thread[0]->inSyscall = true; 6672292SN/A 6682292SN/A // CPU will handle implementation of the interrupt. 6692292SN/A cpu->processInterrupts(); 6702292SN/A 6712292SN/A // Now squash or record that I need to squash this cycle. 6722292SN/A commitStatus[0] = TrapPending; 6732292SN/A 6742292SN/A // Exit state update mode to avoid accidental updating. 6752292SN/A thread[0]->inSyscall = false; 6762292SN/A 6772292SN/A // Generate trap squash event. 6782292SN/A generateTrapEvent(0); 6792292SN/A 6802292SN/A toIEW->commitInfo[0].clearInterrupt = true; 6812292SN/A 6822292SN/A DPRINTF(Commit, "Interrupt detected.\n"); 6832292SN/A } else { 6842292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6852292SN/A } 6861060SN/A } 6871060SN/A#endif // FULL_SYSTEM 6881060SN/A 6891060SN/A //////////////////////////////////// 6902316SN/A // Check for any possible squashes, handle them first 6911060SN/A //////////////////////////////////// 6921060SN/A 6932292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6941060SN/A 6952292SN/A while (threads != (*activeThreads).end()) { 6962292SN/A unsigned tid = *threads++; 6972348SN/A/* 6982307SN/A if (fromFetch->fetchFault && commitStatus[0] != TrapPending) { 6992316SN/A // Record the fault. Wait until it's empty in the ROB. 7002316SN/A // Then handle the trap. Ignore it if there's already a 7012316SN/A // trap pending as fetch will be redirected. 7022292SN/A fetchFault = fromFetch->fetchFault; 7032292SN/A fetchFaultTick = curTick + fetchTrapLatency; 7042292SN/A commitStatus[0] = FetchTrapPending; 7052292SN/A DPRINTF(Commit, "Fault from fetch recorded. Will trap if the " 7062292SN/A "ROB empties without squashing the fault.\n"); 7072292SN/A fetchTrapWait = 0; 7082292SN/A } 7091060SN/A 7102316SN/A // Fetch may tell commit to clear the trap if it's been squashed. 7112292SN/A if (fromFetch->clearFetchFault) { 7122292SN/A DPRINTF(Commit, "Received clear fetch fault signal\n"); 7132292SN/A fetchTrapWait = 0; 7142292SN/A if (commitStatus[0] == FetchTrapPending) { 7152292SN/A DPRINTF(Commit, "Clearing fault from fetch\n"); 7162292SN/A commitStatus[0] = Running; 7172292SN/A } 7182292SN/A } 7192348SN/A*/ 7202292SN/A // Not sure which one takes priority. I think if we have 7212292SN/A // both, that's a bad sign. 7222292SN/A if (trapSquash[tid] == true) { 7232680Sktlim@umich.edu assert(!tcSquash[tid]); 7242292SN/A squashFromTrap(tid); 7252680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7262680Sktlim@umich.edu squashFromTC(tid); 7272292SN/A } 7281061SN/A 7292292SN/A // Squashed sequence number must be older than youngest valid 7302292SN/A // instruction in the ROB. This prevents squashes from younger 7312292SN/A // instructions overriding squashes from older instructions. 7322292SN/A if (fromIEW->squash[tid] && 7332292SN/A commitStatus[tid] != TrapPending && 7342292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7351061SN/A 7362292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7372292SN/A tid, 7382292SN/A fromIEW->mispredPC[tid], 7392292SN/A fromIEW->squashedSeqNum[tid]); 7401061SN/A 7412292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7422292SN/A tid, 7432292SN/A fromIEW->nextPC[tid]); 7441061SN/A 7452292SN/A commitStatus[tid] = ROBSquashing; 7461061SN/A 7472292SN/A ++squashCounter; 7481061SN/A 7492292SN/A // If we want to include the squashing instruction in the squash, 7502292SN/A // then use one older sequence number. 7512292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7521062SN/A 7532292SN/A if (fromIEW->includeSquashInst[tid] == true) 7542292SN/A squashed_inst--; 7552292SN/A 7562292SN/A // All younger instructions will be squashed. Set the sequence 7572292SN/A // number as the youngest instruction in the ROB. 7582292SN/A youngestSeqNum[tid] = squashed_inst; 7592292SN/A 7602292SN/A rob->squash(squashed_inst, tid); 7612292SN/A changedROBNumEntries[tid] = true; 7622292SN/A 7632292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7642292SN/A 7652292SN/A toIEW->commitInfo[tid].squash = true; 7662292SN/A 7672292SN/A // Send back the rob squashing signal so other stages know that 7682292SN/A // the ROB is in the process of squashing. 7692292SN/A toIEW->commitInfo[tid].robSquashing = true; 7702292SN/A 7712292SN/A toIEW->commitInfo[tid].branchMispredict = 7722292SN/A fromIEW->branchMispredict[tid]; 7732292SN/A 7742292SN/A toIEW->commitInfo[tid].branchTaken = 7752292SN/A fromIEW->branchTaken[tid]; 7762292SN/A 7772292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7782292SN/A 7792316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7802292SN/A 7812292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7822292SN/A ++branchMispredicts; 7832292SN/A } 7841062SN/A } 7852292SN/A 7861060SN/A } 7871060SN/A 7882292SN/A setNextStatus(); 7892292SN/A 7902292SN/A if (squashCounter != numThreads) { 7911061SN/A // If we're not currently squashing, then get instructions. 7921060SN/A getInsts(); 7931060SN/A 7941061SN/A // Try to commit any instructions. 7951060SN/A commitInsts(); 7961060SN/A } 7971060SN/A 7982292SN/A //Check for any activity 7992292SN/A threads = (*activeThreads).begin(); 8002292SN/A 8012292SN/A while (threads != (*activeThreads).end()) { 8022292SN/A unsigned tid = *threads++; 8032292SN/A 8042292SN/A if (changedROBNumEntries[tid]) { 8052292SN/A toIEW->commitInfo[tid].usedROB = true; 8062292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8072292SN/A 8082292SN/A if (rob->isEmpty(tid)) { 8092292SN/A toIEW->commitInfo[tid].emptyROB = true; 8102292SN/A } 8112292SN/A 8122292SN/A wroteToTimeBuffer = true; 8132292SN/A changedROBNumEntries[tid] = false; 8142292SN/A } 8151060SN/A } 8161060SN/A} 8171060SN/A 8181061SN/Atemplate <class Impl> 8191060SN/Avoid 8202292SN/ADefaultCommit<Impl>::commitInsts() 8211060SN/A{ 8221060SN/A //////////////////////////////////// 8231060SN/A // Handle commit 8242316SN/A // Note that commit will be handled prior to putting new 8252316SN/A // instructions in the ROB so that the ROB only tries to commit 8262316SN/A // instructions it has in this current cycle, and not instructions 8272316SN/A // it is writing in during this cycle. Can't commit and squash 8282316SN/A // things at the same time... 8291060SN/A //////////////////////////////////// 8301060SN/A 8312292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8321060SN/A 8331060SN/A unsigned num_committed = 0; 8341060SN/A 8352292SN/A DynInstPtr head_inst; 8362316SN/A 8371060SN/A // Commit as many instructions as possible until the commit bandwidth 8381060SN/A // limit is reached, or it becomes impossible to commit any more. 8392292SN/A while (num_committed < commitWidth) { 8402292SN/A int commit_thread = getCommittingThread(); 8411060SN/A 8422292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8432292SN/A break; 8442292SN/A 8452292SN/A head_inst = rob->readHeadInst(commit_thread); 8462292SN/A 8472292SN/A int tid = head_inst->threadNumber; 8482292SN/A 8492292SN/A assert(tid == commit_thread); 8502292SN/A 8512292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8522292SN/A head_inst->seqNum, tid); 8532132SN/A 8542316SN/A // If the head instruction is squashed, it is ready to retire 8552316SN/A // (be removed from the ROB) at any time. 8561060SN/A if (head_inst->isSquashed()) { 8571060SN/A 8582292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8591060SN/A "ROB.\n"); 8601060SN/A 8612292SN/A rob->retireHead(commit_thread); 8621060SN/A 8631062SN/A ++commitSquashedInsts; 8641062SN/A 8652292SN/A // Record that the number of ROB entries has changed. 8662292SN/A changedROBNumEntries[tid] = true; 8671060SN/A } else { 8682292SN/A PC[tid] = head_inst->readPC(); 8692292SN/A nextPC[tid] = head_inst->readNextPC(); 8702292SN/A 8711060SN/A // Increment the total number of non-speculative instructions 8721060SN/A // executed. 8731060SN/A // Hack for now: it really shouldn't happen until after the 8741061SN/A // commit is deemed to be successful, but this count is needed 8751061SN/A // for syscalls. 8762292SN/A thread[tid]->funcExeInst++; 8771060SN/A 8781060SN/A // Try to commit the head instruction. 8791060SN/A bool commit_success = commitHead(head_inst, num_committed); 8801060SN/A 8811062SN/A if (commit_success) { 8821060SN/A ++num_committed; 8831060SN/A 8842292SN/A changedROBNumEntries[tid] = true; 8852292SN/A 8862292SN/A // Set the doneSeqNum to the youngest committed instruction. 8872292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 8881060SN/A 8891062SN/A ++commitCommittedInsts; 8901062SN/A 8912292SN/A // To match the old model, don't count nops and instruction 8922292SN/A // prefetches towards the total commit count. 8932292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 8942292SN/A cpu->instDone(tid); 8951062SN/A } 8962292SN/A 8972292SN/A PC[tid] = nextPC[tid]; 8982307SN/A nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 8992292SN/A#if FULL_SYSTEM 9002292SN/A int count = 0; 9012292SN/A Addr oldpc; 9022292SN/A do { 9032316SN/A // Debug statement. Checks to make sure we're not 9042316SN/A // currently updating state while handling PC events. 9052292SN/A if (count == 0) 9062316SN/A assert(!thread[tid]->inSyscall && 9072316SN/A !thread[tid]->trapPending); 9082292SN/A oldpc = PC[tid]; 9092292SN/A cpu->system->pcEventQueue.service( 9102292SN/A thread[tid]->getXCProxy()); 9112292SN/A count++; 9122292SN/A } while (oldpc != PC[tid]); 9132292SN/A if (count > 1) { 9142292SN/A DPRINTF(Commit, "PC skip function event, stopping commit\n"); 9152292SN/A break; 9162292SN/A } 9172292SN/A#endif 9181060SN/A } else { 9192292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9202292SN/A "[tid:%i] [sn:%i].\n", 9212292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9221060SN/A break; 9231060SN/A } 9241060SN/A } 9251060SN/A } 9261062SN/A 9271063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9282292SN/A numCommittedDist.sample(num_committed); 9292307SN/A 9302307SN/A if (num_committed == commitWidth) { 9312349SN/A commitEligibleSamples++; 9322307SN/A } 9331060SN/A} 9341060SN/A 9351061SN/Atemplate <class Impl> 9361060SN/Abool 9372292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9381060SN/A{ 9391060SN/A assert(head_inst); 9401060SN/A 9412292SN/A int tid = head_inst->threadNumber; 9422292SN/A 9432316SN/A // If the instruction is not executed yet, then it will need extra 9442316SN/A // handling. Signal backwards that it should be executed. 9451061SN/A if (!head_inst->isExecuted()) { 9461061SN/A // Keep this number correct. We have not yet actually executed 9471061SN/A // and committed this instruction. 9482292SN/A thread[tid]->funcExeInst--; 9491062SN/A 9502292SN/A head_inst->reachedCommit = true; 9511060SN/A 9522292SN/A if (head_inst->isNonSpeculative() || 9532348SN/A head_inst->isStoreConditional() || 9542292SN/A head_inst->isMemBarrier() || 9552292SN/A head_inst->isWriteBarrier()) { 9562316SN/A 9572316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9582316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9592316SN/A head_inst->seqNum, head_inst->readPC()); 9602316SN/A 9612292SN/A#if !FULL_SYSTEM 9622316SN/A // Hack to make sure syscalls/memory barriers/quiesces 9632316SN/A // aren't executed until all stores write back their data. 9642316SN/A // This direct communication shouldn't be used for 9652316SN/A // anything other than this. 9662292SN/A if (inst_num > 0 || iewStage->hasStoresToWB()) 9672292SN/A#else 9682292SN/A if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 9692292SN/A head_inst->isQuiesce()) && 9702292SN/A iewStage->hasStoresToWB()) 9712292SN/A#endif 9722292SN/A { 9732292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9742292SN/A return false; 9752292SN/A } 9762292SN/A 9772292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9781061SN/A 9791061SN/A // Change the instruction so it won't try to commit again until 9801061SN/A // it is executed. 9811061SN/A head_inst->clearCanCommit(); 9821061SN/A 9831062SN/A ++commitNonSpecStalls; 9841062SN/A 9851061SN/A return false; 9862292SN/A } else if (head_inst->isLoad()) { 9872292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9882292SN/A head_inst->seqNum, head_inst->readPC()); 9892292SN/A 9902292SN/A // Send back the non-speculative instruction's sequence 9912316SN/A // number. Tell the lsq to re-execute the load. 9922292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9932292SN/A toIEW->commitInfo[tid].uncached = true; 9942292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 9952292SN/A 9962292SN/A head_inst->clearCanCommit(); 9972292SN/A 9982292SN/A return false; 9991061SN/A } else { 10002292SN/A panic("Trying to commit un-executed instruction " 10011061SN/A "of unknown type!\n"); 10021061SN/A } 10031060SN/A } 10041060SN/A 10052316SN/A if (head_inst->isThreadSync()) { 10062292SN/A // Not handled for now. 10072316SN/A panic("Thread sync instructions are not handled yet.\n"); 10082132SN/A } 10092132SN/A 10102316SN/A // Stores mark themselves as completed. 10112310SN/A if (!head_inst->isStore()) { 10122310SN/A head_inst->setCompleted(); 10132310SN/A } 10142310SN/A 10152316SN/A // Use checker prior to updating anything due to traps or PC 10162316SN/A // based events. 10172316SN/A if (cpu->checker) { 10182316SN/A cpu->checker->tick(head_inst); 10191060SN/A } 10201060SN/A 10211060SN/A // Check if the instruction caused a fault. If so, trap. 10222132SN/A Fault inst_fault = head_inst->getFault(); 10231681SN/A 10242112SN/A if (inst_fault != NoFault) { 10252316SN/A head_inst->setCompleted(); 10261858SN/A#if FULL_SYSTEM 10272316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10282316SN/A head_inst->seqNum, head_inst->readPC()); 10292292SN/A 10302316SN/A if (iewStage->hasStoresToWB() || inst_num > 0) { 10312316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10322316SN/A return false; 10332316SN/A } 10342310SN/A 10352316SN/A if (cpu->checker && head_inst->isStore()) { 10362316SN/A cpu->checker->tick(head_inst); 10372316SN/A } 10382292SN/A 10392316SN/A assert(!thread[tid]->inSyscall); 10402292SN/A 10412316SN/A // Mark that we're in state update mode so that the trap's 10422316SN/A // execution doesn't generate extra squashes. 10432316SN/A thread[tid]->inSyscall = true; 10442292SN/A 10452316SN/A // DTB will sometimes need the machine instruction for when 10462316SN/A // faults happen. So we will set it here, prior to the DTB 10472316SN/A // possibly needing it for its fault. 10482316SN/A thread[tid]->setInst( 10492316SN/A static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10502292SN/A 10512316SN/A // Execute the trap. Although it's slightly unrealistic in 10522316SN/A // terms of timing (as it doesn't wait for the full timing of 10532316SN/A // the trap event to complete before updating state), it's 10542316SN/A // needed to update the state as soon as possible. This 10552316SN/A // prevents external agents from changing any specific state 10562316SN/A // that the trap need. 10572316SN/A cpu->trap(inst_fault, tid); 10582292SN/A 10592316SN/A // Exit state update mode to avoid accidental updating. 10602316SN/A thread[tid]->inSyscall = false; 10612292SN/A 10622316SN/A commitStatus[tid] = TrapPending; 10632292SN/A 10642316SN/A // Generate trap squash event. 10652316SN/A generateTrapEvent(tid); 10662316SN/A 10672316SN/A return false; 10681060SN/A#else // !FULL_SYSTEM 10692316SN/A panic("fault (%d) detected @ PC %08p", inst_fault, 10702316SN/A head_inst->PC); 10711062SN/A#endif // FULL_SYSTEM 10721060SN/A } 10731060SN/A 10742301SN/A updateComInstStats(head_inst); 10752132SN/A 10762132SN/A if (head_inst->traceData) { 10772292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 10782292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 10792132SN/A head_inst->traceData->finalize(); 10802292SN/A head_inst->traceData = NULL; 10811060SN/A } 10821060SN/A 10832292SN/A // Update the commit rename map 10842292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 10852292SN/A renameMap[tid]->setEntry(head_inst->destRegIdx(i), 10862292SN/A head_inst->renamedDestRegIdx(i)); 10871060SN/A } 10881062SN/A 10892292SN/A // Finally clear the head ROB entry. 10902292SN/A rob->retireHead(tid); 10911060SN/A 10921060SN/A // Return true to indicate that we have committed an instruction. 10931060SN/A return true; 10941060SN/A} 10951060SN/A 10961061SN/Atemplate <class Impl> 10971060SN/Avoid 10982292SN/ADefaultCommit<Impl>::getInsts() 10991060SN/A{ 11002316SN/A // Read any renamed instructions and place them into the ROB. 11011061SN/A int insts_to_process = min((int)renameWidth, fromRename->size); 11021061SN/A 11032292SN/A for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 11041060SN/A { 11052292SN/A DynInstPtr inst = fromRename->insts[inst_num]; 11062292SN/A int tid = inst->threadNumber; 11072292SN/A 11082292SN/A if (!inst->isSquashed() && 11092292SN/A commitStatus[tid] != ROBSquashing) { 11102292SN/A changedROBNumEntries[tid] = true; 11112292SN/A 11122292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 11132292SN/A inst->readPC(), inst->seqNum, tid); 11142292SN/A 11152292SN/A rob->insertInst(inst); 11162292SN/A 11172292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 11182292SN/A 11192292SN/A youngestSeqNum[tid] = inst->seqNum; 11201061SN/A } else { 11212292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11221061SN/A "squashed, skipping.\n", 11232292SN/A inst->readPC(), inst->seqNum, tid); 11241061SN/A } 11251060SN/A } 11261060SN/A} 11271060SN/A 11281061SN/Atemplate <class Impl> 11291060SN/Avoid 11302292SN/ADefaultCommit<Impl>::markCompletedInsts() 11311060SN/A{ 11321060SN/A // Grab completed insts out of the IEW instruction queue, and mark 11331060SN/A // instructions completed within the ROB. 11341060SN/A for (int inst_num = 0; 11351681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 11361060SN/A ++inst_num) 11371060SN/A { 11382292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 11392316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 11402316SN/A "within ROB.\n", 11412292SN/A fromIEW->insts[inst_num]->threadNumber, 11422292SN/A fromIEW->insts[inst_num]->readPC(), 11432292SN/A fromIEW->insts[inst_num]->seqNum); 11441060SN/A 11452292SN/A // Mark the instruction as ready to commit. 11462292SN/A fromIEW->insts[inst_num]->setCanCommit(); 11472292SN/A } 11481060SN/A } 11491060SN/A} 11501060SN/A 11511061SN/Atemplate <class Impl> 11522292SN/Abool 11532292SN/ADefaultCommit<Impl>::robDoneSquashing() 11541060SN/A{ 11552292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11562292SN/A 11572292SN/A while (threads != (*activeThreads).end()) { 11582292SN/A unsigned tid = *threads++; 11592292SN/A 11602292SN/A if (!rob->isDoneSquashing(tid)) 11612292SN/A return false; 11622292SN/A } 11632292SN/A 11642292SN/A return true; 11651060SN/A} 11662292SN/A 11672301SN/Atemplate <class Impl> 11682301SN/Avoid 11692301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 11702301SN/A{ 11712301SN/A unsigned thread = inst->threadNumber; 11722301SN/A 11732301SN/A // 11742301SN/A // Pick off the software prefetches 11752301SN/A // 11762301SN/A#ifdef TARGET_ALPHA 11772301SN/A if (inst->isDataPrefetch()) { 11782316SN/A statComSwp[thread]++; 11792301SN/A } else { 11802316SN/A statComInst[thread]++; 11812301SN/A } 11822301SN/A#else 11832316SN/A statComInst[thread]++; 11842301SN/A#endif 11852301SN/A 11862301SN/A // 11872301SN/A // Control Instructions 11882301SN/A // 11892301SN/A if (inst->isControl()) 11902316SN/A statComBranches[thread]++; 11912301SN/A 11922301SN/A // 11932301SN/A // Memory references 11942301SN/A // 11952301SN/A if (inst->isMemRef()) { 11962316SN/A statComRefs[thread]++; 11972301SN/A 11982301SN/A if (inst->isLoad()) { 11992316SN/A statComLoads[thread]++; 12002301SN/A } 12012301SN/A } 12022301SN/A 12032301SN/A if (inst->isMemBarrier()) { 12042316SN/A statComMembars[thread]++; 12052301SN/A } 12062301SN/A} 12072301SN/A 12082292SN/A//////////////////////////////////////// 12092292SN/A// // 12102316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 12112292SN/A// // 12122292SN/A//////////////////////////////////////// 12132292SN/Atemplate <class Impl> 12142292SN/Aint 12152292SN/ADefaultCommit<Impl>::getCommittingThread() 12162292SN/A{ 12172292SN/A if (numThreads > 1) { 12182292SN/A switch (commitPolicy) { 12192292SN/A 12202292SN/A case Aggressive: 12212292SN/A //If Policy is Aggressive, commit will call 12222292SN/A //this function multiple times per 12232292SN/A //cycle 12242292SN/A return oldestReady(); 12252292SN/A 12262292SN/A case RoundRobin: 12272292SN/A return roundRobin(); 12282292SN/A 12292292SN/A case OldestReady: 12302292SN/A return oldestReady(); 12312292SN/A 12322292SN/A default: 12332292SN/A return -1; 12342292SN/A } 12352292SN/A } else { 12362292SN/A int tid = (*activeThreads).front(); 12372292SN/A 12382292SN/A if (commitStatus[tid] == Running || 12392292SN/A commitStatus[tid] == Idle || 12402292SN/A commitStatus[tid] == FetchTrapPending) { 12412292SN/A return tid; 12422292SN/A } else { 12432292SN/A return -1; 12442292SN/A } 12452292SN/A } 12462292SN/A} 12472292SN/A 12482292SN/Atemplate<class Impl> 12492292SN/Aint 12502292SN/ADefaultCommit<Impl>::roundRobin() 12512292SN/A{ 12522292SN/A list<unsigned>::iterator pri_iter = priority_list.begin(); 12532292SN/A list<unsigned>::iterator end = priority_list.end(); 12542292SN/A 12552292SN/A while (pri_iter != end) { 12562292SN/A unsigned tid = *pri_iter; 12572292SN/A 12582292SN/A if (commitStatus[tid] == Running || 12592292SN/A commitStatus[tid] == Idle) { 12602292SN/A 12612292SN/A if (rob->isHeadReady(tid)) { 12622292SN/A priority_list.erase(pri_iter); 12632292SN/A priority_list.push_back(tid); 12642292SN/A 12652292SN/A return tid; 12662292SN/A } 12672292SN/A } 12682292SN/A 12692292SN/A pri_iter++; 12702292SN/A } 12712292SN/A 12722292SN/A return -1; 12732292SN/A} 12742292SN/A 12752292SN/Atemplate<class Impl> 12762292SN/Aint 12772292SN/ADefaultCommit<Impl>::oldestReady() 12782292SN/A{ 12792292SN/A unsigned oldest = 0; 12802292SN/A bool first = true; 12812292SN/A 12822292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 12832292SN/A 12842292SN/A while (threads != (*activeThreads).end()) { 12852292SN/A unsigned tid = *threads++; 12862292SN/A 12872292SN/A if (!rob->isEmpty(tid) && 12882292SN/A (commitStatus[tid] == Running || 12892292SN/A commitStatus[tid] == Idle || 12902292SN/A commitStatus[tid] == FetchTrapPending)) { 12912292SN/A 12922292SN/A if (rob->isHeadReady(tid)) { 12932292SN/A 12942292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 12952292SN/A 12962292SN/A if (first) { 12972292SN/A oldest = tid; 12982292SN/A first = false; 12992292SN/A } else if (head_inst->seqNum < oldest) { 13002292SN/A oldest = tid; 13012292SN/A } 13022292SN/A } 13032292SN/A } 13042292SN/A } 13052292SN/A 13062292SN/A if (!first) { 13072292SN/A return oldest; 13082292SN/A } else { 13092292SN/A return -1; 13102292SN/A } 13112292SN/A} 1312