commit_impl.hh revision 2329
12SN/A/* 29955SGeoffrey.Blake@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 39955SGeoffrey.Blake@arm.com * All rights reserved. 49955SGeoffrey.Blake@arm.com * 59955SGeoffrey.Blake@arm.com * Redistribution and use in source and binary forms, with or without 69955SGeoffrey.Blake@arm.com * modification, are permitted provided that the following conditions are 79955SGeoffrey.Blake@arm.com * met: redistributions of source code must retain the above copyright 89955SGeoffrey.Blake@arm.com * notice, this list of conditions and the following disclaimer; 99955SGeoffrey.Blake@arm.com * redistributions in binary form must reproduce the above copyright 109955SGeoffrey.Blake@arm.com * notice, this list of conditions and the following disclaimer in the 119955SGeoffrey.Blake@arm.com * documentation and/or other materials provided with the distribution; 129955SGeoffrey.Blake@arm.com * neither the name of the copyright holders nor the names of its 139955SGeoffrey.Blake@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 157778Sgblack@eecs.umich.edu * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#include <algorithm> 302SN/A#include <string> 312SN/A 322SN/A#include "base/loader/symtab.hh" 332SN/A#include "base/timebuf.hh" 342SN/A#include "cpu/checker/cpu.hh" 352SN/A#include "cpu/exetrace.hh" 362SN/A#include "cpu/o3/commit.hh" 372SN/A#include "cpu/o3/thread_state.hh" 382SN/A 392SN/Ausing namespace std; 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.edutemplate <class Impl> 422665Ssaidi@eecs.umich.eduDefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 437778Sgblack@eecs.umich.edu unsigned _tid) 449955SGeoffrey.Blake@arm.com : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 452SN/A{ 462SN/A this->setFlags(Event::AutoDelete); 471078SN/A} 481078SN/A 491078SN/Atemplate <class Impl> 501114SN/Avoid 511078SN/ADefaultCommit<Impl>::TrapEvent::process() 521114SN/A{ 531114SN/A // This will get reset by commit if it was switched out at the 541114SN/A // time of this event processing. 556216Snate@binkert.org commit->trapSquash[tid] = true; 5611263Sandreas.sandberg@arm.com} 571078SN/A 581078SN/Atemplate <class Impl> 591078SN/Aconst char * 601078SN/ADefaultCommit<Impl>::TrapEvent::description() 611078SN/A{ 621078SN/A return "Trap event"; 631078SN/A} 641078SN/A 651078SN/Atemplate <class Impl> 661078SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 671078SN/A : dcacheInterface(params->dcacheInterface), 681078SN/A squashCounter(0), 691078SN/A iewToCommitDelay(params->iewToCommitDelay), 701078SN/A commitToIEWDelay(params->commitToIEWDelay), 712SN/A renameToROBDelay(params->renameToROBDelay), 721114SN/A fetchToCommitDelay(params->commitToFetchDelay), 732SN/A renameWidth(params->renameWidth), 741114SN/A iewWidth(params->executeWidth), 751114SN/A commitWidth(params->commitWidth), 761114SN/A numThreads(params->numberOfThreads), 771114SN/A switchedOut(false), 781114SN/A trapLatency(params->trapLatency), 791114SN/A fetchTrapLatency(params->fetchTrapLatency) 801114SN/A{ 811078SN/A _status = Active; 821114SN/A _nextStatus = Inactive; 831114SN/A string policy = params->smtCommitPolicy; 841114SN/A 851114SN/A //Convert string to lowercase 861114SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 871114SN/A (int(*)(int)) tolower); 881114SN/A 891079SN/A //Assign commit policy 901114SN/A if (policy == "aggressive"){ 911114SN/A commitPolicy = Aggressive; 921114SN/A 931114SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 941114SN/A } else if (policy == "roundrobin"){ 951114SN/A commitPolicy = RoundRobin; 9610251Satgutier@umich.edu 9710251Satgutier@umich.edu //Set-Up Priority List 9810251Satgutier@umich.edu for (int tid=0; tid < numThreads; tid++) { 9910251Satgutier@umich.edu priority_list.push_back(tid); 10010251Satgutier@umich.edu } 10110251Satgutier@umich.edu 10210251Satgutier@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 10310251Satgutier@umich.edu } else if (policy == "oldestready"){ 10410251Satgutier@umich.edu commitPolicy = OldestReady; 10510251Satgutier@umich.edu 10610251Satgutier@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 10710251Satgutier@umich.edu } else { 1081114SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1091137SN/A "RoundRobin,OldestReady}"); 1101137SN/A } 1111137SN/A 1121137SN/A for (int i=0; i < numThreads; i++) { 1131137SN/A commitStatus[i] = Idle; 1141137SN/A changedROBNumEntries[i] = false; 1151137SN/A trapSquash[i] = false; 1161137SN/A xcSquash[i] = false; 1171137SN/A } 1181137SN/A 1191137SN/A fetchFaultTick = 0; 1201137SN/A fetchTrapWait = 0; 1211137SN/A} 1221114SN/A 1231114SN/Atemplate <class Impl> 1241114SN/Astd::string 1251114SN/ADefaultCommit<Impl>::name() const 1261114SN/A{ 1271114SN/A return cpu->name() + ".commit"; 1281078SN/A} 1299955SGeoffrey.Blake@arm.com 1309955SGeoffrey.Blake@arm.comtemplate <class Impl> 1319955SGeoffrey.Blake@arm.comvoid 1329955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::regStats() 1339955SGeoffrey.Blake@arm.com{ 1349955SGeoffrey.Blake@arm.com using namespace Stats; 1359955SGeoffrey.Blake@arm.com commitCommittedInsts 1369955SGeoffrey.Blake@arm.com .name(name() + ".commitCommittedInsts") 1379955SGeoffrey.Blake@arm.com .desc("The number of committed instructions") 1389955SGeoffrey.Blake@arm.com .prereq(commitCommittedInsts); 1399955SGeoffrey.Blake@arm.com commitSquashedInsts 1409955SGeoffrey.Blake@arm.com .name(name() + ".commitSquashedInsts") 1419955SGeoffrey.Blake@arm.com .desc("The number of squashed insts skipped by commit") 1429955SGeoffrey.Blake@arm.com .prereq(commitSquashedInsts); 1439955SGeoffrey.Blake@arm.com commitSquashEvents 1449955SGeoffrey.Blake@arm.com .name(name() + ".commitSquashEvents") 1451114SN/A .desc("The number of times commit is told to squash") 1461114SN/A .prereq(commitSquashEvents); 1471079SN/A commitNonSpecStalls 1489955SGeoffrey.Blake@arm.com .name(name() + ".commitNonSpecStalls") 1499955SGeoffrey.Blake@arm.com .desc("The number of times commit has been forced to stall to " 1509955SGeoffrey.Blake@arm.com "communicate backwards") 1519955SGeoffrey.Blake@arm.com .prereq(commitNonSpecStalls); 1529955SGeoffrey.Blake@arm.com branchMispredicts 1539955SGeoffrey.Blake@arm.com .name(name() + ".branchMispredicts") 1541079SN/A .desc("The number of times a branch was mispredicted") 1551079SN/A .prereq(branchMispredicts); 1561079SN/A numCommittedDist 1571079SN/A .init(0,commitWidth,1) 1581079SN/A .name(name() + ".COM:committed_per_cycle") 1591078SN/A .desc("Number of insts commited each cycle") 1601078SN/A .flags(Stats::pdf) 1611114SN/A ; 1621114SN/A 1631114SN/A statComInst 1641114SN/A .init(cpu->number_of_threads) 1659955SGeoffrey.Blake@arm.com .name(name() + ".COM:count") 1662566SN/A .desc("Number of instructions committed") 1671114SN/A .flags(total) 1681114SN/A ; 1691114SN/A 1702566SN/A statComSwp 1711114SN/A .init(cpu->number_of_threads) 1721114SN/A .name(name() + ".COM:swp_count") 1731114SN/A .desc("Number of s/w prefetches committed") 1741114SN/A .flags(total) 1751114SN/A ; 1761114SN/A 1771114SN/A statComRefs 1781114SN/A .init(cpu->number_of_threads) 1791114SN/A .name(name() + ".COM:refs") 1802566SN/A .desc("Number of memory references committed") 1811114SN/A .flags(total) 1822566SN/A ; 1832566SN/A 1841114SN/A statComLoads 18510469Sandreas.hansson@arm.com .init(cpu->number_of_threads) 1865782Ssaidi@eecs.umich.edu .name(name() + ".COM:loads") 1875782Ssaidi@eecs.umich.edu .desc("Number of loads committed") 1881114SN/A .flags(total) 1891114SN/A ; 1901114SN/A 1911114SN/A statComMembars 1921114SN/A .init(cpu->number_of_threads) 1937777Sgblack@eecs.umich.edu .name(name() + ".COM:membars") 1947777Sgblack@eecs.umich.edu .desc("Number of memory barriers committed") 1957777Sgblack@eecs.umich.edu .flags(total) 1967777Sgblack@eecs.umich.edu ; 1977777Sgblack@eecs.umich.edu 1987777Sgblack@eecs.umich.edu statComBranches 1997777Sgblack@eecs.umich.edu .init(cpu->number_of_threads) 2007777Sgblack@eecs.umich.edu .name(name() + ".COM:branches") 2017777Sgblack@eecs.umich.edu .desc("Number of branches committed") 2027777Sgblack@eecs.umich.edu .flags(total) 2037777Sgblack@eecs.umich.edu ; 2047777Sgblack@eecs.umich.edu 2057777Sgblack@eecs.umich.edu // 2067777Sgblack@eecs.umich.edu // Commit-Eligible instructions... 2077777Sgblack@eecs.umich.edu // 2087777Sgblack@eecs.umich.edu // -> The number of instructions eligible to commit in those 2097777Sgblack@eecs.umich.edu // cycles where we reached our commit BW limit (less the number 2107777Sgblack@eecs.umich.edu // actually committed) 2117777Sgblack@eecs.umich.edu // 2127777Sgblack@eecs.umich.edu // -> The average value is computed over ALL CYCLES... not just 2137777Sgblack@eecs.umich.edu // the BW limited cycles 2147777Sgblack@eecs.umich.edu // 2157777Sgblack@eecs.umich.edu // -> The standard deviation is computed only over cycles where 2167777Sgblack@eecs.umich.edu // we reached the BW limit 2177777Sgblack@eecs.umich.edu // 2187777Sgblack@eecs.umich.edu commitEligible 2197777Sgblack@eecs.umich.edu .init(cpu->number_of_threads) 2207777Sgblack@eecs.umich.edu .name(name() + ".COM:bw_limited") 2217777Sgblack@eecs.umich.edu .desc("number of insts not committed due to BW limits") 2227777Sgblack@eecs.umich.edu .flags(total) 2237777Sgblack@eecs.umich.edu ; 2247777Sgblack@eecs.umich.edu 2257777Sgblack@eecs.umich.edu commitEligibleSamples 2267777Sgblack@eecs.umich.edu .name(name() + ".COM:bw_lim_events") 2277777Sgblack@eecs.umich.edu .desc("number cycles where commit BW limit reached") 2287777Sgblack@eecs.umich.edu ; 2297777Sgblack@eecs.umich.edu} 2307777Sgblack@eecs.umich.edu 2317777Sgblack@eecs.umich.edutemplate <class Impl> 2327777Sgblack@eecs.umich.eduvoid 2337777Sgblack@eecs.umich.eduDefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr) 2347777Sgblack@eecs.umich.edu{ 2357777Sgblack@eecs.umich.edu DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2367777Sgblack@eecs.umich.edu cpu = cpu_ptr; 2377777Sgblack@eecs.umich.edu 2387777Sgblack@eecs.umich.edu // Commit must broadcast the number of free entries it has at the start of 2397777Sgblack@eecs.umich.edu // the simulation, so it starts as active. 2407777Sgblack@eecs.umich.edu cpu->activateStage(FullCPU::CommitIdx); 2417777Sgblack@eecs.umich.edu 2427777Sgblack@eecs.umich.edu trapLatency = cpu->cycles(trapLatency); 2437777Sgblack@eecs.umich.edu fetchTrapLatency = cpu->cycles(fetchTrapLatency); 2447777Sgblack@eecs.umich.edu} 2457777Sgblack@eecs.umich.edu 2467777Sgblack@eecs.umich.edutemplate <class Impl> 2477777Sgblack@eecs.umich.eduvoid 2487777Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 2497777Sgblack@eecs.umich.edu{ 2507777Sgblack@eecs.umich.edu thread = threads; 2517777Sgblack@eecs.umich.edu} 2521114SN/A 2531114SN/Atemplate <class Impl> 2541078SN/Avoid 2551078SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2561092SN/A{ 2571078SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2581078SN/A timeBuffer = tb_ptr; 2591078SN/A 2601078SN/A // Setup wire to send information back to IEW. 2611078SN/A toIEW = timeBuffer->getWire(0); 2621078SN/A 2631078SN/A // Setup wire to read data from IEW (for the ROB). 2641092SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2651078SN/A} 2661078SN/A 2671078SN/Atemplate <class Impl> 2681092SN/Avoid 2695761Ssaidi@eecs.umich.eduDefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2705761Ssaidi@eecs.umich.edu{ 2715761Ssaidi@eecs.umich.edu DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2721114SN/A fetchQueue = fq_ptr; 2731079SN/A 2741079SN/A // Setup wire to get instructions from rename (for the ROB). 2751079SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2761079SN/A} 2771079SN/A 2781079SN/Atemplate <class Impl> 2791078SN/Avoid 2801078SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2811114SN/A{ 2821114SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2831114SN/A renameQueue = rq_ptr; 2841114SN/A 2851114SN/A // Setup wire to get instructions from rename (for the ROB). 2862566SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2879955SGeoffrey.Blake@arm.com} 2881114SN/A 2892566SN/Atemplate <class Impl> 2901114SN/Avoid 2915484Snate@binkert.orgDefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2929955SGeoffrey.Blake@arm.com{ 2935484Snate@binkert.org DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2945484Snate@binkert.org iewQueue = iq_ptr; 2955484Snate@binkert.org 2965484Snate@binkert.org // Setup wire to get instructions from IEW. 2975484Snate@binkert.org fromIEW = iewQueue->getWire(-iewToCommitDelay); 2989955SGeoffrey.Blake@arm.com} 2999955SGeoffrey.Blake@arm.com 3005484Snate@binkert.orgtemplate <class Impl> 3011114SN/Avoid 3021114SN/ADefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 3031114SN/A{ 3049955SGeoffrey.Blake@arm.com fetchStage = fetch_stage; 3059955SGeoffrey.Blake@arm.com} 3069955SGeoffrey.Blake@arm.com 3079955SGeoffrey.Blake@arm.comtemplate <class Impl> 3081114SN/Avoid 3099955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3109955SGeoffrey.Blake@arm.com{ 3115484Snate@binkert.org iewStage = iew_stage; 3125484Snate@binkert.org} 3131114SN/A 3145484Snate@binkert.orgtemplate<class Impl> 3159955SGeoffrey.Blake@arm.comvoid 3169955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3175484Snate@binkert.org{ 3185484Snate@binkert.org DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3191114SN/A activeThreads = at_ptr; 3202566SN/A} 3211114SN/A 3221114SN/Atemplate <class Impl> 3231114SN/Avoid 3242566SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3252566SN/A{ 3261114SN/A DPRINTF(Commit, "Setting rename map pointers.\n"); 32710469Sandreas.hansson@arm.com 3289955SGeoffrey.Blake@arm.com for (int i=0; i < numThreads; i++) { 3299955SGeoffrey.Blake@arm.com renameMap[i] = &rm_ptr[i]; 3301114SN/A } 3311114SN/A} 3321114SN/A 3331114SN/Atemplate <class Impl> 3341114SN/Avoid 3351114SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3361114SN/A{ 3371114SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3381114SN/A rob = rob_ptr; 3391114SN/A} 3401114SN/A 3411114SN/Atemplate <class Impl> 3421114SN/Avoid 3431114SN/ADefaultCommit<Impl>::initStage() 3441114SN/A{ 3451114SN/A rob->setActiveThreads(activeThreads); 3461114SN/A rob->resetEntries(); 3471114SN/A 3481114SN/A // Broadcast the number of free entries. 3491114SN/A for (int i=0; i < numThreads; i++) { 3501114SN/A toIEW->commitInfo[i].usedROB = true; 3511114SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3521114SN/A } 3531114SN/A 3541114SN/A cpu->activityThisCycle(); 3551114SN/A} 3561114SN/A 3571114SN/Atemplate <class Impl> 3581114SN/Avoid 3591114SN/ADefaultCommit<Impl>::switchOut() 3601114SN/A{ 3619955SGeoffrey.Blake@arm.com switchPending = true; 3629955SGeoffrey.Blake@arm.com} 3639955SGeoffrey.Blake@arm.com 3649955SGeoffrey.Blake@arm.comtemplate <class Impl> 3659955SGeoffrey.Blake@arm.comvoid 3669955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::doSwitchOut() 3679955SGeoffrey.Blake@arm.com{ 3689955SGeoffrey.Blake@arm.com switchedOut = true; 3699955SGeoffrey.Blake@arm.com switchPending = false; 3709955SGeoffrey.Blake@arm.com rob->switchOut(); 3719955SGeoffrey.Blake@arm.com} 3729955SGeoffrey.Blake@arm.com 3739955SGeoffrey.Blake@arm.comtemplate <class Impl> 3749955SGeoffrey.Blake@arm.comvoid 3759955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::takeOverFrom() 3769955SGeoffrey.Blake@arm.com{ 3779955SGeoffrey.Blake@arm.com switchedOut = false; 3789955SGeoffrey.Blake@arm.com _status = Active; 3799955SGeoffrey.Blake@arm.com _nextStatus = Inactive; 3809955SGeoffrey.Blake@arm.com for (int i=0; i < numThreads; i++) { 3819955SGeoffrey.Blake@arm.com commitStatus[i] = Idle; 3829955SGeoffrey.Blake@arm.com changedROBNumEntries[i] = false; 3839955SGeoffrey.Blake@arm.com trapSquash[i] = false; 3849955SGeoffrey.Blake@arm.com xcSquash[i] = false; 3859955SGeoffrey.Blake@arm.com } 3869955SGeoffrey.Blake@arm.com squashCounter = 0; 3879955SGeoffrey.Blake@arm.com rob->takeOverFrom(); 3889955SGeoffrey.Blake@arm.com} 3899955SGeoffrey.Blake@arm.com 3909955SGeoffrey.Blake@arm.comtemplate <class Impl> 3919955SGeoffrey.Blake@arm.comvoid 3929955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::updateStatus() 3939955SGeoffrey.Blake@arm.com{ 3949955SGeoffrey.Blake@arm.com // reset ROB changed variable 3959955SGeoffrey.Blake@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 3969955SGeoffrey.Blake@arm.com while (threads != (*activeThreads).end()) { 3979955SGeoffrey.Blake@arm.com unsigned tid = *threads++; 3989955SGeoffrey.Blake@arm.com changedROBNumEntries[tid] = false; 3999955SGeoffrey.Blake@arm.com 4009955SGeoffrey.Blake@arm.com // Also check if any of the threads has a trap pending 4019955SGeoffrey.Blake@arm.com if (commitStatus[tid] == TrapPending || 4029955SGeoffrey.Blake@arm.com commitStatus[tid] == FetchTrapPending) { 4039955SGeoffrey.Blake@arm.com _nextStatus = Active; 4049955SGeoffrey.Blake@arm.com } 4059955SGeoffrey.Blake@arm.com } 4069955SGeoffrey.Blake@arm.com 4079955SGeoffrey.Blake@arm.com if (_nextStatus == Inactive && _status == Active) { 4089955SGeoffrey.Blake@arm.com DPRINTF(Activity, "Deactivating stage.\n"); 4099955SGeoffrey.Blake@arm.com cpu->deactivateStage(FullCPU::CommitIdx); 4109955SGeoffrey.Blake@arm.com } else if (_nextStatus == Active && _status == Inactive) { 4119955SGeoffrey.Blake@arm.com DPRINTF(Activity, "Activating stage.\n"); 4129955SGeoffrey.Blake@arm.com cpu->activateStage(FullCPU::CommitIdx); 4139955SGeoffrey.Blake@arm.com } 4149955SGeoffrey.Blake@arm.com 4159955SGeoffrey.Blake@arm.com _status = _nextStatus; 4169955SGeoffrey.Blake@arm.com} 4179955SGeoffrey.Blake@arm.com 4189955SGeoffrey.Blake@arm.comtemplate <class Impl> 4199955SGeoffrey.Blake@arm.comvoid 4209955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::setNextStatus() 4219955SGeoffrey.Blake@arm.com{ 4229955SGeoffrey.Blake@arm.com int squashes = 0; 4239955SGeoffrey.Blake@arm.com 4249955SGeoffrey.Blake@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 4259955SGeoffrey.Blake@arm.com 4269955SGeoffrey.Blake@arm.com while (threads != (*activeThreads).end()) { 4279955SGeoffrey.Blake@arm.com unsigned tid = *threads++; 4289955SGeoffrey.Blake@arm.com 4299955SGeoffrey.Blake@arm.com if (commitStatus[tid] == ROBSquashing) { 4309955SGeoffrey.Blake@arm.com squashes++; 4319955SGeoffrey.Blake@arm.com } 4329955SGeoffrey.Blake@arm.com } 4339955SGeoffrey.Blake@arm.com 4349955SGeoffrey.Blake@arm.com assert(squashes == squashCounter); 4359955SGeoffrey.Blake@arm.com 4369955SGeoffrey.Blake@arm.com // If commit is currently squashing, then it will have activity for the 4379955SGeoffrey.Blake@arm.com // next cycle. Set its next status as active. 4389955SGeoffrey.Blake@arm.com if (squashCounter) { 4399955SGeoffrey.Blake@arm.com _nextStatus = Active; 4409955SGeoffrey.Blake@arm.com } 4419955SGeoffrey.Blake@arm.com} 4429955SGeoffrey.Blake@arm.com 44310469Sandreas.hansson@arm.comtemplate <class Impl> 4449955SGeoffrey.Blake@arm.combool 4459955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::changedROBEntries() 4469955SGeoffrey.Blake@arm.com{ 4479955SGeoffrey.Blake@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 4489955SGeoffrey.Blake@arm.com 4499955SGeoffrey.Blake@arm.com while (threads != (*activeThreads).end()) { 4509955SGeoffrey.Blake@arm.com unsigned tid = *threads++; 4519955SGeoffrey.Blake@arm.com 4529955SGeoffrey.Blake@arm.com if (changedROBNumEntries[tid]) { 4539955SGeoffrey.Blake@arm.com return true; 4549955SGeoffrey.Blake@arm.com } 4559955SGeoffrey.Blake@arm.com } 4569955SGeoffrey.Blake@arm.com 4579955SGeoffrey.Blake@arm.com return false; 4589955SGeoffrey.Blake@arm.com} 4599955SGeoffrey.Blake@arm.com 4609955SGeoffrey.Blake@arm.comtemplate <class Impl> 4619955SGeoffrey.Blake@arm.comunsigned 4629955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4639955SGeoffrey.Blake@arm.com{ 4649955SGeoffrey.Blake@arm.com return rob->numFreeEntries(tid); 4659955SGeoffrey.Blake@arm.com} 4669955SGeoffrey.Blake@arm.com 4679955SGeoffrey.Blake@arm.comtemplate <class Impl> 4689955SGeoffrey.Blake@arm.comvoid 4699955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4709955SGeoffrey.Blake@arm.com{ 4719955SGeoffrey.Blake@arm.com DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4729955SGeoffrey.Blake@arm.com 4739955SGeoffrey.Blake@arm.com TrapEvent *trap = new TrapEvent(this, tid); 4749955SGeoffrey.Blake@arm.com 4759955SGeoffrey.Blake@arm.com trap->schedule(curTick + trapLatency); 4769955SGeoffrey.Blake@arm.com 4779955SGeoffrey.Blake@arm.com thread[tid]->trapPending = true; 4789955SGeoffrey.Blake@arm.com} 4799955SGeoffrey.Blake@arm.com 4809955SGeoffrey.Blake@arm.comtemplate <class Impl> 4819955SGeoffrey.Blake@arm.comvoid 4829955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::generateXCEvent(unsigned tid) 4839955SGeoffrey.Blake@arm.com{ 4849955SGeoffrey.Blake@arm.com DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid); 4859955SGeoffrey.Blake@arm.com 4869955SGeoffrey.Blake@arm.com xcSquash[tid] = true; 4879955SGeoffrey.Blake@arm.com} 4889955SGeoffrey.Blake@arm.com 4899955SGeoffrey.Blake@arm.comtemplate <class Impl> 4909955SGeoffrey.Blake@arm.comvoid 4919955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::squashAll(unsigned tid) 4929955SGeoffrey.Blake@arm.com{ 4939955SGeoffrey.Blake@arm.com // If we want to include the squashing instruction in the squash, 4949955SGeoffrey.Blake@arm.com // then use one older sequence number. 4959955SGeoffrey.Blake@arm.com // Hopefully this doesn't mess things up. Basically I want to squash 4969955SGeoffrey.Blake@arm.com // all instructions of this thread. 4979955SGeoffrey.Blake@arm.com InstSeqNum squashed_inst = rob->isEmpty() ? 4989955SGeoffrey.Blake@arm.com 0 : rob->readHeadInst(tid)->seqNum - 1;; 4999955SGeoffrey.Blake@arm.com 5009955SGeoffrey.Blake@arm.com // All younger instructions will be squashed. Set the sequence 5019955SGeoffrey.Blake@arm.com // number as the youngest instruction in the ROB (0 in this case. 5029955SGeoffrey.Blake@arm.com // Hopefully nothing breaks.) 5039955SGeoffrey.Blake@arm.com youngestSeqNum[tid] = 0; 5049955SGeoffrey.Blake@arm.com 5059955SGeoffrey.Blake@arm.com rob->squash(squashed_inst, tid); 5069955SGeoffrey.Blake@arm.com changedROBNumEntries[tid] = true; 5071114SN/A 5081114SN/A // Send back the sequence number of the squashed instruction. 5091114SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5101114SN/A 5111078SN/A // Send back the squash signal to tell stages that they should 5121078SN/A // squash. 5131078SN/A toIEW->commitInfo[tid].squash = true; 5141078SN/A 5151078SN/A // Send back the rob squashing signal so other stages know that 5169955SGeoffrey.Blake@arm.com // the ROB is in the process of squashing. 5171078SN/A toIEW->commitInfo[tid].robSquashing = true; 5181078SN/A 5191092SN/A toIEW->commitInfo[tid].branchMispredict = false; 5201078SN/A 5211078SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5221092SN/A} 5235761Ssaidi@eecs.umich.edu 52411320Ssteve.reinhardt@amd.comtemplate <class Impl> 5251078SN/Avoid 5261114SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5271114SN/A{ 5281079SN/A squashAll(tid); 5291079SN/A 5301079SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5311079SN/A 5321079SN/A thread[tid]->trapPending = false; 5331078SN/A thread[tid]->inSyscall = false; 5341078SN/A 5351114SN/A trapSquash[tid] = false; 5361114SN/A 5371114SN/A commitStatus[tid] = ROBSquashing; 5382566SN/A cpu->activityThisCycle(); 5395782Ssaidi@eecs.umich.edu 5401114SN/A ++squashCounter; 5415782Ssaidi@eecs.umich.edu} 5421114SN/A 5431114SN/Atemplate <class Impl> 5445484Snate@binkert.orgvoid 5459955SGeoffrey.Blake@arm.comDefaultCommit<Impl>::squashFromXC(unsigned tid) 5469955SGeoffrey.Blake@arm.com{ 5479955SGeoffrey.Blake@arm.com squashAll(tid); 5489955SGeoffrey.Blake@arm.com 5499955SGeoffrey.Blake@arm.com DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]); 5509955SGeoffrey.Blake@arm.com 5519955SGeoffrey.Blake@arm.com thread[tid]->inSyscall = false; 5529955SGeoffrey.Blake@arm.com assert(!thread[tid]->trapPending); 5531114SN/A 5541114SN/A commitStatus[tid] = ROBSquashing; 5551114SN/A cpu->activityThisCycle(); 5561114SN/A 5571114SN/A xcSquash[tid] = false; 5585782Ssaidi@eecs.umich.edu 5595782Ssaidi@eecs.umich.edu ++squashCounter; 5609955SGeoffrey.Blake@arm.com} 5615782Ssaidi@eecs.umich.edu 5621114SN/Atemplate <class Impl> 5635782Ssaidi@eecs.umich.eduvoid 5645484Snate@binkert.orgDefaultCommit<Impl>::tick() 5655484Snate@binkert.org{ 5661114SN/A wroteToTimeBuffer = false; 5675782Ssaidi@eecs.umich.edu _nextStatus = Inactive; 5685484Snate@binkert.org 5695484Snate@binkert.org if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5701114SN/A cpu->signalSwitched(); 5719955SGeoffrey.Blake@arm.com return; 5729955SGeoffrey.Blake@arm.com } 5739955SGeoffrey.Blake@arm.com 5749955SGeoffrey.Blake@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 5751114SN/A 5762566SN/A // Check if any of the threads are done squashing. Change the 5772566SN/A // status if they are done. 5781114SN/A while (threads != (*activeThreads).end()) { 57910469Sandreas.hansson@arm.com unsigned tid = *threads++; 5805782Ssaidi@eecs.umich.edu 5815782Ssaidi@eecs.umich.edu if (commitStatus[tid] == ROBSquashing) { 5821114SN/A 5831114SN/A if (rob->isDoneSquashing(tid)) { 5841114SN/A commitStatus[tid] = Running; 5851114SN/A --squashCounter; 5861114SN/A } else { 5871114SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5881114SN/A "insts this cycle.\n", tid); 5891114SN/A } 5901114SN/A } 5911114SN/A } 5921114SN/A 5931114SN/A commit(); 5941114SN/A 5951114SN/A markCompletedInsts(); 5961114SN/A 5971114SN/A threads = (*activeThreads).begin(); 5981114SN/A 5991114SN/A while (threads != (*activeThreads).end()) { 6001114SN/A unsigned tid = *threads++; 6011114SN/A 6021114SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6031114SN/A // The ROB has more instructions it can commit. Its next status 6041114SN/A // will be active. 6051114SN/A _nextStatus = Active; 6061114SN/A 6071114SN/A DynInstPtr inst = rob->readHeadInst(tid); 6081114SN/A 6091114SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6101114SN/A " ROB and ready to commit\n", 6111114SN/A tid, inst->seqNum, inst->readPC()); 6121114SN/A 6131114SN/A } else if (!rob->isEmpty(tid)) { 6141114SN/A DynInstPtr inst = rob->readHeadInst(tid); 6151078SN/A 6161078SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6171078SN/A "%#x is head of ROB and not ready\n", 6181078SN/A tid, inst->seqNum, inst->readPC()); 6191171SN/A } 6201078SN/A 6211171SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6225761Ssaidi@eecs.umich.edu tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6231078SN/A } 6241114SN/A 6251079SN/A 6261079SN/A if (wroteToTimeBuffer) { 6271079SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6281079SN/A cpu->activityThisCycle(); 6291078SN/A } 6301078SN/A 6311114SN/A updateStatus(); 6321114SN/A} 6331114SN/A 6342566SN/Atemplate <class Impl> 6355782Ssaidi@eecs.umich.eduvoid 6361114SN/ADefaultCommit<Impl>::commit() 6375782Ssaidi@eecs.umich.edu{ 6381114SN/A 6391114SN/A ////////////////////////////////////// 6405484Snate@binkert.org // Check for interrupts 6419955SGeoffrey.Blake@arm.com ////////////////////////////////////// 6429955SGeoffrey.Blake@arm.com 6439955SGeoffrey.Blake@arm.com#if FULL_SYSTEM 6449955SGeoffrey.Blake@arm.com // Process interrupts if interrupts are enabled, not in PAL mode, 6459955SGeoffrey.Blake@arm.com // and no other traps or external squashes are currently pending. 6469955SGeoffrey.Blake@arm.com // @todo: Allow other threads to handle interrupts. 6479955SGeoffrey.Blake@arm.com if (cpu->checkInterrupts && 6489955SGeoffrey.Blake@arm.com cpu->check_interrupts() && 6491114SN/A !cpu->inPalMode(readPC()) && 6501114SN/A !trapSquash[0] && 6511114SN/A !xcSquash[0]) { 6521114SN/A // Tell fetch that there is an interrupt pending. This will 6531114SN/A // make fetch wait until it sees a non PAL-mode PC, at which 6545782Ssaidi@eecs.umich.edu // point it stops fetching instructions. 6555782Ssaidi@eecs.umich.edu toIEW->commitInfo[0].interruptPending = true; 6569955SGeoffrey.Blake@arm.com 6575782Ssaidi@eecs.umich.edu // Wait until the ROB is empty and all stores have drained in 6581114SN/A // order to enter the interrupt. 6595782Ssaidi@eecs.umich.edu if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6605484Snate@binkert.org // Not sure which thread should be the one to interrupt. For now 6615484Snate@binkert.org // always do thread 0. 6621114SN/A assert(!thread[0]->inSyscall); 6635782Ssaidi@eecs.umich.edu thread[0]->inSyscall = true; 6645484Snate@binkert.org 6655484Snate@binkert.org // CPU will handle implementation of the interrupt. 6661114SN/A cpu->processInterrupts(); 6671114SN/A 6689955SGeoffrey.Blake@arm.com // Now squash or record that I need to squash this cycle. 6699955SGeoffrey.Blake@arm.com commitStatus[0] = TrapPending; 6701114SN/A 6712566SN/A // Exit state update mode to avoid accidental updating. 6722566SN/A thread[0]->inSyscall = false; 6731114SN/A 67410469Sandreas.hansson@arm.com // Generate trap squash event. 6755782Ssaidi@eecs.umich.edu generateTrapEvent(0); 6765782Ssaidi@eecs.umich.edu 6771114SN/A toIEW->commitInfo[0].clearInterrupt = true; 6781114SN/A 6799955SGeoffrey.Blake@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 6809554Sandreas.hansson@arm.com } else { 6811114SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6821114SN/A } 6835782Ssaidi@eecs.umich.edu } 6845782Ssaidi@eecs.umich.edu#endif // FULL_SYSTEM 6857811Ssteve.reinhardt@amd.com 6861114SN/A //////////////////////////////////// 6871078SN/A // Check for any possible squashes, handle them first 688 //////////////////////////////////// 689 690 list<unsigned>::iterator threads = (*activeThreads).begin(); 691 692 while (threads != (*activeThreads).end()) { 693 unsigned tid = *threads++; 694 695 if (fromFetch->fetchFault && commitStatus[0] != TrapPending) { 696 // Record the fault. Wait until it's empty in the ROB. 697 // Then handle the trap. Ignore it if there's already a 698 // trap pending as fetch will be redirected. 699 fetchFault = fromFetch->fetchFault; 700 fetchFaultTick = curTick + fetchTrapLatency; 701 commitStatus[0] = FetchTrapPending; 702 DPRINTF(Commit, "Fault from fetch recorded. Will trap if the " 703 "ROB empties without squashing the fault.\n"); 704 fetchTrapWait = 0; 705 } 706 707 // Fetch may tell commit to clear the trap if it's been squashed. 708 if (fromFetch->clearFetchFault) { 709 DPRINTF(Commit, "Received clear fetch fault signal\n"); 710 fetchTrapWait = 0; 711 if (commitStatus[0] == FetchTrapPending) { 712 DPRINTF(Commit, "Clearing fault from fetch\n"); 713 commitStatus[0] = Running; 714 } 715 } 716 717 // Not sure which one takes priority. I think if we have 718 // both, that's a bad sign. 719 if (trapSquash[tid] == true) { 720 assert(!xcSquash[tid]); 721 squashFromTrap(tid); 722 } else if (xcSquash[tid] == true) { 723 squashFromXC(tid); 724 } 725 726 // Squashed sequence number must be older than youngest valid 727 // instruction in the ROB. This prevents squashes from younger 728 // instructions overriding squashes from older instructions. 729 if (fromIEW->squash[tid] && 730 commitStatus[tid] != TrapPending && 731 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 732 733 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 734 tid, 735 fromIEW->mispredPC[tid], 736 fromIEW->squashedSeqNum[tid]); 737 738 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 739 tid, 740 fromIEW->nextPC[tid]); 741 742 commitStatus[tid] = ROBSquashing; 743 744 ++squashCounter; 745 746 // If we want to include the squashing instruction in the squash, 747 // then use one older sequence number. 748 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 749 750 if (fromIEW->includeSquashInst[tid] == true) 751 squashed_inst--; 752 753 // All younger instructions will be squashed. Set the sequence 754 // number as the youngest instruction in the ROB. 755 youngestSeqNum[tid] = squashed_inst; 756 757 rob->squash(squashed_inst, tid); 758 changedROBNumEntries[tid] = true; 759 760 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 761 762 toIEW->commitInfo[tid].squash = true; 763 764 // Send back the rob squashing signal so other stages know that 765 // the ROB is in the process of squashing. 766 toIEW->commitInfo[tid].robSquashing = true; 767 768 toIEW->commitInfo[tid].branchMispredict = 769 fromIEW->branchMispredict[tid]; 770 771 toIEW->commitInfo[tid].branchTaken = 772 fromIEW->branchTaken[tid]; 773 774 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 775 776 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 777 778 if (toIEW->commitInfo[tid].branchMispredict) { 779 ++branchMispredicts; 780 } 781 } 782 783 } 784 785 setNextStatus(); 786 787 if (squashCounter != numThreads) { 788 // If we're not currently squashing, then get instructions. 789 getInsts(); 790 791 // Try to commit any instructions. 792 commitInsts(); 793 } 794 795 //Check for any activity 796 threads = (*activeThreads).begin(); 797 798 while (threads != (*activeThreads).end()) { 799 unsigned tid = *threads++; 800 801 if (changedROBNumEntries[tid]) { 802 toIEW->commitInfo[tid].usedROB = true; 803 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 804 805 if (rob->isEmpty(tid)) { 806 toIEW->commitInfo[tid].emptyROB = true; 807 } 808 809 wroteToTimeBuffer = true; 810 changedROBNumEntries[tid] = false; 811 } 812 } 813} 814 815template <class Impl> 816void 817DefaultCommit<Impl>::commitInsts() 818{ 819 //////////////////////////////////// 820 // Handle commit 821 // Note that commit will be handled prior to putting new 822 // instructions in the ROB so that the ROB only tries to commit 823 // instructions it has in this current cycle, and not instructions 824 // it is writing in during this cycle. Can't commit and squash 825 // things at the same time... 826 //////////////////////////////////// 827 828 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 829 830 unsigned num_committed = 0; 831 832 DynInstPtr head_inst; 833 834 // Commit as many instructions as possible until the commit bandwidth 835 // limit is reached, or it becomes impossible to commit any more. 836 while (num_committed < commitWidth) { 837 int commit_thread = getCommittingThread(); 838 839 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 840 break; 841 842 head_inst = rob->readHeadInst(commit_thread); 843 844 int tid = head_inst->threadNumber; 845 846 assert(tid == commit_thread); 847 848 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 849 head_inst->seqNum, tid); 850 851 // If the head instruction is squashed, it is ready to retire 852 // (be removed from the ROB) at any time. 853 if (head_inst->isSquashed()) { 854 855 DPRINTF(Commit, "Retiring squashed instruction from " 856 "ROB.\n"); 857 858 rob->retireHead(commit_thread); 859 860 ++commitSquashedInsts; 861 862 // Record that the number of ROB entries has changed. 863 changedROBNumEntries[tid] = true; 864 } else { 865 PC[tid] = head_inst->readPC(); 866 nextPC[tid] = head_inst->readNextPC(); 867 868 // Increment the total number of non-speculative instructions 869 // executed. 870 // Hack for now: it really shouldn't happen until after the 871 // commit is deemed to be successful, but this count is needed 872 // for syscalls. 873 thread[tid]->funcExeInst++; 874 875 // Try to commit the head instruction. 876 bool commit_success = commitHead(head_inst, num_committed); 877 878 if (commit_success) { 879 ++num_committed; 880 881 changedROBNumEntries[tid] = true; 882 883 // Set the doneSeqNum to the youngest committed instruction. 884 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 885 886 ++commitCommittedInsts; 887 888 // To match the old model, don't count nops and instruction 889 // prefetches towards the total commit count. 890 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 891 cpu->instDone(tid); 892 } 893 894 PC[tid] = nextPC[tid]; 895 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 896#if FULL_SYSTEM 897 int count = 0; 898 Addr oldpc; 899 do { 900 // Debug statement. Checks to make sure we're not 901 // currently updating state while handling PC events. 902 if (count == 0) 903 assert(!thread[tid]->inSyscall && 904 !thread[tid]->trapPending); 905 oldpc = PC[tid]; 906 cpu->system->pcEventQueue.service( 907 thread[tid]->getXCProxy()); 908 count++; 909 } while (oldpc != PC[tid]); 910 if (count > 1) { 911 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 912 break; 913 } 914#endif 915 } else { 916 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 917 "[tid:%i] [sn:%i].\n", 918 head_inst->readPC(), tid ,head_inst->seqNum); 919 break; 920 } 921 } 922 } 923 924 DPRINTF(CommitRate, "%i\n", num_committed); 925 numCommittedDist.sample(num_committed); 926 927 if (num_committed == commitWidth) { 928 commitEligible[0]++; 929 } 930} 931 932template <class Impl> 933bool 934DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 935{ 936 assert(head_inst); 937 938 int tid = head_inst->threadNumber; 939 940 // If the instruction is not executed yet, then it will need extra 941 // handling. Signal backwards that it should be executed. 942 if (!head_inst->isExecuted()) { 943 // Keep this number correct. We have not yet actually executed 944 // and committed this instruction. 945 thread[tid]->funcExeInst--; 946 947 head_inst->reachedCommit = true; 948 949 if (head_inst->isNonSpeculative() || 950 head_inst->isMemBarrier() || 951 head_inst->isWriteBarrier()) { 952 953 DPRINTF(Commit, "Encountered a barrier or non-speculative " 954 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 955 head_inst->seqNum, head_inst->readPC()); 956 957#if !FULL_SYSTEM 958 // Hack to make sure syscalls/memory barriers/quiesces 959 // aren't executed until all stores write back their data. 960 // This direct communication shouldn't be used for 961 // anything other than this. 962 if (inst_num > 0 || iewStage->hasStoresToWB()) 963#else 964 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 965 head_inst->isQuiesce()) && 966 iewStage->hasStoresToWB()) 967#endif 968 { 969 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 970 return false; 971 } 972 973 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 974 975 // Change the instruction so it won't try to commit again until 976 // it is executed. 977 head_inst->clearCanCommit(); 978 979 ++commitNonSpecStalls; 980 981 return false; 982 } else if (head_inst->isLoad()) { 983 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 984 head_inst->seqNum, head_inst->readPC()); 985 986 // Send back the non-speculative instruction's sequence 987 // number. Tell the lsq to re-execute the load. 988 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 989 toIEW->commitInfo[tid].uncached = true; 990 toIEW->commitInfo[tid].uncachedLoad = head_inst; 991 992 head_inst->clearCanCommit(); 993 994 return false; 995 } else { 996 panic("Trying to commit un-executed instruction " 997 "of unknown type!\n"); 998 } 999 } 1000 1001 if (head_inst->isThreadSync()) { 1002 // Not handled for now. 1003 panic("Thread sync instructions are not handled yet.\n"); 1004 } 1005 1006 // Stores mark themselves as completed. 1007 if (!head_inst->isStore()) { 1008 head_inst->setCompleted(); 1009 } 1010 1011 // Use checker prior to updating anything due to traps or PC 1012 // based events. 1013 if (cpu->checker) { 1014 cpu->checker->tick(head_inst); 1015 } 1016 1017 // Check if the instruction caused a fault. If so, trap. 1018 Fault inst_fault = head_inst->getFault(); 1019 1020 if (inst_fault != NoFault) { 1021 head_inst->setCompleted(); 1022#if FULL_SYSTEM 1023 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1024 head_inst->seqNum, head_inst->readPC()); 1025 1026 if (iewStage->hasStoresToWB() || inst_num > 0) { 1027 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1028 return false; 1029 } 1030 1031 if (cpu->checker && head_inst->isStore()) { 1032 cpu->checker->tick(head_inst); 1033 } 1034 1035 assert(!thread[tid]->inSyscall); 1036 1037 // Mark that we're in state update mode so that the trap's 1038 // execution doesn't generate extra squashes. 1039 thread[tid]->inSyscall = true; 1040 1041 // DTB will sometimes need the machine instruction for when 1042 // faults happen. So we will set it here, prior to the DTB 1043 // possibly needing it for its fault. 1044 thread[tid]->setInst( 1045 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1046 1047 // Execute the trap. Although it's slightly unrealistic in 1048 // terms of timing (as it doesn't wait for the full timing of 1049 // the trap event to complete before updating state), it's 1050 // needed to update the state as soon as possible. This 1051 // prevents external agents from changing any specific state 1052 // that the trap need. 1053 cpu->trap(inst_fault, tid); 1054 1055 // Exit state update mode to avoid accidental updating. 1056 thread[tid]->inSyscall = false; 1057 1058 commitStatus[tid] = TrapPending; 1059 1060 // Generate trap squash event. 1061 generateTrapEvent(tid); 1062 1063 return false; 1064#else // !FULL_SYSTEM 1065 panic("fault (%d) detected @ PC %08p", inst_fault, 1066 head_inst->PC); 1067#endif // FULL_SYSTEM 1068 } 1069 1070 updateComInstStats(head_inst); 1071 1072 if (head_inst->traceData) { 1073 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1074 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1075 head_inst->traceData->finalize(); 1076 head_inst->traceData = NULL; 1077 } 1078 1079 // Update the commit rename map 1080 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1081 renameMap[tid]->setEntry(head_inst->destRegIdx(i), 1082 head_inst->renamedDestRegIdx(i)); 1083 } 1084 1085 // Finally clear the head ROB entry. 1086 rob->retireHead(tid); 1087 1088 // Return true to indicate that we have committed an instruction. 1089 return true; 1090} 1091 1092template <class Impl> 1093void 1094DefaultCommit<Impl>::getInsts() 1095{ 1096 // Read any renamed instructions and place them into the ROB. 1097 int insts_to_process = min((int)renameWidth, fromRename->size); 1098 1099 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 1100 { 1101 DynInstPtr inst = fromRename->insts[inst_num]; 1102 int tid = inst->threadNumber; 1103 1104 if (!inst->isSquashed() && 1105 commitStatus[tid] != ROBSquashing) { 1106 changedROBNumEntries[tid] = true; 1107 1108 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1109 inst->readPC(), inst->seqNum, tid); 1110 1111 rob->insertInst(inst); 1112 1113 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1114 1115 youngestSeqNum[tid] = inst->seqNum; 1116 } else { 1117 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1118 "squashed, skipping.\n", 1119 inst->readPC(), inst->seqNum, tid); 1120 } 1121 } 1122} 1123 1124template <class Impl> 1125void 1126DefaultCommit<Impl>::markCompletedInsts() 1127{ 1128 // Grab completed insts out of the IEW instruction queue, and mark 1129 // instructions completed within the ROB. 1130 for (int inst_num = 0; 1131 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1132 ++inst_num) 1133 { 1134 if (!fromIEW->insts[inst_num]->isSquashed()) { 1135 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1136 "within ROB.\n", 1137 fromIEW->insts[inst_num]->threadNumber, 1138 fromIEW->insts[inst_num]->readPC(), 1139 fromIEW->insts[inst_num]->seqNum); 1140 1141 // Mark the instruction as ready to commit. 1142 fromIEW->insts[inst_num]->setCanCommit(); 1143 } 1144 } 1145} 1146 1147template <class Impl> 1148bool 1149DefaultCommit<Impl>::robDoneSquashing() 1150{ 1151 list<unsigned>::iterator threads = (*activeThreads).begin(); 1152 1153 while (threads != (*activeThreads).end()) { 1154 unsigned tid = *threads++; 1155 1156 if (!rob->isDoneSquashing(tid)) 1157 return false; 1158 } 1159 1160 return true; 1161} 1162 1163template <class Impl> 1164void 1165DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1166{ 1167 unsigned thread = inst->threadNumber; 1168 1169 // 1170 // Pick off the software prefetches 1171 // 1172#ifdef TARGET_ALPHA 1173 if (inst->isDataPrefetch()) { 1174 statComSwp[thread]++; 1175 } else { 1176 statComInst[thread]++; 1177 } 1178#else 1179 statComInst[thread]++; 1180#endif 1181 1182 // 1183 // Control Instructions 1184 // 1185 if (inst->isControl()) 1186 statComBranches[thread]++; 1187 1188 // 1189 // Memory references 1190 // 1191 if (inst->isMemRef()) { 1192 statComRefs[thread]++; 1193 1194 if (inst->isLoad()) { 1195 statComLoads[thread]++; 1196 } 1197 } 1198 1199 if (inst->isMemBarrier()) { 1200 statComMembars[thread]++; 1201 } 1202} 1203 1204//////////////////////////////////////// 1205// // 1206// SMT COMMIT POLICY MAINTAINED HERE // 1207// // 1208//////////////////////////////////////// 1209template <class Impl> 1210int 1211DefaultCommit<Impl>::getCommittingThread() 1212{ 1213 if (numThreads > 1) { 1214 switch (commitPolicy) { 1215 1216 case Aggressive: 1217 //If Policy is Aggressive, commit will call 1218 //this function multiple times per 1219 //cycle 1220 return oldestReady(); 1221 1222 case RoundRobin: 1223 return roundRobin(); 1224 1225 case OldestReady: 1226 return oldestReady(); 1227 1228 default: 1229 return -1; 1230 } 1231 } else { 1232 int tid = (*activeThreads).front(); 1233 1234 if (commitStatus[tid] == Running || 1235 commitStatus[tid] == Idle || 1236 commitStatus[tid] == FetchTrapPending) { 1237 return tid; 1238 } else { 1239 return -1; 1240 } 1241 } 1242} 1243 1244template<class Impl> 1245int 1246DefaultCommit<Impl>::roundRobin() 1247{ 1248 list<unsigned>::iterator pri_iter = priority_list.begin(); 1249 list<unsigned>::iterator end = priority_list.end(); 1250 1251 while (pri_iter != end) { 1252 unsigned tid = *pri_iter; 1253 1254 if (commitStatus[tid] == Running || 1255 commitStatus[tid] == Idle) { 1256 1257 if (rob->isHeadReady(tid)) { 1258 priority_list.erase(pri_iter); 1259 priority_list.push_back(tid); 1260 1261 return tid; 1262 } 1263 } 1264 1265 pri_iter++; 1266 } 1267 1268 return -1; 1269} 1270 1271template<class Impl> 1272int 1273DefaultCommit<Impl>::oldestReady() 1274{ 1275 unsigned oldest = 0; 1276 bool first = true; 1277 1278 list<unsigned>::iterator threads = (*activeThreads).begin(); 1279 1280 while (threads != (*activeThreads).end()) { 1281 unsigned tid = *threads++; 1282 1283 if (!rob->isEmpty(tid) && 1284 (commitStatus[tid] == Running || 1285 commitStatus[tid] == Idle || 1286 commitStatus[tid] == FetchTrapPending)) { 1287 1288 if (rob->isHeadReady(tid)) { 1289 1290 DynInstPtr head_inst = rob->readHeadInst(tid); 1291 1292 if (first) { 1293 oldest = tid; 1294 first = false; 1295 } else if (head_inst->seqNum < oldest) { 1296 oldest = tid; 1297 } 1298 } 1299 } 1300 } 1301 1302 if (!first) { 1303 return oldest; 1304 } else { 1305 return -1; 1306 } 1307} 1308