commit_impl.hh revision 2316
11689SN/A/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37783SGiacomo.Gabrielli@arm.com * All rights reserved. 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 67783SGiacomo.Gabrielli@arm.com * modification, are permitted provided that the following conditions are 77783SGiacomo.Gabrielli@arm.com * met: redistributions of source code must retain the above copyright 87783SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 97783SGiacomo.Gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 107783SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 117783SGiacomo.Gabrielli@arm.com * documentation and/or other materials provided with the distribution; 127783SGiacomo.Gabrielli@arm.com * neither the name of the copyright holders nor the names of its 137783SGiacomo.Gabrielli@arm.com * contributors may be used to endorse or promote products derived from 142316SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 291689SN/A#include <algorithm> 301689SN/A#include <cstdio> 311689SN/A#include <cstdlib> 321689SN/A#include <cstring> 331689SN/A#include <iomanip> 341689SN/A#include <stdio.h> 351689SN/A#include <string.h> 361689SN/A 371689SN/A#include "base/loader/symtab.hh" 381689SN/A#include "base/timebuf.hh" 392665Ssaidi@eecs.umich.edu#include "cpu/checker/cpu.hh" 402665Ssaidi@eecs.umich.edu#include "cpu/exetrace.hh" 412965Sksewell@umich.edu#include "cpu/o3/commit.hh" 421689SN/A#include "cpu/o3/thread_state.hh" 431689SN/A 442292SN/Ausing namespace std; 452329SN/A 462292SN/Atemplate <class Impl> 473577Sgblack@eecs.umich.eduDefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 485953Ssaidi@eecs.umich.edu unsigned _tid) 492292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 507813Ssteve.reinhardt@amd.com{ 516221Snate@binkert.org this->setFlags(Event::AutoDelete); 526658Snate@binkert.org} 536221Snate@binkert.org 542292SN/Atemplate <class Impl> 551717SN/Avoid 562292SN/ADefaultCommit<Impl>::TrapEvent::process() 576221Snate@binkert.org{ 582292SN/A // This will get reset by commit if it was switched out at the 592790Sktlim@umich.edu // time of this event processing. 602790Sktlim@umich.edu commit->trapSquash[tid] = true; 612790Sktlim@umich.edu} 622790Sktlim@umich.edu 636221Snate@binkert.orgtemplate <class Impl> 645529Snate@binkert.orgconst char * 651061SN/ADefaultCommit<Impl>::TrapEvent::description() 662292SN/A{ 676221Snate@binkert.org return "Trap event"; 685606Snate@binkert.org} 691060SN/A 705769Snate@binkert.orgtemplate <class Impl> 711060SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 721060SN/A : dcacheInterface(params->dcacheInterface), 731061SN/A squashCounter(0), 741060SN/A iewToCommitDelay(params->iewToCommitDelay), 752292SN/A commitToIEWDelay(params->commitToIEWDelay), 761062SN/A renameToROBDelay(params->renameToROBDelay), 772316SN/A fetchToCommitDelay(params->commitToFetchDelay), 782316SN/A renameWidth(params->renameWidth), 792292SN/A iewWidth(params->executeWidth), 802292SN/A commitWidth(params->commitWidth), 812292SN/A numThreads(params->numberOfThreads), 822292SN/A switchedOut(false), 832292SN/A trapLatency(params->trapLatency), 845336Shines@cs.fsu.edu fetchTrapLatency(params->fetchTrapLatency) 852292SN/A{ 864873Sstever@eecs.umich.edu _status = Active; 872292SN/A _nextStatus = Inactive; 882292SN/A string policy = params->smtCommitPolicy; 892292SN/A 905529Snate@binkert.org //Convert string to lowercase 914329Sktlim@umich.edu std::transform(policy.begin(), policy.end(), policy.begin(), 924329Sktlim@umich.edu (int(*)(int)) tolower); 932292SN/A 942292SN/A //Assign commit policy 952292SN/A if (policy == "aggressive"){ 962292SN/A commitPolicy = Aggressive; 972292SN/A 982292SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 995529Snate@binkert.org } else if (policy == "roundrobin"){ 1002843Sktlim@umich.edu commitPolicy = RoundRobin; 1012316SN/A 1022874Sktlim@umich.edu //Set-Up Priority List 1032292SN/A for (int tid=0; tid < numThreads; tid++) { 1042292SN/A priority_list.push_back(tid); 1052292SN/A } 1062980Sgblack@eecs.umich.edu 1072292SN/A DPRINTF(Commit,"Commit Policy set to Round Robin."); 1082292SN/A } else if (policy == "oldestready"){ 1092292SN/A commitPolicy = OldestReady; 1102292SN/A 1112292SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1122292SN/A } else { 1132292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1142292SN/A "RoundRobin,OldestReady}"); 1152292SN/A } 1164329Sktlim@umich.edu 1172292SN/A for (int i=0; i < numThreads; i++) { 1182292SN/A commitStatus[i] = Idle; 1192292SN/A changedROBNumEntries[i] = false; 1202292SN/A trapSquash[i] = false; 1216221Snate@binkert.org xcSquash[i] = false; 1222292SN/A } 1232292SN/A 1242292SN/A fetchFaultTick = 0; 1254329Sktlim@umich.edu fetchTrapWait = 0; 1262292SN/A} 1272292SN/A 1282292SN/Atemplate <class Impl> 1294329Sktlim@umich.edustd::string 1302292SN/ADefaultCommit<Impl>::name() const 1312292SN/A{ 1322292SN/A return cpu->name() + ".commit"; 1332292SN/A} 1342292SN/A 1356221Snate@binkert.orgtemplate <class Impl> 1366221Snate@binkert.orgvoid 1376221Snate@binkert.orgDefaultCommit<Impl>::regStats() 1386221Snate@binkert.org{ 1396221Snate@binkert.org using namespace Stats; 1406221Snate@binkert.org commitCommittedInsts 1416221Snate@binkert.org .name(name() + ".commitCommittedInsts") 1426221Snate@binkert.org .desc("The number of committed instructions") 1437720Sgblack@eecs.umich.edu .prereq(commitCommittedInsts); 1442292SN/A commitSquashedInsts 1453640Sktlim@umich.edu .name(name() + ".commitSquashedInsts") 1463640Sktlim@umich.edu .desc("The number of squashed insts skipped by commit") 1473640Sktlim@umich.edu .prereq(commitSquashedInsts); 1482292SN/A commitSquashEvents 1492292SN/A .name(name() + ".commitSquashEvents") 1502292SN/A .desc("The number of times commit is told to squash") 1512292SN/A .prereq(commitSquashEvents); 1522292SN/A commitNonSpecStalls 1532292SN/A .name(name() + ".commitNonSpecStalls") 1542292SN/A .desc("The number of times commit has been forced to stall to " 1552292SN/A "communicate backwards") 1562292SN/A .prereq(commitNonSpecStalls); 1572292SN/A branchMispredicts 1582292SN/A .name(name() + ".branchMispredicts") 1592292SN/A .desc("The number of times a branch was mispredicted") 1602132SN/A .prereq(branchMispredicts); 1612301SN/A numCommittedDist 1621062SN/A .init(0,commitWidth,1) 1631062SN/A .name(name() + ".COM:committed_per_cycle") 1641062SN/A .desc("Number of insts commited each cycle") 1651062SN/A .flags(Stats::pdf) 1661062SN/A ; 1671062SN/A 1681062SN/A statComInst 1691062SN/A .init(cpu->number_of_threads) 1701062SN/A .name(name() + ".COM:count") 1711062SN/A .desc("Number of instructions committed") 1721062SN/A .flags(total) 1731062SN/A ; 1741062SN/A 1751062SN/A statComSwp 1761062SN/A .init(cpu->number_of_threads) 1771062SN/A .name(name() + ".COM:swp_count") 1781062SN/A .desc("Number of s/w prefetches committed") 1791062SN/A .flags(total) 1801062SN/A ; 1811062SN/A 1821062SN/A statComRefs 1832292SN/A .init(cpu->number_of_threads) 1841062SN/A .name(name() + ".COM:refs") 1851062SN/A .desc("Number of memory references committed") 1861062SN/A .flags(total) 1871062SN/A ; 1881062SN/A 1892301SN/A statComLoads 1902316SN/A .init(cpu->number_of_threads) 1916221Snate@binkert.org .name(name() + ".COM:loads") 1922301SN/A .desc("Number of loads committed") 1932301SN/A .flags(total) 1942301SN/A ; 1952301SN/A 1962301SN/A statComMembars 1972316SN/A .init(cpu->number_of_threads) 1986221Snate@binkert.org .name(name() + ".COM:membars") 1992301SN/A .desc("Number of memory barriers committed") 2002301SN/A .flags(total) 2012301SN/A ; 2022301SN/A 2032301SN/A statComBranches 2042316SN/A .init(cpu->number_of_threads) 2056221Snate@binkert.org .name(name() + ".COM:branches") 2062301SN/A .desc("Number of branches committed") 2072301SN/A .flags(total) 2082301SN/A ; 2092301SN/A 2102301SN/A // 2112316SN/A // Commit-Eligible instructions... 2126221Snate@binkert.org // 2132301SN/A // -> The number of instructions eligible to commit in those 2142301SN/A // cycles where we reached our commit BW limit (less the number 2152301SN/A // actually committed) 2162301SN/A // 2172301SN/A // -> The average value is computed over ALL CYCLES... not just 2182316SN/A // the BW limited cycles 2196221Snate@binkert.org // 2202301SN/A // -> The standard deviation is computed only over cycles where 2212301SN/A // we reached the BW limit 2222301SN/A // 2232301SN/A commitEligible 2242301SN/A .init(cpu->number_of_threads) 2252316SN/A .name(name() + ".COM:bw_limited") 2266221Snate@binkert.org .desc("number of insts not committed due to BW limits") 2272301SN/A .flags(total) 2282301SN/A ; 2292301SN/A 2302301SN/A commitEligibleSamples 2312301SN/A .name(name() + ".COM:bw_lim_events") 2322316SN/A .desc("number cycles where commit BW limit reached") 2336221Snate@binkert.org ; 2342301SN/A} 2352301SN/A 2362301SN/Atemplate <class Impl> 2372301SN/Avoid 2382301SN/ADefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr) 2392316SN/A{ 2402301SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2412301SN/A cpu = cpu_ptr; 2422301SN/A 2431062SN/A // Commit must broadcast the number of free entries it has at the start of 2441062SN/A // the simulation, so it starts as active. 2451062SN/A cpu->activateStage(FullCPU::CommitIdx); 2461062SN/A 2472980Sgblack@eecs.umich.edu trapLatency = cpu->cycles(trapLatency); 2482292SN/A fetchTrapLatency = cpu->cycles(fetchTrapLatency); 2492292SN/A} 2502292SN/A 2512292SN/Atemplate <class Impl> 2522292SN/Avoid 2532292SN/ADefaultCommit<Impl>::setThreads(vector<Thread *> &threads) 2542292SN/A{ 2551060SN/A thread = threads; 2561060SN/A} 2571060SN/A 2581060SN/Atemplate <class Impl> 2591060SN/Avoid 2601060SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2611060SN/A{ 2621060SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2631060SN/A timeBuffer = tb_ptr; 2641060SN/A 2651061SN/A // Setup wire to send information back to IEW. 2661060SN/A toIEW = timeBuffer->getWire(0); 2672292SN/A 2682292SN/A // Setup wire to read data from IEW (for the ROB). 2692292SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2702292SN/A} 2712292SN/A 2722292SN/Atemplate <class Impl> 2732292SN/Avoid 2742292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2752292SN/A{ 2762292SN/A DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2772292SN/A fetchQueue = fq_ptr; 2781060SN/A 2791060SN/A // Setup wire to get instructions from rename (for the ROB). 2801060SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2811060SN/A} 2821060SN/A 2831060SN/Atemplate <class Impl> 2841060SN/Avoid 2851061SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2861060SN/A{ 2872292SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2881060SN/A renameQueue = rq_ptr; 2891060SN/A 2901060SN/A // Setup wire to get instructions from rename (for the ROB). 2911060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2921060SN/A} 2931060SN/A 2941060SN/Atemplate <class Impl> 2951061SN/Avoid 2961060SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2972292SN/A{ 2982292SN/A DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2992292SN/A iewQueue = iq_ptr; 3002292SN/A 3012292SN/A // Setup wire to get instructions from IEW. 3022292SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3032292SN/A} 3046221Snate@binkert.org 3052292SN/Atemplate <class Impl> 3062292SN/Avoid 3072292SN/ADefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage) 3082292SN/A{ 3092292SN/A fetchStage = fetch_stage; 3102292SN/A} 3112292SN/A 3122292SN/Atemplate <class Impl> 3136221Snate@binkert.orgvoid 3146221Snate@binkert.orgDefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3152292SN/A{ 3162292SN/A iewStage = iew_stage; 3172292SN/A} 3182292SN/A 3192292SN/Atemplate<class Impl> 3201060SN/Avoid 3211060SN/ADefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3221060SN/A{ 3231060SN/A DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3241061SN/A activeThreads = at_ptr; 3251060SN/A} 3262292SN/A 3271060SN/Atemplate <class Impl> 3282292SN/Avoid 3292292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3301060SN/A{ 3312292SN/A DPRINTF(Commit, "Setting rename map pointers.\n"); 3326221Snate@binkert.org 3336221Snate@binkert.org for (int i=0; i < numThreads; i++) { 3346221Snate@binkert.org renameMap[i] = &rm_ptr[i]; 3356221Snate@binkert.org } 3361060SN/A} 3371060SN/A 3384329Sktlim@umich.edutemplate <class Impl> 3394329Sktlim@umich.eduvoid 3404329Sktlim@umich.eduDefaultCommit<Impl>::setROB(ROB *rob_ptr) 3414329Sktlim@umich.edu{ 3422292SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3435100Ssaidi@eecs.umich.edu rob = rob_ptr; 3441060SN/A} 3451060SN/A 3461061SN/Atemplate <class Impl> 3472863Sktlim@umich.eduvoid 3482843Sktlim@umich.eduDefaultCommit<Impl>::initStage() 3491060SN/A{ 3502843Sktlim@umich.edu rob->setActiveThreads(activeThreads); 3512863Sktlim@umich.edu rob->resetEntries(); 3522863Sktlim@umich.edu 3532316SN/A // Broadcast the number of free entries. 3542316SN/A for (int i=0; i < numThreads; i++) { 3552316SN/A toIEW->commitInfo[i].usedROB = true; 3562316SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3572843Sktlim@umich.edu } 3582316SN/A 3592316SN/A cpu->activityThisCycle(); 3602843Sktlim@umich.edu} 3612307SN/A 3622307SN/Atemplate <class Impl> 3632307SN/Avoid 3642307SN/ADefaultCommit<Impl>::switchOut() 3652307SN/A{ 3662843Sktlim@umich.edu switchPending = true; 3672843Sktlim@umich.edu} 3682864Sktlim@umich.edu 3692843Sktlim@umich.edutemplate <class Impl> 3702843Sktlim@umich.eduvoid 3712843Sktlim@umich.eduDefaultCommit<Impl>::doSwitchOut() 3722843Sktlim@umich.edu{ 3732307SN/A switchedOut = true; 3742307SN/A switchPending = false; 3752316SN/A rob->switchOut(); 3762307SN/A} 3772307SN/A 3786221Snate@binkert.orgtemplate <class Impl> 3796221Snate@binkert.orgvoid 3806221Snate@binkert.orgDefaultCommit<Impl>::takeOverFrom() 3816221Snate@binkert.org{ 3826221Snate@binkert.org switchedOut = false; 3832307SN/A _status = Active; 3842307SN/A _nextStatus = Inactive; 3852307SN/A for (int i=0; i < numThreads; i++) { 3862307SN/A commitStatus[i] = Idle; 3872307SN/A changedROBNumEntries[i] = false; 3882307SN/A trapSquash[i] = false; 3892307SN/A xcSquash[i] = false; 3902292SN/A } 3912132SN/A squashCounter = 0; 3922316SN/A rob->takeOverFrom(); 3936221Snate@binkert.org} 3946221Snate@binkert.org 3953867Sbinkertn@umich.edutemplate <class Impl> 3963867Sbinkertn@umich.eduvoid 3976221Snate@binkert.orgDefaultCommit<Impl>::updateStatus() 3983867Sbinkertn@umich.edu{ 3992316SN/A // reset ROB changed variable 4002316SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4012316SN/A while (threads != (*activeThreads).end()) { 4022316SN/A unsigned tid = *threads++; 4032316SN/A changedROBNumEntries[tid] = false; 4042316SN/A 4052316SN/A // Also check if any of the threads has a trap pending 4062292SN/A if (commitStatus[tid] == TrapPending || 4072292SN/A commitStatus[tid] == FetchTrapPending) { 4082292SN/A _nextStatus = Active; 4092292SN/A } 4102733Sktlim@umich.edu } 4112292SN/A 4122292SN/A if (_nextStatus == Inactive && _status == Active) { 4132733Sktlim@umich.edu DPRINTF(Activity, "Deactivating stage.\n"); 4142292SN/A cpu->deactivateStage(FullCPU::CommitIdx); 4152292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4162292SN/A DPRINTF(Activity, "Activating stage.\n"); 4172292SN/A cpu->activateStage(FullCPU::CommitIdx); 4182292SN/A } 4192292SN/A 4202292SN/A _status = _nextStatus; 4212292SN/A} 4222292SN/A 4232292SN/Atemplate <class Impl> 4242292SN/Avoid 4256221Snate@binkert.orgDefaultCommit<Impl>::setNextStatus() 4266221Snate@binkert.org{ 4272292SN/A int squashes = 0; 4283867Sbinkertn@umich.edu 4296221Snate@binkert.org list<unsigned>::iterator threads = (*activeThreads).begin(); 4302292SN/A 4312292SN/A while (threads != (*activeThreads).end()) { 4322292SN/A unsigned tid = *threads++; 4332292SN/A 4342292SN/A if (commitStatus[tid] == ROBSquashing) { 4352292SN/A squashes++; 4362702Sktlim@umich.edu } 4372292SN/A } 4382292SN/A 4392292SN/A assert(squashes == squashCounter); 4402292SN/A 4412292SN/A // If commit is currently squashing, then it will have activity for the 4422292SN/A // next cycle. Set its next status as active. 4432292SN/A if (squashCounter) { 4442292SN/A _nextStatus = Active; 4452292SN/A } 4462292SN/A} 4472292SN/A 4482292SN/Atemplate <class Impl> 4496221Snate@binkert.orgbool 4506221Snate@binkert.orgDefaultCommit<Impl>::changedROBEntries() 4512292SN/A{ 4523867Sbinkertn@umich.edu list<unsigned>::iterator threads = (*activeThreads).begin(); 4536221Snate@binkert.org 4542292SN/A while (threads != (*activeThreads).end()) { 4552292SN/A unsigned tid = *threads++; 4562292SN/A 4572292SN/A if (changedROBNumEntries[tid]) { 4582292SN/A return true; 4592292SN/A } 4602292SN/A } 4612292SN/A 4622292SN/A return false; 4632292SN/A} 4646221Snate@binkert.org 4656221Snate@binkert.orgtemplate <class Impl> 4662292SN/Aunsigned 4672292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4682292SN/A{ 4692292SN/A return rob->numFreeEntries(tid); 4702292SN/A} 4712292SN/A 4726221Snate@binkert.orgtemplate <class Impl> 4732292SN/Avoid 4742292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4752292SN/A{ 4762292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4772292SN/A 4787823Ssteve.reinhardt@amd.com TrapEvent *trap = new TrapEvent(this, tid); 4794035Sktlim@umich.edu 4802292SN/A trap->schedule(curTick + trapLatency); 4812292SN/A 4822292SN/A thread[tid]->trapPending = true; 4832292SN/A} 4846221Snate@binkert.org 4852292SN/Atemplate <class Impl> 4864035Sktlim@umich.eduvoid 4872680Sktlim@umich.eduDefaultCommit<Impl>::generateXCEvent(unsigned tid) 4882292SN/A{ 4892680Sktlim@umich.edu DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid); 4902292SN/A 4912292SN/A xcSquash[tid] = true; 4922292SN/A} 4932292SN/A 4946221Snate@binkert.orgtemplate <class Impl> 4952292SN/Avoid 4962292SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4972292SN/A{ 4982292SN/A // If we want to include the squashing instruction in the squash, 4992292SN/A // then use one older sequence number. 5002292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5014035Sktlim@umich.edu // all instructions of this thread. 5022292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5032292SN/A 0 : rob->readHeadInst(tid)->seqNum - 1;; 5042292SN/A 5052292SN/A // All younger instructions will be squashed. Set the sequence 5062292SN/A // number as the youngest instruction in the ROB (0 in this case. 5072292SN/A // Hopefully nothing breaks.) 5082292SN/A youngestSeqNum[tid] = 0; 5092292SN/A 5102292SN/A rob->squash(squashed_inst, tid); 5112292SN/A changedROBNumEntries[tid] = true; 5122292SN/A 5132292SN/A // Send back the sequence number of the squashed instruction. 5142292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5152292SN/A 5162292SN/A // Send back the squash signal to tell stages that they should 5172292SN/A // squash. 5182292SN/A toIEW->commitInfo[tid].squash = true; 5192292SN/A 5202292SN/A // Send back the rob squashing signal so other stages know that 5212292SN/A // the ROB is in the process of squashing. 5222292SN/A toIEW->commitInfo[tid].robSquashing = true; 5232292SN/A 5247720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].branchMispredict = false; 5252316SN/A 5262292SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5272316SN/A} 5282316SN/A 5296221Snate@binkert.orgtemplate <class Impl> 5302316SN/Avoid 5312316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5322316SN/A{ 5337720Sgblack@eecs.umich.edu squashAll(tid); 5342316SN/A 5352316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5362316SN/A 5374035Sktlim@umich.edu thread[tid]->trapPending = false; 5382316SN/A thread[tid]->inSyscall = false; 5392316SN/A 5402316SN/A trapSquash[tid] = false; 5412316SN/A 5422316SN/A commitStatus[tid] = ROBSquashing; 5432316SN/A cpu->activityThisCycle(); 5442316SN/A 5452316SN/A ++squashCounter; 5462316SN/A} 5476221Snate@binkert.org 5482316SN/Atemplate <class Impl> 5492316SN/Avoid 5502292SN/ADefaultCommit<Impl>::squashFromXC(unsigned tid) 5517720Sgblack@eecs.umich.edu{ 5522292SN/A squashAll(tid); 5532292SN/A 5542292SN/A DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]); 5552316SN/A 5562292SN/A thread[tid]->inSyscall = false; 5572292SN/A assert(!thread[tid]->trapPending); 5582292SN/A 5592680Sktlim@umich.edu commitStatus[tid] = ROBSquashing; 5602292SN/A cpu->activityThisCycle(); 5612292SN/A 5622292SN/A xcSquash[tid] = false; 5632292SN/A 5647784SAli.Saidi@ARM.com ++squashCounter; 5657784SAli.Saidi@ARM.com} 5667784SAli.Saidi@ARM.com 5677784SAli.Saidi@ARM.comtemplate <class Impl> 5687784SAli.Saidi@ARM.comvoid 5697784SAli.Saidi@ARM.comDefaultCommit<Impl>::tick() 5707784SAli.Saidi@ARM.com{ 5717784SAli.Saidi@ARM.com wroteToTimeBuffer = false; 5727784SAli.Saidi@ARM.com _nextStatus = Inactive; 5737784SAli.Saidi@ARM.com 5747784SAli.Saidi@ARM.com if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5757784SAli.Saidi@ARM.com cpu->signalSwitched(); 5767784SAli.Saidi@ARM.com return; 5777784SAli.Saidi@ARM.com } 5787784SAli.Saidi@ARM.com 5797784SAli.Saidi@ARM.com list<unsigned>::iterator threads = (*activeThreads).begin(); 5807784SAli.Saidi@ARM.com 5817784SAli.Saidi@ARM.com // Check if any of the threads are done squashing. Change the 5827784SAli.Saidi@ARM.com // status if they are done. 5837784SAli.Saidi@ARM.com while (threads != (*activeThreads).end()) { 5847784SAli.Saidi@ARM.com unsigned tid = *threads++; 5857784SAli.Saidi@ARM.com 5867784SAli.Saidi@ARM.com if (commitStatus[tid] == ROBSquashing) { 5877784SAli.Saidi@ARM.com 5887784SAli.Saidi@ARM.com if (rob->isDoneSquashing(tid)) { 5897784SAli.Saidi@ARM.com commitStatus[tid] = Running; 5907784SAli.Saidi@ARM.com --squashCounter; 5912292SN/A } else { 5922292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5932292SN/A "insts this cycle.\n", tid); 5942292SN/A } 5952292SN/A } 5962843Sktlim@umich.edu } 5972843Sktlim@umich.edu 5982843Sktlim@umich.edu commit(); 5992316SN/A 6002316SN/A markCompletedInsts(); 6012316SN/A 6023867Sbinkertn@umich.edu threads = (*activeThreads).begin(); 6032875Sksewell@umich.edu 6042875Sksewell@umich.edu while (threads != (*activeThreads).end()) { 6056221Snate@binkert.org unsigned tid = *threads++; 6066221Snate@binkert.org 6072292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6082316SN/A // The ROB has more instructions it can commit. Its next status 6092316SN/A // will be active. 6103867Sbinkertn@umich.edu _nextStatus = Active; 6116221Snate@binkert.org 6122292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6134035Sktlim@umich.edu 6144035Sktlim@umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6154035Sktlim@umich.edu " ROB and ready to commit\n", 6164035Sktlim@umich.edu tid, inst->seqNum, inst->readPC()); 6172292SN/A 6182292SN/A } else if (!rob->isEmpty(tid)) { 6192292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6202292SN/A 6212292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6222292SN/A "%#x is head of ROB and not ready\n", 6232877Sksewell@umich.edu tid, inst->seqNum, inst->readPC()); 6242702Sktlim@umich.edu } 6252702Sktlim@umich.edu 6262702Sktlim@umich.edu DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6272292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6282292SN/A } 6292292SN/A 6302292SN/A 6312292SN/A if (wroteToTimeBuffer) { 6322292SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6332292SN/A cpu->activityThisCycle(); 6342292SN/A } 6353867Sbinkertn@umich.edu 6362292SN/A updateStatus(); 6373867Sbinkertn@umich.edu} 6386221Snate@binkert.org 6392292SN/Atemplate <class Impl> 6402292SN/Avoid 6412292SN/ADefaultCommit<Impl>::commit() 6422292SN/A{ 6432292SN/A 6442292SN/A ////////////////////////////////////// 6452292SN/A // Check for interrupts 6462292SN/A ////////////////////////////////////// 6477720Sgblack@eecs.umich.edu 6482292SN/A#if FULL_SYSTEM 6497720Sgblack@eecs.umich.edu // Process interrupts if interrupts are enabled, not in PAL mode, 6502292SN/A // and no other traps or external squashes are currently pending. 6512292SN/A // @todo: Allow other threads to handle interrupts. 6522292SN/A if (cpu->checkInterrupts && 6532292SN/A cpu->check_interrupts() && 6542292SN/A !cpu->inPalMode(readPC()) && 6557720Sgblack@eecs.umich.edu !trapSquash[0] && 6567720Sgblack@eecs.umich.edu !xcSquash[0]) { 6572292SN/A // Tell fetch that there is an interrupt pending. This will 6582292SN/A // make fetch wait until it sees a non PAL-mode PC, at which 6592292SN/A // point it stops fetching instructions. 6602292SN/A toIEW->commitInfo[0].interruptPending = true; 6612292SN/A 6622292SN/A // Wait until the ROB is empty and all stores have drained in 6632292SN/A // order to enter the interrupt. 6642292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6652316SN/A // Not sure which thread should be the one to interrupt. For now 6662292SN/A // always do thread 0. 6672292SN/A assert(!thread[0]->inSyscall); 6682292SN/A thread[0]->inSyscall = true; 6692292SN/A 6702292SN/A // CPU will handle implementation of the interrupt. 6712292SN/A cpu->processInterrupts(); 6724035Sktlim@umich.edu 6732292SN/A // Now squash or record that I need to squash this cycle. 6742292SN/A commitStatus[0] = TrapPending; 6754035Sktlim@umich.edu 6762292SN/A // Exit state update mode to avoid accidental updating. 6773640Sktlim@umich.edu thread[0]->inSyscall = false; 6782316SN/A 6792316SN/A // Generate trap squash event. 6802292SN/A generateTrapEvent(0); 6813633Sktlim@umich.edu 6823633Sktlim@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 6833633Sktlim@umich.edu 6843633Sktlim@umich.edu DPRINTF(Commit, "Interrupt detected.\n"); 6854035Sktlim@umich.edu } else { 6864035Sktlim@umich.edu DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6874035Sktlim@umich.edu } 6882292SN/A } 6892292SN/A#endif // FULL_SYSTEM 6902292SN/A 6913633Sktlim@umich.edu //////////////////////////////////// 6923640Sktlim@umich.edu // Check for any possible squashes, handle them first 6932292SN/A //////////////////////////////////// 6943633Sktlim@umich.edu 6953633Sktlim@umich.edu list<unsigned>::iterator threads = (*activeThreads).begin(); 6962292SN/A 6972292SN/A while (threads != (*activeThreads).end()) { 6982292SN/A unsigned tid = *threads++; 6992292SN/A 7002292SN/A if (fromFetch->fetchFault && commitStatus[0] != TrapPending) { 7013640Sktlim@umich.edu // Record the fault. Wait until it's empty in the ROB. 7022292SN/A // Then handle the trap. Ignore it if there's already a 7032292SN/A // trap pending as fetch will be redirected. 7042292SN/A fetchFault = fromFetch->fetchFault; 7054035Sktlim@umich.edu fetchFaultTick = curTick + fetchTrapLatency; 7065704Snate@binkert.org commitStatus[0] = FetchTrapPending; 7074035Sktlim@umich.edu DPRINTF(Commit, "Fault from fetch recorded. Will trap if the " 7084035Sktlim@umich.edu "ROB empties without squashing the fault.\n"); 7093640Sktlim@umich.edu fetchTrapWait = 0; 7103640Sktlim@umich.edu } 7113640Sktlim@umich.edu 7123640Sktlim@umich.edu // Fetch may tell commit to clear the trap if it's been squashed. 7133640Sktlim@umich.edu if (fromFetch->clearFetchFault) { 7143640Sktlim@umich.edu DPRINTF(Commit, "Received clear fetch fault signal\n"); 7153640Sktlim@umich.edu fetchTrapWait = 0; 7163640Sktlim@umich.edu if (commitStatus[0] == FetchTrapPending) { 7173640Sktlim@umich.edu DPRINTF(Commit, "Clearing fault from fetch\n"); 7183640Sktlim@umich.edu commitStatus[0] = Running; 7193640Sktlim@umich.edu } 7203640Sktlim@umich.edu } 7213640Sktlim@umich.edu 7223640Sktlim@umich.edu // Not sure which one takes priority. I think if we have 7231060SN/A // both, that's a bad sign. 7244035Sktlim@umich.edu if (trapSquash[tid] == true) { 7254035Sktlim@umich.edu assert(!xcSquash[tid]); 7263634Sktlim@umich.edu squashFromTrap(tid); 7274035Sktlim@umich.edu } else if (xcSquash[tid] == true) { 7284035Sktlim@umich.edu squashFromXC(tid); 7294035Sktlim@umich.edu } 7304035Sktlim@umich.edu 7314035Sktlim@umich.edu // Squashed sequence number must be older than youngest valid 7324035Sktlim@umich.edu // instruction in the ROB. This prevents squashes from younger 7334035Sktlim@umich.edu // instructions overriding squashes from older instructions. 7344035Sktlim@umich.edu if (fromIEW->squash[tid] && 7354035Sktlim@umich.edu commitStatus[tid] != TrapPending && 7365704Snate@binkert.org fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7374035Sktlim@umich.edu 7384035Sktlim@umich.edu DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7391060SN/A tid, 7401060SN/A fromIEW->mispredPC[tid], 7411060SN/A fromIEW->squashedSeqNum[tid]); 7422316SN/A 7431060SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7446221Snate@binkert.org tid, 7456221Snate@binkert.org fromIEW->nextPC[tid]); 7461060SN/A 7473867Sbinkertn@umich.edu commitStatus[tid] = ROBSquashing; 7486221Snate@binkert.org 7491060SN/A ++squashCounter; 7502292SN/A 7512292SN/A // If we want to include the squashing instruction in the squash, 7522292SN/A // then use one older sequence number. 7532680Sktlim@umich.edu InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7542292SN/A 7552680Sktlim@umich.edu if (fromIEW->includeSquashInst[tid] == true) 7564035Sktlim@umich.edu squashed_inst--; 7572680Sktlim@umich.edu 7582292SN/A // All younger instructions will be squashed. Set the sequence 7591061SN/A // number as the youngest instruction in the ROB. 7602292SN/A youngestSeqNum[tid] = squashed_inst; 7612292SN/A 7622292SN/A rob->squash(squashed_inst, tid); 7632292SN/A changedROBNumEntries[tid] = true; 7642292SN/A 7652292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7661061SN/A 7672292SN/A toIEW->commitInfo[tid].squash = true; 7682292SN/A 7692292SN/A // Send back the rob squashing signal so other stages know that 7702292SN/A // the ROB is in the process of squashing. 7711061SN/A toIEW->commitInfo[tid].robSquashing = true; 7722292SN/A 7732292SN/A toIEW->commitInfo[tid].branchMispredict = 7747720Sgblack@eecs.umich.edu fromIEW->branchMispredict[tid]; 7751061SN/A 7762292SN/A toIEW->commitInfo[tid].branchTaken = 7771061SN/A fromIEW->branchTaken[tid]; 7782292SN/A 7792292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7802292SN/A 7811062SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7822935Sksewell@umich.edu 7832292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7842935Sksewell@umich.edu ++branchMispredicts; 7854035Sktlim@umich.edu } 7862292SN/A } 7872292SN/A 7882292SN/A } 7892292SN/A 7903093Sksewell@umich.edu setNextStatus(); 7912292SN/A 7922292SN/A if (squashCounter != numThreads) { 7932292SN/A // If we're not currently squashing, then get instructions. 7942292SN/A getInsts(); 7952292SN/A 7962292SN/A // Try to commit any instructions. 7972292SN/A commitInsts(); 7982292SN/A } 7992292SN/A 8002292SN/A //Check for any activity 8012292SN/A threads = (*activeThreads).begin(); 8022292SN/A 8032292SN/A while (threads != (*activeThreads).end()) { 8042292SN/A unsigned tid = *threads++; 8052292SN/A 8062292SN/A if (changedROBNumEntries[tid]) { 8077720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].usedROB = true; 8082292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8092316SN/A 8102292SN/A if (rob->isEmpty(tid)) { 8112292SN/A toIEW->commitInfo[tid].emptyROB = true; 8122292SN/A } 8132292SN/A 8141062SN/A wroteToTimeBuffer = true; 8152292SN/A changedROBNumEntries[tid] = false; 8161060SN/A } 8171060SN/A } 8182292SN/A} 8192292SN/A 8202292SN/Atemplate <class Impl> 8211061SN/Avoid 8221060SN/ADefaultCommit<Impl>::commitInsts() 8231060SN/A{ 8241061SN/A //////////////////////////////////// 8251060SN/A // Handle commit 8261060SN/A // Note that commit will be handled prior to putting new 8271060SN/A // instructions in the ROB so that the ROB only tries to commit 8282292SN/A // instructions it has in this current cycle, and not instructions 8293867Sbinkertn@umich.edu // it is writing in during this cycle. Can't commit and squash 8302292SN/A // things at the same time... 8313867Sbinkertn@umich.edu //////////////////////////////////// 8326221Snate@binkert.org 8332292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8342292SN/A 8352292SN/A unsigned num_committed = 0; 8362292SN/A 8372292SN/A DynInstPtr head_inst; 8382292SN/A#if FULL_SYSTEM 8392292SN/A // Not the best way to check if the front end is empty, but it should 8404035Sktlim@umich.edu // work. 8414035Sktlim@umich.edu // @todo: Try to avoid directly accessing fetch. 8422292SN/A if (commitStatus[0] == FetchTrapPending && rob->isEmpty()) { 8434035Sktlim@umich.edu DPRINTF(Commit, "Fault from fetch is pending.\n"); 8444035Sktlim@umich.edu 8454035Sktlim@umich.edu fetchTrapWait++; 8464035Sktlim@umich.edu if (fetchTrapWait > 10000000) { 8474035Sktlim@umich.edu panic("Fetch trap has been pending for a long time!"); 8484035Sktlim@umich.edu } 8494035Sktlim@umich.edu if (fetchFaultTick > curTick) { 8504035Sktlim@umich.edu DPRINTF(Commit, "Not enough cycles since fault, fault will " 8514035Sktlim@umich.edu "happen on %lli\n", 8524035Sktlim@umich.edu fetchFaultTick); 8535557Sktlim@umich.edu cpu->activityThisCycle(); 8544035Sktlim@umich.edu return; 8554035Sktlim@umich.edu } else if (iewStage->hasStoresToWB()) { 8564035Sktlim@umich.edu DPRINTF(Commit, "IEW still has stores to WB. Waiting until " 8574035Sktlim@umich.edu "they are completed. fetchTrapWait:%i\n", 8584035Sktlim@umich.edu fetchTrapWait); 8594035Sktlim@umich.edu cpu->activityThisCycle(); 8604035Sktlim@umich.edu return; 8611060SN/A } else if (cpu->inPalMode(readPC())) { 8621060SN/A DPRINTF(Commit, "In pal mode right now. fetchTrapWait:%i\n", 8631060SN/A fetchTrapWait); 8641061SN/A return; 8651060SN/A } else if (fetchStage->getYoungestSN() > youngestSeqNum[0]) { 8662292SN/A DPRINTF(Commit, "Waiting for front end to drain. fetchTrapWait:%i\n", 8671060SN/A fetchTrapWait); 8681060SN/A return; 8691060SN/A } 8702316SN/A fetchTrapWait = 0; 8712316SN/A DPRINTF(Commit, "ROB is empty, handling fetch trap.\n"); 8722316SN/A 8732316SN/A assert(!thread[0]->inSyscall); 8742316SN/A 8751060SN/A thread[0]->inSyscall = true; 8761060SN/A 8772292SN/A // Consider holding onto the trap and waiting until the trap event 8781060SN/A // happens for this to be executed. 8791060SN/A cpu->trap(fetchFault, 0); 8801060SN/A 8812292SN/A // Exit state update mode to avoid accidental updating. 8822316SN/A thread[0]->inSyscall = false; 8831060SN/A 8841060SN/A commitStatus[0] = TrapPending; 8852292SN/A // Set it up so that we squash next cycle 8862292SN/A trapSquash[0] = true; 8871060SN/A return; 8882292SN/A } 8892292SN/A#endif 8902292SN/A 8912292SN/A // Commit as many instructions as possible until the commit bandwidth 8922292SN/A // limit is reached, or it becomes impossible to commit any more. 8936221Snate@binkert.org while (num_committed < commitWidth) { 8942292SN/A int commit_thread = getCommittingThread(); 8952292SN/A 8962292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8972292SN/A break; 8982292SN/A 8992132SN/A head_inst = rob->readHeadInst(commit_thread); 9002316SN/A 9012316SN/A int tid = head_inst->threadNumber; 9021060SN/A 9031060SN/A assert(tid == commit_thread); 9042292SN/A 9051060SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 9061060SN/A head_inst->seqNum, tid); 9072292SN/A 9081060SN/A // If the head instruction is squashed, it is ready to retire 9091062SN/A // (be removed from the ROB) at any time. 9101062SN/A if (head_inst->isSquashed()) { 9112292SN/A 9122292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 9131060SN/A "ROB.\n"); 9147720Sgblack@eecs.umich.edu 9152292SN/A rob->retireHead(commit_thread); 9161060SN/A 9171060SN/A ++commitSquashedInsts; 9181060SN/A 9191061SN/A // Record that the number of ROB entries has changed. 9201061SN/A changedROBNumEntries[tid] = true; 9212292SN/A } else { 9221060SN/A PC[tid] = head_inst->readPC(); 9231060SN/A nextPC[tid] = head_inst->readNextPC(); 9241060SN/A 9251060SN/A // Increment the total number of non-speculative instructions 9261062SN/A // executed. 9271060SN/A // Hack for now: it really shouldn't happen until after the 9281060SN/A // commit is deemed to be successful, but this count is needed 9292292SN/A // for syscalls. 9302292SN/A thread[tid]->funcExeInst++; 9312292SN/A 9322292SN/A // Try to commit the head instruction. 9331060SN/A bool commit_success = commitHead(head_inst, num_committed); 9341062SN/A 9351062SN/A if (commit_success) { 9362292SN/A ++num_committed; 9372292SN/A 9382292SN/A changedROBNumEntries[tid] = true; 9392292SN/A 9401062SN/A // Set the doneSeqNum to the youngest committed instruction. 9412292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9427783SGiacomo.Gabrielli@arm.com 9437783SGiacomo.Gabrielli@arm.com ++commitCommittedInsts; 9447783SGiacomo.Gabrielli@arm.com 9457720Sgblack@eecs.umich.edu // To match the old model, don't count nops and instruction 9462935Sksewell@umich.edu // prefetches towards the total commit count. 9477784SAli.Saidi@ARM.com if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9487784SAli.Saidi@ARM.com cpu->instDone(tid); 9497784SAli.Saidi@ARM.com } 9507784SAli.Saidi@ARM.com 9517784SAli.Saidi@ARM.com PC[tid] = nextPC[tid]; 9522292SN/A nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 9532292SN/A#if FULL_SYSTEM 9545108Sgblack@eecs.umich.edu int count = 0; 9555108Sgblack@eecs.umich.edu Addr oldpc; 9565108Sgblack@eecs.umich.edu do { 9572292SN/A // Debug statement. Checks to make sure we're not 9587720Sgblack@eecs.umich.edu // currently updating state while handling PC events. 9595108Sgblack@eecs.umich.edu if (count == 0) 9602292SN/A assert(!thread[tid]->inSyscall && 9617720Sgblack@eecs.umich.edu !thread[tid]->trapPending); 9622292SN/A oldpc = PC[tid]; 9635108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service( 9645108Sgblack@eecs.umich.edu thread[tid]->getXCProxy()); 9652292SN/A count++; 9662292SN/A } while (oldpc != PC[tid]); 9671060SN/A if (count > 1) { 9687720Sgblack@eecs.umich.edu DPRINTF(Commit, "PC skip function event, stopping commit\n"); 9692292SN/A break; 9707720Sgblack@eecs.umich.edu } 9711060SN/A#endif 9721060SN/A } else { 9731060SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9741060SN/A "[tid:%i] [sn:%i].\n", 9751062SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9761063SN/A break; 9772292SN/A } 9782307SN/A } 9792307SN/A } 9802349SN/A 9812307SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9821060SN/A numCommittedDist.sample(num_committed); 9831060SN/A 9841061SN/A if (num_committed == commitWidth) { 9851060SN/A commitEligible[0]++; 9862292SN/A } 9871060SN/A} 9881060SN/A 9891060SN/Atemplate <class Impl> 9906221Snate@binkert.orgbool 9912292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9922316SN/A{ 9932316SN/A assert(head_inst); 9941061SN/A 9951061SN/A int tid = head_inst->threadNumber; 9961061SN/A 9972292SN/A // If the instruction is not executed yet, then it will need extra 9981062SN/A // handling. Signal backwards that it should be executed. 9992292SN/A if (!head_inst->isExecuted()) { 10002348SN/A // Keep this number correct. We have not yet actually executed 10012292SN/A // and committed this instruction. 10022292SN/A thread[tid]->funcExeInst--; 10032316SN/A 10042316SN/A head_inst->reachedCommit = true; 10057720Sgblack@eecs.umich.edu 10067720Sgblack@eecs.umich.edu if (head_inst->isNonSpeculative() || 10072316SN/A head_inst->isMemBarrier() || 10085557Sktlim@umich.edu head_inst->isWriteBarrier()) { 10092292SN/A 10102292SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 10112292SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 10122292SN/A head_inst->seqNum, head_inst->readPC()); 10132292SN/A 10141061SN/A#if !FULL_SYSTEM 10151061SN/A // Hack to make sure syscalls/memory barriers/quiesces 10161061SN/A // aren't executed until all stores write back their data. 10171061SN/A // This direct communication shouldn't be used for 10181061SN/A // anything other than this. 10191062SN/A if (inst_num > 0 || iewStage->hasStoresToWB()) 10201062SN/A#else 10211061SN/A if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 10222292SN/A head_inst->isQuiesce()) && 10235557Sktlim@umich.edu iewStage->hasStoresToWB()) 10244035Sktlim@umich.edu#endif 10254035Sktlim@umich.edu { 10264035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10274035Sktlim@umich.edu return false; 10284035Sktlim@umich.edu } 10297720Sgblack@eecs.umich.edu 10307720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10312292SN/A 10322292SN/A // Change the instruction so it won't try to commit again until 10332316SN/A // it is executed. 10342292SN/A head_inst->clearCanCommit(); 10352292SN/A 10362292SN/A ++commitNonSpecStalls; 10372292SN/A 10382292SN/A return false; 10392292SN/A } else if (head_inst->isLoad()) { 10402292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 10411061SN/A head_inst->seqNum, head_inst->readPC()); 10422292SN/A 10431061SN/A // Send back the non-speculative instruction's sequence 10441061SN/A // number. Tell the lsq to re-execute the load. 10451060SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10461060SN/A toIEW->commitInfo[tid].uncached = true; 10472316SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10482292SN/A 10492316SN/A head_inst->clearCanCommit(); 10502132SN/A 10512132SN/A return false; 10524035Sktlim@umich.edu } else { 10534035Sktlim@umich.edu panic("Trying to commit un-executed instruction " 10544035Sktlim@umich.edu "of unknown type!\n"); 10552316SN/A } 10564035Sktlim@umich.edu } 10572310SN/A 10582310SN/A if (head_inst->isThreadSync()) { 10592310SN/A // Not handled for now. 10602733Sktlim@umich.edu panic("Thread sync instructions are not handled yet.\n"); 10612316SN/A } 10622316SN/A 10632316SN/A // Stores mark themselves as completed. 10642732Sktlim@umich.edu if (!head_inst->isStore()) { 10651060SN/A head_inst->setCompleted(); 10662733Sktlim@umich.edu } 10671060SN/A 10682112SN/A // Use checker prior to updating anything due to traps or PC 10697720Sgblack@eecs.umich.edu // based events. 10707720Sgblack@eecs.umich.edu if (cpu->checker) { 10712292SN/A cpu->checker->tick(head_inst); 10725557Sktlim@umich.edu } 10732316SN/A 10742316SN/A // Check if the instruction caused a fault. If so, trap. 10752316SN/A Fault inst_fault = head_inst->getFault(); 10762310SN/A 10774035Sktlim@umich.edu if (inst_fault != NoFault) { 10784035Sktlim@umich.edu head_inst->setCompleted(); 10792733Sktlim@umich.edu#if FULL_SYSTEM 10802316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10812732Sktlim@umich.edu head_inst->seqNum, head_inst->readPC()); 10822316SN/A 10832733Sktlim@umich.edu if (iewStage->hasStoresToWB() || inst_num > 0) { 10842292SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10852316SN/A return false; 10862292SN/A } 10872316SN/A 10882316SN/A if (cpu->checker && head_inst->isStore()) { 10892316SN/A cpu->checker->tick(head_inst); 10902292SN/A } 10912316SN/A 10922316SN/A assert(!thread[tid]->inSyscall); 10932316SN/A 10942316SN/A // Mark that we're in state update mode so that the trap's 10952316SN/A // execution doesn't generate extra squashes. 10962316SN/A thread[tid]->inSyscall = true; 10977684Sgblack@eecs.umich.edu 10982292SN/A // DTB will sometimes need the machine instruction for when 10992316SN/A // faults happen. So we will set it here, prior to the DTB 11002316SN/A // possibly needing it for its fault. 11012292SN/A thread[tid]->setInst( 11022316SN/A static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 11032292SN/A 11044035Sktlim@umich.edu // Execute the trap. Although it's slightly unrealistic in 11056667Ssteve.reinhardt@amd.com // terms of timing (as it doesn't wait for the full timing of 11066667Ssteve.reinhardt@amd.com // the trap event to complete before updating state), it's 11076667Ssteve.reinhardt@amd.com // needed to update the state as soon as possible. This 11086667Ssteve.reinhardt@amd.com // prevents external agents from changing any specific state 11096667Ssteve.reinhardt@amd.com // that the trap need. 11104288Sktlim@umich.edu cpu->trap(inst_fault, tid); 11114035Sktlim@umich.edu 11124035Sktlim@umich.edu // Exit state update mode to avoid accidental updating. 11134035Sktlim@umich.edu thread[tid]->inSyscall = false; 11142316SN/A 11152316SN/A commitStatus[tid] = TrapPending; 11162316SN/A 11171060SN/A // Generate trap squash event. 11181060SN/A generateTrapEvent(tid); 11192301SN/A 11202132SN/A return false; 11212362SN/A#else // !FULL_SYSTEM 11222362SN/A panic("fault (%d) detected @ PC %08p", inst_fault, 11237720Sgblack@eecs.umich.edu head_inst->PC); 11243126Sktlim@umich.edu#endif // FULL_SYSTEM 11252362SN/A } 11262362SN/A 11272362SN/A updateComInstStats(head_inst); 11282362SN/A 11292362SN/A if (head_inst->traceData) { 11305953Ssaidi@eecs.umich.edu head_inst->traceData->setFetchSeq(head_inst->seqNum); 11315953Ssaidi@eecs.umich.edu head_inst->traceData->setCPSeq(thread[tid]->numInst); 11325953Ssaidi@eecs.umich.edu head_inst->traceData->finalize(); 11337720Sgblack@eecs.umich.edu head_inst->traceData = NULL; 11345953Ssaidi@eecs.umich.edu } 11355953Ssaidi@eecs.umich.edu 11362362SN/A // Update the commit rename map 11372362SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11382132SN/A renameMap[tid]->setEntry(head_inst->destRegIdx(i), 11392292SN/A head_inst->renamedDestRegIdx(i)); 11402292SN/A } 11414046Sbinkertn@umich.edu 11424046Sbinkertn@umich.edu // Finally clear the head ROB entry. 11432292SN/A rob->retireHead(tid); 11441060SN/A 11451060SN/A // Return true to indicate that we have committed an instruction. 11462292SN/A return true; 11472292SN/A} 11483771Sgblack@eecs.umich.edu 11492292SN/Atemplate <class Impl> 11501060SN/Avoid 11511062SN/ADefaultCommit<Impl>::getInsts() 11522353SN/A{ 11532353SN/A // Read any renamed instructions and place them into the ROB. 11542353SN/A int insts_to_process = min((int)renameWidth, fromRename->size); 11552292SN/A 11562292SN/A for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) 11571060SN/A { 11584035Sktlim@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 11594035Sktlim@umich.edu int tid = inst->threadNumber; 11604035Sktlim@umich.edu 11614035Sktlim@umich.edu if (!inst->isSquashed() && 11621060SN/A commitStatus[tid] != ROBSquashing) { 11631060SN/A changedROBNumEntries[tid] = true; 11641060SN/A 11651060SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 11661061SN/A inst->readPC(), inst->seqNum, tid); 11671060SN/A 11682292SN/A rob->insertInst(inst); 11691060SN/A 11702935Sksewell@umich.edu assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 11712935Sksewell@umich.edu 11723093Sksewell@umich.edu youngestSeqNum[tid] = inst->seqNum; 11733093Sksewell@umich.edu } else { 11742965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11752965Sksewell@umich.edu "squashed, skipping.\n", 11762965Sksewell@umich.edu inst->readPC(), inst->seqNum, tid); 11772965Sksewell@umich.edu } 11783093Sksewell@umich.edu } 11796221Snate@binkert.org} 11802292SN/A 11812292SN/Atemplate <class Impl> 11824035Sktlim@umich.eduvoid 11834035Sktlim@umich.eduDefaultCommit<Impl>::markCompletedInsts() 11842292SN/A{ 11852292SN/A // Grab completed insts out of the IEW instruction queue, and mark 11867720Sgblack@eecs.umich.edu // instructions completed within the ROB. 11877720Sgblack@eecs.umich.edu for (int inst_num = 0; 11882292SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 11892292SN/A ++inst_num) 11902292SN/A { 11912292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 11922292SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 11932292SN/A "within ROB.\n", 11941061SN/A fromIEW->insts[inst_num]->threadNumber, 11957720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->readPC(), 11961061SN/A fromIEW->insts[inst_num]->seqNum); 11977720Sgblack@eecs.umich.edu 11981061SN/A // Mark the instruction as ready to commit. 11991060SN/A fromIEW->insts[inst_num]->setCanCommit(); 12002965Sksewell@umich.edu } 12012965Sksewell@umich.edu } 12022965Sksewell@umich.edu} 12032965Sksewell@umich.edu 12042965Sksewell@umich.edutemplate <class Impl> 12052965Sksewell@umich.edubool 12062965Sksewell@umich.eduDefaultCommit<Impl>::robDoneSquashing() 12072965Sksewell@umich.edu{ 12082965Sksewell@umich.edu list<unsigned>::iterator threads = (*activeThreads).begin(); 12092965Sksewell@umich.edu 12102965Sksewell@umich.edu while (threads != (*activeThreads).end()) { 12112965Sksewell@umich.edu unsigned tid = *threads++; 12122965Sksewell@umich.edu 12137720Sgblack@eecs.umich.edu if (!rob->isDoneSquashing(tid)) 12147720Sgblack@eecs.umich.edu return false; 12153221Sktlim@umich.edu } 12162965Sksewell@umich.edu 12172965Sksewell@umich.edu return true; 12187720Sgblack@eecs.umich.edu} 12192965Sksewell@umich.edu 12207720Sgblack@eecs.umich.edutemplate <class Impl> 12212965Sksewell@umich.eduvoid 12222965Sksewell@umich.eduDefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 12231060SN/A{ 12241060SN/A unsigned thread = inst->threadNumber; 12251061SN/A 12261060SN/A // 12272292SN/A // Pick off the software prefetches 12281060SN/A // 12291060SN/A#ifdef TARGET_ALPHA 12301060SN/A if (inst->isDataPrefetch()) { 12311060SN/A statComSwp[thread]++; 12321681SN/A } else { 12331060SN/A statComInst[thread]++; 12341060SN/A } 12352292SN/A#else 12367720Sgblack@eecs.umich.edu statComInst[thread]++; 12372316SN/A#endif 12382292SN/A 12397720Sgblack@eecs.umich.edu // 12402292SN/A // Control Instructions 12411060SN/A // 12422292SN/A if (inst->isControl()) 12432292SN/A statComBranches[thread]++; 12442292SN/A 12451060SN/A // 12461060SN/A // Memory references 12471060SN/A // 12481061SN/A if (inst->isMemRef()) { 12492292SN/A statComRefs[thread]++; 12502292SN/A 12511060SN/A if (inst->isLoad()) { 12526221Snate@binkert.org statComLoads[thread]++; 12536221Snate@binkert.org } 12542292SN/A } 12553867Sbinkertn@umich.edu 12566221Snate@binkert.org if (inst->isMemBarrier()) { 12572292SN/A statComMembars[thread]++; 12582292SN/A } 12592292SN/A} 12602292SN/A 12612292SN/A//////////////////////////////////////// 12622292SN/A// // 12631060SN/A// SMT COMMIT POLICY MAINTAINED HERE // 12642292SN/A// // 12652301SN/A//////////////////////////////////////// 12662301SN/Atemplate <class Impl> 12672301SN/Aint 12682301SN/ADefaultCommit<Impl>::getCommittingThread() 12696221Snate@binkert.org{ 12702301SN/A if (numThreads > 1) { 12712301SN/A switch (commitPolicy) { 12722301SN/A 12732301SN/A case Aggressive: 12742301SN/A //If Policy is Aggressive, commit will call 12752301SN/A //this function multiple times per 12766221Snate@binkert.org //cycle 12772301SN/A return oldestReady(); 12786221Snate@binkert.org 12792301SN/A case RoundRobin: 12802301SN/A return roundRobin(); 12816221Snate@binkert.org 12822301SN/A case OldestReady: 12832301SN/A return oldestReady(); 12842301SN/A 12852301SN/A default: 12862301SN/A return -1; 12872301SN/A } 12886221Snate@binkert.org } else { 12892301SN/A int tid = (*activeThreads).front(); 12902301SN/A 12912301SN/A if (commitStatus[tid] == Running || 12922301SN/A commitStatus[tid] == Idle || 12932301SN/A commitStatus[tid] == FetchTrapPending) { 12946221Snate@binkert.org return tid; 12952301SN/A } else { 12962301SN/A return -1; 12976221Snate@binkert.org } 12982301SN/A } 12992301SN/A} 13002301SN/A 13012301SN/Atemplate<class Impl> 13026221Snate@binkert.orgint 13032301SN/ADefaultCommit<Impl>::roundRobin() 13042301SN/A{ 13052301SN/A list<unsigned>::iterator pri_iter = priority_list.begin(); 13062292SN/A list<unsigned>::iterator end = priority_list.end(); 13072292SN/A 13082316SN/A while (pri_iter != end) { 13092292SN/A unsigned tid = *pri_iter; 13102292SN/A 13112292SN/A if (commitStatus[tid] == Running || 13126221Snate@binkert.org commitStatus[tid] == Idle) { 13132292SN/A 13142292SN/A if (rob->isHeadReady(tid)) { 13152292SN/A priority_list.erase(pri_iter); 13162292SN/A priority_list.push_back(tid); 13172292SN/A 13182292SN/A return tid; 13192292SN/A } 13202292SN/A } 13212292SN/A 13222292SN/A pri_iter++; 13232292SN/A } 13242292SN/A 13252292SN/A return -1; 13262292SN/A} 13272292SN/A 13282292SN/Atemplate<class Impl> 13292292SN/Aint 13302292SN/ADefaultCommit<Impl>::oldestReady() 13316221Snate@binkert.org{ 13322292SN/A unsigned oldest = 0; 13332292SN/A bool first = true; 13343867Sbinkertn@umich.edu 13356221Snate@binkert.org list<unsigned>::iterator threads = (*activeThreads).begin(); 13362292SN/A 13372292SN/A while (threads != (*activeThreads).end()) { 13382292SN/A unsigned tid = *threads++; 13392292SN/A 13402292SN/A if (!rob->isEmpty(tid) && 13412292SN/A (commitStatus[tid] == Running || 13426221Snate@binkert.org commitStatus[tid] == Idle || 13432292SN/A commitStatus[tid] == FetchTrapPending)) { 13442292SN/A 13452292SN/A if (rob->isHeadReady(tid)) { 13462292SN/A 13472292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 13486221Snate@binkert.org 13492292SN/A if (first) { 13502292SN/A oldest = tid; 13516221Snate@binkert.org first = false; 13526221Snate@binkert.org } else if (head_inst->seqNum < oldest) { 13532292SN/A oldest = tid; 13542292SN/A } 13556221Snate@binkert.org } 13562292SN/A } 13572292SN/A } 13582831Sksewell@umich.edu 13592831Sksewell@umich.edu if (!first) { 13602292SN/A return oldest; 13612292SN/A } else { 13622292SN/A return -1; 13632292SN/A } 13642292SN/A} 13652292SN/A