commit_impl.hh revision 13831
11689SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 312216Snikos.nikoleris@arm.com * Copyright (c) 2010-2014, 2017 ARM Limited 47783SGiacomo.Gabrielli@arm.com * All rights reserved 57783SGiacomo.Gabrielli@arm.com * 67783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147783SGiacomo.Gabrielli@arm.com * 152316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422965Sksewell@umich.edu * Korey Sewell 431689SN/A */ 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_COMMIT_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_COMMIT_IMPL_HH__ 461689SN/A 472292SN/A#include <algorithm> 489516SAli.Saidi@ARM.com#include <set> 492329SN/A#include <string> 502292SN/A 513577Sgblack@eecs.umich.edu#include "arch/utility.hh" 5213449Sgabeblack@google.com#include "base/cp_annotate.hh" 538229Snate@binkert.org#include "base/loader/symtab.hh" 5413449Sgabeblack@google.com#include "base/logging.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 571717SN/A#include "cpu/o3/commit.hh" 582292SN/A#include "cpu/o3/thread_state.hh" 598662SAli.Saidi@ARM.com#include "cpu/base.hh" 608229Snate@binkert.org#include "cpu/exetrace.hh" 618229Snate@binkert.org#include "cpu/timebuf.hh" 628232Snate@binkert.org#include "debug/Activity.hh" 638232Snate@binkert.org#include "debug/Commit.hh" 648232Snate@binkert.org#include "debug/CommitRate.hh" 659444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 668232Snate@binkert.org#include "debug/ExecFaulting.hh" 679527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 686221Snate@binkert.org#include "params/DerivO3CPU.hh" 698230Snate@binkert.org#include "sim/faults.hh" 708793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 712292SN/A 726221Snate@binkert.orgusing namespace std; 735529Snate@binkert.org 741061SN/Atemplate <class Impl> 751060SN/Avoid 7612127Sspwilson2@wisc.eduDefaultCommit<Impl>::processTrapEvent(ThreadID tid) 771062SN/A{ 782316SN/A // This will get reset by commit if it was switched out at the 792316SN/A // time of this event processing. 8012127Sspwilson2@wisc.edu trapSquash[tid] = true; 812292SN/A} 822292SN/A 832292SN/Atemplate <class Impl> 845529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 8513563Snikos.nikoleris@arm.com : commitPolicy(params->smtCommitPolicy), 8613563Snikos.nikoleris@arm.com cpu(_cpu), 872292SN/A iewToCommitDelay(params->iewToCommitDelay), 882292SN/A commitToIEWDelay(params->commitToIEWDelay), 892292SN/A renameToROBDelay(params->renameToROBDelay), 902292SN/A fetchToCommitDelay(params->commitToFetchDelay), 912292SN/A renameWidth(params->renameWidth), 922292SN/A commitWidth(params->commitWidth), 935529Snate@binkert.org numThreads(params->numThreads), 942843Sktlim@umich.edu drainPending(false), 9510340Smitch.hayenga@arm.com drainImminent(false), 968823Snilay@cs.wisc.edu trapLatency(params->trapLatency), 979513SAli.Saidi@ARM.com canHandleInterrupts(true), 989513SAli.Saidi@ARM.com avoidQuiesceLiveLock(false) 992292SN/A{ 10010172Sdam.sunwoo@arm.com if (commitWidth > Impl::MaxWidth) 10110172Sdam.sunwoo@arm.com fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 10210172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 10310172Sdam.sunwoo@arm.com commitWidth, static_cast<int>(Impl::MaxWidth)); 10410172Sdam.sunwoo@arm.com 1052292SN/A _status = Active; 1062292SN/A _nextStatus = Inactive; 1072292SN/A 10813563Snikos.nikoleris@arm.com if (commitPolicy == CommitPolicy::RoundRobin) { 1092292SN/A //Set-Up Priority List 1106221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1112292SN/A priority_list.push_back(tid); 1122292SN/A } 1132292SN/A } 1142292SN/A 11513453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1166221Snate@binkert.org commitStatus[tid] = Idle; 1176221Snate@binkert.org changedROBNumEntries[tid] = false; 11813453Srekai.gonzalezalberquilla@arm.com trapSquash[tid] = false; 11913453Srekai.gonzalezalberquilla@arm.com tcSquash[tid] = false; 12013453Srekai.gonzalezalberquilla@arm.com squashAfterInst[tid] = nullptr; 12113453Srekai.gonzalezalberquilla@arm.com pc[tid].set(0); 12213453Srekai.gonzalezalberquilla@arm.com youngestSeqNum[tid] = 0; 12313453Srekai.gonzalezalberquilla@arm.com lastCommitedSeqNum[tid] = 0; 1246221Snate@binkert.org trapInFlight[tid] = false; 1256221Snate@binkert.org committedStores[tid] = false; 12613453Srekai.gonzalezalberquilla@arm.com checkEmptyROB[tid] = false; 12713453Srekai.gonzalezalberquilla@arm.com renameMap[tid] = nullptr; 1282292SN/A } 1293640Sktlim@umich.edu interrupt = NoFault; 1302292SN/A} 1312292SN/A 1322292SN/Atemplate <class Impl> 1332292SN/Astd::string 1342292SN/ADefaultCommit<Impl>::name() const 1352292SN/A{ 1362292SN/A return cpu->name() + ".commit"; 1372292SN/A} 1382292SN/A 1392292SN/Atemplate <class Impl> 1402292SN/Avoid 14110023Smatt.horsnell@ARM.comDefaultCommit<Impl>::regProbePoints() 14210023Smatt.horsnell@ARM.com{ 14310023Smatt.horsnell@ARM.com ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 14410023Smatt.horsnell@ARM.com ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 14511246Sradhika.jagtap@ARM.com ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash"); 14610023Smatt.horsnell@ARM.com} 14710023Smatt.horsnell@ARM.com 14810023Smatt.horsnell@ARM.comtemplate <class Impl> 14910023Smatt.horsnell@ARM.comvoid 1502292SN/ADefaultCommit<Impl>::regStats() 1512132SN/A{ 1522301SN/A using namespace Stats; 1531062SN/A commitSquashedInsts 1541062SN/A .name(name() + ".commitSquashedInsts") 1551062SN/A .desc("The number of squashed insts skipped by commit") 1561062SN/A .prereq(commitSquashedInsts); 15710731Snilay@cs.wisc.edu 1581062SN/A commitNonSpecStalls 1591062SN/A .name(name() + ".commitNonSpecStalls") 1601062SN/A .desc("The number of times commit has been forced to stall to " 1611062SN/A "communicate backwards") 1621062SN/A .prereq(commitNonSpecStalls); 16310731Snilay@cs.wisc.edu 1641062SN/A branchMispredicts 1651062SN/A .name(name() + ".branchMispredicts") 1661062SN/A .desc("The number of times a branch was mispredicted") 1671062SN/A .prereq(branchMispredicts); 16810731Snilay@cs.wisc.edu 1692292SN/A numCommittedDist 1701062SN/A .init(0,commitWidth,1) 1718240Snate@binkert.org .name(name() + ".committed_per_cycle") 1721062SN/A .desc("Number of insts commited each cycle") 1731062SN/A .flags(Stats::pdf) 1741062SN/A ; 1752301SN/A 1768834Satgutier@umich.edu instsCommitted 1776221Snate@binkert.org .init(cpu->numThreads) 1788834Satgutier@umich.edu .name(name() + ".committedInsts") 1792301SN/A .desc("Number of instructions committed") 1802301SN/A .flags(total) 1812301SN/A ; 1822301SN/A 1838834Satgutier@umich.edu opsCommitted 1848834Satgutier@umich.edu .init(cpu->numThreads) 1858834Satgutier@umich.edu .name(name() + ".committedOps") 1868834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 1878834Satgutier@umich.edu .flags(total) 1888834Satgutier@umich.edu ; 1898834Satgutier@umich.edu 1902316SN/A statComSwp 1916221Snate@binkert.org .init(cpu->numThreads) 1928240Snate@binkert.org .name(name() + ".swp_count") 1932301SN/A .desc("Number of s/w prefetches committed") 1942301SN/A .flags(total) 1952301SN/A ; 1962301SN/A 1972316SN/A statComRefs 1986221Snate@binkert.org .init(cpu->numThreads) 1998240Snate@binkert.org .name(name() + ".refs") 2002301SN/A .desc("Number of memory references committed") 2012301SN/A .flags(total) 2022301SN/A ; 2032301SN/A 2042316SN/A statComLoads 2056221Snate@binkert.org .init(cpu->numThreads) 2068240Snate@binkert.org .name(name() + ".loads") 2072301SN/A .desc("Number of loads committed") 2082301SN/A .flags(total) 2092301SN/A ; 2102301SN/A 21113652Sqtt2@cornell.edu statComAmos 21213652Sqtt2@cornell.edu .init(cpu->numThreads) 21313652Sqtt2@cornell.edu .name(name() + ".amos") 21413652Sqtt2@cornell.edu .desc("Number of atomic instructions committed") 21513652Sqtt2@cornell.edu .flags(total) 21613652Sqtt2@cornell.edu ; 21713652Sqtt2@cornell.edu 2182316SN/A statComMembars 2196221Snate@binkert.org .init(cpu->numThreads) 2208240Snate@binkert.org .name(name() + ".membars") 2212301SN/A .desc("Number of memory barriers committed") 2222301SN/A .flags(total) 2232301SN/A ; 2242301SN/A 2252316SN/A statComBranches 2266221Snate@binkert.org .init(cpu->numThreads) 2278240Snate@binkert.org .name(name() + ".branches") 2282301SN/A .desc("Number of branches committed") 2292301SN/A .flags(total) 2302301SN/A ; 2312301SN/A 2327897Shestness@cs.utexas.edu statComFloating 2337897Shestness@cs.utexas.edu .init(cpu->numThreads) 2348240Snate@binkert.org .name(name() + ".fp_insts") 2357897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2367897Shestness@cs.utexas.edu .flags(total) 2377897Shestness@cs.utexas.edu ; 2387897Shestness@cs.utexas.edu 23912110SRekai.GonzalezAlberquilla@arm.com statComVector 24012110SRekai.GonzalezAlberquilla@arm.com .init(cpu->numThreads) 24112110SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_insts") 24212110SRekai.GonzalezAlberquilla@arm.com .desc("Number of committed Vector instructions.") 24312110SRekai.GonzalezAlberquilla@arm.com .flags(total) 24412110SRekai.GonzalezAlberquilla@arm.com ; 24512110SRekai.GonzalezAlberquilla@arm.com 2467897Shestness@cs.utexas.edu statComInteger 2477897Shestness@cs.utexas.edu .init(cpu->numThreads) 2488240Snate@binkert.org .name(name()+".int_insts") 2497897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2507897Shestness@cs.utexas.edu .flags(total) 2517897Shestness@cs.utexas.edu ; 2527897Shestness@cs.utexas.edu 2537897Shestness@cs.utexas.edu statComFunctionCalls 2547897Shestness@cs.utexas.edu .init(cpu->numThreads) 2558240Snate@binkert.org .name(name()+".function_calls") 2567897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2577897Shestness@cs.utexas.edu .flags(total) 2587897Shestness@cs.utexas.edu ; 2597897Shestness@cs.utexas.edu 26010193SCurtis.Dunham@arm.com statCommittedInstType 26110193SCurtis.Dunham@arm.com .init(numThreads,Enums::Num_OpClass) 26210193SCurtis.Dunham@arm.com .name(name() + ".op_class") 26310193SCurtis.Dunham@arm.com .desc("Class of committed instruction") 26410193SCurtis.Dunham@arm.com .flags(total | pdf | dist) 26510193SCurtis.Dunham@arm.com ; 26610193SCurtis.Dunham@arm.com statCommittedInstType.ysubnames(Enums::OpClassStrings); 26710193SCurtis.Dunham@arm.com 2682316SN/A commitEligibleSamples 2698240Snate@binkert.org .name(name() + ".bw_lim_events") 2702301SN/A .desc("number cycles where commit BW limit reached") 2712301SN/A ; 2721062SN/A} 2731062SN/A 2741062SN/Atemplate <class Impl> 2751062SN/Avoid 2762980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2772292SN/A{ 2782292SN/A thread = threads; 2792292SN/A} 2802292SN/A 2812292SN/Atemplate <class Impl> 2822292SN/Avoid 2832292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2841060SN/A{ 2851060SN/A timeBuffer = tb_ptr; 2861060SN/A 2871060SN/A // Setup wire to send information back to IEW. 2881060SN/A toIEW = timeBuffer->getWire(0); 2891060SN/A 2901060SN/A // Setup wire to read data from IEW (for the ROB). 2911060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2921060SN/A} 2931060SN/A 2941061SN/Atemplate <class Impl> 2951060SN/Avoid 2962292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2972292SN/A{ 2982292SN/A fetchQueue = fq_ptr; 2992292SN/A 3002292SN/A // Setup wire to get instructions from rename (for the ROB). 3012292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 3022292SN/A} 3032292SN/A 3042292SN/Atemplate <class Impl> 3052292SN/Avoid 3062292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3071060SN/A{ 3081060SN/A renameQueue = rq_ptr; 3091060SN/A 3101060SN/A // Setup wire to get instructions from rename (for the ROB). 3111060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3121060SN/A} 3131060SN/A 3141061SN/Atemplate <class Impl> 3151060SN/Avoid 3162292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3171060SN/A{ 3181060SN/A iewQueue = iq_ptr; 3191060SN/A 3201060SN/A // Setup wire to get instructions from IEW. 3211060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3221060SN/A} 3231060SN/A 3241061SN/Atemplate <class Impl> 3251060SN/Avoid 3262292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3272292SN/A{ 3282292SN/A iewStage = iew_stage; 3292292SN/A} 3302292SN/A 3312292SN/Atemplate<class Impl> 3322292SN/Avoid 3336221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3342292SN/A{ 3352292SN/A activeThreads = at_ptr; 3362292SN/A} 3372292SN/A 3382292SN/Atemplate <class Impl> 3392292SN/Avoid 3402292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3412292SN/A{ 3426221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3436221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3442292SN/A} 3452292SN/A 3462292SN/Atemplate <class Impl> 3472292SN/Avoid 3482292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3491060SN/A{ 3501060SN/A rob = rob_ptr; 3511060SN/A} 3521060SN/A 3531061SN/Atemplate <class Impl> 3541060SN/Avoid 3559427SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::startupStage() 3561060SN/A{ 3572292SN/A rob->setActiveThreads(activeThreads); 3582292SN/A rob->resetEntries(); 3591060SN/A 3602292SN/A // Broadcast the number of free entries. 3616221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3626221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3636221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3646221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3651060SN/A } 3661060SN/A 3674329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3684329Sktlim@umich.edu // start of the simulation, so it starts as active. 3694329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3704329Sktlim@umich.edu 3712292SN/A cpu->activityThisCycle(); 3721060SN/A} 3731060SN/A 3741061SN/Atemplate <class Impl> 3759444SAndreas.Sandberg@ARM.comvoid 37613641Sqtt2@cornell.eduDefaultCommit<Impl>::clearStates(ThreadID tid) 37713641Sqtt2@cornell.edu{ 37813641Sqtt2@cornell.edu commitStatus[tid] = Idle; 37913641Sqtt2@cornell.edu changedROBNumEntries[tid] = false; 38013641Sqtt2@cornell.edu checkEmptyROB[tid] = false; 38113641Sqtt2@cornell.edu trapInFlight[tid] = false; 38213641Sqtt2@cornell.edu committedStores[tid] = false; 38313641Sqtt2@cornell.edu trapSquash[tid] = false; 38413641Sqtt2@cornell.edu tcSquash[tid] = false; 38513641Sqtt2@cornell.edu pc[tid].set(0); 38613641Sqtt2@cornell.edu lastCommitedSeqNum[tid] = 0; 38713641Sqtt2@cornell.edu squashAfterInst[tid] = NULL; 38813641Sqtt2@cornell.edu} 38913641Sqtt2@cornell.edu 39013641Sqtt2@cornell.edutemplate <class Impl> 39113641Sqtt2@cornell.eduvoid 3922843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3931060SN/A{ 3942843Sktlim@umich.edu drainPending = true; 3952316SN/A} 3962316SN/A 3972316SN/Atemplate <class Impl> 3982316SN/Avoid 3999444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainResume() 4002843Sktlim@umich.edu{ 4012864Sktlim@umich.edu drainPending = false; 40210340Smitch.hayenga@arm.com drainImminent = false; 4032843Sktlim@umich.edu} 4042843Sktlim@umich.edu 4052843Sktlim@umich.edutemplate <class Impl> 4062843Sktlim@umich.eduvoid 4079444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainSanityCheck() const 4089444SAndreas.Sandberg@ARM.com{ 4099444SAndreas.Sandberg@ARM.com assert(isDrained()); 4109444SAndreas.Sandberg@ARM.com rob->drainSanityCheck(); 4119444SAndreas.Sandberg@ARM.com} 4129444SAndreas.Sandberg@ARM.com 4139444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4149444SAndreas.Sandberg@ARM.combool 4159444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::isDrained() const 4169444SAndreas.Sandberg@ARM.com{ 4179444SAndreas.Sandberg@ARM.com /* Make sure no one is executing microcode. There are two reasons 4189444SAndreas.Sandberg@ARM.com * for this: 4199444SAndreas.Sandberg@ARM.com * - Hardware virtualized CPUs can't switch into the middle of a 4209444SAndreas.Sandberg@ARM.com * microcode sequence. 4219444SAndreas.Sandberg@ARM.com * - The current fetch implementation will most likely get very 4229444SAndreas.Sandberg@ARM.com * confused if it tries to start fetching an instruction that 4239444SAndreas.Sandberg@ARM.com * is executing in the middle of a ucode sequence that changes 4249444SAndreas.Sandberg@ARM.com * address mappings. This can happen on for example x86. 4259444SAndreas.Sandberg@ARM.com */ 4269444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 4279444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() != 0) 4289444SAndreas.Sandberg@ARM.com return false; 4299444SAndreas.Sandberg@ARM.com } 4309444SAndreas.Sandberg@ARM.com 4319444SAndreas.Sandberg@ARM.com /* Make sure that all instructions have finished committing before 4329444SAndreas.Sandberg@ARM.com * declaring the system as drained. We want the pipeline to be 4339444SAndreas.Sandberg@ARM.com * completely empty when we declare the CPU to be drained. This 4349444SAndreas.Sandberg@ARM.com * makes debugging easier since CPU handover and restoring from a 4359444SAndreas.Sandberg@ARM.com * checkpoint with a different CPU should have the same timing. 4369444SAndreas.Sandberg@ARM.com */ 4379444SAndreas.Sandberg@ARM.com return rob->isEmpty() && 4389444SAndreas.Sandberg@ARM.com interrupt == NoFault; 4399444SAndreas.Sandberg@ARM.com} 4409444SAndreas.Sandberg@ARM.com 4419444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4429444SAndreas.Sandberg@ARM.comvoid 4432307SN/ADefaultCommit<Impl>::takeOverFrom() 4442307SN/A{ 4452307SN/A _status = Active; 4462307SN/A _nextStatus = Inactive; 4476221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4486221Snate@binkert.org commitStatus[tid] = Idle; 4496221Snate@binkert.org changedROBNumEntries[tid] = false; 4506221Snate@binkert.org trapSquash[tid] = false; 4516221Snate@binkert.org tcSquash[tid] = false; 4529437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 4532307SN/A } 4542307SN/A rob->takeOverFrom(); 4552307SN/A} 4562307SN/A 4572307SN/Atemplate <class Impl> 4582307SN/Avoid 45910331Smitch.hayenga@arm.comDefaultCommit<Impl>::deactivateThread(ThreadID tid) 46010331Smitch.hayenga@arm.com{ 46110331Smitch.hayenga@arm.com list<ThreadID>::iterator thread_it = std::find(priority_list.begin(), 46210331Smitch.hayenga@arm.com priority_list.end(), tid); 46310331Smitch.hayenga@arm.com 46410331Smitch.hayenga@arm.com if (thread_it != priority_list.end()) { 46510331Smitch.hayenga@arm.com priority_list.erase(thread_it); 46610331Smitch.hayenga@arm.com } 46710331Smitch.hayenga@arm.com} 46810331Smitch.hayenga@arm.com 46910331Smitch.hayenga@arm.com 47010331Smitch.hayenga@arm.comtemplate <class Impl> 47110331Smitch.hayenga@arm.comvoid 4722292SN/ADefaultCommit<Impl>::updateStatus() 4732132SN/A{ 4742316SN/A // reset ROB changed variable 4756221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4766221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4773867Sbinkertn@umich.edu 4783867Sbinkertn@umich.edu while (threads != end) { 4796221Snate@binkert.org ThreadID tid = *threads++; 4803867Sbinkertn@umich.edu 4812316SN/A changedROBNumEntries[tid] = false; 4822316SN/A 4832316SN/A // Also check if any of the threads has a trap pending 4842316SN/A if (commitStatus[tid] == TrapPending || 4852316SN/A commitStatus[tid] == FetchTrapPending) { 4862316SN/A _nextStatus = Active; 4872316SN/A } 4882292SN/A } 4892292SN/A 4902292SN/A if (_nextStatus == Inactive && _status == Active) { 4912292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4922733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4932292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4942292SN/A DPRINTF(Activity, "Activating stage.\n"); 4952733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4962292SN/A } 4972292SN/A 4982292SN/A _status = _nextStatus; 4992292SN/A} 5002292SN/A 5012292SN/Atemplate <class Impl> 5022292SN/Abool 5032292SN/ADefaultCommit<Impl>::changedROBEntries() 5042292SN/A{ 5056221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5066221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5072292SN/A 5083867Sbinkertn@umich.edu while (threads != end) { 5096221Snate@binkert.org ThreadID tid = *threads++; 5102292SN/A 5112292SN/A if (changedROBNumEntries[tid]) { 5122292SN/A return true; 5132292SN/A } 5142292SN/A } 5152292SN/A 5162292SN/A return false; 5172292SN/A} 5182292SN/A 5192292SN/Atemplate <class Impl> 5206221Snate@binkert.orgsize_t 5216221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 5222292SN/A{ 5232292SN/A return rob->numFreeEntries(tid); 5242292SN/A} 5252292SN/A 5262292SN/Atemplate <class Impl> 5272292SN/Avoid 52811877Sbrandon.potter@amd.comDefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault) 5292292SN/A{ 5302292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5312292SN/A 53212127Sspwilson2@wisc.edu EventFunctionWrapper *trap = new EventFunctionWrapper( 53312127Sspwilson2@wisc.edu [this, tid]{ processTrapEvent(tid); }, 53412127Sspwilson2@wisc.edu "Trap", true, Event::CPU_Tick_Pri); 5352292SN/A 53611877Sbrandon.potter@amd.com Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ? 53711877Sbrandon.potter@amd.com cpu->syscallRetryLatency : trapLatency; 53811877Sbrandon.potter@amd.com 53911877Sbrandon.potter@amd.com cpu->schedule(trap, cpu->clockEdge(latency)); 5404035Sktlim@umich.edu trapInFlight[tid] = true; 5418518Sgeoffrey.blake@arm.com thread[tid]->trapPending = true; 5422292SN/A} 5432292SN/A 5442292SN/Atemplate <class Impl> 5452292SN/Avoid 5466221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5472292SN/A{ 5484035Sktlim@umich.edu assert(!trapInFlight[tid]); 5492680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5502292SN/A 5512680Sktlim@umich.edu tcSquash[tid] = true; 5522292SN/A} 5532292SN/A 5542292SN/Atemplate <class Impl> 5552292SN/Avoid 5566221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5572292SN/A{ 5582292SN/A // If we want to include the squashing instruction in the squash, 5592292SN/A // then use one older sequence number. 5602292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5612292SN/A // all instructions of this thread. 56210164Ssleimanf@umich.edu InstSeqNum squashed_inst = rob->isEmpty(tid) ? 5637855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5642292SN/A 5652292SN/A // All younger instructions will be squashed. Set the sequence 5662292SN/A // number as the youngest instruction in the ROB (0 in this case. 5672292SN/A // Hopefully nothing breaks.) 5687855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5692292SN/A 5702292SN/A rob->squash(squashed_inst, tid); 5712292SN/A changedROBNumEntries[tid] = true; 5722292SN/A 5732292SN/A // Send back the sequence number of the squashed instruction. 5742292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5752292SN/A 5762292SN/A // Send back the squash signal to tell stages that they should 5772292SN/A // squash. 5782292SN/A toIEW->commitInfo[tid].squash = true; 5792292SN/A 5802292SN/A // Send back the rob squashing signal so other stages know that 5812292SN/A // the ROB is in the process of squashing. 5822292SN/A toIEW->commitInfo[tid].robSquashing = true; 5832292SN/A 5847851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 5858137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 5862292SN/A 5877720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5882316SN/A} 5892292SN/A 5902316SN/Atemplate <class Impl> 5912316SN/Avoid 5926221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5932316SN/A{ 5942316SN/A squashAll(tid); 5952316SN/A 5967720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5972316SN/A 5982316SN/A thread[tid]->trapPending = false; 5999382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6004035Sktlim@umich.edu trapInFlight[tid] = false; 6012316SN/A 6022316SN/A trapSquash[tid] = false; 6032316SN/A 6042316SN/A commitStatus[tid] = ROBSquashing; 6052316SN/A cpu->activityThisCycle(); 6062316SN/A} 6072316SN/A 6082316SN/Atemplate <class Impl> 6092316SN/Avoid 6106221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 6112316SN/A{ 6122316SN/A squashAll(tid); 6132292SN/A 6147720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 6152292SN/A 6169382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6172292SN/A assert(!thread[tid]->trapPending); 6182316SN/A 6192292SN/A commitStatus[tid] = ROBSquashing; 6202292SN/A cpu->activityThisCycle(); 6212292SN/A 6222680Sktlim@umich.edu tcSquash[tid] = false; 6232292SN/A} 6242292SN/A 6252292SN/Atemplate <class Impl> 6262292SN/Avoid 6279437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 6287784SAli.Saidi@ARM.com{ 6299437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Squashing after squash after request, " 6309437SAndreas.Sandberg@ARM.com "restarting at PC %s\n", pc[tid]); 6317784SAli.Saidi@ARM.com 6329437SAndreas.Sandberg@ARM.com squashAll(tid); 6339437SAndreas.Sandberg@ARM.com // Make sure to inform the fetch stage of which instruction caused 6349437SAndreas.Sandberg@ARM.com // the squash. It'll try to re-fetch an instruction executing in 6359437SAndreas.Sandberg@ARM.com // microcode unless this is set. 6369437SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 6379437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 6387784SAli.Saidi@ARM.com 6399437SAndreas.Sandberg@ARM.com commitStatus[tid] = ROBSquashing; 6409437SAndreas.Sandberg@ARM.com cpu->activityThisCycle(); 6419437SAndreas.Sandberg@ARM.com} 6427784SAli.Saidi@ARM.com 6439437SAndreas.Sandberg@ARM.comtemplate <class Impl> 6449437SAndreas.Sandberg@ARM.comvoid 64513429Srekai.gonzalezalberquilla@arm.comDefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst) 6469437SAndreas.Sandberg@ARM.com{ 64713831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%llu]\n", 6489437SAndreas.Sandberg@ARM.com tid, head_inst->seqNum); 6497784SAli.Saidi@ARM.com 6509437SAndreas.Sandberg@ARM.com assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 6519437SAndreas.Sandberg@ARM.com commitStatus[tid] = SquashAfterPending; 6529437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = head_inst; 6537784SAli.Saidi@ARM.com} 6547784SAli.Saidi@ARM.com 6557784SAli.Saidi@ARM.comtemplate <class Impl> 6567784SAli.Saidi@ARM.comvoid 6572292SN/ADefaultCommit<Impl>::tick() 6582292SN/A{ 6592292SN/A wroteToTimeBuffer = false; 6602292SN/A _nextStatus = Inactive; 6612292SN/A 6623867Sbinkertn@umich.edu if (activeThreads->empty()) 6632875Sksewell@umich.edu return; 6642875Sksewell@umich.edu 6656221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6666221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6672292SN/A 6682316SN/A // Check if any of the threads are done squashing. Change the 6692316SN/A // status if they are done. 6703867Sbinkertn@umich.edu while (threads != end) { 6716221Snate@binkert.org ThreadID tid = *threads++; 6722292SN/A 6734035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6744035Sktlim@umich.edu // this cycle. 6754035Sktlim@umich.edu committedStores[tid] = false; 6764035Sktlim@umich.edu 6772292SN/A if (commitStatus[tid] == ROBSquashing) { 6782292SN/A 6792292SN/A if (rob->isDoneSquashing(tid)) { 6802292SN/A commitStatus[tid] = Running; 6812292SN/A } else { 68213831SAndrea.Mondelli@ucf.edu DPRINTF(Commit,"[tid:%i] Still Squashing, cannot commit any" 6832877Sksewell@umich.edu " insts this cycle.\n", tid); 6842702Sktlim@umich.edu rob->doSquash(tid); 6852702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6862702Sktlim@umich.edu wroteToTimeBuffer = true; 6872292SN/A } 6882292SN/A } 6892292SN/A } 6902292SN/A 6912292SN/A commit(); 6922292SN/A 6932292SN/A markCompletedInsts(); 6942292SN/A 6953867Sbinkertn@umich.edu threads = activeThreads->begin(); 6962292SN/A 6973867Sbinkertn@umich.edu while (threads != end) { 6986221Snate@binkert.org ThreadID tid = *threads++; 6992292SN/A 7002292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 7012292SN/A // The ROB has more instructions it can commit. Its next status 7022292SN/A // will be active. 7032292SN/A _nextStatus = Active; 7042292SN/A 70513429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid); 7062292SN/A 70713831SAndrea.Mondelli@ucf.edu DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of" 7082292SN/A " ROB and ready to commit\n", 7097720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7102292SN/A 7112292SN/A } else if (!rob->isEmpty(tid)) { 71213429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst = rob->readHeadInst(tid); 7132292SN/A 71410023Smatt.horsnell@ARM.com ppCommitStall->notify(inst); 71510023Smatt.horsnell@ARM.com 71613831SAndrea.Mondelli@ucf.edu DPRINTF(Commit,"[tid:%i] Can't commit, Instruction [sn:%llu] PC " 7177720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 7187720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7192292SN/A } 7202292SN/A 72113831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n", 7222292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 7232292SN/A } 7242292SN/A 7252292SN/A 7262292SN/A if (wroteToTimeBuffer) { 7272316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 7282292SN/A cpu->activityThisCycle(); 7292292SN/A } 7302292SN/A 7312292SN/A updateStatus(); 7322292SN/A} 7332292SN/A 7342292SN/Atemplate <class Impl> 7352292SN/Avoid 7364035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 7372292SN/A{ 7387847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7397847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7407847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7417847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7427847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7437847Sminkyu.jeong@arm.com interrupt = NoFault; 7449513SAli.Saidi@ARM.com avoidQuiesceLiveLock = true; 7457847Sminkyu.jeong@arm.com return; 7467847Sminkyu.jeong@arm.com } 7473633Sktlim@umich.edu 7488493Sgblack@eecs.umich.edu // Wait until all in flight instructions are finished before enterring 7498493Sgblack@eecs.umich.edu // the interrupt. 7508823Snilay@cs.wisc.edu if (canHandleInterrupts && cpu->instList.empty()) { 7517847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7527847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7537847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7544035Sktlim@umich.edu 7557847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7567847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7572292SN/A 7589382SAli.Saidi@ARM.com assert(!thread[0]->noSquashFromTC); 7599382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = true; 7602292SN/A 7618733Sgeoffrey.blake@arm.com if (cpu->checker) { 7628733Sgeoffrey.blake@arm.com cpu->checker->handlePendingInt(); 7638733Sgeoffrey.blake@arm.com } 7648733Sgeoffrey.blake@arm.com 7659624Snilay@cs.wisc.edu // CPU will handle interrupt. Note that we ignore the local copy of 7669624Snilay@cs.wisc.edu // interrupt. This is because the local copy may no longer be the 7679624Snilay@cs.wisc.edu // interrupt that the interrupt controller thinks is being handled. 7689624Snilay@cs.wisc.edu cpu->processInterrupts(cpu->getInterrupts()); 7693633Sktlim@umich.edu 7709382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = false; 7712292SN/A 7727847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7732292SN/A 77411877Sbrandon.potter@amd.com interrupt = NoFault; 77511877Sbrandon.potter@amd.com 7767847Sminkyu.jeong@arm.com // Generate trap squash event. 77711877Sbrandon.potter@amd.com generateTrapEvent(0, interrupt); 7783640Sktlim@umich.edu 7799513SAli.Saidi@ARM.com avoidQuiesceLiveLock = false; 7807847Sminkyu.jeong@arm.com } else { 7818823Snilay@cs.wisc.edu DPRINTF(Commit, "Interrupt pending: instruction is %sin " 7828823Snilay@cs.wisc.edu "flight, ROB is %sempty\n", 7838823Snilay@cs.wisc.edu canHandleInterrupts ? "not " : "", 7848823Snilay@cs.wisc.edu cpu->instList.empty() ? "" : "not " ); 7851060SN/A } 7864035Sktlim@umich.edu} 7877847Sminkyu.jeong@arm.com 7887847Sminkyu.jeong@arm.comtemplate <class Impl> 7897847Sminkyu.jeong@arm.comvoid 7907847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 7917847Sminkyu.jeong@arm.com{ 79210340Smitch.hayenga@arm.com // Don't propagate intterupts if we are currently handling a trap or 79310340Smitch.hayenga@arm.com // in draining and the last observable instruction has been committed. 7947847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 79510340Smitch.hayenga@arm.com tcSquash[0] || drainImminent) 7967847Sminkyu.jeong@arm.com return; 7977847Sminkyu.jeong@arm.com 7987847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 7997847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 8007847Sminkyu.jeong@arm.com // pending. 8017847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 8027847Sminkyu.jeong@arm.com 8037847Sminkyu.jeong@arm.com // Get any interrupt that happened 8047847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 8057847Sminkyu.jeong@arm.com 8067847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 8077847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 8087847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 8097847Sminkyu.jeong@arm.com if (interrupt != NoFault) 8107847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 8117847Sminkyu.jeong@arm.com} 8127847Sminkyu.jeong@arm.com 8134035Sktlim@umich.edutemplate <class Impl> 8144035Sktlim@umich.eduvoid 8154035Sktlim@umich.eduDefaultCommit<Impl>::commit() 8164035Sktlim@umich.edu{ 8178793Sgblack@eecs.umich.edu if (FullSystem) { 8188793Sgblack@eecs.umich.edu // Check if we have a interrupt and get read to handle it 8198793Sgblack@eecs.umich.edu if (cpu->checkInterrupts(cpu->tcBase(0))) 8208793Sgblack@eecs.umich.edu propagateInterrupt(); 8218793Sgblack@eecs.umich.edu } 8221060SN/A 8231060SN/A //////////////////////////////////// 8242316SN/A // Check for any possible squashes, handle them first 8251060SN/A //////////////////////////////////// 8266221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8276221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8281060SN/A 82910729Snilay@cs.wisc.edu int num_squashing_threads = 0; 83010729Snilay@cs.wisc.edu 8313867Sbinkertn@umich.edu while (threads != end) { 8326221Snate@binkert.org ThreadID tid = *threads++; 8331060SN/A 8342292SN/A // Not sure which one takes priority. I think if we have 8352292SN/A // both, that's a bad sign. 83610231Ssteve.reinhardt@amd.com if (trapSquash[tid]) { 8372680Sktlim@umich.edu assert(!tcSquash[tid]); 8382292SN/A squashFromTrap(tid); 83913641Sqtt2@cornell.edu 84013641Sqtt2@cornell.edu // If the thread is trying to exit (i.e., an exit syscall was 84113641Sqtt2@cornell.edu // executed), this trapSquash was originated by the exit 84213641Sqtt2@cornell.edu // syscall earlier. In this case, schedule an exit event in 84313641Sqtt2@cornell.edu // the next cycle to fully terminate this thread 84413641Sqtt2@cornell.edu if (cpu->isThreadExiting(tid)) 84513641Sqtt2@cornell.edu cpu->scheduleThreadExitEvent(tid); 84610231Ssteve.reinhardt@amd.com } else if (tcSquash[tid]) { 8474035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 8482680Sktlim@umich.edu squashFromTC(tid); 8499437SAndreas.Sandberg@ARM.com } else if (commitStatus[tid] == SquashAfterPending) { 8509437SAndreas.Sandberg@ARM.com // A squash from the previous cycle of the commit stage (i.e., 8519437SAndreas.Sandberg@ARM.com // commitInsts() called squashAfter) is pending. Squash the 8529437SAndreas.Sandberg@ARM.com // thread now. 8539437SAndreas.Sandberg@ARM.com squashFromSquashAfter(tid); 8542292SN/A } 8551061SN/A 8562292SN/A // Squashed sequence number must be older than youngest valid 8572292SN/A // instruction in the ROB. This prevents squashes from younger 8582292SN/A // instructions overriding squashes from older instructions. 8592292SN/A if (fromIEW->squash[tid] && 8602292SN/A commitStatus[tid] != TrapPending && 8612292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8621061SN/A 8638137SAli.Saidi@ARM.com if (fromIEW->mispredictInst[tid]) { 8648137SAli.Saidi@ARM.com DPRINTF(Commit, 86513831SAndrea.Mondelli@ucf.edu "[tid:%i] Squashing due to branch mispred " 86613831SAndrea.Mondelli@ucf.edu "PC:%#x [sn:%llu]\n", 8672292SN/A tid, 8688137SAli.Saidi@ARM.com fromIEW->mispredictInst[tid]->instAddr(), 8692292SN/A fromIEW->squashedSeqNum[tid]); 8708137SAli.Saidi@ARM.com } else { 8718137SAli.Saidi@ARM.com DPRINTF(Commit, 87213831SAndrea.Mondelli@ucf.edu "[tid:%i] Squashing due to order violation [sn:%llu]\n", 8738137SAli.Saidi@ARM.com tid, fromIEW->squashedSeqNum[tid]); 8748137SAli.Saidi@ARM.com } 8751061SN/A 87613831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, "[tid:%i] Redirecting to PC %#x\n", 8772292SN/A tid, 8787720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8791061SN/A 8802292SN/A commitStatus[tid] = ROBSquashing; 8811061SN/A 8822292SN/A // If we want to include the squashing instruction in the squash, 8832292SN/A // then use one older sequence number. 8842292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8851062SN/A 88610231Ssteve.reinhardt@amd.com if (fromIEW->includeSquashInst[tid]) { 8872292SN/A squashed_inst--; 8882935Sksewell@umich.edu } 8894035Sktlim@umich.edu 8902292SN/A // All younger instructions will be squashed. Set the sequence 8912292SN/A // number as the youngest instruction in the ROB. 8922292SN/A youngestSeqNum[tid] = squashed_inst; 8932292SN/A 8943093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8952292SN/A changedROBNumEntries[tid] = true; 8962292SN/A 8972292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8982292SN/A 8992292SN/A toIEW->commitInfo[tid].squash = true; 9002292SN/A 9012292SN/A // Send back the rob squashing signal so other stages know that 9022292SN/A // the ROB is in the process of squashing. 9032292SN/A toIEW->commitInfo[tid].robSquashing = true; 9042292SN/A 9057851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 9067851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 9072292SN/A toIEW->commitInfo[tid].branchTaken = 9082292SN/A fromIEW->branchTaken[tid]; 9098822Snilay@cs.wisc.edu toIEW->commitInfo[tid].squashInst = 9108822Snilay@cs.wisc.edu rob->findInst(tid, squashed_inst); 9118842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst) { 9128842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 9138842Smrinmoy.ghosh@arm.com toIEW->commitInfo[tid].branchTaken = true; 9148842Smrinmoy.ghosh@arm.com } 91510730Snilay@cs.wisc.edu ++branchMispredicts; 9168842Smrinmoy.ghosh@arm.com } 9172292SN/A 9187720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 9191062SN/A } 9202292SN/A 92110729Snilay@cs.wisc.edu if (commitStatus[tid] == ROBSquashing) { 92210729Snilay@cs.wisc.edu num_squashing_threads++; 92310729Snilay@cs.wisc.edu } 9241060SN/A } 9251060SN/A 92610729Snilay@cs.wisc.edu // If commit is currently squashing, then it will have activity for the 92710729Snilay@cs.wisc.edu // next cycle. Set its next status as active. 92810729Snilay@cs.wisc.edu if (num_squashing_threads) { 92910729Snilay@cs.wisc.edu _nextStatus = Active; 93010729Snilay@cs.wisc.edu } 9312292SN/A 93210729Snilay@cs.wisc.edu if (num_squashing_threads != numThreads) { 9331061SN/A // If we're not currently squashing, then get instructions. 9341060SN/A getInsts(); 9351060SN/A 9361061SN/A // Try to commit any instructions. 9371060SN/A commitInsts(); 9381060SN/A } 9391060SN/A 9402292SN/A //Check for any activity 9413867Sbinkertn@umich.edu threads = activeThreads->begin(); 9422292SN/A 9433867Sbinkertn@umich.edu while (threads != end) { 9446221Snate@binkert.org ThreadID tid = *threads++; 9452292SN/A 9462292SN/A if (changedROBNumEntries[tid]) { 9472292SN/A toIEW->commitInfo[tid].usedROB = true; 9482292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9492292SN/A 9502292SN/A wroteToTimeBuffer = true; 9512292SN/A changedROBNumEntries[tid] = false; 9524035Sktlim@umich.edu if (rob->isEmpty(tid)) 9534035Sktlim@umich.edu checkEmptyROB[tid] = true; 9542292SN/A } 9554035Sktlim@umich.edu 9564035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 9574035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 9584035Sktlim@umich.edu // stage has received any information regarding stores that 9594035Sktlim@umich.edu // committed. 9604035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 9614035Sktlim@umich.edu // on the same cycle as when stores have been committed. 9624035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 9634035Sktlim@umich.edu // commit and IEW. 9644035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9655557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9664035Sktlim@umich.edu checkEmptyROB[tid] = false; 9674035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 9684035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 9694035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9704035Sktlim@umich.edu wroteToTimeBuffer = true; 9714035Sktlim@umich.edu } 9724035Sktlim@umich.edu 9731060SN/A } 9741060SN/A} 9751060SN/A 9761061SN/Atemplate <class Impl> 9771060SN/Avoid 9782292SN/ADefaultCommit<Impl>::commitInsts() 9791060SN/A{ 9801060SN/A //////////////////////////////////// 9811060SN/A // Handle commit 9822316SN/A // Note that commit will be handled prior to putting new 9832316SN/A // instructions in the ROB so that the ROB only tries to commit 9842316SN/A // instructions it has in this current cycle, and not instructions 9852316SN/A // it is writing in during this cycle. Can't commit and squash 9862316SN/A // things at the same time... 9871060SN/A //////////////////////////////////// 9881060SN/A 9892292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9901060SN/A 9911060SN/A unsigned num_committed = 0; 9921060SN/A 9932292SN/A DynInstPtr head_inst; 9942316SN/A 9951060SN/A // Commit as many instructions as possible until the commit bandwidth 9961060SN/A // limit is reached, or it becomes impossible to commit any more. 9972292SN/A while (num_committed < commitWidth) { 9988823Snilay@cs.wisc.edu // Check for any interrupt that we've already squashed for 9998823Snilay@cs.wisc.edu // and start processing it. 10008823Snilay@cs.wisc.edu if (interrupt != NoFault) 10018823Snilay@cs.wisc.edu handleInterrupt(); 10028823Snilay@cs.wisc.edu 100310731Snilay@cs.wisc.edu ThreadID commit_thread = getCommittingThread(); 10041060SN/A 10052292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 10062292SN/A break; 10072292SN/A 10082292SN/A head_inst = rob->readHeadInst(commit_thread); 10092292SN/A 10106221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 10112292SN/A 10122292SN/A assert(tid == commit_thread); 10132292SN/A 101413831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, 101513831SAndrea.Mondelli@ucf.edu "Trying to commit head instruction, [tid:%i] [sn:%llu]\n", 101613831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum); 10172132SN/A 10182316SN/A // If the head instruction is squashed, it is ready to retire 10192316SN/A // (be removed from the ROB) at any time. 10201060SN/A if (head_inst->isSquashed()) { 10211060SN/A 10222292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 10231060SN/A "ROB.\n"); 10241060SN/A 10252292SN/A rob->retireHead(commit_thread); 10261060SN/A 10271062SN/A ++commitSquashedInsts; 102811246Sradhika.jagtap@ARM.com // Notify potential listeners that this instruction is squashed 102911246Sradhika.jagtap@ARM.com ppSquash->notify(head_inst); 10301062SN/A 10312292SN/A // Record that the number of ROB entries has changed. 10322292SN/A changedROBNumEntries[tid] = true; 10331060SN/A } else { 10347720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 10352292SN/A 10361060SN/A // Increment the total number of non-speculative instructions 10371060SN/A // executed. 10381060SN/A // Hack for now: it really shouldn't happen until after the 10391061SN/A // commit is deemed to be successful, but this count is needed 10401061SN/A // for syscalls. 10412292SN/A thread[tid]->funcExeInst++; 10421060SN/A 10431060SN/A // Try to commit the head instruction. 10441060SN/A bool commit_success = commitHead(head_inst, num_committed); 10451060SN/A 10461062SN/A if (commit_success) { 10471060SN/A ++num_committed; 104810193SCurtis.Dunham@arm.com statCommittedInstType[tid][head_inst->opClass()]++; 104910023Smatt.horsnell@ARM.com ppCommit->notify(head_inst); 10501060SN/A 10512292SN/A changedROBNumEntries[tid] = true; 10522292SN/A 10532292SN/A // Set the doneSeqNum to the youngest committed instruction. 10542292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 10551060SN/A 10568823Snilay@cs.wisc.edu if (tid == 0) { 10578823Snilay@cs.wisc.edu canHandleInterrupts = (!head_inst->isDelayedCommit()) && 10588823Snilay@cs.wisc.edu ((THE_ISA != ALPHA_ISA) || 10598823Snilay@cs.wisc.edu (!(pc[0].instAddr() & 0x3))); 10608823Snilay@cs.wisc.edu } 10618823Snilay@cs.wisc.edu 106212216Snikos.nikoleris@arm.com // at this point store conditionals should either have 106312216Snikos.nikoleris@arm.com // been completed or predicated false 106412216Snikos.nikoleris@arm.com assert(!head_inst->isStoreConditional() || 106512216Snikos.nikoleris@arm.com head_inst->isCompleted() || 106612216Snikos.nikoleris@arm.com !head_inst->readPredicate()); 106712216Snikos.nikoleris@arm.com 10687783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 10697783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 10707783SGiacomo.Gabrielli@arm.com 107110034SGeoffrey.Blake@arm.com // Check instruction execution if it successfully commits and 107210034SGeoffrey.Blake@arm.com // is not carrying a fault. 107310034SGeoffrey.Blake@arm.com if (cpu->checker) { 107410034SGeoffrey.Blake@arm.com cpu->checker->verify(head_inst); 107510034SGeoffrey.Blake@arm.com } 107610034SGeoffrey.Blake@arm.com 10778662SAli.Saidi@ARM.com cpu->traceFunctions(pc[tid].instAddr()); 10788662SAli.Saidi@ARM.com 10797720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 10802935Sksewell@umich.edu 10817855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 10827855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 10837855SAli.Saidi@ARM.com 10847784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 10857784SAli.Saidi@ARM.com // others squash everything and restart fetch 10867784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 10879437SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10887784SAli.Saidi@ARM.com 10899444SAndreas.Sandberg@ARM.com if (drainPending) { 109010340Smitch.hayenga@arm.com if (pc[tid].microPC() == 0 && interrupt == NoFault && 109110340Smitch.hayenga@arm.com !thread[tid]->trapPending) { 109210340Smitch.hayenga@arm.com // Last architectually committed instruction. 109310340Smitch.hayenga@arm.com // Squash the pipeline, stall fetch, and use 109410340Smitch.hayenga@arm.com // drainImminent to disable interrupts 109510340Smitch.hayenga@arm.com DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 10969444SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10979444SAndreas.Sandberg@ARM.com cpu->commitDrained(tid); 109810340Smitch.hayenga@arm.com drainImminent = true; 10999444SAndreas.Sandberg@ARM.com } 11009444SAndreas.Sandberg@ARM.com } 11019444SAndreas.Sandberg@ARM.com 110210596Sgabeblack@google.com bool onInstBoundary = !head_inst->isMicroop() || 110310596Sgabeblack@google.com head_inst->isLastMicroop() || 110410596Sgabeblack@google.com !head_inst->isDelayedCommit(); 110510596Sgabeblack@google.com 110610596Sgabeblack@google.com if (onInstBoundary) { 110710596Sgabeblack@google.com int count = 0; 110810596Sgabeblack@google.com Addr oldpc; 110910596Sgabeblack@google.com // Make sure we're not currently updating state while 111010596Sgabeblack@google.com // handling PC events. 111110596Sgabeblack@google.com assert(!thread[tid]->noSquashFromTC && 111210596Sgabeblack@google.com !thread[tid]->trapPending); 111310596Sgabeblack@google.com do { 111410596Sgabeblack@google.com oldpc = pc[tid].instAddr(); 111510596Sgabeblack@google.com cpu->system->pcEventQueue.service(thread[tid]->getTC()); 111610596Sgabeblack@google.com count++; 111710596Sgabeblack@google.com } while (oldpc != pc[tid].instAddr()); 111810596Sgabeblack@google.com if (count > 1) { 111910596Sgabeblack@google.com DPRINTF(Commit, 112010596Sgabeblack@google.com "PC skip function event, stopping commit\n"); 112110596Sgabeblack@google.com break; 112210596Sgabeblack@google.com } 11232292SN/A } 11249513SAli.Saidi@ARM.com 11259513SAli.Saidi@ARM.com // Check if an instruction just enabled interrupts and we've 11269513SAli.Saidi@ARM.com // previously had an interrupt pending that was not handled 11279513SAli.Saidi@ARM.com // because interrupts were subsequently disabled before the 11289513SAli.Saidi@ARM.com // pipeline reached a place to handle the interrupt. In that 11299513SAli.Saidi@ARM.com // case squash now to make sure the interrupt is handled. 11309513SAli.Saidi@ARM.com // 11319513SAli.Saidi@ARM.com // If we don't do this, we might end up in a live lock situation 113210596Sgabeblack@google.com if (!interrupt && avoidQuiesceLiveLock && 113310596Sgabeblack@google.com onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0))) 11349513SAli.Saidi@ARM.com squashAfter(tid, head_inst); 11351060SN/A } else { 11367720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 113713831SAndrea.Mondelli@ucf.edu "[tid:%i] [sn:%llu].\n", 11387720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 11391060SN/A break; 11401060SN/A } 11411060SN/A } 11421060SN/A } 11431062SN/A 11441063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 11452292SN/A numCommittedDist.sample(num_committed); 11462307SN/A 11472307SN/A if (num_committed == commitWidth) { 11482349SN/A commitEligibleSamples++; 11492307SN/A } 11501060SN/A} 11511060SN/A 11521061SN/Atemplate <class Impl> 11531060SN/Abool 115413429Srekai.gonzalezalberquilla@arm.comDefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) 11551060SN/A{ 11561060SN/A assert(head_inst); 11571060SN/A 11586221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 11592292SN/A 11602316SN/A // If the instruction is not executed yet, then it will need extra 11612316SN/A // handling. Signal backwards that it should be executed. 11621061SN/A if (!head_inst->isExecuted()) { 11631061SN/A // Keep this number correct. We have not yet actually executed 11641061SN/A // and committed this instruction. 11652292SN/A thread[tid]->funcExeInst--; 11661062SN/A 11679948SAli.Saidi@ARM.com // Make sure we are only trying to commit un-executed instructions we 11689948SAli.Saidi@ARM.com // think are possible. 11699948SAli.Saidi@ARM.com assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 117013652Sqtt2@cornell.edu || head_inst->isMemBarrier() || head_inst->isWriteBarrier() 117113652Sqtt2@cornell.edu || head_inst->isAtomic() 117213652Sqtt2@cornell.edu || (head_inst->isLoad() && head_inst->strictlyOrdered())); 11732316SN/A 117413831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, 117513831SAndrea.Mondelli@ucf.edu "Encountered a barrier or non-speculative " 117613831SAndrea.Mondelli@ucf.edu "instruction [tid:%i] [sn:%llu] " 117713831SAndrea.Mondelli@ucf.edu "at the head of the ROB, PC %s.\n", 117813831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum, head_inst->pcState()); 11792316SN/A 11809948SAli.Saidi@ARM.com if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 118113831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, 118213831SAndrea.Mondelli@ucf.edu "[tid:%i] [sn:%llu] " 118313831SAndrea.Mondelli@ucf.edu "Waiting for all stores to writeback.\n", 118413831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum); 11859948SAli.Saidi@ARM.com return false; 11869948SAli.Saidi@ARM.com } 11872292SN/A 11889948SAli.Saidi@ARM.com toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 11891061SN/A 11909948SAli.Saidi@ARM.com // Change the instruction so it won't try to commit again until 11919948SAli.Saidi@ARM.com // it is executed. 11929948SAli.Saidi@ARM.com head_inst->clearCanCommit(); 11931061SN/A 119410824SAndreas.Sandberg@ARM.com if (head_inst->isLoad() && head_inst->strictlyOrdered()) { 119513831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, "[tid:%i] [sn:%llu] " 119613831SAndrea.Mondelli@ucf.edu "Strictly ordered load, PC %s.\n", 119713831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum, head_inst->pcState()); 119810824SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].strictlyOrdered = true; 119910824SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst; 12009948SAli.Saidi@ARM.com } else { 12019948SAli.Saidi@ARM.com ++commitNonSpecStalls; 12029948SAli.Saidi@ARM.com } 12032292SN/A 12049948SAli.Saidi@ARM.com return false; 12051060SN/A } 12061060SN/A 12072316SN/A if (head_inst->isThreadSync()) { 12082292SN/A // Not handled for now. 12092316SN/A panic("Thread sync instructions are not handled yet.\n"); 12102132SN/A } 12112132SN/A 12124035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 12134035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 12144035Sktlim@umich.edu 12152316SN/A // Stores mark themselves as completed. 12164035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 12172310SN/A head_inst->setCompleted(); 12182310SN/A } 12192310SN/A 12202112SN/A if (inst_fault != NoFault) { 122113831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, "Inst [tid:%i] [sn:%llu] PC %s has a fault\n", 122213831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum, head_inst->pcState()); 12232292SN/A 12245557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 122513831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, 122613831SAndrea.Mondelli@ucf.edu "[tid:%i] [sn:%llu] " 122713831SAndrea.Mondelli@ucf.edu "Stores outstanding, fault must wait.\n", 122813831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum); 12292316SN/A return false; 12302316SN/A } 12312310SN/A 12324035Sktlim@umich.edu head_inst->setCompleted(); 12334035Sktlim@umich.edu 123410034SGeoffrey.Blake@arm.com // If instruction has faulted, let the checker execute it and 123510034SGeoffrey.Blake@arm.com // check if it sees the same fault and control flow. 12368733Sgeoffrey.blake@arm.com if (cpu->checker) { 12378733Sgeoffrey.blake@arm.com // Need to check the instruction before its fault is processed 12382732Sktlim@umich.edu cpu->checker->verify(head_inst); 12392316SN/A } 12402292SN/A 12419382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC); 12422292SN/A 12432316SN/A // Mark that we're in state update mode so that the trap's 12442316SN/A // execution doesn't generate extra squashes. 12459382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 12462292SN/A 12472316SN/A // Execute the trap. Although it's slightly unrealistic in 12482316SN/A // terms of timing (as it doesn't wait for the full timing of 12492316SN/A // the trap event to complete before updating state), it's 12502316SN/A // needed to update the state as soon as possible. This 12512316SN/A // prevents external agents from changing any specific state 12522316SN/A // that the trap need. 125312422Sgabeblack@google.com cpu->trap(inst_fault, tid, 125412422Sgabeblack@google.com head_inst->notAnInst() ? 125512422Sgabeblack@google.com StaticInst::nullStaticInstPtr : 125612422Sgabeblack@google.com head_inst->staticInst); 12572292SN/A 12582316SN/A // Exit state update mode to avoid accidental updating. 12599382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 12602292SN/A 12612316SN/A commitStatus[tid] = TrapPending; 12622292SN/A 126313831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, 126413831SAndrea.Mondelli@ucf.edu "[tid:%i] [sn:%llu] Committing instruction with fault\n", 126513831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum); 12664035Sktlim@umich.edu if (head_inst->traceData) { 12676667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 12686667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 12698834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12706667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 12716667Ssteve.reinhardt@amd.com } 12724288Sktlim@umich.edu delete head_inst->traceData; 12734035Sktlim@umich.edu head_inst->traceData = NULL; 12744035Sktlim@umich.edu } 12754035Sktlim@umich.edu 12762316SN/A // Generate trap squash event. 127711877Sbrandon.potter@amd.com generateTrapEvent(tid, inst_fault); 12782316SN/A return false; 12791060SN/A } 12801060SN/A 12812301SN/A updateComInstStats(head_inst); 12822132SN/A 12838793Sgblack@eecs.umich.edu if (FullSystem) { 12848793Sgblack@eecs.umich.edu if (thread[tid]->profile) { 12858793Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 12868793Sgblack@eecs.umich.edu ProfileNode *node = thread[tid]->profile->consume( 12878793Sgblack@eecs.umich.edu thread[tid]->getTC(), head_inst->staticInst); 12882362SN/A 12898793Sgblack@eecs.umich.edu if (node) 12908793Sgblack@eecs.umich.edu thread[tid]->profileNode = node; 12918793Sgblack@eecs.umich.edu } 12928793Sgblack@eecs.umich.edu if (CPA::available()) { 12938793Sgblack@eecs.umich.edu if (head_inst->isControl()) { 12948793Sgblack@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 12958793Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 12968793Sgblack@eecs.umich.edu } 12975953Ssaidi@eecs.umich.edu } 12985953Ssaidi@eecs.umich.edu } 129913831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, 130013831SAndrea.Mondelli@ucf.edu "[tid:%i] [sn:%llu] Committing instruction with PC %s\n", 130113831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum, head_inst->pcState()); 13022132SN/A if (head_inst->traceData) { 13032292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 13048834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 13054046Sbinkertn@umich.edu head_inst->traceData->dump(); 13064046Sbinkertn@umich.edu delete head_inst->traceData; 13072292SN/A head_inst->traceData = NULL; 13081060SN/A } 13098843Smrinmoy.ghosh@arm.com if (head_inst->isReturn()) { 131013831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, 131113831SAndrea.Mondelli@ucf.edu "[tid:%i] [sn:%llu] Return Instruction Committed PC %s \n", 131213831SAndrea.Mondelli@ucf.edu tid, head_inst->seqNum, head_inst->pcState()); 13138843Smrinmoy.ghosh@arm.com } 13141060SN/A 13152292SN/A // Update the commit rename map 13162292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 13173771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 13182292SN/A head_inst->renamedDestRegIdx(i)); 13191060SN/A } 13201062SN/A 13212292SN/A // Finally clear the head ROB entry. 13222292SN/A rob->retireHead(tid); 13231060SN/A 13248471SGiacomo.Gabrielli@arm.com#if TRACING_ON 13259527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 13269527SMatt.Horsnell@arm.com head_inst->commitTick = curTick() - head_inst->fetchTick; 13279527SMatt.Horsnell@arm.com } 13288471SGiacomo.Gabrielli@arm.com#endif 13298471SGiacomo.Gabrielli@arm.com 13304035Sktlim@umich.edu // If this was a store, record it for this cycle. 133113652Sqtt2@cornell.edu if (head_inst->isStore() || head_inst->isAtomic()) 13324035Sktlim@umich.edu committedStores[tid] = true; 13334035Sktlim@umich.edu 13341060SN/A // Return true to indicate that we have committed an instruction. 13351060SN/A return true; 13361060SN/A} 13371060SN/A 13381061SN/Atemplate <class Impl> 13391060SN/Avoid 13402292SN/ADefaultCommit<Impl>::getInsts() 13411060SN/A{ 13422935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 13432935Sksewell@umich.edu 13443093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 13453093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 13462965Sksewell@umich.edu 13472965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 134813429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst = fromRename->insts[inst_num]; 13496221Snate@binkert.org ThreadID tid = inst->threadNumber; 13502292SN/A 13512292SN/A if (!inst->isSquashed() && 13524035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 13534035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 13542292SN/A changedROBNumEntries[tid] = true; 13552292SN/A 135613831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, "[tid:%i] [sn:%llu] Inserting PC %s into ROB.\n", 135713831SAndrea.Mondelli@ucf.edu inst->seqNum, tid, inst->pcState()); 13582292SN/A 13592292SN/A rob->insertInst(inst); 13602292SN/A 13612292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 13622292SN/A 13632292SN/A youngestSeqNum[tid] = inst->seqNum; 13641061SN/A } else { 136513831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, "[tid:%i] [sn:%llu] " 136613831SAndrea.Mondelli@ucf.edu "Instruction PC %s was squashed, skipping.\n", 136713831SAndrea.Mondelli@ucf.edu inst->seqNum, tid, inst->pcState()); 13681061SN/A } 13691060SN/A } 13702965Sksewell@umich.edu} 13712965Sksewell@umich.edu 13722965Sksewell@umich.edutemplate <class Impl> 13732965Sksewell@umich.eduvoid 13742292SN/ADefaultCommit<Impl>::markCompletedInsts() 13751060SN/A{ 13761060SN/A // Grab completed insts out of the IEW instruction queue, and mark 13771060SN/A // instructions completed within the ROB. 137810734Snilay@cs.wisc.edu for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) { 137910734Snilay@cs.wisc.edu assert(fromIEW->insts[inst_num]); 13802292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 138113831SAndrea.Mondelli@ucf.edu DPRINTF(Commit, "[tid:%i] Marking PC %s, [sn:%llu] ready " 13822316SN/A "within ROB.\n", 13832292SN/A fromIEW->insts[inst_num]->threadNumber, 13847720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 13852292SN/A fromIEW->insts[inst_num]->seqNum); 13861060SN/A 13872292SN/A // Mark the instruction as ready to commit. 13882292SN/A fromIEW->insts[inst_num]->setCanCommit(); 13892292SN/A } 13901060SN/A } 13911060SN/A} 13921060SN/A 13931061SN/Atemplate <class Impl> 13942301SN/Avoid 139513429Srekai.gonzalezalberquilla@arm.comDefaultCommit<Impl>::updateComInstStats(const DynInstPtr &inst) 13962301SN/A{ 13976221Snate@binkert.org ThreadID tid = inst->threadNumber; 13982301SN/A 13998834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) 14008834Satgutier@umich.edu instsCommitted[tid]++; 14018834Satgutier@umich.edu opsCommitted[tid]++; 14022301SN/A 14039218Satgutier@umich.edu // To match the old model, don't count nops and instruction 14049218Satgutier@umich.edu // prefetches towards the total commit count. 14059218Satgutier@umich.edu if (!inst->isNop() && !inst->isInstPrefetch()) { 14069218Satgutier@umich.edu cpu->instDone(tid, inst); 14079218Satgutier@umich.edu } 14089218Satgutier@umich.edu 14092301SN/A // 14102301SN/A // Control Instructions 14112301SN/A // 14122301SN/A if (inst->isControl()) 14136221Snate@binkert.org statComBranches[tid]++; 14142301SN/A 14152301SN/A // 14162301SN/A // Memory references 14172301SN/A // 14182301SN/A if (inst->isMemRef()) { 14196221Snate@binkert.org statComRefs[tid]++; 14202301SN/A 14212301SN/A if (inst->isLoad()) { 14226221Snate@binkert.org statComLoads[tid]++; 14232301SN/A } 142413652Sqtt2@cornell.edu 142513652Sqtt2@cornell.edu if (inst->isAtomic()) { 142613652Sqtt2@cornell.edu statComAmos[tid]++; 142713652Sqtt2@cornell.edu } 14282301SN/A } 14292301SN/A 14302301SN/A if (inst->isMemBarrier()) { 14316221Snate@binkert.org statComMembars[tid]++; 14322301SN/A } 14337897Shestness@cs.utexas.edu 14347897Shestness@cs.utexas.edu // Integer Instruction 14357897Shestness@cs.utexas.edu if (inst->isInteger()) 14367897Shestness@cs.utexas.edu statComInteger[tid]++; 14377897Shestness@cs.utexas.edu 14387897Shestness@cs.utexas.edu // Floating Point Instruction 14397897Shestness@cs.utexas.edu if (inst->isFloating()) 14407897Shestness@cs.utexas.edu statComFloating[tid]++; 144112110SRekai.GonzalezAlberquilla@arm.com // Vector Instruction 144212110SRekai.GonzalezAlberquilla@arm.com if (inst->isVector()) 144312110SRekai.GonzalezAlberquilla@arm.com statComVector[tid]++; 14447897Shestness@cs.utexas.edu 14457897Shestness@cs.utexas.edu // Function Calls 14467897Shestness@cs.utexas.edu if (inst->isCall()) 14477897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 14487897Shestness@cs.utexas.edu 14492301SN/A} 14502301SN/A 14512292SN/A//////////////////////////////////////// 14522292SN/A// // 14532316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 14542292SN/A// // 14552292SN/A//////////////////////////////////////// 14562292SN/Atemplate <class Impl> 14576221Snate@binkert.orgThreadID 14582292SN/ADefaultCommit<Impl>::getCommittingThread() 14592292SN/A{ 14602292SN/A if (numThreads > 1) { 14612292SN/A switch (commitPolicy) { 14622292SN/A 146313563Snikos.nikoleris@arm.com case CommitPolicy::Aggressive: 14642292SN/A //If Policy is Aggressive, commit will call 14652292SN/A //this function multiple times per 14662292SN/A //cycle 14672292SN/A return oldestReady(); 14682292SN/A 146913563Snikos.nikoleris@arm.com case CommitPolicy::RoundRobin: 14702292SN/A return roundRobin(); 14712292SN/A 147213563Snikos.nikoleris@arm.com case CommitPolicy::OldestReady: 14732292SN/A return oldestReady(); 14742292SN/A 14752292SN/A default: 14766221Snate@binkert.org return InvalidThreadID; 14772292SN/A } 14782292SN/A } else { 14793867Sbinkertn@umich.edu assert(!activeThreads->empty()); 14806221Snate@binkert.org ThreadID tid = activeThreads->front(); 14812292SN/A 14822292SN/A if (commitStatus[tid] == Running || 14832292SN/A commitStatus[tid] == Idle || 14842292SN/A commitStatus[tid] == FetchTrapPending) { 14852292SN/A return tid; 14862292SN/A } else { 14876221Snate@binkert.org return InvalidThreadID; 14882292SN/A } 14892292SN/A } 14902292SN/A} 14912292SN/A 14922292SN/Atemplate<class Impl> 14936221Snate@binkert.orgThreadID 14942292SN/ADefaultCommit<Impl>::roundRobin() 14952292SN/A{ 14966221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14976221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14982292SN/A 14992292SN/A while (pri_iter != end) { 15006221Snate@binkert.org ThreadID tid = *pri_iter; 15012292SN/A 15022292SN/A if (commitStatus[tid] == Running || 15032831Sksewell@umich.edu commitStatus[tid] == Idle || 15042831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 15052292SN/A 15062292SN/A if (rob->isHeadReady(tid)) { 15072292SN/A priority_list.erase(pri_iter); 15082292SN/A priority_list.push_back(tid); 15092292SN/A 15102292SN/A return tid; 15112292SN/A } 15122292SN/A } 15132292SN/A 15142292SN/A pri_iter++; 15152292SN/A } 15162292SN/A 15176221Snate@binkert.org return InvalidThreadID; 15182292SN/A} 15192292SN/A 15202292SN/Atemplate<class Impl> 15216221Snate@binkert.orgThreadID 15222292SN/ADefaultCommit<Impl>::oldestReady() 15232292SN/A{ 15242292SN/A unsigned oldest = 0; 15252292SN/A bool first = true; 15262292SN/A 15276221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15286221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15292292SN/A 15303867Sbinkertn@umich.edu while (threads != end) { 15316221Snate@binkert.org ThreadID tid = *threads++; 15322292SN/A 15332292SN/A if (!rob->isEmpty(tid) && 15342292SN/A (commitStatus[tid] == Running || 15352292SN/A commitStatus[tid] == Idle || 15362292SN/A commitStatus[tid] == FetchTrapPending)) { 15372292SN/A 15382292SN/A if (rob->isHeadReady(tid)) { 15392292SN/A 154013429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &head_inst = rob->readHeadInst(tid); 15412292SN/A 15422292SN/A if (first) { 15432292SN/A oldest = tid; 15442292SN/A first = false; 15452292SN/A } else if (head_inst->seqNum < oldest) { 15462292SN/A oldest = tid; 15472292SN/A } 15482292SN/A } 15492292SN/A } 15502292SN/A } 15512292SN/A 15522292SN/A if (!first) { 15532292SN/A return oldest; 15542292SN/A } else { 15556221Snate@binkert.org return InvalidThreadID; 15562292SN/A } 15572292SN/A} 15589944Smatt.horsnell@ARM.com 15599944Smatt.horsnell@ARM.com#endif//__CPU_O3_COMMIT_IMPL_HH__ 1560