commit_impl.hh revision 13641
11689SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 312216Snikos.nikoleris@arm.com * Copyright (c) 2010-2014, 2017 ARM Limited 47783SGiacomo.Gabrielli@arm.com * All rights reserved 57783SGiacomo.Gabrielli@arm.com * 67783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147783SGiacomo.Gabrielli@arm.com * 152316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422965Sksewell@umich.edu * Korey Sewell 431689SN/A */ 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_COMMIT_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_COMMIT_IMPL_HH__ 461689SN/A 472292SN/A#include <algorithm> 489516SAli.Saidi@ARM.com#include <set> 492329SN/A#include <string> 502292SN/A 513577Sgblack@eecs.umich.edu#include "arch/utility.hh" 5213449Sgabeblack@google.com#include "base/cp_annotate.hh" 538229Snate@binkert.org#include "base/loader/symtab.hh" 5413449Sgabeblack@google.com#include "base/logging.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 571717SN/A#include "cpu/o3/commit.hh" 582292SN/A#include "cpu/o3/thread_state.hh" 598662SAli.Saidi@ARM.com#include "cpu/base.hh" 608229Snate@binkert.org#include "cpu/exetrace.hh" 618229Snate@binkert.org#include "cpu/timebuf.hh" 628232Snate@binkert.org#include "debug/Activity.hh" 638232Snate@binkert.org#include "debug/Commit.hh" 648232Snate@binkert.org#include "debug/CommitRate.hh" 659444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 668232Snate@binkert.org#include "debug/ExecFaulting.hh" 679527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 686221Snate@binkert.org#include "params/DerivO3CPU.hh" 698230Snate@binkert.org#include "sim/faults.hh" 708793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 712292SN/A 726221Snate@binkert.orgusing namespace std; 735529Snate@binkert.org 741061SN/Atemplate <class Impl> 751060SN/Avoid 7612127Sspwilson2@wisc.eduDefaultCommit<Impl>::processTrapEvent(ThreadID tid) 771062SN/A{ 782316SN/A // This will get reset by commit if it was switched out at the 792316SN/A // time of this event processing. 8012127Sspwilson2@wisc.edu trapSquash[tid] = true; 812292SN/A} 822292SN/A 832292SN/Atemplate <class Impl> 845529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 8513563Snikos.nikoleris@arm.com : commitPolicy(params->smtCommitPolicy), 8613563Snikos.nikoleris@arm.com cpu(_cpu), 872292SN/A iewToCommitDelay(params->iewToCommitDelay), 882292SN/A commitToIEWDelay(params->commitToIEWDelay), 892292SN/A renameToROBDelay(params->renameToROBDelay), 902292SN/A fetchToCommitDelay(params->commitToFetchDelay), 912292SN/A renameWidth(params->renameWidth), 922292SN/A commitWidth(params->commitWidth), 935529Snate@binkert.org numThreads(params->numThreads), 942843Sktlim@umich.edu drainPending(false), 9510340Smitch.hayenga@arm.com drainImminent(false), 968823Snilay@cs.wisc.edu trapLatency(params->trapLatency), 979513SAli.Saidi@ARM.com canHandleInterrupts(true), 989513SAli.Saidi@ARM.com avoidQuiesceLiveLock(false) 992292SN/A{ 10010172Sdam.sunwoo@arm.com if (commitWidth > Impl::MaxWidth) 10110172Sdam.sunwoo@arm.com fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 10210172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 10310172Sdam.sunwoo@arm.com commitWidth, static_cast<int>(Impl::MaxWidth)); 10410172Sdam.sunwoo@arm.com 1052292SN/A _status = Active; 1062292SN/A _nextStatus = Inactive; 1072292SN/A 10813563Snikos.nikoleris@arm.com if (commitPolicy == CommitPolicy::RoundRobin) { 1092292SN/A //Set-Up Priority List 1106221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1112292SN/A priority_list.push_back(tid); 1122292SN/A } 1132292SN/A } 1142292SN/A 11513453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1166221Snate@binkert.org commitStatus[tid] = Idle; 1176221Snate@binkert.org changedROBNumEntries[tid] = false; 11813453Srekai.gonzalezalberquilla@arm.com trapSquash[tid] = false; 11913453Srekai.gonzalezalberquilla@arm.com tcSquash[tid] = false; 12013453Srekai.gonzalezalberquilla@arm.com squashAfterInst[tid] = nullptr; 12113453Srekai.gonzalezalberquilla@arm.com pc[tid].set(0); 12213453Srekai.gonzalezalberquilla@arm.com youngestSeqNum[tid] = 0; 12313453Srekai.gonzalezalberquilla@arm.com lastCommitedSeqNum[tid] = 0; 1246221Snate@binkert.org trapInFlight[tid] = false; 1256221Snate@binkert.org committedStores[tid] = false; 12613453Srekai.gonzalezalberquilla@arm.com checkEmptyROB[tid] = false; 12713453Srekai.gonzalezalberquilla@arm.com renameMap[tid] = nullptr; 1282292SN/A } 1293640Sktlim@umich.edu interrupt = NoFault; 1302292SN/A} 1312292SN/A 1322292SN/Atemplate <class Impl> 1332292SN/Astd::string 1342292SN/ADefaultCommit<Impl>::name() const 1352292SN/A{ 1362292SN/A return cpu->name() + ".commit"; 1372292SN/A} 1382292SN/A 1392292SN/Atemplate <class Impl> 1402292SN/Avoid 14110023Smatt.horsnell@ARM.comDefaultCommit<Impl>::regProbePoints() 14210023Smatt.horsnell@ARM.com{ 14310023Smatt.horsnell@ARM.com ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 14410023Smatt.horsnell@ARM.com ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 14511246Sradhika.jagtap@ARM.com ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash"); 14610023Smatt.horsnell@ARM.com} 14710023Smatt.horsnell@ARM.com 14810023Smatt.horsnell@ARM.comtemplate <class Impl> 14910023Smatt.horsnell@ARM.comvoid 1502292SN/ADefaultCommit<Impl>::regStats() 1512132SN/A{ 1522301SN/A using namespace Stats; 1531062SN/A commitSquashedInsts 1541062SN/A .name(name() + ".commitSquashedInsts") 1551062SN/A .desc("The number of squashed insts skipped by commit") 1561062SN/A .prereq(commitSquashedInsts); 15710731Snilay@cs.wisc.edu 1581062SN/A commitNonSpecStalls 1591062SN/A .name(name() + ".commitNonSpecStalls") 1601062SN/A .desc("The number of times commit has been forced to stall to " 1611062SN/A "communicate backwards") 1621062SN/A .prereq(commitNonSpecStalls); 16310731Snilay@cs.wisc.edu 1641062SN/A branchMispredicts 1651062SN/A .name(name() + ".branchMispredicts") 1661062SN/A .desc("The number of times a branch was mispredicted") 1671062SN/A .prereq(branchMispredicts); 16810731Snilay@cs.wisc.edu 1692292SN/A numCommittedDist 1701062SN/A .init(0,commitWidth,1) 1718240Snate@binkert.org .name(name() + ".committed_per_cycle") 1721062SN/A .desc("Number of insts commited each cycle") 1731062SN/A .flags(Stats::pdf) 1741062SN/A ; 1752301SN/A 1768834Satgutier@umich.edu instsCommitted 1776221Snate@binkert.org .init(cpu->numThreads) 1788834Satgutier@umich.edu .name(name() + ".committedInsts") 1792301SN/A .desc("Number of instructions committed") 1802301SN/A .flags(total) 1812301SN/A ; 1822301SN/A 1838834Satgutier@umich.edu opsCommitted 1848834Satgutier@umich.edu .init(cpu->numThreads) 1858834Satgutier@umich.edu .name(name() + ".committedOps") 1868834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 1878834Satgutier@umich.edu .flags(total) 1888834Satgutier@umich.edu ; 1898834Satgutier@umich.edu 1902316SN/A statComSwp 1916221Snate@binkert.org .init(cpu->numThreads) 1928240Snate@binkert.org .name(name() + ".swp_count") 1932301SN/A .desc("Number of s/w prefetches committed") 1942301SN/A .flags(total) 1952301SN/A ; 1962301SN/A 1972316SN/A statComRefs 1986221Snate@binkert.org .init(cpu->numThreads) 1998240Snate@binkert.org .name(name() + ".refs") 2002301SN/A .desc("Number of memory references committed") 2012301SN/A .flags(total) 2022301SN/A ; 2032301SN/A 2042316SN/A statComLoads 2056221Snate@binkert.org .init(cpu->numThreads) 2068240Snate@binkert.org .name(name() + ".loads") 2072301SN/A .desc("Number of loads committed") 2082301SN/A .flags(total) 2092301SN/A ; 2102301SN/A 2112316SN/A statComMembars 2126221Snate@binkert.org .init(cpu->numThreads) 2138240Snate@binkert.org .name(name() + ".membars") 2142301SN/A .desc("Number of memory barriers committed") 2152301SN/A .flags(total) 2162301SN/A ; 2172301SN/A 2182316SN/A statComBranches 2196221Snate@binkert.org .init(cpu->numThreads) 2208240Snate@binkert.org .name(name() + ".branches") 2212301SN/A .desc("Number of branches committed") 2222301SN/A .flags(total) 2232301SN/A ; 2242301SN/A 2257897Shestness@cs.utexas.edu statComFloating 2267897Shestness@cs.utexas.edu .init(cpu->numThreads) 2278240Snate@binkert.org .name(name() + ".fp_insts") 2287897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2297897Shestness@cs.utexas.edu .flags(total) 2307897Shestness@cs.utexas.edu ; 2317897Shestness@cs.utexas.edu 23212110SRekai.GonzalezAlberquilla@arm.com statComVector 23312110SRekai.GonzalezAlberquilla@arm.com .init(cpu->numThreads) 23412110SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_insts") 23512110SRekai.GonzalezAlberquilla@arm.com .desc("Number of committed Vector instructions.") 23612110SRekai.GonzalezAlberquilla@arm.com .flags(total) 23712110SRekai.GonzalezAlberquilla@arm.com ; 23812110SRekai.GonzalezAlberquilla@arm.com 2397897Shestness@cs.utexas.edu statComInteger 2407897Shestness@cs.utexas.edu .init(cpu->numThreads) 2418240Snate@binkert.org .name(name()+".int_insts") 2427897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2437897Shestness@cs.utexas.edu .flags(total) 2447897Shestness@cs.utexas.edu ; 2457897Shestness@cs.utexas.edu 2467897Shestness@cs.utexas.edu statComFunctionCalls 2477897Shestness@cs.utexas.edu .init(cpu->numThreads) 2488240Snate@binkert.org .name(name()+".function_calls") 2497897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2507897Shestness@cs.utexas.edu .flags(total) 2517897Shestness@cs.utexas.edu ; 2527897Shestness@cs.utexas.edu 25310193SCurtis.Dunham@arm.com statCommittedInstType 25410193SCurtis.Dunham@arm.com .init(numThreads,Enums::Num_OpClass) 25510193SCurtis.Dunham@arm.com .name(name() + ".op_class") 25610193SCurtis.Dunham@arm.com .desc("Class of committed instruction") 25710193SCurtis.Dunham@arm.com .flags(total | pdf | dist) 25810193SCurtis.Dunham@arm.com ; 25910193SCurtis.Dunham@arm.com statCommittedInstType.ysubnames(Enums::OpClassStrings); 26010193SCurtis.Dunham@arm.com 2612316SN/A commitEligibleSamples 2628240Snate@binkert.org .name(name() + ".bw_lim_events") 2632301SN/A .desc("number cycles where commit BW limit reached") 2642301SN/A ; 2651062SN/A} 2661062SN/A 2671062SN/Atemplate <class Impl> 2681062SN/Avoid 2692980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2702292SN/A{ 2712292SN/A thread = threads; 2722292SN/A} 2732292SN/A 2742292SN/Atemplate <class Impl> 2752292SN/Avoid 2762292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2771060SN/A{ 2781060SN/A timeBuffer = tb_ptr; 2791060SN/A 2801060SN/A // Setup wire to send information back to IEW. 2811060SN/A toIEW = timeBuffer->getWire(0); 2821060SN/A 2831060SN/A // Setup wire to read data from IEW (for the ROB). 2841060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2851060SN/A} 2861060SN/A 2871061SN/Atemplate <class Impl> 2881060SN/Avoid 2892292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2902292SN/A{ 2912292SN/A fetchQueue = fq_ptr; 2922292SN/A 2932292SN/A // Setup wire to get instructions from rename (for the ROB). 2942292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2952292SN/A} 2962292SN/A 2972292SN/Atemplate <class Impl> 2982292SN/Avoid 2992292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3001060SN/A{ 3011060SN/A renameQueue = rq_ptr; 3021060SN/A 3031060SN/A // Setup wire to get instructions from rename (for the ROB). 3041060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3051060SN/A} 3061060SN/A 3071061SN/Atemplate <class Impl> 3081060SN/Avoid 3092292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3101060SN/A{ 3111060SN/A iewQueue = iq_ptr; 3121060SN/A 3131060SN/A // Setup wire to get instructions from IEW. 3141060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3151060SN/A} 3161060SN/A 3171061SN/Atemplate <class Impl> 3181060SN/Avoid 3192292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3202292SN/A{ 3212292SN/A iewStage = iew_stage; 3222292SN/A} 3232292SN/A 3242292SN/Atemplate<class Impl> 3252292SN/Avoid 3266221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3272292SN/A{ 3282292SN/A activeThreads = at_ptr; 3292292SN/A} 3302292SN/A 3312292SN/Atemplate <class Impl> 3322292SN/Avoid 3332292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3342292SN/A{ 3356221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3366221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3372292SN/A} 3382292SN/A 3392292SN/Atemplate <class Impl> 3402292SN/Avoid 3412292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3421060SN/A{ 3431060SN/A rob = rob_ptr; 3441060SN/A} 3451060SN/A 3461061SN/Atemplate <class Impl> 3471060SN/Avoid 3489427SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::startupStage() 3491060SN/A{ 3502292SN/A rob->setActiveThreads(activeThreads); 3512292SN/A rob->resetEntries(); 3521060SN/A 3532292SN/A // Broadcast the number of free entries. 3546221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3556221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3566221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3576221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3581060SN/A } 3591060SN/A 3604329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3614329Sktlim@umich.edu // start of the simulation, so it starts as active. 3624329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3634329Sktlim@umich.edu 3642292SN/A cpu->activityThisCycle(); 3651060SN/A} 3661060SN/A 3671061SN/Atemplate <class Impl> 3689444SAndreas.Sandberg@ARM.comvoid 36913641Sqtt2@cornell.eduDefaultCommit<Impl>::clearStates(ThreadID tid) 37013641Sqtt2@cornell.edu{ 37113641Sqtt2@cornell.edu commitStatus[tid] = Idle; 37213641Sqtt2@cornell.edu changedROBNumEntries[tid] = false; 37313641Sqtt2@cornell.edu checkEmptyROB[tid] = false; 37413641Sqtt2@cornell.edu trapInFlight[tid] = false; 37513641Sqtt2@cornell.edu committedStores[tid] = false; 37613641Sqtt2@cornell.edu trapSquash[tid] = false; 37713641Sqtt2@cornell.edu tcSquash[tid] = false; 37813641Sqtt2@cornell.edu pc[tid].set(0); 37913641Sqtt2@cornell.edu lastCommitedSeqNum[tid] = 0; 38013641Sqtt2@cornell.edu squashAfterInst[tid] = NULL; 38113641Sqtt2@cornell.edu} 38213641Sqtt2@cornell.edu 38313641Sqtt2@cornell.edutemplate <class Impl> 38413641Sqtt2@cornell.eduvoid 3852843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3861060SN/A{ 3872843Sktlim@umich.edu drainPending = true; 3882316SN/A} 3892316SN/A 3902316SN/Atemplate <class Impl> 3912316SN/Avoid 3929444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainResume() 3932843Sktlim@umich.edu{ 3942864Sktlim@umich.edu drainPending = false; 39510340Smitch.hayenga@arm.com drainImminent = false; 3962843Sktlim@umich.edu} 3972843Sktlim@umich.edu 3982843Sktlim@umich.edutemplate <class Impl> 3992843Sktlim@umich.eduvoid 4009444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainSanityCheck() const 4019444SAndreas.Sandberg@ARM.com{ 4029444SAndreas.Sandberg@ARM.com assert(isDrained()); 4039444SAndreas.Sandberg@ARM.com rob->drainSanityCheck(); 4049444SAndreas.Sandberg@ARM.com} 4059444SAndreas.Sandberg@ARM.com 4069444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4079444SAndreas.Sandberg@ARM.combool 4089444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::isDrained() const 4099444SAndreas.Sandberg@ARM.com{ 4109444SAndreas.Sandberg@ARM.com /* Make sure no one is executing microcode. There are two reasons 4119444SAndreas.Sandberg@ARM.com * for this: 4129444SAndreas.Sandberg@ARM.com * - Hardware virtualized CPUs can't switch into the middle of a 4139444SAndreas.Sandberg@ARM.com * microcode sequence. 4149444SAndreas.Sandberg@ARM.com * - The current fetch implementation will most likely get very 4159444SAndreas.Sandberg@ARM.com * confused if it tries to start fetching an instruction that 4169444SAndreas.Sandberg@ARM.com * is executing in the middle of a ucode sequence that changes 4179444SAndreas.Sandberg@ARM.com * address mappings. This can happen on for example x86. 4189444SAndreas.Sandberg@ARM.com */ 4199444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 4209444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() != 0) 4219444SAndreas.Sandberg@ARM.com return false; 4229444SAndreas.Sandberg@ARM.com } 4239444SAndreas.Sandberg@ARM.com 4249444SAndreas.Sandberg@ARM.com /* Make sure that all instructions have finished committing before 4259444SAndreas.Sandberg@ARM.com * declaring the system as drained. We want the pipeline to be 4269444SAndreas.Sandberg@ARM.com * completely empty when we declare the CPU to be drained. This 4279444SAndreas.Sandberg@ARM.com * makes debugging easier since CPU handover and restoring from a 4289444SAndreas.Sandberg@ARM.com * checkpoint with a different CPU should have the same timing. 4299444SAndreas.Sandberg@ARM.com */ 4309444SAndreas.Sandberg@ARM.com return rob->isEmpty() && 4319444SAndreas.Sandberg@ARM.com interrupt == NoFault; 4329444SAndreas.Sandberg@ARM.com} 4339444SAndreas.Sandberg@ARM.com 4349444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4359444SAndreas.Sandberg@ARM.comvoid 4362307SN/ADefaultCommit<Impl>::takeOverFrom() 4372307SN/A{ 4382307SN/A _status = Active; 4392307SN/A _nextStatus = Inactive; 4406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4416221Snate@binkert.org commitStatus[tid] = Idle; 4426221Snate@binkert.org changedROBNumEntries[tid] = false; 4436221Snate@binkert.org trapSquash[tid] = false; 4446221Snate@binkert.org tcSquash[tid] = false; 4459437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 4462307SN/A } 4472307SN/A rob->takeOverFrom(); 4482307SN/A} 4492307SN/A 4502307SN/Atemplate <class Impl> 4512307SN/Avoid 45210331Smitch.hayenga@arm.comDefaultCommit<Impl>::deactivateThread(ThreadID tid) 45310331Smitch.hayenga@arm.com{ 45410331Smitch.hayenga@arm.com list<ThreadID>::iterator thread_it = std::find(priority_list.begin(), 45510331Smitch.hayenga@arm.com priority_list.end(), tid); 45610331Smitch.hayenga@arm.com 45710331Smitch.hayenga@arm.com if (thread_it != priority_list.end()) { 45810331Smitch.hayenga@arm.com priority_list.erase(thread_it); 45910331Smitch.hayenga@arm.com } 46010331Smitch.hayenga@arm.com} 46110331Smitch.hayenga@arm.com 46210331Smitch.hayenga@arm.com 46310331Smitch.hayenga@arm.comtemplate <class Impl> 46410331Smitch.hayenga@arm.comvoid 4652292SN/ADefaultCommit<Impl>::updateStatus() 4662132SN/A{ 4672316SN/A // reset ROB changed variable 4686221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4696221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4703867Sbinkertn@umich.edu 4713867Sbinkertn@umich.edu while (threads != end) { 4726221Snate@binkert.org ThreadID tid = *threads++; 4733867Sbinkertn@umich.edu 4742316SN/A changedROBNumEntries[tid] = false; 4752316SN/A 4762316SN/A // Also check if any of the threads has a trap pending 4772316SN/A if (commitStatus[tid] == TrapPending || 4782316SN/A commitStatus[tid] == FetchTrapPending) { 4792316SN/A _nextStatus = Active; 4802316SN/A } 4812292SN/A } 4822292SN/A 4832292SN/A if (_nextStatus == Inactive && _status == Active) { 4842292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4852733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4862292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4872292SN/A DPRINTF(Activity, "Activating stage.\n"); 4882733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4892292SN/A } 4902292SN/A 4912292SN/A _status = _nextStatus; 4922292SN/A} 4932292SN/A 4942292SN/Atemplate <class Impl> 4952292SN/Abool 4962292SN/ADefaultCommit<Impl>::changedROBEntries() 4972292SN/A{ 4986221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4996221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5002292SN/A 5013867Sbinkertn@umich.edu while (threads != end) { 5026221Snate@binkert.org ThreadID tid = *threads++; 5032292SN/A 5042292SN/A if (changedROBNumEntries[tid]) { 5052292SN/A return true; 5062292SN/A } 5072292SN/A } 5082292SN/A 5092292SN/A return false; 5102292SN/A} 5112292SN/A 5122292SN/Atemplate <class Impl> 5136221Snate@binkert.orgsize_t 5146221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 5152292SN/A{ 5162292SN/A return rob->numFreeEntries(tid); 5172292SN/A} 5182292SN/A 5192292SN/Atemplate <class Impl> 5202292SN/Avoid 52111877Sbrandon.potter@amd.comDefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault) 5222292SN/A{ 5232292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5242292SN/A 52512127Sspwilson2@wisc.edu EventFunctionWrapper *trap = new EventFunctionWrapper( 52612127Sspwilson2@wisc.edu [this, tid]{ processTrapEvent(tid); }, 52712127Sspwilson2@wisc.edu "Trap", true, Event::CPU_Tick_Pri); 5282292SN/A 52911877Sbrandon.potter@amd.com Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ? 53011877Sbrandon.potter@amd.com cpu->syscallRetryLatency : trapLatency; 53111877Sbrandon.potter@amd.com 53211877Sbrandon.potter@amd.com cpu->schedule(trap, cpu->clockEdge(latency)); 5334035Sktlim@umich.edu trapInFlight[tid] = true; 5348518Sgeoffrey.blake@arm.com thread[tid]->trapPending = true; 5352292SN/A} 5362292SN/A 5372292SN/Atemplate <class Impl> 5382292SN/Avoid 5396221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5402292SN/A{ 5414035Sktlim@umich.edu assert(!trapInFlight[tid]); 5422680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5432292SN/A 5442680Sktlim@umich.edu tcSquash[tid] = true; 5452292SN/A} 5462292SN/A 5472292SN/Atemplate <class Impl> 5482292SN/Avoid 5496221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5502292SN/A{ 5512292SN/A // If we want to include the squashing instruction in the squash, 5522292SN/A // then use one older sequence number. 5532292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5542292SN/A // all instructions of this thread. 55510164Ssleimanf@umich.edu InstSeqNum squashed_inst = rob->isEmpty(tid) ? 5567855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5572292SN/A 5582292SN/A // All younger instructions will be squashed. Set the sequence 5592292SN/A // number as the youngest instruction in the ROB (0 in this case. 5602292SN/A // Hopefully nothing breaks.) 5617855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5622292SN/A 5632292SN/A rob->squash(squashed_inst, tid); 5642292SN/A changedROBNumEntries[tid] = true; 5652292SN/A 5662292SN/A // Send back the sequence number of the squashed instruction. 5672292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5682292SN/A 5692292SN/A // Send back the squash signal to tell stages that they should 5702292SN/A // squash. 5712292SN/A toIEW->commitInfo[tid].squash = true; 5722292SN/A 5732292SN/A // Send back the rob squashing signal so other stages know that 5742292SN/A // the ROB is in the process of squashing. 5752292SN/A toIEW->commitInfo[tid].robSquashing = true; 5762292SN/A 5777851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 5788137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 5792292SN/A 5807720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5812316SN/A} 5822292SN/A 5832316SN/Atemplate <class Impl> 5842316SN/Avoid 5856221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5862316SN/A{ 5872316SN/A squashAll(tid); 5882316SN/A 5897720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5902316SN/A 5912316SN/A thread[tid]->trapPending = false; 5929382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 5934035Sktlim@umich.edu trapInFlight[tid] = false; 5942316SN/A 5952316SN/A trapSquash[tid] = false; 5962316SN/A 5972316SN/A commitStatus[tid] = ROBSquashing; 5982316SN/A cpu->activityThisCycle(); 5992316SN/A} 6002316SN/A 6012316SN/Atemplate <class Impl> 6022316SN/Avoid 6036221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 6042316SN/A{ 6052316SN/A squashAll(tid); 6062292SN/A 6077720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 6082292SN/A 6099382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6102292SN/A assert(!thread[tid]->trapPending); 6112316SN/A 6122292SN/A commitStatus[tid] = ROBSquashing; 6132292SN/A cpu->activityThisCycle(); 6142292SN/A 6152680Sktlim@umich.edu tcSquash[tid] = false; 6162292SN/A} 6172292SN/A 6182292SN/Atemplate <class Impl> 6192292SN/Avoid 6209437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 6217784SAli.Saidi@ARM.com{ 6229437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Squashing after squash after request, " 6239437SAndreas.Sandberg@ARM.com "restarting at PC %s\n", pc[tid]); 6247784SAli.Saidi@ARM.com 6259437SAndreas.Sandberg@ARM.com squashAll(tid); 6269437SAndreas.Sandberg@ARM.com // Make sure to inform the fetch stage of which instruction caused 6279437SAndreas.Sandberg@ARM.com // the squash. It'll try to re-fetch an instruction executing in 6289437SAndreas.Sandberg@ARM.com // microcode unless this is set. 6299437SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 6309437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 6317784SAli.Saidi@ARM.com 6329437SAndreas.Sandberg@ARM.com commitStatus[tid] = ROBSquashing; 6339437SAndreas.Sandberg@ARM.com cpu->activityThisCycle(); 6349437SAndreas.Sandberg@ARM.com} 6357784SAli.Saidi@ARM.com 6369437SAndreas.Sandberg@ARM.comtemplate <class Impl> 6379437SAndreas.Sandberg@ARM.comvoid 63813429Srekai.gonzalezalberquilla@arm.comDefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst) 6399437SAndreas.Sandberg@ARM.com{ 6409437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6419437SAndreas.Sandberg@ARM.com tid, head_inst->seqNum); 6427784SAli.Saidi@ARM.com 6439437SAndreas.Sandberg@ARM.com assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 6449437SAndreas.Sandberg@ARM.com commitStatus[tid] = SquashAfterPending; 6459437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = head_inst; 6467784SAli.Saidi@ARM.com} 6477784SAli.Saidi@ARM.com 6487784SAli.Saidi@ARM.comtemplate <class Impl> 6497784SAli.Saidi@ARM.comvoid 6502292SN/ADefaultCommit<Impl>::tick() 6512292SN/A{ 6522292SN/A wroteToTimeBuffer = false; 6532292SN/A _nextStatus = Inactive; 6542292SN/A 6553867Sbinkertn@umich.edu if (activeThreads->empty()) 6562875Sksewell@umich.edu return; 6572875Sksewell@umich.edu 6586221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6596221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6602292SN/A 6612316SN/A // Check if any of the threads are done squashing. Change the 6622316SN/A // status if they are done. 6633867Sbinkertn@umich.edu while (threads != end) { 6646221Snate@binkert.org ThreadID tid = *threads++; 6652292SN/A 6664035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6674035Sktlim@umich.edu // this cycle. 6684035Sktlim@umich.edu committedStores[tid] = false; 6694035Sktlim@umich.edu 6702292SN/A if (commitStatus[tid] == ROBSquashing) { 6712292SN/A 6722292SN/A if (rob->isDoneSquashing(tid)) { 6732292SN/A commitStatus[tid] = Running; 6742292SN/A } else { 6752292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6762877Sksewell@umich.edu " insts this cycle.\n", tid); 6772702Sktlim@umich.edu rob->doSquash(tid); 6782702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6792702Sktlim@umich.edu wroteToTimeBuffer = true; 6802292SN/A } 6812292SN/A } 6822292SN/A } 6832292SN/A 6842292SN/A commit(); 6852292SN/A 6862292SN/A markCompletedInsts(); 6872292SN/A 6883867Sbinkertn@umich.edu threads = activeThreads->begin(); 6892292SN/A 6903867Sbinkertn@umich.edu while (threads != end) { 6916221Snate@binkert.org ThreadID tid = *threads++; 6922292SN/A 6932292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6942292SN/A // The ROB has more instructions it can commit. Its next status 6952292SN/A // will be active. 6962292SN/A _nextStatus = Active; 6972292SN/A 69813429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid); 6992292SN/A 7007720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 7012292SN/A " ROB and ready to commit\n", 7027720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7032292SN/A 7042292SN/A } else if (!rob->isEmpty(tid)) { 70513429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst = rob->readHeadInst(tid); 7062292SN/A 70710023Smatt.horsnell@ARM.com ppCommitStall->notify(inst); 70810023Smatt.horsnell@ARM.com 7092292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 7107720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 7117720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7122292SN/A } 7132292SN/A 7142292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 7152292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 7162292SN/A } 7172292SN/A 7182292SN/A 7192292SN/A if (wroteToTimeBuffer) { 7202316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 7212292SN/A cpu->activityThisCycle(); 7222292SN/A } 7232292SN/A 7242292SN/A updateStatus(); 7252292SN/A} 7262292SN/A 7272292SN/Atemplate <class Impl> 7282292SN/Avoid 7294035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 7302292SN/A{ 7317847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7327847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7337847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7347847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7357847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7367847Sminkyu.jeong@arm.com interrupt = NoFault; 7379513SAli.Saidi@ARM.com avoidQuiesceLiveLock = true; 7387847Sminkyu.jeong@arm.com return; 7397847Sminkyu.jeong@arm.com } 7403633Sktlim@umich.edu 7418493Sgblack@eecs.umich.edu // Wait until all in flight instructions are finished before enterring 7428493Sgblack@eecs.umich.edu // the interrupt. 7438823Snilay@cs.wisc.edu if (canHandleInterrupts && cpu->instList.empty()) { 7447847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7457847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7467847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7474035Sktlim@umich.edu 7487847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7497847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7502292SN/A 7519382SAli.Saidi@ARM.com assert(!thread[0]->noSquashFromTC); 7529382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = true; 7532292SN/A 7548733Sgeoffrey.blake@arm.com if (cpu->checker) { 7558733Sgeoffrey.blake@arm.com cpu->checker->handlePendingInt(); 7568733Sgeoffrey.blake@arm.com } 7578733Sgeoffrey.blake@arm.com 7589624Snilay@cs.wisc.edu // CPU will handle interrupt. Note that we ignore the local copy of 7599624Snilay@cs.wisc.edu // interrupt. This is because the local copy may no longer be the 7609624Snilay@cs.wisc.edu // interrupt that the interrupt controller thinks is being handled. 7619624Snilay@cs.wisc.edu cpu->processInterrupts(cpu->getInterrupts()); 7623633Sktlim@umich.edu 7639382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = false; 7642292SN/A 7657847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7662292SN/A 76711877Sbrandon.potter@amd.com interrupt = NoFault; 76811877Sbrandon.potter@amd.com 7697847Sminkyu.jeong@arm.com // Generate trap squash event. 77011877Sbrandon.potter@amd.com generateTrapEvent(0, interrupt); 7713640Sktlim@umich.edu 7729513SAli.Saidi@ARM.com avoidQuiesceLiveLock = false; 7737847Sminkyu.jeong@arm.com } else { 7748823Snilay@cs.wisc.edu DPRINTF(Commit, "Interrupt pending: instruction is %sin " 7758823Snilay@cs.wisc.edu "flight, ROB is %sempty\n", 7768823Snilay@cs.wisc.edu canHandleInterrupts ? "not " : "", 7778823Snilay@cs.wisc.edu cpu->instList.empty() ? "" : "not " ); 7781060SN/A } 7794035Sktlim@umich.edu} 7807847Sminkyu.jeong@arm.com 7817847Sminkyu.jeong@arm.comtemplate <class Impl> 7827847Sminkyu.jeong@arm.comvoid 7837847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 7847847Sminkyu.jeong@arm.com{ 78510340Smitch.hayenga@arm.com // Don't propagate intterupts if we are currently handling a trap or 78610340Smitch.hayenga@arm.com // in draining and the last observable instruction has been committed. 7877847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 78810340Smitch.hayenga@arm.com tcSquash[0] || drainImminent) 7897847Sminkyu.jeong@arm.com return; 7907847Sminkyu.jeong@arm.com 7917847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 7927847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 7937847Sminkyu.jeong@arm.com // pending. 7947847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 7957847Sminkyu.jeong@arm.com 7967847Sminkyu.jeong@arm.com // Get any interrupt that happened 7977847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 7987847Sminkyu.jeong@arm.com 7997847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 8007847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 8017847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 8027847Sminkyu.jeong@arm.com if (interrupt != NoFault) 8037847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 8047847Sminkyu.jeong@arm.com} 8057847Sminkyu.jeong@arm.com 8064035Sktlim@umich.edutemplate <class Impl> 8074035Sktlim@umich.eduvoid 8084035Sktlim@umich.eduDefaultCommit<Impl>::commit() 8094035Sktlim@umich.edu{ 8108793Sgblack@eecs.umich.edu if (FullSystem) { 8118793Sgblack@eecs.umich.edu // Check if we have a interrupt and get read to handle it 8128793Sgblack@eecs.umich.edu if (cpu->checkInterrupts(cpu->tcBase(0))) 8138793Sgblack@eecs.umich.edu propagateInterrupt(); 8148793Sgblack@eecs.umich.edu } 8151060SN/A 8161060SN/A //////////////////////////////////// 8172316SN/A // Check for any possible squashes, handle them first 8181060SN/A //////////////////////////////////// 8196221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8206221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8211060SN/A 82210729Snilay@cs.wisc.edu int num_squashing_threads = 0; 82310729Snilay@cs.wisc.edu 8243867Sbinkertn@umich.edu while (threads != end) { 8256221Snate@binkert.org ThreadID tid = *threads++; 8261060SN/A 8272292SN/A // Not sure which one takes priority. I think if we have 8282292SN/A // both, that's a bad sign. 82910231Ssteve.reinhardt@amd.com if (trapSquash[tid]) { 8302680Sktlim@umich.edu assert(!tcSquash[tid]); 8312292SN/A squashFromTrap(tid); 83213641Sqtt2@cornell.edu 83313641Sqtt2@cornell.edu // If the thread is trying to exit (i.e., an exit syscall was 83413641Sqtt2@cornell.edu // executed), this trapSquash was originated by the exit 83513641Sqtt2@cornell.edu // syscall earlier. In this case, schedule an exit event in 83613641Sqtt2@cornell.edu // the next cycle to fully terminate this thread 83713641Sqtt2@cornell.edu if (cpu->isThreadExiting(tid)) 83813641Sqtt2@cornell.edu cpu->scheduleThreadExitEvent(tid); 83910231Ssteve.reinhardt@amd.com } else if (tcSquash[tid]) { 8404035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 8412680Sktlim@umich.edu squashFromTC(tid); 8429437SAndreas.Sandberg@ARM.com } else if (commitStatus[tid] == SquashAfterPending) { 8439437SAndreas.Sandberg@ARM.com // A squash from the previous cycle of the commit stage (i.e., 8449437SAndreas.Sandberg@ARM.com // commitInsts() called squashAfter) is pending. Squash the 8459437SAndreas.Sandberg@ARM.com // thread now. 8469437SAndreas.Sandberg@ARM.com squashFromSquashAfter(tid); 8472292SN/A } 8481061SN/A 8492292SN/A // Squashed sequence number must be older than youngest valid 8502292SN/A // instruction in the ROB. This prevents squashes from younger 8512292SN/A // instructions overriding squashes from older instructions. 8522292SN/A if (fromIEW->squash[tid] && 8532292SN/A commitStatus[tid] != TrapPending && 8542292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8551061SN/A 8568137SAli.Saidi@ARM.com if (fromIEW->mispredictInst[tid]) { 8578137SAli.Saidi@ARM.com DPRINTF(Commit, 8588137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 8592292SN/A tid, 8608137SAli.Saidi@ARM.com fromIEW->mispredictInst[tid]->instAddr(), 8612292SN/A fromIEW->squashedSeqNum[tid]); 8628137SAli.Saidi@ARM.com } else { 8638137SAli.Saidi@ARM.com DPRINTF(Commit, 8648137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to order violation [sn:%i]\n", 8658137SAli.Saidi@ARM.com tid, fromIEW->squashedSeqNum[tid]); 8668137SAli.Saidi@ARM.com } 8671061SN/A 8682292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8692292SN/A tid, 8707720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8711061SN/A 8722292SN/A commitStatus[tid] = ROBSquashing; 8731061SN/A 8742292SN/A // If we want to include the squashing instruction in the squash, 8752292SN/A // then use one older sequence number. 8762292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8771062SN/A 87810231Ssteve.reinhardt@amd.com if (fromIEW->includeSquashInst[tid]) { 8792292SN/A squashed_inst--; 8802935Sksewell@umich.edu } 8814035Sktlim@umich.edu 8822292SN/A // All younger instructions will be squashed. Set the sequence 8832292SN/A // number as the youngest instruction in the ROB. 8842292SN/A youngestSeqNum[tid] = squashed_inst; 8852292SN/A 8863093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8872292SN/A changedROBNumEntries[tid] = true; 8882292SN/A 8892292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8902292SN/A 8912292SN/A toIEW->commitInfo[tid].squash = true; 8922292SN/A 8932292SN/A // Send back the rob squashing signal so other stages know that 8942292SN/A // the ROB is in the process of squashing. 8952292SN/A toIEW->commitInfo[tid].robSquashing = true; 8962292SN/A 8977851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 8987851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 8992292SN/A toIEW->commitInfo[tid].branchTaken = 9002292SN/A fromIEW->branchTaken[tid]; 9018822Snilay@cs.wisc.edu toIEW->commitInfo[tid].squashInst = 9028822Snilay@cs.wisc.edu rob->findInst(tid, squashed_inst); 9038842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst) { 9048842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 9058842Smrinmoy.ghosh@arm.com toIEW->commitInfo[tid].branchTaken = true; 9068842Smrinmoy.ghosh@arm.com } 90710730Snilay@cs.wisc.edu ++branchMispredicts; 9088842Smrinmoy.ghosh@arm.com } 9092292SN/A 9107720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 9111062SN/A } 9122292SN/A 91310729Snilay@cs.wisc.edu if (commitStatus[tid] == ROBSquashing) { 91410729Snilay@cs.wisc.edu num_squashing_threads++; 91510729Snilay@cs.wisc.edu } 9161060SN/A } 9171060SN/A 91810729Snilay@cs.wisc.edu // If commit is currently squashing, then it will have activity for the 91910729Snilay@cs.wisc.edu // next cycle. Set its next status as active. 92010729Snilay@cs.wisc.edu if (num_squashing_threads) { 92110729Snilay@cs.wisc.edu _nextStatus = Active; 92210729Snilay@cs.wisc.edu } 9232292SN/A 92410729Snilay@cs.wisc.edu if (num_squashing_threads != numThreads) { 9251061SN/A // If we're not currently squashing, then get instructions. 9261060SN/A getInsts(); 9271060SN/A 9281061SN/A // Try to commit any instructions. 9291060SN/A commitInsts(); 9301060SN/A } 9311060SN/A 9322292SN/A //Check for any activity 9333867Sbinkertn@umich.edu threads = activeThreads->begin(); 9342292SN/A 9353867Sbinkertn@umich.edu while (threads != end) { 9366221Snate@binkert.org ThreadID tid = *threads++; 9372292SN/A 9382292SN/A if (changedROBNumEntries[tid]) { 9392292SN/A toIEW->commitInfo[tid].usedROB = true; 9402292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9412292SN/A 9422292SN/A wroteToTimeBuffer = true; 9432292SN/A changedROBNumEntries[tid] = false; 9444035Sktlim@umich.edu if (rob->isEmpty(tid)) 9454035Sktlim@umich.edu checkEmptyROB[tid] = true; 9462292SN/A } 9474035Sktlim@umich.edu 9484035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 9494035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 9504035Sktlim@umich.edu // stage has received any information regarding stores that 9514035Sktlim@umich.edu // committed. 9524035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 9534035Sktlim@umich.edu // on the same cycle as when stores have been committed. 9544035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 9554035Sktlim@umich.edu // commit and IEW. 9564035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9575557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9584035Sktlim@umich.edu checkEmptyROB[tid] = false; 9594035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 9604035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 9614035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9624035Sktlim@umich.edu wroteToTimeBuffer = true; 9634035Sktlim@umich.edu } 9644035Sktlim@umich.edu 9651060SN/A } 9661060SN/A} 9671060SN/A 9681061SN/Atemplate <class Impl> 9691060SN/Avoid 9702292SN/ADefaultCommit<Impl>::commitInsts() 9711060SN/A{ 9721060SN/A //////////////////////////////////// 9731060SN/A // Handle commit 9742316SN/A // Note that commit will be handled prior to putting new 9752316SN/A // instructions in the ROB so that the ROB only tries to commit 9762316SN/A // instructions it has in this current cycle, and not instructions 9772316SN/A // it is writing in during this cycle. Can't commit and squash 9782316SN/A // things at the same time... 9791060SN/A //////////////////////////////////// 9801060SN/A 9812292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9821060SN/A 9831060SN/A unsigned num_committed = 0; 9841060SN/A 9852292SN/A DynInstPtr head_inst; 9862316SN/A 9871060SN/A // Commit as many instructions as possible until the commit bandwidth 9881060SN/A // limit is reached, or it becomes impossible to commit any more. 9892292SN/A while (num_committed < commitWidth) { 9908823Snilay@cs.wisc.edu // Check for any interrupt that we've already squashed for 9918823Snilay@cs.wisc.edu // and start processing it. 9928823Snilay@cs.wisc.edu if (interrupt != NoFault) 9938823Snilay@cs.wisc.edu handleInterrupt(); 9948823Snilay@cs.wisc.edu 99510731Snilay@cs.wisc.edu ThreadID commit_thread = getCommittingThread(); 9961060SN/A 9972292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9982292SN/A break; 9992292SN/A 10002292SN/A head_inst = rob->readHeadInst(commit_thread); 10012292SN/A 10026221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 10032292SN/A 10042292SN/A assert(tid == commit_thread); 10052292SN/A 10062292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 10072292SN/A head_inst->seqNum, tid); 10082132SN/A 10092316SN/A // If the head instruction is squashed, it is ready to retire 10102316SN/A // (be removed from the ROB) at any time. 10111060SN/A if (head_inst->isSquashed()) { 10121060SN/A 10132292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 10141060SN/A "ROB.\n"); 10151060SN/A 10162292SN/A rob->retireHead(commit_thread); 10171060SN/A 10181062SN/A ++commitSquashedInsts; 101911246Sradhika.jagtap@ARM.com // Notify potential listeners that this instruction is squashed 102011246Sradhika.jagtap@ARM.com ppSquash->notify(head_inst); 10211062SN/A 10222292SN/A // Record that the number of ROB entries has changed. 10232292SN/A changedROBNumEntries[tid] = true; 10241060SN/A } else { 10257720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 10262292SN/A 10271060SN/A // Increment the total number of non-speculative instructions 10281060SN/A // executed. 10291060SN/A // Hack for now: it really shouldn't happen until after the 10301061SN/A // commit is deemed to be successful, but this count is needed 10311061SN/A // for syscalls. 10322292SN/A thread[tid]->funcExeInst++; 10331060SN/A 10341060SN/A // Try to commit the head instruction. 10351060SN/A bool commit_success = commitHead(head_inst, num_committed); 10361060SN/A 10371062SN/A if (commit_success) { 10381060SN/A ++num_committed; 103910193SCurtis.Dunham@arm.com statCommittedInstType[tid][head_inst->opClass()]++; 104010023Smatt.horsnell@ARM.com ppCommit->notify(head_inst); 10411060SN/A 10422292SN/A changedROBNumEntries[tid] = true; 10432292SN/A 10442292SN/A // Set the doneSeqNum to the youngest committed instruction. 10452292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 10461060SN/A 10478823Snilay@cs.wisc.edu if (tid == 0) { 10488823Snilay@cs.wisc.edu canHandleInterrupts = (!head_inst->isDelayedCommit()) && 10498823Snilay@cs.wisc.edu ((THE_ISA != ALPHA_ISA) || 10508823Snilay@cs.wisc.edu (!(pc[0].instAddr() & 0x3))); 10518823Snilay@cs.wisc.edu } 10528823Snilay@cs.wisc.edu 105312216Snikos.nikoleris@arm.com // at this point store conditionals should either have 105412216Snikos.nikoleris@arm.com // been completed or predicated false 105512216Snikos.nikoleris@arm.com assert(!head_inst->isStoreConditional() || 105612216Snikos.nikoleris@arm.com head_inst->isCompleted() || 105712216Snikos.nikoleris@arm.com !head_inst->readPredicate()); 105812216Snikos.nikoleris@arm.com 10597783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 10607783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 10617783SGiacomo.Gabrielli@arm.com 106210034SGeoffrey.Blake@arm.com // Check instruction execution if it successfully commits and 106310034SGeoffrey.Blake@arm.com // is not carrying a fault. 106410034SGeoffrey.Blake@arm.com if (cpu->checker) { 106510034SGeoffrey.Blake@arm.com cpu->checker->verify(head_inst); 106610034SGeoffrey.Blake@arm.com } 106710034SGeoffrey.Blake@arm.com 10688662SAli.Saidi@ARM.com cpu->traceFunctions(pc[tid].instAddr()); 10698662SAli.Saidi@ARM.com 10707720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 10712935Sksewell@umich.edu 10727855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 10737855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 10747855SAli.Saidi@ARM.com 10757784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 10767784SAli.Saidi@ARM.com // others squash everything and restart fetch 10777784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 10789437SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10797784SAli.Saidi@ARM.com 10809444SAndreas.Sandberg@ARM.com if (drainPending) { 108110340Smitch.hayenga@arm.com if (pc[tid].microPC() == 0 && interrupt == NoFault && 108210340Smitch.hayenga@arm.com !thread[tid]->trapPending) { 108310340Smitch.hayenga@arm.com // Last architectually committed instruction. 108410340Smitch.hayenga@arm.com // Squash the pipeline, stall fetch, and use 108510340Smitch.hayenga@arm.com // drainImminent to disable interrupts 108610340Smitch.hayenga@arm.com DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 10879444SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10889444SAndreas.Sandberg@ARM.com cpu->commitDrained(tid); 108910340Smitch.hayenga@arm.com drainImminent = true; 10909444SAndreas.Sandberg@ARM.com } 10919444SAndreas.Sandberg@ARM.com } 10929444SAndreas.Sandberg@ARM.com 109310596Sgabeblack@google.com bool onInstBoundary = !head_inst->isMicroop() || 109410596Sgabeblack@google.com head_inst->isLastMicroop() || 109510596Sgabeblack@google.com !head_inst->isDelayedCommit(); 109610596Sgabeblack@google.com 109710596Sgabeblack@google.com if (onInstBoundary) { 109810596Sgabeblack@google.com int count = 0; 109910596Sgabeblack@google.com Addr oldpc; 110010596Sgabeblack@google.com // Make sure we're not currently updating state while 110110596Sgabeblack@google.com // handling PC events. 110210596Sgabeblack@google.com assert(!thread[tid]->noSquashFromTC && 110310596Sgabeblack@google.com !thread[tid]->trapPending); 110410596Sgabeblack@google.com do { 110510596Sgabeblack@google.com oldpc = pc[tid].instAddr(); 110610596Sgabeblack@google.com cpu->system->pcEventQueue.service(thread[tid]->getTC()); 110710596Sgabeblack@google.com count++; 110810596Sgabeblack@google.com } while (oldpc != pc[tid].instAddr()); 110910596Sgabeblack@google.com if (count > 1) { 111010596Sgabeblack@google.com DPRINTF(Commit, 111110596Sgabeblack@google.com "PC skip function event, stopping commit\n"); 111210596Sgabeblack@google.com break; 111310596Sgabeblack@google.com } 11142292SN/A } 11159513SAli.Saidi@ARM.com 11169513SAli.Saidi@ARM.com // Check if an instruction just enabled interrupts and we've 11179513SAli.Saidi@ARM.com // previously had an interrupt pending that was not handled 11189513SAli.Saidi@ARM.com // because interrupts were subsequently disabled before the 11199513SAli.Saidi@ARM.com // pipeline reached a place to handle the interrupt. In that 11209513SAli.Saidi@ARM.com // case squash now to make sure the interrupt is handled. 11219513SAli.Saidi@ARM.com // 11229513SAli.Saidi@ARM.com // If we don't do this, we might end up in a live lock situation 112310596Sgabeblack@google.com if (!interrupt && avoidQuiesceLiveLock && 112410596Sgabeblack@google.com onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0))) 11259513SAli.Saidi@ARM.com squashAfter(tid, head_inst); 11261060SN/A } else { 11277720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 11282292SN/A "[tid:%i] [sn:%i].\n", 11297720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 11301060SN/A break; 11311060SN/A } 11321060SN/A } 11331060SN/A } 11341062SN/A 11351063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 11362292SN/A numCommittedDist.sample(num_committed); 11372307SN/A 11382307SN/A if (num_committed == commitWidth) { 11392349SN/A commitEligibleSamples++; 11402307SN/A } 11411060SN/A} 11421060SN/A 11431061SN/Atemplate <class Impl> 11441060SN/Abool 114513429Srekai.gonzalezalberquilla@arm.comDefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) 11461060SN/A{ 11471060SN/A assert(head_inst); 11481060SN/A 11496221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 11502292SN/A 11512316SN/A // If the instruction is not executed yet, then it will need extra 11522316SN/A // handling. Signal backwards that it should be executed. 11531061SN/A if (!head_inst->isExecuted()) { 11541061SN/A // Keep this number correct. We have not yet actually executed 11551061SN/A // and committed this instruction. 11562292SN/A thread[tid]->funcExeInst--; 11571062SN/A 11589948SAli.Saidi@ARM.com // Make sure we are only trying to commit un-executed instructions we 11599948SAli.Saidi@ARM.com // think are possible. 11609948SAli.Saidi@ARM.com assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 11619948SAli.Saidi@ARM.com || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 116210824SAndreas.Sandberg@ARM.com (head_inst->isLoad() && head_inst->strictlyOrdered())); 11632316SN/A 11649948SAli.Saidi@ARM.com DPRINTF(Commit, "Encountered a barrier or non-speculative " 11659948SAli.Saidi@ARM.com "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 11669948SAli.Saidi@ARM.com head_inst->seqNum, head_inst->pcState()); 11672316SN/A 11689948SAli.Saidi@ARM.com if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 11699948SAli.Saidi@ARM.com DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 11709948SAli.Saidi@ARM.com return false; 11719948SAli.Saidi@ARM.com } 11722292SN/A 11739948SAli.Saidi@ARM.com toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 11741061SN/A 11759948SAli.Saidi@ARM.com // Change the instruction so it won't try to commit again until 11769948SAli.Saidi@ARM.com // it is executed. 11779948SAli.Saidi@ARM.com head_inst->clearCanCommit(); 11781061SN/A 117910824SAndreas.Sandberg@ARM.com if (head_inst->isLoad() && head_inst->strictlyOrdered()) { 118010824SAndreas.Sandberg@ARM.com DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n", 11817720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 118210824SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].strictlyOrdered = true; 118310824SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst; 11849948SAli.Saidi@ARM.com } else { 11859948SAli.Saidi@ARM.com ++commitNonSpecStalls; 11869948SAli.Saidi@ARM.com } 11872292SN/A 11889948SAli.Saidi@ARM.com return false; 11891060SN/A } 11901060SN/A 11912316SN/A if (head_inst->isThreadSync()) { 11922292SN/A // Not handled for now. 11932316SN/A panic("Thread sync instructions are not handled yet.\n"); 11942132SN/A } 11952132SN/A 11964035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 11974035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 11984035Sktlim@umich.edu 11992316SN/A // Stores mark themselves as completed. 12004035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 12012310SN/A head_inst->setCompleted(); 12022310SN/A } 12032310SN/A 12042112SN/A if (inst_fault != NoFault) { 12057720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 12067720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 12072292SN/A 12085557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 12092316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 12102316SN/A return false; 12112316SN/A } 12122310SN/A 12134035Sktlim@umich.edu head_inst->setCompleted(); 12144035Sktlim@umich.edu 121510034SGeoffrey.Blake@arm.com // If instruction has faulted, let the checker execute it and 121610034SGeoffrey.Blake@arm.com // check if it sees the same fault and control flow. 12178733Sgeoffrey.blake@arm.com if (cpu->checker) { 12188733Sgeoffrey.blake@arm.com // Need to check the instruction before its fault is processed 12192732Sktlim@umich.edu cpu->checker->verify(head_inst); 12202316SN/A } 12212292SN/A 12229382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC); 12232292SN/A 12242316SN/A // Mark that we're in state update mode so that the trap's 12252316SN/A // execution doesn't generate extra squashes. 12269382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 12272292SN/A 12282316SN/A // Execute the trap. Although it's slightly unrealistic in 12292316SN/A // terms of timing (as it doesn't wait for the full timing of 12302316SN/A // the trap event to complete before updating state), it's 12312316SN/A // needed to update the state as soon as possible. This 12322316SN/A // prevents external agents from changing any specific state 12332316SN/A // that the trap need. 123412422Sgabeblack@google.com cpu->trap(inst_fault, tid, 123512422Sgabeblack@google.com head_inst->notAnInst() ? 123612422Sgabeblack@google.com StaticInst::nullStaticInstPtr : 123712422Sgabeblack@google.com head_inst->staticInst); 12382292SN/A 12392316SN/A // Exit state update mode to avoid accidental updating. 12409382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 12412292SN/A 12422316SN/A commitStatus[tid] = TrapPending; 12432292SN/A 12448067SAli.Saidi@ARM.com DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 12458067SAli.Saidi@ARM.com head_inst->seqNum); 12464035Sktlim@umich.edu if (head_inst->traceData) { 12476667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 12486667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 12498834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12506667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 12516667Ssteve.reinhardt@amd.com } 12524288Sktlim@umich.edu delete head_inst->traceData; 12534035Sktlim@umich.edu head_inst->traceData = NULL; 12544035Sktlim@umich.edu } 12554035Sktlim@umich.edu 12562316SN/A // Generate trap squash event. 125711877Sbrandon.potter@amd.com generateTrapEvent(tid, inst_fault); 12582316SN/A return false; 12591060SN/A } 12601060SN/A 12612301SN/A updateComInstStats(head_inst); 12622132SN/A 12638793Sgblack@eecs.umich.edu if (FullSystem) { 12648793Sgblack@eecs.umich.edu if (thread[tid]->profile) { 12658793Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 12668793Sgblack@eecs.umich.edu ProfileNode *node = thread[tid]->profile->consume( 12678793Sgblack@eecs.umich.edu thread[tid]->getTC(), head_inst->staticInst); 12682362SN/A 12698793Sgblack@eecs.umich.edu if (node) 12708793Sgblack@eecs.umich.edu thread[tid]->profileNode = node; 12718793Sgblack@eecs.umich.edu } 12728793Sgblack@eecs.umich.edu if (CPA::available()) { 12738793Sgblack@eecs.umich.edu if (head_inst->isControl()) { 12748793Sgblack@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 12758793Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 12768793Sgblack@eecs.umich.edu } 12775953Ssaidi@eecs.umich.edu } 12785953Ssaidi@eecs.umich.edu } 12798516SMrinmoy.Ghosh@arm.com DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 12808516SMrinmoy.Ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12812132SN/A if (head_inst->traceData) { 12822292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 12838834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12844046Sbinkertn@umich.edu head_inst->traceData->dump(); 12854046Sbinkertn@umich.edu delete head_inst->traceData; 12862292SN/A head_inst->traceData = NULL; 12871060SN/A } 12888843Smrinmoy.ghosh@arm.com if (head_inst->isReturn()) { 12898843Smrinmoy.ghosh@arm.com DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 12908843Smrinmoy.ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12918843Smrinmoy.ghosh@arm.com } 12921060SN/A 12932292SN/A // Update the commit rename map 12942292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 12953771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 12962292SN/A head_inst->renamedDestRegIdx(i)); 12971060SN/A } 12981062SN/A 12992292SN/A // Finally clear the head ROB entry. 13002292SN/A rob->retireHead(tid); 13011060SN/A 13028471SGiacomo.Gabrielli@arm.com#if TRACING_ON 13039527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 13049527SMatt.Horsnell@arm.com head_inst->commitTick = curTick() - head_inst->fetchTick; 13059527SMatt.Horsnell@arm.com } 13068471SGiacomo.Gabrielli@arm.com#endif 13078471SGiacomo.Gabrielli@arm.com 13084035Sktlim@umich.edu // If this was a store, record it for this cycle. 13094035Sktlim@umich.edu if (head_inst->isStore()) 13104035Sktlim@umich.edu committedStores[tid] = true; 13114035Sktlim@umich.edu 13121060SN/A // Return true to indicate that we have committed an instruction. 13131060SN/A return true; 13141060SN/A} 13151060SN/A 13161061SN/Atemplate <class Impl> 13171060SN/Avoid 13182292SN/ADefaultCommit<Impl>::getInsts() 13191060SN/A{ 13202935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 13212935Sksewell@umich.edu 13223093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 13233093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 13242965Sksewell@umich.edu 13252965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 132613429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst = fromRename->insts[inst_num]; 13276221Snate@binkert.org ThreadID tid = inst->threadNumber; 13282292SN/A 13292292SN/A if (!inst->isSquashed() && 13304035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 13314035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 13322292SN/A changedROBNumEntries[tid] = true; 13332292SN/A 13347720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 13357720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13362292SN/A 13372292SN/A rob->insertInst(inst); 13382292SN/A 13392292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 13402292SN/A 13412292SN/A youngestSeqNum[tid] = inst->seqNum; 13421061SN/A } else { 13437720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 13441061SN/A "squashed, skipping.\n", 13457720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13461061SN/A } 13471060SN/A } 13482965Sksewell@umich.edu} 13492965Sksewell@umich.edu 13502965Sksewell@umich.edutemplate <class Impl> 13512965Sksewell@umich.eduvoid 13522292SN/ADefaultCommit<Impl>::markCompletedInsts() 13531060SN/A{ 13541060SN/A // Grab completed insts out of the IEW instruction queue, and mark 13551060SN/A // instructions completed within the ROB. 135610734Snilay@cs.wisc.edu for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) { 135710734Snilay@cs.wisc.edu assert(fromIEW->insts[inst_num]); 13582292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 13597720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 13602316SN/A "within ROB.\n", 13612292SN/A fromIEW->insts[inst_num]->threadNumber, 13627720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 13632292SN/A fromIEW->insts[inst_num]->seqNum); 13641060SN/A 13652292SN/A // Mark the instruction as ready to commit. 13662292SN/A fromIEW->insts[inst_num]->setCanCommit(); 13672292SN/A } 13681060SN/A } 13691060SN/A} 13701060SN/A 13711061SN/Atemplate <class Impl> 13722301SN/Avoid 137313429Srekai.gonzalezalberquilla@arm.comDefaultCommit<Impl>::updateComInstStats(const DynInstPtr &inst) 13742301SN/A{ 13756221Snate@binkert.org ThreadID tid = inst->threadNumber; 13762301SN/A 13778834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) 13788834Satgutier@umich.edu instsCommitted[tid]++; 13798834Satgutier@umich.edu opsCommitted[tid]++; 13802301SN/A 13819218Satgutier@umich.edu // To match the old model, don't count nops and instruction 13829218Satgutier@umich.edu // prefetches towards the total commit count. 13839218Satgutier@umich.edu if (!inst->isNop() && !inst->isInstPrefetch()) { 13849218Satgutier@umich.edu cpu->instDone(tid, inst); 13859218Satgutier@umich.edu } 13869218Satgutier@umich.edu 13872301SN/A // 13882301SN/A // Control Instructions 13892301SN/A // 13902301SN/A if (inst->isControl()) 13916221Snate@binkert.org statComBranches[tid]++; 13922301SN/A 13932301SN/A // 13942301SN/A // Memory references 13952301SN/A // 13962301SN/A if (inst->isMemRef()) { 13976221Snate@binkert.org statComRefs[tid]++; 13982301SN/A 13992301SN/A if (inst->isLoad()) { 14006221Snate@binkert.org statComLoads[tid]++; 14012301SN/A } 14022301SN/A } 14032301SN/A 14042301SN/A if (inst->isMemBarrier()) { 14056221Snate@binkert.org statComMembars[tid]++; 14062301SN/A } 14077897Shestness@cs.utexas.edu 14087897Shestness@cs.utexas.edu // Integer Instruction 14097897Shestness@cs.utexas.edu if (inst->isInteger()) 14107897Shestness@cs.utexas.edu statComInteger[tid]++; 14117897Shestness@cs.utexas.edu 14127897Shestness@cs.utexas.edu // Floating Point Instruction 14137897Shestness@cs.utexas.edu if (inst->isFloating()) 14147897Shestness@cs.utexas.edu statComFloating[tid]++; 141512110SRekai.GonzalezAlberquilla@arm.com // Vector Instruction 141612110SRekai.GonzalezAlberquilla@arm.com if (inst->isVector()) 141712110SRekai.GonzalezAlberquilla@arm.com statComVector[tid]++; 14187897Shestness@cs.utexas.edu 14197897Shestness@cs.utexas.edu // Function Calls 14207897Shestness@cs.utexas.edu if (inst->isCall()) 14217897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 14227897Shestness@cs.utexas.edu 14232301SN/A} 14242301SN/A 14252292SN/A//////////////////////////////////////// 14262292SN/A// // 14272316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 14282292SN/A// // 14292292SN/A//////////////////////////////////////// 14302292SN/Atemplate <class Impl> 14316221Snate@binkert.orgThreadID 14322292SN/ADefaultCommit<Impl>::getCommittingThread() 14332292SN/A{ 14342292SN/A if (numThreads > 1) { 14352292SN/A switch (commitPolicy) { 14362292SN/A 143713563Snikos.nikoleris@arm.com case CommitPolicy::Aggressive: 14382292SN/A //If Policy is Aggressive, commit will call 14392292SN/A //this function multiple times per 14402292SN/A //cycle 14412292SN/A return oldestReady(); 14422292SN/A 144313563Snikos.nikoleris@arm.com case CommitPolicy::RoundRobin: 14442292SN/A return roundRobin(); 14452292SN/A 144613563Snikos.nikoleris@arm.com case CommitPolicy::OldestReady: 14472292SN/A return oldestReady(); 14482292SN/A 14492292SN/A default: 14506221Snate@binkert.org return InvalidThreadID; 14512292SN/A } 14522292SN/A } else { 14533867Sbinkertn@umich.edu assert(!activeThreads->empty()); 14546221Snate@binkert.org ThreadID tid = activeThreads->front(); 14552292SN/A 14562292SN/A if (commitStatus[tid] == Running || 14572292SN/A commitStatus[tid] == Idle || 14582292SN/A commitStatus[tid] == FetchTrapPending) { 14592292SN/A return tid; 14602292SN/A } else { 14616221Snate@binkert.org return InvalidThreadID; 14622292SN/A } 14632292SN/A } 14642292SN/A} 14652292SN/A 14662292SN/Atemplate<class Impl> 14676221Snate@binkert.orgThreadID 14682292SN/ADefaultCommit<Impl>::roundRobin() 14692292SN/A{ 14706221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14716221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14722292SN/A 14732292SN/A while (pri_iter != end) { 14746221Snate@binkert.org ThreadID tid = *pri_iter; 14752292SN/A 14762292SN/A if (commitStatus[tid] == Running || 14772831Sksewell@umich.edu commitStatus[tid] == Idle || 14782831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 14792292SN/A 14802292SN/A if (rob->isHeadReady(tid)) { 14812292SN/A priority_list.erase(pri_iter); 14822292SN/A priority_list.push_back(tid); 14832292SN/A 14842292SN/A return tid; 14852292SN/A } 14862292SN/A } 14872292SN/A 14882292SN/A pri_iter++; 14892292SN/A } 14902292SN/A 14916221Snate@binkert.org return InvalidThreadID; 14922292SN/A} 14932292SN/A 14942292SN/Atemplate<class Impl> 14956221Snate@binkert.orgThreadID 14962292SN/ADefaultCommit<Impl>::oldestReady() 14972292SN/A{ 14982292SN/A unsigned oldest = 0; 14992292SN/A bool first = true; 15002292SN/A 15016221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15026221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15032292SN/A 15043867Sbinkertn@umich.edu while (threads != end) { 15056221Snate@binkert.org ThreadID tid = *threads++; 15062292SN/A 15072292SN/A if (!rob->isEmpty(tid) && 15082292SN/A (commitStatus[tid] == Running || 15092292SN/A commitStatus[tid] == Idle || 15102292SN/A commitStatus[tid] == FetchTrapPending)) { 15112292SN/A 15122292SN/A if (rob->isHeadReady(tid)) { 15132292SN/A 151413429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &head_inst = rob->readHeadInst(tid); 15152292SN/A 15162292SN/A if (first) { 15172292SN/A oldest = tid; 15182292SN/A first = false; 15192292SN/A } else if (head_inst->seqNum < oldest) { 15202292SN/A oldest = tid; 15212292SN/A } 15222292SN/A } 15232292SN/A } 15242292SN/A } 15252292SN/A 15262292SN/A if (!first) { 15272292SN/A return oldest; 15282292SN/A } else { 15296221Snate@binkert.org return InvalidThreadID; 15302292SN/A } 15312292SN/A} 15329944Smatt.horsnell@ARM.com 15339944Smatt.horsnell@ARM.com#endif//__CPU_O3_COMMIT_IMPL_HH__ 1534