commit_impl.hh revision 11246
11689SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 310331Smitch.hayenga@arm.com * Copyright (c) 2010-2014 ARM Limited 47783SGiacomo.Gabrielli@arm.com * All rights reserved 57783SGiacomo.Gabrielli@arm.com * 67783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147783SGiacomo.Gabrielli@arm.com * 152316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422965Sksewell@umich.edu * Korey Sewell 431689SN/A */ 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_COMMIT_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_COMMIT_IMPL_HH__ 461689SN/A 472292SN/A#include <algorithm> 489516SAli.Saidi@ARM.com#include <set> 492329SN/A#include <string> 502292SN/A 513577Sgblack@eecs.umich.edu#include "arch/utility.hh" 528229Snate@binkert.org#include "base/loader/symtab.hh" 535953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 561717SN/A#include "cpu/o3/commit.hh" 572292SN/A#include "cpu/o3/thread_state.hh" 588662SAli.Saidi@ARM.com#include "cpu/base.hh" 598229Snate@binkert.org#include "cpu/exetrace.hh" 608229Snate@binkert.org#include "cpu/timebuf.hh" 618232Snate@binkert.org#include "debug/Activity.hh" 628232Snate@binkert.org#include "debug/Commit.hh" 638232Snate@binkert.org#include "debug/CommitRate.hh" 649444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 658232Snate@binkert.org#include "debug/ExecFaulting.hh" 669527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 676221Snate@binkert.org#include "params/DerivO3CPU.hh" 688230Snate@binkert.org#include "sim/faults.hh" 698793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 702292SN/A 716221Snate@binkert.orgusing namespace std; 725529Snate@binkert.org 731061SN/Atemplate <class Impl> 742292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 756221Snate@binkert.org ThreadID _tid) 768581Ssteve.reinhardt@amd.com : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 771060SN/A{ 781060SN/A} 791060SN/A 801061SN/Atemplate <class Impl> 811060SN/Avoid 822292SN/ADefaultCommit<Impl>::TrapEvent::process() 831062SN/A{ 842316SN/A // This will get reset by commit if it was switched out at the 852316SN/A // time of this event processing. 862292SN/A commit->trapSquash[tid] = true; 872292SN/A} 882292SN/A 892292SN/Atemplate <class Impl> 902292SN/Aconst char * 915336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 922292SN/A{ 934873Sstever@eecs.umich.edu return "Trap"; 942292SN/A} 952292SN/A 962292SN/Atemplate <class Impl> 975529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 984329Sktlim@umich.edu : cpu(_cpu), 992292SN/A iewToCommitDelay(params->iewToCommitDelay), 1002292SN/A commitToIEWDelay(params->commitToIEWDelay), 1012292SN/A renameToROBDelay(params->renameToROBDelay), 1022292SN/A fetchToCommitDelay(params->commitToFetchDelay), 1032292SN/A renameWidth(params->renameWidth), 1042292SN/A commitWidth(params->commitWidth), 1055529Snate@binkert.org numThreads(params->numThreads), 1062843Sktlim@umich.edu drainPending(false), 10710340Smitch.hayenga@arm.com drainImminent(false), 1088823Snilay@cs.wisc.edu trapLatency(params->trapLatency), 1099513SAli.Saidi@ARM.com canHandleInterrupts(true), 1109513SAli.Saidi@ARM.com avoidQuiesceLiveLock(false) 1112292SN/A{ 11210172Sdam.sunwoo@arm.com if (commitWidth > Impl::MaxWidth) 11310172Sdam.sunwoo@arm.com fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 11410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 11510172Sdam.sunwoo@arm.com commitWidth, static_cast<int>(Impl::MaxWidth)); 11610172Sdam.sunwoo@arm.com 1172292SN/A _status = Active; 1182292SN/A _nextStatus = Inactive; 1192980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1202292SN/A 1212292SN/A //Convert string to lowercase 1222292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1232292SN/A (int(*)(int)) tolower); 1242292SN/A 1252292SN/A //Assign commit policy 1262292SN/A if (policy == "aggressive"){ 1272292SN/A commitPolicy = Aggressive; 1282292SN/A 1298346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 1302292SN/A } else if (policy == "roundrobin"){ 1312292SN/A commitPolicy = RoundRobin; 1322292SN/A 1332292SN/A //Set-Up Priority List 1346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1352292SN/A priority_list.push_back(tid); 1362292SN/A } 1372292SN/A 1388346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 1392292SN/A } else if (policy == "oldestready"){ 1402292SN/A commitPolicy = OldestReady; 1412292SN/A 1424329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1432292SN/A } else { 1442292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1452292SN/A "RoundRobin,OldestReady}"); 1462292SN/A } 1472292SN/A 1486221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1496221Snate@binkert.org commitStatus[tid] = Idle; 1506221Snate@binkert.org changedROBNumEntries[tid] = false; 1516221Snate@binkert.org checkEmptyROB[tid] = false; 1526221Snate@binkert.org trapInFlight[tid] = false; 1536221Snate@binkert.org committedStores[tid] = false; 1546221Snate@binkert.org trapSquash[tid] = false; 1556221Snate@binkert.org tcSquash[tid] = false; 1567720Sgblack@eecs.umich.edu pc[tid].set(0); 1577855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = 0; 1589437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 1592292SN/A } 1603640Sktlim@umich.edu interrupt = NoFault; 1612292SN/A} 1622292SN/A 1632292SN/Atemplate <class Impl> 1642292SN/Astd::string 1652292SN/ADefaultCommit<Impl>::name() const 1662292SN/A{ 1672292SN/A return cpu->name() + ".commit"; 1682292SN/A} 1692292SN/A 1702292SN/Atemplate <class Impl> 1712292SN/Avoid 17210023Smatt.horsnell@ARM.comDefaultCommit<Impl>::regProbePoints() 17310023Smatt.horsnell@ARM.com{ 17410023Smatt.horsnell@ARM.com ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 17510023Smatt.horsnell@ARM.com ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 17611246Sradhika.jagtap@ARM.com ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash"); 17710023Smatt.horsnell@ARM.com} 17810023Smatt.horsnell@ARM.com 17910023Smatt.horsnell@ARM.comtemplate <class Impl> 18010023Smatt.horsnell@ARM.comvoid 1812292SN/ADefaultCommit<Impl>::regStats() 1822132SN/A{ 1832301SN/A using namespace Stats; 1841062SN/A commitSquashedInsts 1851062SN/A .name(name() + ".commitSquashedInsts") 1861062SN/A .desc("The number of squashed insts skipped by commit") 1871062SN/A .prereq(commitSquashedInsts); 18810731Snilay@cs.wisc.edu 1891062SN/A commitNonSpecStalls 1901062SN/A .name(name() + ".commitNonSpecStalls") 1911062SN/A .desc("The number of times commit has been forced to stall to " 1921062SN/A "communicate backwards") 1931062SN/A .prereq(commitNonSpecStalls); 19410731Snilay@cs.wisc.edu 1951062SN/A branchMispredicts 1961062SN/A .name(name() + ".branchMispredicts") 1971062SN/A .desc("The number of times a branch was mispredicted") 1981062SN/A .prereq(branchMispredicts); 19910731Snilay@cs.wisc.edu 2002292SN/A numCommittedDist 2011062SN/A .init(0,commitWidth,1) 2028240Snate@binkert.org .name(name() + ".committed_per_cycle") 2031062SN/A .desc("Number of insts commited each cycle") 2041062SN/A .flags(Stats::pdf) 2051062SN/A ; 2062301SN/A 2078834Satgutier@umich.edu instsCommitted 2086221Snate@binkert.org .init(cpu->numThreads) 2098834Satgutier@umich.edu .name(name() + ".committedInsts") 2102301SN/A .desc("Number of instructions committed") 2112301SN/A .flags(total) 2122301SN/A ; 2132301SN/A 2148834Satgutier@umich.edu opsCommitted 2158834Satgutier@umich.edu .init(cpu->numThreads) 2168834Satgutier@umich.edu .name(name() + ".committedOps") 2178834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 2188834Satgutier@umich.edu .flags(total) 2198834Satgutier@umich.edu ; 2208834Satgutier@umich.edu 2212316SN/A statComSwp 2226221Snate@binkert.org .init(cpu->numThreads) 2238240Snate@binkert.org .name(name() + ".swp_count") 2242301SN/A .desc("Number of s/w prefetches committed") 2252301SN/A .flags(total) 2262301SN/A ; 2272301SN/A 2282316SN/A statComRefs 2296221Snate@binkert.org .init(cpu->numThreads) 2308240Snate@binkert.org .name(name() + ".refs") 2312301SN/A .desc("Number of memory references committed") 2322301SN/A .flags(total) 2332301SN/A ; 2342301SN/A 2352316SN/A statComLoads 2366221Snate@binkert.org .init(cpu->numThreads) 2378240Snate@binkert.org .name(name() + ".loads") 2382301SN/A .desc("Number of loads committed") 2392301SN/A .flags(total) 2402301SN/A ; 2412301SN/A 2422316SN/A statComMembars 2436221Snate@binkert.org .init(cpu->numThreads) 2448240Snate@binkert.org .name(name() + ".membars") 2452301SN/A .desc("Number of memory barriers committed") 2462301SN/A .flags(total) 2472301SN/A ; 2482301SN/A 2492316SN/A statComBranches 2506221Snate@binkert.org .init(cpu->numThreads) 2518240Snate@binkert.org .name(name() + ".branches") 2522301SN/A .desc("Number of branches committed") 2532301SN/A .flags(total) 2542301SN/A ; 2552301SN/A 2567897Shestness@cs.utexas.edu statComFloating 2577897Shestness@cs.utexas.edu .init(cpu->numThreads) 2588240Snate@binkert.org .name(name() + ".fp_insts") 2597897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2607897Shestness@cs.utexas.edu .flags(total) 2617897Shestness@cs.utexas.edu ; 2627897Shestness@cs.utexas.edu 2637897Shestness@cs.utexas.edu statComInteger 2647897Shestness@cs.utexas.edu .init(cpu->numThreads) 2658240Snate@binkert.org .name(name()+".int_insts") 2667897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2677897Shestness@cs.utexas.edu .flags(total) 2687897Shestness@cs.utexas.edu ; 2697897Shestness@cs.utexas.edu 2707897Shestness@cs.utexas.edu statComFunctionCalls 2717897Shestness@cs.utexas.edu .init(cpu->numThreads) 2728240Snate@binkert.org .name(name()+".function_calls") 2737897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2747897Shestness@cs.utexas.edu .flags(total) 2757897Shestness@cs.utexas.edu ; 2767897Shestness@cs.utexas.edu 27710193SCurtis.Dunham@arm.com statCommittedInstType 27810193SCurtis.Dunham@arm.com .init(numThreads,Enums::Num_OpClass) 27910193SCurtis.Dunham@arm.com .name(name() + ".op_class") 28010193SCurtis.Dunham@arm.com .desc("Class of committed instruction") 28110193SCurtis.Dunham@arm.com .flags(total | pdf | dist) 28210193SCurtis.Dunham@arm.com ; 28310193SCurtis.Dunham@arm.com statCommittedInstType.ysubnames(Enums::OpClassStrings); 28410193SCurtis.Dunham@arm.com 2852316SN/A commitEligibleSamples 2868240Snate@binkert.org .name(name() + ".bw_lim_events") 2872301SN/A .desc("number cycles where commit BW limit reached") 2882301SN/A ; 2891062SN/A} 2901062SN/A 2911062SN/Atemplate <class Impl> 2921062SN/Avoid 2932980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2942292SN/A{ 2952292SN/A thread = threads; 2962292SN/A} 2972292SN/A 2982292SN/Atemplate <class Impl> 2992292SN/Avoid 3002292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3011060SN/A{ 3021060SN/A timeBuffer = tb_ptr; 3031060SN/A 3041060SN/A // Setup wire to send information back to IEW. 3051060SN/A toIEW = timeBuffer->getWire(0); 3061060SN/A 3071060SN/A // Setup wire to read data from IEW (for the ROB). 3081060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 3091060SN/A} 3101060SN/A 3111061SN/Atemplate <class Impl> 3121060SN/Avoid 3132292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 3142292SN/A{ 3152292SN/A fetchQueue = fq_ptr; 3162292SN/A 3172292SN/A // Setup wire to get instructions from rename (for the ROB). 3182292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 3192292SN/A} 3202292SN/A 3212292SN/Atemplate <class Impl> 3222292SN/Avoid 3232292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3241060SN/A{ 3251060SN/A renameQueue = rq_ptr; 3261060SN/A 3271060SN/A // Setup wire to get instructions from rename (for the ROB). 3281060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3291060SN/A} 3301060SN/A 3311061SN/Atemplate <class Impl> 3321060SN/Avoid 3332292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3341060SN/A{ 3351060SN/A iewQueue = iq_ptr; 3361060SN/A 3371060SN/A // Setup wire to get instructions from IEW. 3381060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3391060SN/A} 3401060SN/A 3411061SN/Atemplate <class Impl> 3421060SN/Avoid 3432292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3442292SN/A{ 3452292SN/A iewStage = iew_stage; 3462292SN/A} 3472292SN/A 3482292SN/Atemplate<class Impl> 3492292SN/Avoid 3506221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3512292SN/A{ 3522292SN/A activeThreads = at_ptr; 3532292SN/A} 3542292SN/A 3552292SN/Atemplate <class Impl> 3562292SN/Avoid 3572292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3582292SN/A{ 3596221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3606221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3612292SN/A} 3622292SN/A 3632292SN/Atemplate <class Impl> 3642292SN/Avoid 3652292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3661060SN/A{ 3671060SN/A rob = rob_ptr; 3681060SN/A} 3691060SN/A 3701061SN/Atemplate <class Impl> 3711060SN/Avoid 3729427SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::startupStage() 3731060SN/A{ 3742292SN/A rob->setActiveThreads(activeThreads); 3752292SN/A rob->resetEntries(); 3761060SN/A 3772292SN/A // Broadcast the number of free entries. 3786221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3796221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3806221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3816221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3821060SN/A } 3831060SN/A 3844329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3854329Sktlim@umich.edu // start of the simulation, so it starts as active. 3864329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3874329Sktlim@umich.edu 3882292SN/A cpu->activityThisCycle(); 3891060SN/A} 3901060SN/A 3911061SN/Atemplate <class Impl> 3929444SAndreas.Sandberg@ARM.comvoid 3932843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3941060SN/A{ 3952843Sktlim@umich.edu drainPending = true; 3962316SN/A} 3972316SN/A 3982316SN/Atemplate <class Impl> 3992316SN/Avoid 4009444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainResume() 4012843Sktlim@umich.edu{ 4022864Sktlim@umich.edu drainPending = false; 40310340Smitch.hayenga@arm.com drainImminent = false; 4042843Sktlim@umich.edu} 4052843Sktlim@umich.edu 4062843Sktlim@umich.edutemplate <class Impl> 4072843Sktlim@umich.eduvoid 4089444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainSanityCheck() const 4099444SAndreas.Sandberg@ARM.com{ 4109444SAndreas.Sandberg@ARM.com assert(isDrained()); 4119444SAndreas.Sandberg@ARM.com rob->drainSanityCheck(); 4129444SAndreas.Sandberg@ARM.com} 4139444SAndreas.Sandberg@ARM.com 4149444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4159444SAndreas.Sandberg@ARM.combool 4169444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::isDrained() const 4179444SAndreas.Sandberg@ARM.com{ 4189444SAndreas.Sandberg@ARM.com /* Make sure no one is executing microcode. There are two reasons 4199444SAndreas.Sandberg@ARM.com * for this: 4209444SAndreas.Sandberg@ARM.com * - Hardware virtualized CPUs can't switch into the middle of a 4219444SAndreas.Sandberg@ARM.com * microcode sequence. 4229444SAndreas.Sandberg@ARM.com * - The current fetch implementation will most likely get very 4239444SAndreas.Sandberg@ARM.com * confused if it tries to start fetching an instruction that 4249444SAndreas.Sandberg@ARM.com * is executing in the middle of a ucode sequence that changes 4259444SAndreas.Sandberg@ARM.com * address mappings. This can happen on for example x86. 4269444SAndreas.Sandberg@ARM.com */ 4279444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 4289444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() != 0) 4299444SAndreas.Sandberg@ARM.com return false; 4309444SAndreas.Sandberg@ARM.com } 4319444SAndreas.Sandberg@ARM.com 4329444SAndreas.Sandberg@ARM.com /* Make sure that all instructions have finished committing before 4339444SAndreas.Sandberg@ARM.com * declaring the system as drained. We want the pipeline to be 4349444SAndreas.Sandberg@ARM.com * completely empty when we declare the CPU to be drained. This 4359444SAndreas.Sandberg@ARM.com * makes debugging easier since CPU handover and restoring from a 4369444SAndreas.Sandberg@ARM.com * checkpoint with a different CPU should have the same timing. 4379444SAndreas.Sandberg@ARM.com */ 4389444SAndreas.Sandberg@ARM.com return rob->isEmpty() && 4399444SAndreas.Sandberg@ARM.com interrupt == NoFault; 4409444SAndreas.Sandberg@ARM.com} 4419444SAndreas.Sandberg@ARM.com 4429444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4439444SAndreas.Sandberg@ARM.comvoid 4442307SN/ADefaultCommit<Impl>::takeOverFrom() 4452307SN/A{ 4462307SN/A _status = Active; 4472307SN/A _nextStatus = Inactive; 4486221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4496221Snate@binkert.org commitStatus[tid] = Idle; 4506221Snate@binkert.org changedROBNumEntries[tid] = false; 4516221Snate@binkert.org trapSquash[tid] = false; 4526221Snate@binkert.org tcSquash[tid] = false; 4539437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 4542307SN/A } 4552307SN/A rob->takeOverFrom(); 4562307SN/A} 4572307SN/A 4582307SN/Atemplate <class Impl> 4592307SN/Avoid 46010331Smitch.hayenga@arm.comDefaultCommit<Impl>::deactivateThread(ThreadID tid) 46110331Smitch.hayenga@arm.com{ 46210331Smitch.hayenga@arm.com list<ThreadID>::iterator thread_it = std::find(priority_list.begin(), 46310331Smitch.hayenga@arm.com priority_list.end(), tid); 46410331Smitch.hayenga@arm.com 46510331Smitch.hayenga@arm.com if (thread_it != priority_list.end()) { 46610331Smitch.hayenga@arm.com priority_list.erase(thread_it); 46710331Smitch.hayenga@arm.com } 46810331Smitch.hayenga@arm.com} 46910331Smitch.hayenga@arm.com 47010331Smitch.hayenga@arm.com 47110331Smitch.hayenga@arm.comtemplate <class Impl> 47210331Smitch.hayenga@arm.comvoid 4732292SN/ADefaultCommit<Impl>::updateStatus() 4742132SN/A{ 4752316SN/A // reset ROB changed variable 4766221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4776221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4783867Sbinkertn@umich.edu 4793867Sbinkertn@umich.edu while (threads != end) { 4806221Snate@binkert.org ThreadID tid = *threads++; 4813867Sbinkertn@umich.edu 4822316SN/A changedROBNumEntries[tid] = false; 4832316SN/A 4842316SN/A // Also check if any of the threads has a trap pending 4852316SN/A if (commitStatus[tid] == TrapPending || 4862316SN/A commitStatus[tid] == FetchTrapPending) { 4872316SN/A _nextStatus = Active; 4882316SN/A } 4892292SN/A } 4902292SN/A 4912292SN/A if (_nextStatus == Inactive && _status == Active) { 4922292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4932733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4942292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4952292SN/A DPRINTF(Activity, "Activating stage.\n"); 4962733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4972292SN/A } 4982292SN/A 4992292SN/A _status = _nextStatus; 5002292SN/A} 5012292SN/A 5022292SN/Atemplate <class Impl> 5032292SN/Abool 5042292SN/ADefaultCommit<Impl>::changedROBEntries() 5052292SN/A{ 5066221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5076221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5082292SN/A 5093867Sbinkertn@umich.edu while (threads != end) { 5106221Snate@binkert.org ThreadID tid = *threads++; 5112292SN/A 5122292SN/A if (changedROBNumEntries[tid]) { 5132292SN/A return true; 5142292SN/A } 5152292SN/A } 5162292SN/A 5172292SN/A return false; 5182292SN/A} 5192292SN/A 5202292SN/Atemplate <class Impl> 5216221Snate@binkert.orgsize_t 5226221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 5232292SN/A{ 5242292SN/A return rob->numFreeEntries(tid); 5252292SN/A} 5262292SN/A 5272292SN/Atemplate <class Impl> 5282292SN/Avoid 5296221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 5302292SN/A{ 5312292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5322292SN/A 5332292SN/A TrapEvent *trap = new TrapEvent(this, tid); 5342292SN/A 5359179Sandreas.hansson@arm.com cpu->schedule(trap, cpu->clockEdge(trapLatency)); 5364035Sktlim@umich.edu trapInFlight[tid] = true; 5378518Sgeoffrey.blake@arm.com thread[tid]->trapPending = true; 5382292SN/A} 5392292SN/A 5402292SN/Atemplate <class Impl> 5412292SN/Avoid 5426221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5432292SN/A{ 5444035Sktlim@umich.edu assert(!trapInFlight[tid]); 5452680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5462292SN/A 5472680Sktlim@umich.edu tcSquash[tid] = true; 5482292SN/A} 5492292SN/A 5502292SN/Atemplate <class Impl> 5512292SN/Avoid 5526221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5532292SN/A{ 5542292SN/A // If we want to include the squashing instruction in the squash, 5552292SN/A // then use one older sequence number. 5562292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5572292SN/A // all instructions of this thread. 55810164Ssleimanf@umich.edu InstSeqNum squashed_inst = rob->isEmpty(tid) ? 5597855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5602292SN/A 5612292SN/A // All younger instructions will be squashed. Set the sequence 5622292SN/A // number as the youngest instruction in the ROB (0 in this case. 5632292SN/A // Hopefully nothing breaks.) 5647855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5652292SN/A 5662292SN/A rob->squash(squashed_inst, tid); 5672292SN/A changedROBNumEntries[tid] = true; 5682292SN/A 5692292SN/A // Send back the sequence number of the squashed instruction. 5702292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5712292SN/A 5722292SN/A // Send back the squash signal to tell stages that they should 5732292SN/A // squash. 5742292SN/A toIEW->commitInfo[tid].squash = true; 5752292SN/A 5762292SN/A // Send back the rob squashing signal so other stages know that 5772292SN/A // the ROB is in the process of squashing. 5782292SN/A toIEW->commitInfo[tid].robSquashing = true; 5792292SN/A 5807851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 5818137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 5822292SN/A 5837720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5842316SN/A} 5852292SN/A 5862316SN/Atemplate <class Impl> 5872316SN/Avoid 5886221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5892316SN/A{ 5902316SN/A squashAll(tid); 5912316SN/A 5927720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5932316SN/A 5942316SN/A thread[tid]->trapPending = false; 5959382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 5964035Sktlim@umich.edu trapInFlight[tid] = false; 5972316SN/A 5982316SN/A trapSquash[tid] = false; 5992316SN/A 6002316SN/A commitStatus[tid] = ROBSquashing; 6012316SN/A cpu->activityThisCycle(); 6022316SN/A} 6032316SN/A 6042316SN/Atemplate <class Impl> 6052316SN/Avoid 6066221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 6072316SN/A{ 6082316SN/A squashAll(tid); 6092292SN/A 6107720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 6112292SN/A 6129382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6132292SN/A assert(!thread[tid]->trapPending); 6142316SN/A 6152292SN/A commitStatus[tid] = ROBSquashing; 6162292SN/A cpu->activityThisCycle(); 6172292SN/A 6182680Sktlim@umich.edu tcSquash[tid] = false; 6192292SN/A} 6202292SN/A 6212292SN/Atemplate <class Impl> 6222292SN/Avoid 6239437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 6247784SAli.Saidi@ARM.com{ 6259437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Squashing after squash after request, " 6269437SAndreas.Sandberg@ARM.com "restarting at PC %s\n", pc[tid]); 6277784SAli.Saidi@ARM.com 6289437SAndreas.Sandberg@ARM.com squashAll(tid); 6299437SAndreas.Sandberg@ARM.com // Make sure to inform the fetch stage of which instruction caused 6309437SAndreas.Sandberg@ARM.com // the squash. It'll try to re-fetch an instruction executing in 6319437SAndreas.Sandberg@ARM.com // microcode unless this is set. 6329437SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 6339437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 6347784SAli.Saidi@ARM.com 6359437SAndreas.Sandberg@ARM.com commitStatus[tid] = ROBSquashing; 6369437SAndreas.Sandberg@ARM.com cpu->activityThisCycle(); 6379437SAndreas.Sandberg@ARM.com} 6387784SAli.Saidi@ARM.com 6399437SAndreas.Sandberg@ARM.comtemplate <class Impl> 6409437SAndreas.Sandberg@ARM.comvoid 6419437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst) 6429437SAndreas.Sandberg@ARM.com{ 6439437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6449437SAndreas.Sandberg@ARM.com tid, head_inst->seqNum); 6457784SAli.Saidi@ARM.com 6469437SAndreas.Sandberg@ARM.com assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 6479437SAndreas.Sandberg@ARM.com commitStatus[tid] = SquashAfterPending; 6489437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = head_inst; 6497784SAli.Saidi@ARM.com} 6507784SAli.Saidi@ARM.com 6517784SAli.Saidi@ARM.comtemplate <class Impl> 6527784SAli.Saidi@ARM.comvoid 6532292SN/ADefaultCommit<Impl>::tick() 6542292SN/A{ 6552292SN/A wroteToTimeBuffer = false; 6562292SN/A _nextStatus = Inactive; 6572292SN/A 6583867Sbinkertn@umich.edu if (activeThreads->empty()) 6592875Sksewell@umich.edu return; 6602875Sksewell@umich.edu 6616221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6626221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6632292SN/A 6642316SN/A // Check if any of the threads are done squashing. Change the 6652316SN/A // status if they are done. 6663867Sbinkertn@umich.edu while (threads != end) { 6676221Snate@binkert.org ThreadID tid = *threads++; 6682292SN/A 6694035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6704035Sktlim@umich.edu // this cycle. 6714035Sktlim@umich.edu committedStores[tid] = false; 6724035Sktlim@umich.edu 6732292SN/A if (commitStatus[tid] == ROBSquashing) { 6742292SN/A 6752292SN/A if (rob->isDoneSquashing(tid)) { 6762292SN/A commitStatus[tid] = Running; 6772292SN/A } else { 6782292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6792877Sksewell@umich.edu " insts this cycle.\n", tid); 6802702Sktlim@umich.edu rob->doSquash(tid); 6812702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6822702Sktlim@umich.edu wroteToTimeBuffer = true; 6832292SN/A } 6842292SN/A } 6852292SN/A } 6862292SN/A 6872292SN/A commit(); 6882292SN/A 6892292SN/A markCompletedInsts(); 6902292SN/A 6913867Sbinkertn@umich.edu threads = activeThreads->begin(); 6922292SN/A 6933867Sbinkertn@umich.edu while (threads != end) { 6946221Snate@binkert.org ThreadID tid = *threads++; 6952292SN/A 6962292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6972292SN/A // The ROB has more instructions it can commit. Its next status 6982292SN/A // will be active. 6992292SN/A _nextStatus = Active; 7002292SN/A 7012292SN/A DynInstPtr inst = rob->readHeadInst(tid); 7022292SN/A 7037720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 7042292SN/A " ROB and ready to commit\n", 7057720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7062292SN/A 7072292SN/A } else if (!rob->isEmpty(tid)) { 7082292SN/A DynInstPtr inst = rob->readHeadInst(tid); 7092292SN/A 71010023Smatt.horsnell@ARM.com ppCommitStall->notify(inst); 71110023Smatt.horsnell@ARM.com 7122292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 7137720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 7147720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7152292SN/A } 7162292SN/A 7172292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 7182292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 7192292SN/A } 7202292SN/A 7212292SN/A 7222292SN/A if (wroteToTimeBuffer) { 7232316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 7242292SN/A cpu->activityThisCycle(); 7252292SN/A } 7262292SN/A 7272292SN/A updateStatus(); 7282292SN/A} 7292292SN/A 7302292SN/Atemplate <class Impl> 7312292SN/Avoid 7324035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 7332292SN/A{ 7347847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7357847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7367847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7377847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7387847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7397847Sminkyu.jeong@arm.com interrupt = NoFault; 7409513SAli.Saidi@ARM.com avoidQuiesceLiveLock = true; 7417847Sminkyu.jeong@arm.com return; 7427847Sminkyu.jeong@arm.com } 7433633Sktlim@umich.edu 7448493Sgblack@eecs.umich.edu // Wait until all in flight instructions are finished before enterring 7458493Sgblack@eecs.umich.edu // the interrupt. 7468823Snilay@cs.wisc.edu if (canHandleInterrupts && cpu->instList.empty()) { 7477847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7487847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7497847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7504035Sktlim@umich.edu 7517847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7527847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7532292SN/A 7549382SAli.Saidi@ARM.com assert(!thread[0]->noSquashFromTC); 7559382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = true; 7562292SN/A 7578733Sgeoffrey.blake@arm.com if (cpu->checker) { 7588733Sgeoffrey.blake@arm.com cpu->checker->handlePendingInt(); 7598733Sgeoffrey.blake@arm.com } 7608733Sgeoffrey.blake@arm.com 7619624Snilay@cs.wisc.edu // CPU will handle interrupt. Note that we ignore the local copy of 7629624Snilay@cs.wisc.edu // interrupt. This is because the local copy may no longer be the 7639624Snilay@cs.wisc.edu // interrupt that the interrupt controller thinks is being handled. 7649624Snilay@cs.wisc.edu cpu->processInterrupts(cpu->getInterrupts()); 7653633Sktlim@umich.edu 7669382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = false; 7672292SN/A 7687847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7692292SN/A 7707847Sminkyu.jeong@arm.com // Generate trap squash event. 7717847Sminkyu.jeong@arm.com generateTrapEvent(0); 7723640Sktlim@umich.edu 7737847Sminkyu.jeong@arm.com interrupt = NoFault; 7749513SAli.Saidi@ARM.com avoidQuiesceLiveLock = false; 7757847Sminkyu.jeong@arm.com } else { 7768823Snilay@cs.wisc.edu DPRINTF(Commit, "Interrupt pending: instruction is %sin " 7778823Snilay@cs.wisc.edu "flight, ROB is %sempty\n", 7788823Snilay@cs.wisc.edu canHandleInterrupts ? "not " : "", 7798823Snilay@cs.wisc.edu cpu->instList.empty() ? "" : "not " ); 7801060SN/A } 7814035Sktlim@umich.edu} 7827847Sminkyu.jeong@arm.com 7837847Sminkyu.jeong@arm.comtemplate <class Impl> 7847847Sminkyu.jeong@arm.comvoid 7857847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 7867847Sminkyu.jeong@arm.com{ 78710340Smitch.hayenga@arm.com // Don't propagate intterupts if we are currently handling a trap or 78810340Smitch.hayenga@arm.com // in draining and the last observable instruction has been committed. 7897847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 79010340Smitch.hayenga@arm.com tcSquash[0] || drainImminent) 7917847Sminkyu.jeong@arm.com return; 7927847Sminkyu.jeong@arm.com 7937847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 7947847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 7957847Sminkyu.jeong@arm.com // pending. 7967847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 7977847Sminkyu.jeong@arm.com 7987847Sminkyu.jeong@arm.com // Get any interrupt that happened 7997847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 8007847Sminkyu.jeong@arm.com 8017847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 8027847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 8037847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 8047847Sminkyu.jeong@arm.com if (interrupt != NoFault) 8057847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 8067847Sminkyu.jeong@arm.com} 8077847Sminkyu.jeong@arm.com 8084035Sktlim@umich.edutemplate <class Impl> 8094035Sktlim@umich.eduvoid 8104035Sktlim@umich.eduDefaultCommit<Impl>::commit() 8114035Sktlim@umich.edu{ 8128793Sgblack@eecs.umich.edu if (FullSystem) { 8138793Sgblack@eecs.umich.edu // Check if we have a interrupt and get read to handle it 8148793Sgblack@eecs.umich.edu if (cpu->checkInterrupts(cpu->tcBase(0))) 8158793Sgblack@eecs.umich.edu propagateInterrupt(); 8168793Sgblack@eecs.umich.edu } 8171060SN/A 8181060SN/A //////////////////////////////////// 8192316SN/A // Check for any possible squashes, handle them first 8201060SN/A //////////////////////////////////// 8216221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8226221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8231060SN/A 82410729Snilay@cs.wisc.edu int num_squashing_threads = 0; 82510729Snilay@cs.wisc.edu 8263867Sbinkertn@umich.edu while (threads != end) { 8276221Snate@binkert.org ThreadID tid = *threads++; 8281060SN/A 8292292SN/A // Not sure which one takes priority. I think if we have 8302292SN/A // both, that's a bad sign. 83110231Ssteve.reinhardt@amd.com if (trapSquash[tid]) { 8322680Sktlim@umich.edu assert(!tcSquash[tid]); 8332292SN/A squashFromTrap(tid); 83410231Ssteve.reinhardt@amd.com } else if (tcSquash[tid]) { 8354035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 8362680Sktlim@umich.edu squashFromTC(tid); 8379437SAndreas.Sandberg@ARM.com } else if (commitStatus[tid] == SquashAfterPending) { 8389437SAndreas.Sandberg@ARM.com // A squash from the previous cycle of the commit stage (i.e., 8399437SAndreas.Sandberg@ARM.com // commitInsts() called squashAfter) is pending. Squash the 8409437SAndreas.Sandberg@ARM.com // thread now. 8419437SAndreas.Sandberg@ARM.com squashFromSquashAfter(tid); 8422292SN/A } 8431061SN/A 8442292SN/A // Squashed sequence number must be older than youngest valid 8452292SN/A // instruction in the ROB. This prevents squashes from younger 8462292SN/A // instructions overriding squashes from older instructions. 8472292SN/A if (fromIEW->squash[tid] && 8482292SN/A commitStatus[tid] != TrapPending && 8492292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8501061SN/A 8518137SAli.Saidi@ARM.com if (fromIEW->mispredictInst[tid]) { 8528137SAli.Saidi@ARM.com DPRINTF(Commit, 8538137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 8542292SN/A tid, 8558137SAli.Saidi@ARM.com fromIEW->mispredictInst[tid]->instAddr(), 8562292SN/A fromIEW->squashedSeqNum[tid]); 8578137SAli.Saidi@ARM.com } else { 8588137SAli.Saidi@ARM.com DPRINTF(Commit, 8598137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to order violation [sn:%i]\n", 8608137SAli.Saidi@ARM.com tid, fromIEW->squashedSeqNum[tid]); 8618137SAli.Saidi@ARM.com } 8621061SN/A 8632292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8642292SN/A tid, 8657720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8661061SN/A 8672292SN/A commitStatus[tid] = ROBSquashing; 8681061SN/A 8692292SN/A // If we want to include the squashing instruction in the squash, 8702292SN/A // then use one older sequence number. 8712292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8721062SN/A 87310231Ssteve.reinhardt@amd.com if (fromIEW->includeSquashInst[tid]) { 8742292SN/A squashed_inst--; 8752935Sksewell@umich.edu } 8764035Sktlim@umich.edu 8772292SN/A // All younger instructions will be squashed. Set the sequence 8782292SN/A // number as the youngest instruction in the ROB. 8792292SN/A youngestSeqNum[tid] = squashed_inst; 8802292SN/A 8813093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8822292SN/A changedROBNumEntries[tid] = true; 8832292SN/A 8842292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8852292SN/A 8862292SN/A toIEW->commitInfo[tid].squash = true; 8872292SN/A 8882292SN/A // Send back the rob squashing signal so other stages know that 8892292SN/A // the ROB is in the process of squashing. 8902292SN/A toIEW->commitInfo[tid].robSquashing = true; 8912292SN/A 8927851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 8937851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 8942292SN/A toIEW->commitInfo[tid].branchTaken = 8952292SN/A fromIEW->branchTaken[tid]; 8968822Snilay@cs.wisc.edu toIEW->commitInfo[tid].squashInst = 8978822Snilay@cs.wisc.edu rob->findInst(tid, squashed_inst); 8988842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst) { 8998842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 9008842Smrinmoy.ghosh@arm.com toIEW->commitInfo[tid].branchTaken = true; 9018842Smrinmoy.ghosh@arm.com } 90210730Snilay@cs.wisc.edu ++branchMispredicts; 9038842Smrinmoy.ghosh@arm.com } 9042292SN/A 9057720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 9061062SN/A } 9072292SN/A 90810729Snilay@cs.wisc.edu if (commitStatus[tid] == ROBSquashing) { 90910729Snilay@cs.wisc.edu num_squashing_threads++; 91010729Snilay@cs.wisc.edu } 9111060SN/A } 9121060SN/A 91310729Snilay@cs.wisc.edu // If commit is currently squashing, then it will have activity for the 91410729Snilay@cs.wisc.edu // next cycle. Set its next status as active. 91510729Snilay@cs.wisc.edu if (num_squashing_threads) { 91610729Snilay@cs.wisc.edu _nextStatus = Active; 91710729Snilay@cs.wisc.edu } 9182292SN/A 91910729Snilay@cs.wisc.edu if (num_squashing_threads != numThreads) { 9201061SN/A // If we're not currently squashing, then get instructions. 9211060SN/A getInsts(); 9221060SN/A 9231061SN/A // Try to commit any instructions. 9241060SN/A commitInsts(); 9251060SN/A } 9261060SN/A 9272292SN/A //Check for any activity 9283867Sbinkertn@umich.edu threads = activeThreads->begin(); 9292292SN/A 9303867Sbinkertn@umich.edu while (threads != end) { 9316221Snate@binkert.org ThreadID tid = *threads++; 9322292SN/A 9332292SN/A if (changedROBNumEntries[tid]) { 9342292SN/A toIEW->commitInfo[tid].usedROB = true; 9352292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9362292SN/A 9372292SN/A wroteToTimeBuffer = true; 9382292SN/A changedROBNumEntries[tid] = false; 9394035Sktlim@umich.edu if (rob->isEmpty(tid)) 9404035Sktlim@umich.edu checkEmptyROB[tid] = true; 9412292SN/A } 9424035Sktlim@umich.edu 9434035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 9444035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 9454035Sktlim@umich.edu // stage has received any information regarding stores that 9464035Sktlim@umich.edu // committed. 9474035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 9484035Sktlim@umich.edu // on the same cycle as when stores have been committed. 9494035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 9504035Sktlim@umich.edu // commit and IEW. 9514035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9525557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9534035Sktlim@umich.edu checkEmptyROB[tid] = false; 9544035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 9554035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 9564035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9574035Sktlim@umich.edu wroteToTimeBuffer = true; 9584035Sktlim@umich.edu } 9594035Sktlim@umich.edu 9601060SN/A } 9611060SN/A} 9621060SN/A 9631061SN/Atemplate <class Impl> 9641060SN/Avoid 9652292SN/ADefaultCommit<Impl>::commitInsts() 9661060SN/A{ 9671060SN/A //////////////////////////////////// 9681060SN/A // Handle commit 9692316SN/A // Note that commit will be handled prior to putting new 9702316SN/A // instructions in the ROB so that the ROB only tries to commit 9712316SN/A // instructions it has in this current cycle, and not instructions 9722316SN/A // it is writing in during this cycle. Can't commit and squash 9732316SN/A // things at the same time... 9741060SN/A //////////////////////////////////// 9751060SN/A 9762292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9771060SN/A 9781060SN/A unsigned num_committed = 0; 9791060SN/A 9802292SN/A DynInstPtr head_inst; 9812316SN/A 9821060SN/A // Commit as many instructions as possible until the commit bandwidth 9831060SN/A // limit is reached, or it becomes impossible to commit any more. 9842292SN/A while (num_committed < commitWidth) { 9858823Snilay@cs.wisc.edu // Check for any interrupt that we've already squashed for 9868823Snilay@cs.wisc.edu // and start processing it. 9878823Snilay@cs.wisc.edu if (interrupt != NoFault) 9888823Snilay@cs.wisc.edu handleInterrupt(); 9898823Snilay@cs.wisc.edu 99010731Snilay@cs.wisc.edu ThreadID commit_thread = getCommittingThread(); 9911060SN/A 9922292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9932292SN/A break; 9942292SN/A 9952292SN/A head_inst = rob->readHeadInst(commit_thread); 9962292SN/A 9976221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 9982292SN/A 9992292SN/A assert(tid == commit_thread); 10002292SN/A 10012292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 10022292SN/A head_inst->seqNum, tid); 10032132SN/A 10042316SN/A // If the head instruction is squashed, it is ready to retire 10052316SN/A // (be removed from the ROB) at any time. 10061060SN/A if (head_inst->isSquashed()) { 10071060SN/A 10082292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 10091060SN/A "ROB.\n"); 10101060SN/A 10112292SN/A rob->retireHead(commit_thread); 10121060SN/A 10131062SN/A ++commitSquashedInsts; 101411246Sradhika.jagtap@ARM.com // Notify potential listeners that this instruction is squashed 101511246Sradhika.jagtap@ARM.com ppSquash->notify(head_inst); 10161062SN/A 10172292SN/A // Record that the number of ROB entries has changed. 10182292SN/A changedROBNumEntries[tid] = true; 10191060SN/A } else { 10207720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 10212292SN/A 10221060SN/A // Increment the total number of non-speculative instructions 10231060SN/A // executed. 10241060SN/A // Hack for now: it really shouldn't happen until after the 10251061SN/A // commit is deemed to be successful, but this count is needed 10261061SN/A // for syscalls. 10272292SN/A thread[tid]->funcExeInst++; 10281060SN/A 10291060SN/A // Try to commit the head instruction. 10301060SN/A bool commit_success = commitHead(head_inst, num_committed); 10311060SN/A 10321062SN/A if (commit_success) { 10331060SN/A ++num_committed; 103410193SCurtis.Dunham@arm.com statCommittedInstType[tid][head_inst->opClass()]++; 103510023Smatt.horsnell@ARM.com ppCommit->notify(head_inst); 10361060SN/A 10372292SN/A changedROBNumEntries[tid] = true; 10382292SN/A 10392292SN/A // Set the doneSeqNum to the youngest committed instruction. 10402292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 10411060SN/A 10428823Snilay@cs.wisc.edu if (tid == 0) { 10438823Snilay@cs.wisc.edu canHandleInterrupts = (!head_inst->isDelayedCommit()) && 10448823Snilay@cs.wisc.edu ((THE_ISA != ALPHA_ISA) || 10458823Snilay@cs.wisc.edu (!(pc[0].instAddr() & 0x3))); 10468823Snilay@cs.wisc.edu } 10478823Snilay@cs.wisc.edu 10487783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 10497783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 10507783SGiacomo.Gabrielli@arm.com 105110034SGeoffrey.Blake@arm.com // Check instruction execution if it successfully commits and 105210034SGeoffrey.Blake@arm.com // is not carrying a fault. 105310034SGeoffrey.Blake@arm.com if (cpu->checker) { 105410034SGeoffrey.Blake@arm.com cpu->checker->verify(head_inst); 105510034SGeoffrey.Blake@arm.com } 105610034SGeoffrey.Blake@arm.com 10578662SAli.Saidi@ARM.com cpu->traceFunctions(pc[tid].instAddr()); 10588662SAli.Saidi@ARM.com 10597720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 10602935Sksewell@umich.edu 10617855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 10627855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 10637855SAli.Saidi@ARM.com 10647784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 10657784SAli.Saidi@ARM.com // others squash everything and restart fetch 10667784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 10679437SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10687784SAli.Saidi@ARM.com 10699444SAndreas.Sandberg@ARM.com if (drainPending) { 107010340Smitch.hayenga@arm.com if (pc[tid].microPC() == 0 && interrupt == NoFault && 107110340Smitch.hayenga@arm.com !thread[tid]->trapPending) { 107210340Smitch.hayenga@arm.com // Last architectually committed instruction. 107310340Smitch.hayenga@arm.com // Squash the pipeline, stall fetch, and use 107410340Smitch.hayenga@arm.com // drainImminent to disable interrupts 107510340Smitch.hayenga@arm.com DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 10769444SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10779444SAndreas.Sandberg@ARM.com cpu->commitDrained(tid); 107810340Smitch.hayenga@arm.com drainImminent = true; 10799444SAndreas.Sandberg@ARM.com } 10809444SAndreas.Sandberg@ARM.com } 10819444SAndreas.Sandberg@ARM.com 108210596Sgabeblack@google.com bool onInstBoundary = !head_inst->isMicroop() || 108310596Sgabeblack@google.com head_inst->isLastMicroop() || 108410596Sgabeblack@google.com !head_inst->isDelayedCommit(); 108510596Sgabeblack@google.com 108610596Sgabeblack@google.com if (onInstBoundary) { 108710596Sgabeblack@google.com int count = 0; 108810596Sgabeblack@google.com Addr oldpc; 108910596Sgabeblack@google.com // Make sure we're not currently updating state while 109010596Sgabeblack@google.com // handling PC events. 109110596Sgabeblack@google.com assert(!thread[tid]->noSquashFromTC && 109210596Sgabeblack@google.com !thread[tid]->trapPending); 109310596Sgabeblack@google.com do { 109410596Sgabeblack@google.com oldpc = pc[tid].instAddr(); 109510596Sgabeblack@google.com cpu->system->pcEventQueue.service(thread[tid]->getTC()); 109610596Sgabeblack@google.com count++; 109710596Sgabeblack@google.com } while (oldpc != pc[tid].instAddr()); 109810596Sgabeblack@google.com if (count > 1) { 109910596Sgabeblack@google.com DPRINTF(Commit, 110010596Sgabeblack@google.com "PC skip function event, stopping commit\n"); 110110596Sgabeblack@google.com break; 110210596Sgabeblack@google.com } 11032292SN/A } 11049513SAli.Saidi@ARM.com 11059513SAli.Saidi@ARM.com // Check if an instruction just enabled interrupts and we've 11069513SAli.Saidi@ARM.com // previously had an interrupt pending that was not handled 11079513SAli.Saidi@ARM.com // because interrupts were subsequently disabled before the 11089513SAli.Saidi@ARM.com // pipeline reached a place to handle the interrupt. In that 11099513SAli.Saidi@ARM.com // case squash now to make sure the interrupt is handled. 11109513SAli.Saidi@ARM.com // 11119513SAli.Saidi@ARM.com // If we don't do this, we might end up in a live lock situation 111210596Sgabeblack@google.com if (!interrupt && avoidQuiesceLiveLock && 111310596Sgabeblack@google.com onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0))) 11149513SAli.Saidi@ARM.com squashAfter(tid, head_inst); 11151060SN/A } else { 11167720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 11172292SN/A "[tid:%i] [sn:%i].\n", 11187720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 11191060SN/A break; 11201060SN/A } 11211060SN/A } 11221060SN/A } 11231062SN/A 11241063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 11252292SN/A numCommittedDist.sample(num_committed); 11262307SN/A 11272307SN/A if (num_committed == commitWidth) { 11282349SN/A commitEligibleSamples++; 11292307SN/A } 11301060SN/A} 11311060SN/A 11321061SN/Atemplate <class Impl> 11331060SN/Abool 11342292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 11351060SN/A{ 11361060SN/A assert(head_inst); 11371060SN/A 11386221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 11392292SN/A 11402316SN/A // If the instruction is not executed yet, then it will need extra 11412316SN/A // handling. Signal backwards that it should be executed. 11421061SN/A if (!head_inst->isExecuted()) { 11431061SN/A // Keep this number correct. We have not yet actually executed 11441061SN/A // and committed this instruction. 11452292SN/A thread[tid]->funcExeInst--; 11461062SN/A 11479948SAli.Saidi@ARM.com // Make sure we are only trying to commit un-executed instructions we 11489948SAli.Saidi@ARM.com // think are possible. 11499948SAli.Saidi@ARM.com assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 11509948SAli.Saidi@ARM.com || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 115110824SAndreas.Sandberg@ARM.com (head_inst->isLoad() && head_inst->strictlyOrdered())); 11522316SN/A 11539948SAli.Saidi@ARM.com DPRINTF(Commit, "Encountered a barrier or non-speculative " 11549948SAli.Saidi@ARM.com "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 11559948SAli.Saidi@ARM.com head_inst->seqNum, head_inst->pcState()); 11562316SN/A 11579948SAli.Saidi@ARM.com if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 11589948SAli.Saidi@ARM.com DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 11599948SAli.Saidi@ARM.com return false; 11609948SAli.Saidi@ARM.com } 11612292SN/A 11629948SAli.Saidi@ARM.com toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 11631061SN/A 11649948SAli.Saidi@ARM.com // Change the instruction so it won't try to commit again until 11659948SAli.Saidi@ARM.com // it is executed. 11669948SAli.Saidi@ARM.com head_inst->clearCanCommit(); 11671061SN/A 116810824SAndreas.Sandberg@ARM.com if (head_inst->isLoad() && head_inst->strictlyOrdered()) { 116910824SAndreas.Sandberg@ARM.com DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n", 11707720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 117110824SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].strictlyOrdered = true; 117210824SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst; 11739948SAli.Saidi@ARM.com } else { 11749948SAli.Saidi@ARM.com ++commitNonSpecStalls; 11759948SAli.Saidi@ARM.com } 11762292SN/A 11779948SAli.Saidi@ARM.com return false; 11781060SN/A } 11791060SN/A 11802316SN/A if (head_inst->isThreadSync()) { 11812292SN/A // Not handled for now. 11822316SN/A panic("Thread sync instructions are not handled yet.\n"); 11832132SN/A } 11842132SN/A 11854035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 11864035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 11874035Sktlim@umich.edu 11882316SN/A // Stores mark themselves as completed. 11894035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 11902310SN/A head_inst->setCompleted(); 11912310SN/A } 11922310SN/A 11932112SN/A if (inst_fault != NoFault) { 11947720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 11957720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11962292SN/A 11975557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 11982316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 11992316SN/A return false; 12002316SN/A } 12012310SN/A 12024035Sktlim@umich.edu head_inst->setCompleted(); 12034035Sktlim@umich.edu 120410034SGeoffrey.Blake@arm.com // If instruction has faulted, let the checker execute it and 120510034SGeoffrey.Blake@arm.com // check if it sees the same fault and control flow. 12068733Sgeoffrey.blake@arm.com if (cpu->checker) { 12078733Sgeoffrey.blake@arm.com // Need to check the instruction before its fault is processed 12082732Sktlim@umich.edu cpu->checker->verify(head_inst); 12092316SN/A } 12102292SN/A 12119382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC); 12122292SN/A 12132316SN/A // Mark that we're in state update mode so that the trap's 12142316SN/A // execution doesn't generate extra squashes. 12159382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 12162292SN/A 12172316SN/A // Execute the trap. Although it's slightly unrealistic in 12182316SN/A // terms of timing (as it doesn't wait for the full timing of 12192316SN/A // the trap event to complete before updating state), it's 12202316SN/A // needed to update the state as soon as possible. This 12212316SN/A // prevents external agents from changing any specific state 12222316SN/A // that the trap need. 12237684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 12242292SN/A 12252316SN/A // Exit state update mode to avoid accidental updating. 12269382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 12272292SN/A 12282316SN/A commitStatus[tid] = TrapPending; 12292292SN/A 12308067SAli.Saidi@ARM.com DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 12318067SAli.Saidi@ARM.com head_inst->seqNum); 12324035Sktlim@umich.edu if (head_inst->traceData) { 12336667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 12346667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 12358834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12366667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 12376667Ssteve.reinhardt@amd.com } 12384288Sktlim@umich.edu delete head_inst->traceData; 12394035Sktlim@umich.edu head_inst->traceData = NULL; 12404035Sktlim@umich.edu } 12414035Sktlim@umich.edu 12422316SN/A // Generate trap squash event. 12432316SN/A generateTrapEvent(tid); 12442316SN/A return false; 12451060SN/A } 12461060SN/A 12472301SN/A updateComInstStats(head_inst); 12482132SN/A 12498793Sgblack@eecs.umich.edu if (FullSystem) { 12508793Sgblack@eecs.umich.edu if (thread[tid]->profile) { 12518793Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 12528793Sgblack@eecs.umich.edu ProfileNode *node = thread[tid]->profile->consume( 12538793Sgblack@eecs.umich.edu thread[tid]->getTC(), head_inst->staticInst); 12542362SN/A 12558793Sgblack@eecs.umich.edu if (node) 12568793Sgblack@eecs.umich.edu thread[tid]->profileNode = node; 12578793Sgblack@eecs.umich.edu } 12588793Sgblack@eecs.umich.edu if (CPA::available()) { 12598793Sgblack@eecs.umich.edu if (head_inst->isControl()) { 12608793Sgblack@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 12618793Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 12628793Sgblack@eecs.umich.edu } 12635953Ssaidi@eecs.umich.edu } 12645953Ssaidi@eecs.umich.edu } 12658516SMrinmoy.Ghosh@arm.com DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 12668516SMrinmoy.Ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12672132SN/A if (head_inst->traceData) { 12682292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 12698834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12704046Sbinkertn@umich.edu head_inst->traceData->dump(); 12714046Sbinkertn@umich.edu delete head_inst->traceData; 12722292SN/A head_inst->traceData = NULL; 12731060SN/A } 12748843Smrinmoy.ghosh@arm.com if (head_inst->isReturn()) { 12758843Smrinmoy.ghosh@arm.com DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 12768843Smrinmoy.ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12778843Smrinmoy.ghosh@arm.com } 12781060SN/A 12792292SN/A // Update the commit rename map 12802292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 12813771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 12822292SN/A head_inst->renamedDestRegIdx(i)); 12831060SN/A } 12841062SN/A 12852292SN/A // Finally clear the head ROB entry. 12862292SN/A rob->retireHead(tid); 12871060SN/A 12888471SGiacomo.Gabrielli@arm.com#if TRACING_ON 12899527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 12909527SMatt.Horsnell@arm.com head_inst->commitTick = curTick() - head_inst->fetchTick; 12919527SMatt.Horsnell@arm.com } 12928471SGiacomo.Gabrielli@arm.com#endif 12938471SGiacomo.Gabrielli@arm.com 12944035Sktlim@umich.edu // If this was a store, record it for this cycle. 12954035Sktlim@umich.edu if (head_inst->isStore()) 12964035Sktlim@umich.edu committedStores[tid] = true; 12974035Sktlim@umich.edu 12981060SN/A // Return true to indicate that we have committed an instruction. 12991060SN/A return true; 13001060SN/A} 13011060SN/A 13021061SN/Atemplate <class Impl> 13031060SN/Avoid 13042292SN/ADefaultCommit<Impl>::getInsts() 13051060SN/A{ 13062935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 13072935Sksewell@umich.edu 13083093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 13093093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 13102965Sksewell@umich.edu 13112965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 13122965Sksewell@umich.edu DynInstPtr inst; 13132965Sksewell@umich.edu 13143093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 13156221Snate@binkert.org ThreadID tid = inst->threadNumber; 13162292SN/A 13172292SN/A if (!inst->isSquashed() && 13184035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 13194035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 13202292SN/A changedROBNumEntries[tid] = true; 13212292SN/A 13227720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 13237720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13242292SN/A 13252292SN/A rob->insertInst(inst); 13262292SN/A 13272292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 13282292SN/A 13292292SN/A youngestSeqNum[tid] = inst->seqNum; 13301061SN/A } else { 13317720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 13321061SN/A "squashed, skipping.\n", 13337720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13341061SN/A } 13351060SN/A } 13362965Sksewell@umich.edu} 13372965Sksewell@umich.edu 13382965Sksewell@umich.edutemplate <class Impl> 13392965Sksewell@umich.eduvoid 13402292SN/ADefaultCommit<Impl>::markCompletedInsts() 13411060SN/A{ 13421060SN/A // Grab completed insts out of the IEW instruction queue, and mark 13431060SN/A // instructions completed within the ROB. 134410734Snilay@cs.wisc.edu for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) { 134510734Snilay@cs.wisc.edu assert(fromIEW->insts[inst_num]); 13462292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 13477720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 13482316SN/A "within ROB.\n", 13492292SN/A fromIEW->insts[inst_num]->threadNumber, 13507720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 13512292SN/A fromIEW->insts[inst_num]->seqNum); 13521060SN/A 13532292SN/A // Mark the instruction as ready to commit. 13542292SN/A fromIEW->insts[inst_num]->setCanCommit(); 13552292SN/A } 13561060SN/A } 13571060SN/A} 13581060SN/A 13591061SN/Atemplate <class Impl> 13602301SN/Avoid 13612301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 13622301SN/A{ 13636221Snate@binkert.org ThreadID tid = inst->threadNumber; 13642301SN/A 13658834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) 13668834Satgutier@umich.edu instsCommitted[tid]++; 13678834Satgutier@umich.edu opsCommitted[tid]++; 13682301SN/A 13699218Satgutier@umich.edu // To match the old model, don't count nops and instruction 13709218Satgutier@umich.edu // prefetches towards the total commit count. 13719218Satgutier@umich.edu if (!inst->isNop() && !inst->isInstPrefetch()) { 13729218Satgutier@umich.edu cpu->instDone(tid, inst); 13739218Satgutier@umich.edu } 13749218Satgutier@umich.edu 13752301SN/A // 13762301SN/A // Control Instructions 13772301SN/A // 13782301SN/A if (inst->isControl()) 13796221Snate@binkert.org statComBranches[tid]++; 13802301SN/A 13812301SN/A // 13822301SN/A // Memory references 13832301SN/A // 13842301SN/A if (inst->isMemRef()) { 13856221Snate@binkert.org statComRefs[tid]++; 13862301SN/A 13872301SN/A if (inst->isLoad()) { 13886221Snate@binkert.org statComLoads[tid]++; 13892301SN/A } 13902301SN/A } 13912301SN/A 13922301SN/A if (inst->isMemBarrier()) { 13936221Snate@binkert.org statComMembars[tid]++; 13942301SN/A } 13957897Shestness@cs.utexas.edu 13967897Shestness@cs.utexas.edu // Integer Instruction 13977897Shestness@cs.utexas.edu if (inst->isInteger()) 13987897Shestness@cs.utexas.edu statComInteger[tid]++; 13997897Shestness@cs.utexas.edu 14007897Shestness@cs.utexas.edu // Floating Point Instruction 14017897Shestness@cs.utexas.edu if (inst->isFloating()) 14027897Shestness@cs.utexas.edu statComFloating[tid]++; 14037897Shestness@cs.utexas.edu 14047897Shestness@cs.utexas.edu // Function Calls 14057897Shestness@cs.utexas.edu if (inst->isCall()) 14067897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 14077897Shestness@cs.utexas.edu 14082301SN/A} 14092301SN/A 14102292SN/A//////////////////////////////////////// 14112292SN/A// // 14122316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 14132292SN/A// // 14142292SN/A//////////////////////////////////////// 14152292SN/Atemplate <class Impl> 14166221Snate@binkert.orgThreadID 14172292SN/ADefaultCommit<Impl>::getCommittingThread() 14182292SN/A{ 14192292SN/A if (numThreads > 1) { 14202292SN/A switch (commitPolicy) { 14212292SN/A 14222292SN/A case Aggressive: 14232292SN/A //If Policy is Aggressive, commit will call 14242292SN/A //this function multiple times per 14252292SN/A //cycle 14262292SN/A return oldestReady(); 14272292SN/A 14282292SN/A case RoundRobin: 14292292SN/A return roundRobin(); 14302292SN/A 14312292SN/A case OldestReady: 14322292SN/A return oldestReady(); 14332292SN/A 14342292SN/A default: 14356221Snate@binkert.org return InvalidThreadID; 14362292SN/A } 14372292SN/A } else { 14383867Sbinkertn@umich.edu assert(!activeThreads->empty()); 14396221Snate@binkert.org ThreadID tid = activeThreads->front(); 14402292SN/A 14412292SN/A if (commitStatus[tid] == Running || 14422292SN/A commitStatus[tid] == Idle || 14432292SN/A commitStatus[tid] == FetchTrapPending) { 14442292SN/A return tid; 14452292SN/A } else { 14466221Snate@binkert.org return InvalidThreadID; 14472292SN/A } 14482292SN/A } 14492292SN/A} 14502292SN/A 14512292SN/Atemplate<class Impl> 14526221Snate@binkert.orgThreadID 14532292SN/ADefaultCommit<Impl>::roundRobin() 14542292SN/A{ 14556221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14566221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14572292SN/A 14582292SN/A while (pri_iter != end) { 14596221Snate@binkert.org ThreadID tid = *pri_iter; 14602292SN/A 14612292SN/A if (commitStatus[tid] == Running || 14622831Sksewell@umich.edu commitStatus[tid] == Idle || 14632831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 14642292SN/A 14652292SN/A if (rob->isHeadReady(tid)) { 14662292SN/A priority_list.erase(pri_iter); 14672292SN/A priority_list.push_back(tid); 14682292SN/A 14692292SN/A return tid; 14702292SN/A } 14712292SN/A } 14722292SN/A 14732292SN/A pri_iter++; 14742292SN/A } 14752292SN/A 14766221Snate@binkert.org return InvalidThreadID; 14772292SN/A} 14782292SN/A 14792292SN/Atemplate<class Impl> 14806221Snate@binkert.orgThreadID 14812292SN/ADefaultCommit<Impl>::oldestReady() 14822292SN/A{ 14832292SN/A unsigned oldest = 0; 14842292SN/A bool first = true; 14852292SN/A 14866221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14876221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14882292SN/A 14893867Sbinkertn@umich.edu while (threads != end) { 14906221Snate@binkert.org ThreadID tid = *threads++; 14912292SN/A 14922292SN/A if (!rob->isEmpty(tid) && 14932292SN/A (commitStatus[tid] == Running || 14942292SN/A commitStatus[tid] == Idle || 14952292SN/A commitStatus[tid] == FetchTrapPending)) { 14962292SN/A 14972292SN/A if (rob->isHeadReady(tid)) { 14982292SN/A 14992292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 15002292SN/A 15012292SN/A if (first) { 15022292SN/A oldest = tid; 15032292SN/A first = false; 15042292SN/A } else if (head_inst->seqNum < oldest) { 15052292SN/A oldest = tid; 15062292SN/A } 15072292SN/A } 15082292SN/A } 15092292SN/A } 15102292SN/A 15112292SN/A if (!first) { 15122292SN/A return oldest; 15132292SN/A } else { 15146221Snate@binkert.org return InvalidThreadID; 15152292SN/A } 15162292SN/A} 15179944Smatt.horsnell@ARM.com 15189944Smatt.horsnell@ARM.com#endif//__CPU_O3_COMMIT_IMPL_HH__ 1519