commit_impl.hh revision 10193
11689SN/A/* 29948SAli.Saidi@ARM.com * Copyright (c) 2010-2013 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412965Sksewell@umich.edu * Korey Sewell 421689SN/A */ 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_COMMIT_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_COMMIT_IMPL_HH__ 451689SN/A 462292SN/A#include <algorithm> 479516SAli.Saidi@ARM.com#include <set> 482329SN/A#include <string> 492292SN/A 503577Sgblack@eecs.umich.edu#include "arch/utility.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 525953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 551717SN/A#include "cpu/o3/commit.hh" 562292SN/A#include "cpu/o3/thread_state.hh" 578662SAli.Saidi@ARM.com#include "cpu/base.hh" 588229Snate@binkert.org#include "cpu/exetrace.hh" 598229Snate@binkert.org#include "cpu/timebuf.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 618232Snate@binkert.org#include "debug/Commit.hh" 628232Snate@binkert.org#include "debug/CommitRate.hh" 639444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 648232Snate@binkert.org#include "debug/ExecFaulting.hh" 659527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 666221Snate@binkert.org#include "params/DerivO3CPU.hh" 678230Snate@binkert.org#include "sim/faults.hh" 688793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 692292SN/A 706221Snate@binkert.orgusing namespace std; 715529Snate@binkert.org 721061SN/Atemplate <class Impl> 732292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 746221Snate@binkert.org ThreadID _tid) 758581Ssteve.reinhardt@amd.com : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 761060SN/A{ 771060SN/A} 781060SN/A 791061SN/Atemplate <class Impl> 801060SN/Avoid 812292SN/ADefaultCommit<Impl>::TrapEvent::process() 821062SN/A{ 832316SN/A // This will get reset by commit if it was switched out at the 842316SN/A // time of this event processing. 852292SN/A commit->trapSquash[tid] = true; 862292SN/A} 872292SN/A 882292SN/Atemplate <class Impl> 892292SN/Aconst char * 905336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 912292SN/A{ 924873Sstever@eecs.umich.edu return "Trap"; 932292SN/A} 942292SN/A 952292SN/Atemplate <class Impl> 965529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 974329Sktlim@umich.edu : cpu(_cpu), 984329Sktlim@umich.edu squashCounter(0), 992292SN/A iewToCommitDelay(params->iewToCommitDelay), 1002292SN/A commitToIEWDelay(params->commitToIEWDelay), 1012292SN/A renameToROBDelay(params->renameToROBDelay), 1022292SN/A fetchToCommitDelay(params->commitToFetchDelay), 1032292SN/A renameWidth(params->renameWidth), 1042292SN/A commitWidth(params->commitWidth), 1055529Snate@binkert.org numThreads(params->numThreads), 1062843Sktlim@umich.edu drainPending(false), 1078823Snilay@cs.wisc.edu trapLatency(params->trapLatency), 1089513SAli.Saidi@ARM.com canHandleInterrupts(true), 1099513SAli.Saidi@ARM.com avoidQuiesceLiveLock(false) 1102292SN/A{ 11110172Sdam.sunwoo@arm.com if (commitWidth > Impl::MaxWidth) 11210172Sdam.sunwoo@arm.com fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 11310172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 11410172Sdam.sunwoo@arm.com commitWidth, static_cast<int>(Impl::MaxWidth)); 11510172Sdam.sunwoo@arm.com 1162292SN/A _status = Active; 1172292SN/A _nextStatus = Inactive; 1182980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1192292SN/A 1202292SN/A //Convert string to lowercase 1212292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1222292SN/A (int(*)(int)) tolower); 1232292SN/A 1242292SN/A //Assign commit policy 1252292SN/A if (policy == "aggressive"){ 1262292SN/A commitPolicy = Aggressive; 1272292SN/A 1288346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 1292292SN/A } else if (policy == "roundrobin"){ 1302292SN/A commitPolicy = RoundRobin; 1312292SN/A 1322292SN/A //Set-Up Priority List 1336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1342292SN/A priority_list.push_back(tid); 1352292SN/A } 1362292SN/A 1378346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 1382292SN/A } else if (policy == "oldestready"){ 1392292SN/A commitPolicy = OldestReady; 1402292SN/A 1414329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1422292SN/A } else { 1432292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1442292SN/A "RoundRobin,OldestReady}"); 1452292SN/A } 1462292SN/A 1476221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1486221Snate@binkert.org commitStatus[tid] = Idle; 1496221Snate@binkert.org changedROBNumEntries[tid] = false; 1506221Snate@binkert.org checkEmptyROB[tid] = false; 1516221Snate@binkert.org trapInFlight[tid] = false; 1526221Snate@binkert.org committedStores[tid] = false; 1536221Snate@binkert.org trapSquash[tid] = false; 1546221Snate@binkert.org tcSquash[tid] = false; 1557720Sgblack@eecs.umich.edu pc[tid].set(0); 1567855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = 0; 1579437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 1582292SN/A } 1593640Sktlim@umich.edu interrupt = NoFault; 1602292SN/A} 1612292SN/A 1622292SN/Atemplate <class Impl> 1632292SN/Astd::string 1642292SN/ADefaultCommit<Impl>::name() const 1652292SN/A{ 1662292SN/A return cpu->name() + ".commit"; 1672292SN/A} 1682292SN/A 1692292SN/Atemplate <class Impl> 1702292SN/Avoid 17110023Smatt.horsnell@ARM.comDefaultCommit<Impl>::regProbePoints() 17210023Smatt.horsnell@ARM.com{ 17310023Smatt.horsnell@ARM.com ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 17410023Smatt.horsnell@ARM.com ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 17510023Smatt.horsnell@ARM.com} 17610023Smatt.horsnell@ARM.com 17710023Smatt.horsnell@ARM.comtemplate <class Impl> 17810023Smatt.horsnell@ARM.comvoid 1792292SN/ADefaultCommit<Impl>::regStats() 1802132SN/A{ 1812301SN/A using namespace Stats; 1821062SN/A commitSquashedInsts 1831062SN/A .name(name() + ".commitSquashedInsts") 1841062SN/A .desc("The number of squashed insts skipped by commit") 1851062SN/A .prereq(commitSquashedInsts); 1861062SN/A commitSquashEvents 1871062SN/A .name(name() + ".commitSquashEvents") 1881062SN/A .desc("The number of times commit is told to squash") 1891062SN/A .prereq(commitSquashEvents); 1901062SN/A commitNonSpecStalls 1911062SN/A .name(name() + ".commitNonSpecStalls") 1921062SN/A .desc("The number of times commit has been forced to stall to " 1931062SN/A "communicate backwards") 1941062SN/A .prereq(commitNonSpecStalls); 1951062SN/A branchMispredicts 1961062SN/A .name(name() + ".branchMispredicts") 1971062SN/A .desc("The number of times a branch was mispredicted") 1981062SN/A .prereq(branchMispredicts); 1992292SN/A numCommittedDist 2001062SN/A .init(0,commitWidth,1) 2018240Snate@binkert.org .name(name() + ".committed_per_cycle") 2021062SN/A .desc("Number of insts commited each cycle") 2031062SN/A .flags(Stats::pdf) 2041062SN/A ; 2052301SN/A 2068834Satgutier@umich.edu instsCommitted 2076221Snate@binkert.org .init(cpu->numThreads) 2088834Satgutier@umich.edu .name(name() + ".committedInsts") 2092301SN/A .desc("Number of instructions committed") 2102301SN/A .flags(total) 2112301SN/A ; 2122301SN/A 2138834Satgutier@umich.edu opsCommitted 2148834Satgutier@umich.edu .init(cpu->numThreads) 2158834Satgutier@umich.edu .name(name() + ".committedOps") 2168834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 2178834Satgutier@umich.edu .flags(total) 2188834Satgutier@umich.edu ; 2198834Satgutier@umich.edu 2202316SN/A statComSwp 2216221Snate@binkert.org .init(cpu->numThreads) 2228240Snate@binkert.org .name(name() + ".swp_count") 2232301SN/A .desc("Number of s/w prefetches committed") 2242301SN/A .flags(total) 2252301SN/A ; 2262301SN/A 2272316SN/A statComRefs 2286221Snate@binkert.org .init(cpu->numThreads) 2298240Snate@binkert.org .name(name() + ".refs") 2302301SN/A .desc("Number of memory references committed") 2312301SN/A .flags(total) 2322301SN/A ; 2332301SN/A 2342316SN/A statComLoads 2356221Snate@binkert.org .init(cpu->numThreads) 2368240Snate@binkert.org .name(name() + ".loads") 2372301SN/A .desc("Number of loads committed") 2382301SN/A .flags(total) 2392301SN/A ; 2402301SN/A 2412316SN/A statComMembars 2426221Snate@binkert.org .init(cpu->numThreads) 2438240Snate@binkert.org .name(name() + ".membars") 2442301SN/A .desc("Number of memory barriers committed") 2452301SN/A .flags(total) 2462301SN/A ; 2472301SN/A 2482316SN/A statComBranches 2496221Snate@binkert.org .init(cpu->numThreads) 2508240Snate@binkert.org .name(name() + ".branches") 2512301SN/A .desc("Number of branches committed") 2522301SN/A .flags(total) 2532301SN/A ; 2542301SN/A 2557897Shestness@cs.utexas.edu statComFloating 2567897Shestness@cs.utexas.edu .init(cpu->numThreads) 2578240Snate@binkert.org .name(name() + ".fp_insts") 2587897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2597897Shestness@cs.utexas.edu .flags(total) 2607897Shestness@cs.utexas.edu ; 2617897Shestness@cs.utexas.edu 2627897Shestness@cs.utexas.edu statComInteger 2637897Shestness@cs.utexas.edu .init(cpu->numThreads) 2648240Snate@binkert.org .name(name()+".int_insts") 2657897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2667897Shestness@cs.utexas.edu .flags(total) 2677897Shestness@cs.utexas.edu ; 2687897Shestness@cs.utexas.edu 2697897Shestness@cs.utexas.edu statComFunctionCalls 2707897Shestness@cs.utexas.edu .init(cpu->numThreads) 2718240Snate@binkert.org .name(name()+".function_calls") 2727897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2737897Shestness@cs.utexas.edu .flags(total) 2747897Shestness@cs.utexas.edu ; 2757897Shestness@cs.utexas.edu 27610193SCurtis.Dunham@arm.com statCommittedInstType 27710193SCurtis.Dunham@arm.com .init(numThreads,Enums::Num_OpClass) 27810193SCurtis.Dunham@arm.com .name(name() + ".op_class") 27910193SCurtis.Dunham@arm.com .desc("Class of committed instruction") 28010193SCurtis.Dunham@arm.com .flags(total | pdf | dist) 28110193SCurtis.Dunham@arm.com ; 28210193SCurtis.Dunham@arm.com statCommittedInstType.ysubnames(Enums::OpClassStrings); 28310193SCurtis.Dunham@arm.com 2842316SN/A commitEligible 2856221Snate@binkert.org .init(cpu->numThreads) 2868240Snate@binkert.org .name(name() + ".bw_limited") 2872301SN/A .desc("number of insts not committed due to BW limits") 2882301SN/A .flags(total) 2892301SN/A ; 2902301SN/A 2912316SN/A commitEligibleSamples 2928240Snate@binkert.org .name(name() + ".bw_lim_events") 2932301SN/A .desc("number cycles where commit BW limit reached") 2942301SN/A ; 2951062SN/A} 2961062SN/A 2971062SN/Atemplate <class Impl> 2981062SN/Avoid 2992980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 3002292SN/A{ 3012292SN/A thread = threads; 3022292SN/A} 3032292SN/A 3042292SN/Atemplate <class Impl> 3052292SN/Avoid 3062292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3071060SN/A{ 3081060SN/A timeBuffer = tb_ptr; 3091060SN/A 3101060SN/A // Setup wire to send information back to IEW. 3111060SN/A toIEW = timeBuffer->getWire(0); 3121060SN/A 3131060SN/A // Setup wire to read data from IEW (for the ROB). 3141060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 3151060SN/A} 3161060SN/A 3171061SN/Atemplate <class Impl> 3181060SN/Avoid 3192292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 3202292SN/A{ 3212292SN/A fetchQueue = fq_ptr; 3222292SN/A 3232292SN/A // Setup wire to get instructions from rename (for the ROB). 3242292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 3252292SN/A} 3262292SN/A 3272292SN/Atemplate <class Impl> 3282292SN/Avoid 3292292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3301060SN/A{ 3311060SN/A renameQueue = rq_ptr; 3321060SN/A 3331060SN/A // Setup wire to get instructions from rename (for the ROB). 3341060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3351060SN/A} 3361060SN/A 3371061SN/Atemplate <class Impl> 3381060SN/Avoid 3392292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3401060SN/A{ 3411060SN/A iewQueue = iq_ptr; 3421060SN/A 3431060SN/A // Setup wire to get instructions from IEW. 3441060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3451060SN/A} 3461060SN/A 3471061SN/Atemplate <class Impl> 3481060SN/Avoid 3492292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3502292SN/A{ 3512292SN/A iewStage = iew_stage; 3522292SN/A} 3532292SN/A 3542292SN/Atemplate<class Impl> 3552292SN/Avoid 3566221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3572292SN/A{ 3582292SN/A activeThreads = at_ptr; 3592292SN/A} 3602292SN/A 3612292SN/Atemplate <class Impl> 3622292SN/Avoid 3632292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3642292SN/A{ 3656221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3666221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3672292SN/A} 3682292SN/A 3692292SN/Atemplate <class Impl> 3702292SN/Avoid 3712292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3721060SN/A{ 3731060SN/A rob = rob_ptr; 3741060SN/A} 3751060SN/A 3761061SN/Atemplate <class Impl> 3771060SN/Avoid 3789427SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::startupStage() 3791060SN/A{ 3802292SN/A rob->setActiveThreads(activeThreads); 3812292SN/A rob->resetEntries(); 3821060SN/A 3832292SN/A // Broadcast the number of free entries. 3846221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3856221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3866221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3876221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3881060SN/A } 3891060SN/A 3904329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3914329Sktlim@umich.edu // start of the simulation, so it starts as active. 3924329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3934329Sktlim@umich.edu 3942292SN/A cpu->activityThisCycle(); 3951060SN/A} 3961060SN/A 3971061SN/Atemplate <class Impl> 3989444SAndreas.Sandberg@ARM.comvoid 3992843Sktlim@umich.eduDefaultCommit<Impl>::drain() 4001060SN/A{ 4012843Sktlim@umich.edu drainPending = true; 4022316SN/A} 4032316SN/A 4042316SN/Atemplate <class Impl> 4052316SN/Avoid 4069444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainResume() 4072843Sktlim@umich.edu{ 4082864Sktlim@umich.edu drainPending = false; 4092843Sktlim@umich.edu} 4102843Sktlim@umich.edu 4112843Sktlim@umich.edutemplate <class Impl> 4122843Sktlim@umich.eduvoid 4139444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainSanityCheck() const 4149444SAndreas.Sandberg@ARM.com{ 4159444SAndreas.Sandberg@ARM.com assert(isDrained()); 4169444SAndreas.Sandberg@ARM.com rob->drainSanityCheck(); 4179444SAndreas.Sandberg@ARM.com} 4189444SAndreas.Sandberg@ARM.com 4199444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4209444SAndreas.Sandberg@ARM.combool 4219444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::isDrained() const 4229444SAndreas.Sandberg@ARM.com{ 4239444SAndreas.Sandberg@ARM.com /* Make sure no one is executing microcode. There are two reasons 4249444SAndreas.Sandberg@ARM.com * for this: 4259444SAndreas.Sandberg@ARM.com * - Hardware virtualized CPUs can't switch into the middle of a 4269444SAndreas.Sandberg@ARM.com * microcode sequence. 4279444SAndreas.Sandberg@ARM.com * - The current fetch implementation will most likely get very 4289444SAndreas.Sandberg@ARM.com * confused if it tries to start fetching an instruction that 4299444SAndreas.Sandberg@ARM.com * is executing in the middle of a ucode sequence that changes 4309444SAndreas.Sandberg@ARM.com * address mappings. This can happen on for example x86. 4319444SAndreas.Sandberg@ARM.com */ 4329444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 4339444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() != 0) 4349444SAndreas.Sandberg@ARM.com return false; 4359444SAndreas.Sandberg@ARM.com } 4369444SAndreas.Sandberg@ARM.com 4379444SAndreas.Sandberg@ARM.com /* Make sure that all instructions have finished committing before 4389444SAndreas.Sandberg@ARM.com * declaring the system as drained. We want the pipeline to be 4399444SAndreas.Sandberg@ARM.com * completely empty when we declare the CPU to be drained. This 4409444SAndreas.Sandberg@ARM.com * makes debugging easier since CPU handover and restoring from a 4419444SAndreas.Sandberg@ARM.com * checkpoint with a different CPU should have the same timing. 4429444SAndreas.Sandberg@ARM.com */ 4439444SAndreas.Sandberg@ARM.com return rob->isEmpty() && 4449444SAndreas.Sandberg@ARM.com interrupt == NoFault; 4459444SAndreas.Sandberg@ARM.com} 4469444SAndreas.Sandberg@ARM.com 4479444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4489444SAndreas.Sandberg@ARM.comvoid 4492307SN/ADefaultCommit<Impl>::takeOverFrom() 4502307SN/A{ 4512307SN/A _status = Active; 4522307SN/A _nextStatus = Inactive; 4536221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4546221Snate@binkert.org commitStatus[tid] = Idle; 4556221Snate@binkert.org changedROBNumEntries[tid] = false; 4566221Snate@binkert.org trapSquash[tid] = false; 4576221Snate@binkert.org tcSquash[tid] = false; 4589437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 4592307SN/A } 4602307SN/A squashCounter = 0; 4612307SN/A rob->takeOverFrom(); 4622307SN/A} 4632307SN/A 4642307SN/Atemplate <class Impl> 4652307SN/Avoid 4662292SN/ADefaultCommit<Impl>::updateStatus() 4672132SN/A{ 4682316SN/A // reset ROB changed variable 4696221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4706221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4713867Sbinkertn@umich.edu 4723867Sbinkertn@umich.edu while (threads != end) { 4736221Snate@binkert.org ThreadID tid = *threads++; 4743867Sbinkertn@umich.edu 4752316SN/A changedROBNumEntries[tid] = false; 4762316SN/A 4772316SN/A // Also check if any of the threads has a trap pending 4782316SN/A if (commitStatus[tid] == TrapPending || 4792316SN/A commitStatus[tid] == FetchTrapPending) { 4802316SN/A _nextStatus = Active; 4812316SN/A } 4822292SN/A } 4832292SN/A 4842292SN/A if (_nextStatus == Inactive && _status == Active) { 4852292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4862733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4872292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4882292SN/A DPRINTF(Activity, "Activating stage.\n"); 4892733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4902292SN/A } 4912292SN/A 4922292SN/A _status = _nextStatus; 4932292SN/A} 4942292SN/A 4952292SN/Atemplate <class Impl> 4962292SN/Avoid 4972292SN/ADefaultCommit<Impl>::setNextStatus() 4982292SN/A{ 4992292SN/A int squashes = 0; 5002292SN/A 5016221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5026221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5032292SN/A 5043867Sbinkertn@umich.edu while (threads != end) { 5056221Snate@binkert.org ThreadID tid = *threads++; 5062292SN/A 5072292SN/A if (commitStatus[tid] == ROBSquashing) { 5082292SN/A squashes++; 5092292SN/A } 5102292SN/A } 5112292SN/A 5122702Sktlim@umich.edu squashCounter = squashes; 5132292SN/A 5142292SN/A // If commit is currently squashing, then it will have activity for the 5152292SN/A // next cycle. Set its next status as active. 5162292SN/A if (squashCounter) { 5172292SN/A _nextStatus = Active; 5182292SN/A } 5192292SN/A} 5202292SN/A 5212292SN/Atemplate <class Impl> 5222292SN/Abool 5232292SN/ADefaultCommit<Impl>::changedROBEntries() 5242292SN/A{ 5256221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5266221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5272292SN/A 5283867Sbinkertn@umich.edu while (threads != end) { 5296221Snate@binkert.org ThreadID tid = *threads++; 5302292SN/A 5312292SN/A if (changedROBNumEntries[tid]) { 5322292SN/A return true; 5332292SN/A } 5342292SN/A } 5352292SN/A 5362292SN/A return false; 5372292SN/A} 5382292SN/A 5392292SN/Atemplate <class Impl> 5406221Snate@binkert.orgsize_t 5416221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 5422292SN/A{ 5432292SN/A return rob->numFreeEntries(tid); 5442292SN/A} 5452292SN/A 5462292SN/Atemplate <class Impl> 5472292SN/Avoid 5486221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 5492292SN/A{ 5502292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5512292SN/A 5522292SN/A TrapEvent *trap = new TrapEvent(this, tid); 5532292SN/A 5549179Sandreas.hansson@arm.com cpu->schedule(trap, cpu->clockEdge(trapLatency)); 5554035Sktlim@umich.edu trapInFlight[tid] = true; 5568518Sgeoffrey.blake@arm.com thread[tid]->trapPending = true; 5572292SN/A} 5582292SN/A 5592292SN/Atemplate <class Impl> 5602292SN/Avoid 5616221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5622292SN/A{ 5634035Sktlim@umich.edu assert(!trapInFlight[tid]); 5642680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5652292SN/A 5662680Sktlim@umich.edu tcSquash[tid] = true; 5672292SN/A} 5682292SN/A 5692292SN/Atemplate <class Impl> 5702292SN/Avoid 5716221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5722292SN/A{ 5732292SN/A // If we want to include the squashing instruction in the squash, 5742292SN/A // then use one older sequence number. 5752292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5762292SN/A // all instructions of this thread. 57710164Ssleimanf@umich.edu InstSeqNum squashed_inst = rob->isEmpty(tid) ? 5787855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5792292SN/A 5802292SN/A // All younger instructions will be squashed. Set the sequence 5812292SN/A // number as the youngest instruction in the ROB (0 in this case. 5822292SN/A // Hopefully nothing breaks.) 5837855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5842292SN/A 5852292SN/A rob->squash(squashed_inst, tid); 5862292SN/A changedROBNumEntries[tid] = true; 5872292SN/A 5882292SN/A // Send back the sequence number of the squashed instruction. 5892292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5902292SN/A 5912292SN/A // Send back the squash signal to tell stages that they should 5922292SN/A // squash. 5932292SN/A toIEW->commitInfo[tid].squash = true; 5942292SN/A 5952292SN/A // Send back the rob squashing signal so other stages know that 5962292SN/A // the ROB is in the process of squashing. 5972292SN/A toIEW->commitInfo[tid].robSquashing = true; 5982292SN/A 5997851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 6008137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 6012292SN/A 6027720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 6032316SN/A} 6042292SN/A 6052316SN/Atemplate <class Impl> 6062316SN/Avoid 6076221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 6082316SN/A{ 6092316SN/A squashAll(tid); 6102316SN/A 6117720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 6122316SN/A 6132316SN/A thread[tid]->trapPending = false; 6149382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6154035Sktlim@umich.edu trapInFlight[tid] = false; 6162316SN/A 6172316SN/A trapSquash[tid] = false; 6182316SN/A 6192316SN/A commitStatus[tid] = ROBSquashing; 6202316SN/A cpu->activityThisCycle(); 6212316SN/A} 6222316SN/A 6232316SN/Atemplate <class Impl> 6242316SN/Avoid 6256221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 6262316SN/A{ 6272316SN/A squashAll(tid); 6282292SN/A 6297720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 6302292SN/A 6319382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6322292SN/A assert(!thread[tid]->trapPending); 6332316SN/A 6342292SN/A commitStatus[tid] = ROBSquashing; 6352292SN/A cpu->activityThisCycle(); 6362292SN/A 6372680Sktlim@umich.edu tcSquash[tid] = false; 6382292SN/A} 6392292SN/A 6402292SN/Atemplate <class Impl> 6412292SN/Avoid 6429437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 6437784SAli.Saidi@ARM.com{ 6449437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Squashing after squash after request, " 6459437SAndreas.Sandberg@ARM.com "restarting at PC %s\n", pc[tid]); 6467784SAli.Saidi@ARM.com 6479437SAndreas.Sandberg@ARM.com squashAll(tid); 6489437SAndreas.Sandberg@ARM.com // Make sure to inform the fetch stage of which instruction caused 6499437SAndreas.Sandberg@ARM.com // the squash. It'll try to re-fetch an instruction executing in 6509437SAndreas.Sandberg@ARM.com // microcode unless this is set. 6519437SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 6529437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 6537784SAli.Saidi@ARM.com 6549437SAndreas.Sandberg@ARM.com commitStatus[tid] = ROBSquashing; 6559437SAndreas.Sandberg@ARM.com cpu->activityThisCycle(); 6569437SAndreas.Sandberg@ARM.com} 6577784SAli.Saidi@ARM.com 6589437SAndreas.Sandberg@ARM.comtemplate <class Impl> 6599437SAndreas.Sandberg@ARM.comvoid 6609437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst) 6619437SAndreas.Sandberg@ARM.com{ 6629437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6639437SAndreas.Sandberg@ARM.com tid, head_inst->seqNum); 6647784SAli.Saidi@ARM.com 6659437SAndreas.Sandberg@ARM.com assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 6669437SAndreas.Sandberg@ARM.com commitStatus[tid] = SquashAfterPending; 6679437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = head_inst; 6687784SAli.Saidi@ARM.com} 6697784SAli.Saidi@ARM.com 6707784SAli.Saidi@ARM.comtemplate <class Impl> 6717784SAli.Saidi@ARM.comvoid 6722292SN/ADefaultCommit<Impl>::tick() 6732292SN/A{ 6742292SN/A wroteToTimeBuffer = false; 6752292SN/A _nextStatus = Inactive; 6762292SN/A 6773867Sbinkertn@umich.edu if (activeThreads->empty()) 6782875Sksewell@umich.edu return; 6792875Sksewell@umich.edu 6806221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6816221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6822292SN/A 6832316SN/A // Check if any of the threads are done squashing. Change the 6842316SN/A // status if they are done. 6853867Sbinkertn@umich.edu while (threads != end) { 6866221Snate@binkert.org ThreadID tid = *threads++; 6872292SN/A 6884035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6894035Sktlim@umich.edu // this cycle. 6904035Sktlim@umich.edu committedStores[tid] = false; 6914035Sktlim@umich.edu 6922292SN/A if (commitStatus[tid] == ROBSquashing) { 6932292SN/A 6942292SN/A if (rob->isDoneSquashing(tid)) { 6952292SN/A commitStatus[tid] = Running; 6962292SN/A } else { 6972292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6982877Sksewell@umich.edu " insts this cycle.\n", tid); 6992702Sktlim@umich.edu rob->doSquash(tid); 7002702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 7012702Sktlim@umich.edu wroteToTimeBuffer = true; 7022292SN/A } 7032292SN/A } 7042292SN/A } 7052292SN/A 7062292SN/A commit(); 7072292SN/A 7082292SN/A markCompletedInsts(); 7092292SN/A 7103867Sbinkertn@umich.edu threads = activeThreads->begin(); 7112292SN/A 7123867Sbinkertn@umich.edu while (threads != end) { 7136221Snate@binkert.org ThreadID tid = *threads++; 7142292SN/A 7152292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 7162292SN/A // The ROB has more instructions it can commit. Its next status 7172292SN/A // will be active. 7182292SN/A _nextStatus = Active; 7192292SN/A 7202292SN/A DynInstPtr inst = rob->readHeadInst(tid); 7212292SN/A 7227720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 7232292SN/A " ROB and ready to commit\n", 7247720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7252292SN/A 7262292SN/A } else if (!rob->isEmpty(tid)) { 7272292SN/A DynInstPtr inst = rob->readHeadInst(tid); 7282292SN/A 72910023Smatt.horsnell@ARM.com ppCommitStall->notify(inst); 73010023Smatt.horsnell@ARM.com 7312292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 7327720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 7337720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7342292SN/A } 7352292SN/A 7362292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 7372292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 7382292SN/A } 7392292SN/A 7402292SN/A 7412292SN/A if (wroteToTimeBuffer) { 7422316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 7432292SN/A cpu->activityThisCycle(); 7442292SN/A } 7452292SN/A 7462292SN/A updateStatus(); 7472292SN/A} 7482292SN/A 7492292SN/Atemplate <class Impl> 7502292SN/Avoid 7514035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 7522292SN/A{ 7537847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7547847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7557847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7567847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7577847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7587847Sminkyu.jeong@arm.com interrupt = NoFault; 7599513SAli.Saidi@ARM.com avoidQuiesceLiveLock = true; 7607847Sminkyu.jeong@arm.com return; 7617847Sminkyu.jeong@arm.com } 7623633Sktlim@umich.edu 7638493Sgblack@eecs.umich.edu // Wait until all in flight instructions are finished before enterring 7648493Sgblack@eecs.umich.edu // the interrupt. 7658823Snilay@cs.wisc.edu if (canHandleInterrupts && cpu->instList.empty()) { 7667847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7677847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7687847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7694035Sktlim@umich.edu 7707847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7717847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7722292SN/A 7739382SAli.Saidi@ARM.com assert(!thread[0]->noSquashFromTC); 7749382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = true; 7752292SN/A 7768733Sgeoffrey.blake@arm.com if (cpu->checker) { 7778733Sgeoffrey.blake@arm.com cpu->checker->handlePendingInt(); 7788733Sgeoffrey.blake@arm.com } 7798733Sgeoffrey.blake@arm.com 7809624Snilay@cs.wisc.edu // CPU will handle interrupt. Note that we ignore the local copy of 7819624Snilay@cs.wisc.edu // interrupt. This is because the local copy may no longer be the 7829624Snilay@cs.wisc.edu // interrupt that the interrupt controller thinks is being handled. 7839624Snilay@cs.wisc.edu cpu->processInterrupts(cpu->getInterrupts()); 7843633Sktlim@umich.edu 7859382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = false; 7862292SN/A 7877847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7882292SN/A 7897847Sminkyu.jeong@arm.com // Generate trap squash event. 7907847Sminkyu.jeong@arm.com generateTrapEvent(0); 7913640Sktlim@umich.edu 7927847Sminkyu.jeong@arm.com interrupt = NoFault; 7939513SAli.Saidi@ARM.com avoidQuiesceLiveLock = false; 7947847Sminkyu.jeong@arm.com } else { 7958823Snilay@cs.wisc.edu DPRINTF(Commit, "Interrupt pending: instruction is %sin " 7968823Snilay@cs.wisc.edu "flight, ROB is %sempty\n", 7978823Snilay@cs.wisc.edu canHandleInterrupts ? "not " : "", 7988823Snilay@cs.wisc.edu cpu->instList.empty() ? "" : "not " ); 7991060SN/A } 8004035Sktlim@umich.edu} 8017847Sminkyu.jeong@arm.com 8027847Sminkyu.jeong@arm.comtemplate <class Impl> 8037847Sminkyu.jeong@arm.comvoid 8047847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 8057847Sminkyu.jeong@arm.com{ 8067847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 8077847Sminkyu.jeong@arm.com tcSquash[0]) 8087847Sminkyu.jeong@arm.com return; 8097847Sminkyu.jeong@arm.com 8107847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 8117847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 8127847Sminkyu.jeong@arm.com // pending. 8137847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 8147847Sminkyu.jeong@arm.com 8157847Sminkyu.jeong@arm.com // Get any interrupt that happened 8167847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 8177847Sminkyu.jeong@arm.com 8187847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 8197847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 8207847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 8217847Sminkyu.jeong@arm.com if (interrupt != NoFault) 8227847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 8237847Sminkyu.jeong@arm.com} 8247847Sminkyu.jeong@arm.com 8254035Sktlim@umich.edutemplate <class Impl> 8264035Sktlim@umich.eduvoid 8274035Sktlim@umich.eduDefaultCommit<Impl>::commit() 8284035Sktlim@umich.edu{ 8298793Sgblack@eecs.umich.edu if (FullSystem) { 8308793Sgblack@eecs.umich.edu // Check if we have a interrupt and get read to handle it 8318793Sgblack@eecs.umich.edu if (cpu->checkInterrupts(cpu->tcBase(0))) 8328793Sgblack@eecs.umich.edu propagateInterrupt(); 8338793Sgblack@eecs.umich.edu } 8341060SN/A 8351060SN/A //////////////////////////////////// 8362316SN/A // Check for any possible squashes, handle them first 8371060SN/A //////////////////////////////////// 8386221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8396221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8401060SN/A 8413867Sbinkertn@umich.edu while (threads != end) { 8426221Snate@binkert.org ThreadID tid = *threads++; 8431060SN/A 8442292SN/A // Not sure which one takes priority. I think if we have 8452292SN/A // both, that's a bad sign. 8462292SN/A if (trapSquash[tid] == true) { 8472680Sktlim@umich.edu assert(!tcSquash[tid]); 8482292SN/A squashFromTrap(tid); 8492680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 8504035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 8512680Sktlim@umich.edu squashFromTC(tid); 8529437SAndreas.Sandberg@ARM.com } else if (commitStatus[tid] == SquashAfterPending) { 8539437SAndreas.Sandberg@ARM.com // A squash from the previous cycle of the commit stage (i.e., 8549437SAndreas.Sandberg@ARM.com // commitInsts() called squashAfter) is pending. Squash the 8559437SAndreas.Sandberg@ARM.com // thread now. 8569437SAndreas.Sandberg@ARM.com squashFromSquashAfter(tid); 8572292SN/A } 8581061SN/A 8592292SN/A // Squashed sequence number must be older than youngest valid 8602292SN/A // instruction in the ROB. This prevents squashes from younger 8612292SN/A // instructions overriding squashes from older instructions. 8622292SN/A if (fromIEW->squash[tid] && 8632292SN/A commitStatus[tid] != TrapPending && 8642292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8651061SN/A 8668137SAli.Saidi@ARM.com if (fromIEW->mispredictInst[tid]) { 8678137SAli.Saidi@ARM.com DPRINTF(Commit, 8688137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 8692292SN/A tid, 8708137SAli.Saidi@ARM.com fromIEW->mispredictInst[tid]->instAddr(), 8712292SN/A fromIEW->squashedSeqNum[tid]); 8728137SAli.Saidi@ARM.com } else { 8738137SAli.Saidi@ARM.com DPRINTF(Commit, 8748137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to order violation [sn:%i]\n", 8758137SAli.Saidi@ARM.com tid, fromIEW->squashedSeqNum[tid]); 8768137SAli.Saidi@ARM.com } 8771061SN/A 8782292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8792292SN/A tid, 8807720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8811061SN/A 8822292SN/A commitStatus[tid] = ROBSquashing; 8831061SN/A 8842292SN/A // If we want to include the squashing instruction in the squash, 8852292SN/A // then use one older sequence number. 8862292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8871062SN/A 8882935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 8892292SN/A squashed_inst--; 8902935Sksewell@umich.edu } 8914035Sktlim@umich.edu 8922292SN/A // All younger instructions will be squashed. Set the sequence 8932292SN/A // number as the youngest instruction in the ROB. 8942292SN/A youngestSeqNum[tid] = squashed_inst; 8952292SN/A 8963093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8972292SN/A changedROBNumEntries[tid] = true; 8982292SN/A 8992292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 9002292SN/A 9012292SN/A toIEW->commitInfo[tid].squash = true; 9022292SN/A 9032292SN/A // Send back the rob squashing signal so other stages know that 9042292SN/A // the ROB is in the process of squashing. 9052292SN/A toIEW->commitInfo[tid].robSquashing = true; 9062292SN/A 9077851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 9087851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 9092292SN/A toIEW->commitInfo[tid].branchTaken = 9102292SN/A fromIEW->branchTaken[tid]; 9118822Snilay@cs.wisc.edu toIEW->commitInfo[tid].squashInst = 9128822Snilay@cs.wisc.edu rob->findInst(tid, squashed_inst); 9138842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst) { 9148842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 9158842Smrinmoy.ghosh@arm.com toIEW->commitInfo[tid].branchTaken = true; 9168842Smrinmoy.ghosh@arm.com } 9178842Smrinmoy.ghosh@arm.com } 9182292SN/A 9197720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 9202292SN/A 9218137SAli.Saidi@ARM.com if (toIEW->commitInfo[tid].mispredictInst) { 9222292SN/A ++branchMispredicts; 9232292SN/A } 9241062SN/A } 9252292SN/A 9261060SN/A } 9271060SN/A 9282292SN/A setNextStatus(); 9292292SN/A 9302292SN/A if (squashCounter != numThreads) { 9311061SN/A // If we're not currently squashing, then get instructions. 9321060SN/A getInsts(); 9331060SN/A 9341061SN/A // Try to commit any instructions. 9351060SN/A commitInsts(); 9361060SN/A } 9371060SN/A 9382292SN/A //Check for any activity 9393867Sbinkertn@umich.edu threads = activeThreads->begin(); 9402292SN/A 9413867Sbinkertn@umich.edu while (threads != end) { 9426221Snate@binkert.org ThreadID tid = *threads++; 9432292SN/A 9442292SN/A if (changedROBNumEntries[tid]) { 9452292SN/A toIEW->commitInfo[tid].usedROB = true; 9462292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9472292SN/A 9482292SN/A wroteToTimeBuffer = true; 9492292SN/A changedROBNumEntries[tid] = false; 9504035Sktlim@umich.edu if (rob->isEmpty(tid)) 9514035Sktlim@umich.edu checkEmptyROB[tid] = true; 9522292SN/A } 9534035Sktlim@umich.edu 9544035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 9554035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 9564035Sktlim@umich.edu // stage has received any information regarding stores that 9574035Sktlim@umich.edu // committed. 9584035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 9594035Sktlim@umich.edu // on the same cycle as when stores have been committed. 9604035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 9614035Sktlim@umich.edu // commit and IEW. 9624035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9635557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9644035Sktlim@umich.edu checkEmptyROB[tid] = false; 9654035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 9664035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 9674035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9684035Sktlim@umich.edu wroteToTimeBuffer = true; 9694035Sktlim@umich.edu } 9704035Sktlim@umich.edu 9711060SN/A } 9721060SN/A} 9731060SN/A 9741061SN/Atemplate <class Impl> 9751060SN/Avoid 9762292SN/ADefaultCommit<Impl>::commitInsts() 9771060SN/A{ 9781060SN/A //////////////////////////////////// 9791060SN/A // Handle commit 9802316SN/A // Note that commit will be handled prior to putting new 9812316SN/A // instructions in the ROB so that the ROB only tries to commit 9822316SN/A // instructions it has in this current cycle, and not instructions 9832316SN/A // it is writing in during this cycle. Can't commit and squash 9842316SN/A // things at the same time... 9851060SN/A //////////////////////////////////// 9861060SN/A 9872292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9881060SN/A 9891060SN/A unsigned num_committed = 0; 9901060SN/A 9912292SN/A DynInstPtr head_inst; 9922316SN/A 9931060SN/A // Commit as many instructions as possible until the commit bandwidth 9941060SN/A // limit is reached, or it becomes impossible to commit any more. 9952292SN/A while (num_committed < commitWidth) { 9968823Snilay@cs.wisc.edu // Check for any interrupt that we've already squashed for 9978823Snilay@cs.wisc.edu // and start processing it. 9988823Snilay@cs.wisc.edu if (interrupt != NoFault) 9998823Snilay@cs.wisc.edu handleInterrupt(); 10008823Snilay@cs.wisc.edu 10012292SN/A int commit_thread = getCommittingThread(); 10021060SN/A 10032292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 10042292SN/A break; 10052292SN/A 10062292SN/A head_inst = rob->readHeadInst(commit_thread); 10072292SN/A 10086221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 10092292SN/A 10102292SN/A assert(tid == commit_thread); 10112292SN/A 10122292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 10132292SN/A head_inst->seqNum, tid); 10142132SN/A 10152316SN/A // If the head instruction is squashed, it is ready to retire 10162316SN/A // (be removed from the ROB) at any time. 10171060SN/A if (head_inst->isSquashed()) { 10181060SN/A 10192292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 10201060SN/A "ROB.\n"); 10211060SN/A 10222292SN/A rob->retireHead(commit_thread); 10231060SN/A 10241062SN/A ++commitSquashedInsts; 10251062SN/A 10262292SN/A // Record that the number of ROB entries has changed. 10272292SN/A changedROBNumEntries[tid] = true; 10281060SN/A } else { 10297720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 10302292SN/A 10311060SN/A // Increment the total number of non-speculative instructions 10321060SN/A // executed. 10331060SN/A // Hack for now: it really shouldn't happen until after the 10341061SN/A // commit is deemed to be successful, but this count is needed 10351061SN/A // for syscalls. 10362292SN/A thread[tid]->funcExeInst++; 10371060SN/A 10381060SN/A // Try to commit the head instruction. 10391060SN/A bool commit_success = commitHead(head_inst, num_committed); 10401060SN/A 10411062SN/A if (commit_success) { 10421060SN/A ++num_committed; 104310193SCurtis.Dunham@arm.com statCommittedInstType[tid][head_inst->opClass()]++; 104410023Smatt.horsnell@ARM.com ppCommit->notify(head_inst); 10451060SN/A 10462292SN/A changedROBNumEntries[tid] = true; 10472292SN/A 10482292SN/A // Set the doneSeqNum to the youngest committed instruction. 10492292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 10501060SN/A 10518823Snilay@cs.wisc.edu if (tid == 0) { 10528823Snilay@cs.wisc.edu canHandleInterrupts = (!head_inst->isDelayedCommit()) && 10538823Snilay@cs.wisc.edu ((THE_ISA != ALPHA_ISA) || 10548823Snilay@cs.wisc.edu (!(pc[0].instAddr() & 0x3))); 10558823Snilay@cs.wisc.edu } 10568823Snilay@cs.wisc.edu 10577783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 10587783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 10597783SGiacomo.Gabrielli@arm.com 106010034SGeoffrey.Blake@arm.com // Check instruction execution if it successfully commits and 106110034SGeoffrey.Blake@arm.com // is not carrying a fault. 106210034SGeoffrey.Blake@arm.com if (cpu->checker) { 106310034SGeoffrey.Blake@arm.com cpu->checker->verify(head_inst); 106410034SGeoffrey.Blake@arm.com } 106510034SGeoffrey.Blake@arm.com 10668662SAli.Saidi@ARM.com cpu->traceFunctions(pc[tid].instAddr()); 10678662SAli.Saidi@ARM.com 10687720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 10692935Sksewell@umich.edu 10707855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 10717855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 10727855SAli.Saidi@ARM.com 10737784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 10747784SAli.Saidi@ARM.com // others squash everything and restart fetch 10757784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 10769437SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10777784SAli.Saidi@ARM.com 10789444SAndreas.Sandberg@ARM.com if (drainPending) { 10799444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 10809444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() == 0 && interrupt == NoFault) { 10819444SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10829444SAndreas.Sandberg@ARM.com cpu->commitDrained(tid); 10839444SAndreas.Sandberg@ARM.com } 10849444SAndreas.Sandberg@ARM.com } 10859444SAndreas.Sandberg@ARM.com 10862292SN/A int count = 0; 10872292SN/A Addr oldpc; 10885108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 10895108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 10909382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending); 10912292SN/A do { 10927720Sgblack@eecs.umich.edu oldpc = pc[tid].instAddr(); 10935108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 10942292SN/A count++; 10957720Sgblack@eecs.umich.edu } while (oldpc != pc[tid].instAddr()); 10962292SN/A if (count > 1) { 10975108Sgblack@eecs.umich.edu DPRINTF(Commit, 10985108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 10992292SN/A break; 11002292SN/A } 11019513SAli.Saidi@ARM.com 11029513SAli.Saidi@ARM.com // Check if an instruction just enabled interrupts and we've 11039513SAli.Saidi@ARM.com // previously had an interrupt pending that was not handled 11049513SAli.Saidi@ARM.com // because interrupts were subsequently disabled before the 11059513SAli.Saidi@ARM.com // pipeline reached a place to handle the interrupt. In that 11069513SAli.Saidi@ARM.com // case squash now to make sure the interrupt is handled. 11079513SAli.Saidi@ARM.com // 11089513SAli.Saidi@ARM.com // If we don't do this, we might end up in a live lock situation 11099513SAli.Saidi@ARM.com if (!interrupt && avoidQuiesceLiveLock && 11109513SAli.Saidi@ARM.com (!head_inst->isMicroop() || head_inst->isLastMicroop()) && 11119513SAli.Saidi@ARM.com cpu->checkInterrupts(cpu->tcBase(0))) 11129513SAli.Saidi@ARM.com squashAfter(tid, head_inst); 11131060SN/A } else { 11147720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 11152292SN/A "[tid:%i] [sn:%i].\n", 11167720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 11171060SN/A break; 11181060SN/A } 11191060SN/A } 11201060SN/A } 11211062SN/A 11221063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 11232292SN/A numCommittedDist.sample(num_committed); 11242307SN/A 11252307SN/A if (num_committed == commitWidth) { 11262349SN/A commitEligibleSamples++; 11272307SN/A } 11281060SN/A} 11291060SN/A 11301061SN/Atemplate <class Impl> 11311060SN/Abool 11322292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 11331060SN/A{ 11341060SN/A assert(head_inst); 11351060SN/A 11366221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 11372292SN/A 11382316SN/A // If the instruction is not executed yet, then it will need extra 11392316SN/A // handling. Signal backwards that it should be executed. 11401061SN/A if (!head_inst->isExecuted()) { 11411061SN/A // Keep this number correct. We have not yet actually executed 11421061SN/A // and committed this instruction. 11432292SN/A thread[tid]->funcExeInst--; 11441062SN/A 11459948SAli.Saidi@ARM.com // Make sure we are only trying to commit un-executed instructions we 11469948SAli.Saidi@ARM.com // think are possible. 11479948SAli.Saidi@ARM.com assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 11489948SAli.Saidi@ARM.com || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 11499948SAli.Saidi@ARM.com (head_inst->isLoad() && head_inst->uncacheable())); 11502316SN/A 11519948SAli.Saidi@ARM.com DPRINTF(Commit, "Encountered a barrier or non-speculative " 11529948SAli.Saidi@ARM.com "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 11539948SAli.Saidi@ARM.com head_inst->seqNum, head_inst->pcState()); 11542316SN/A 11559948SAli.Saidi@ARM.com if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 11569948SAli.Saidi@ARM.com DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 11579948SAli.Saidi@ARM.com return false; 11589948SAli.Saidi@ARM.com } 11592292SN/A 11609948SAli.Saidi@ARM.com toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 11611061SN/A 11629948SAli.Saidi@ARM.com // Change the instruction so it won't try to commit again until 11639948SAli.Saidi@ARM.com // it is executed. 11649948SAli.Saidi@ARM.com head_inst->clearCanCommit(); 11651061SN/A 11669948SAli.Saidi@ARM.com if (head_inst->isLoad() && head_inst->uncacheable()) { 11677720Sgblack@eecs.umich.edu DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 11687720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11692292SN/A toIEW->commitInfo[tid].uncached = true; 11702292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 11719948SAli.Saidi@ARM.com } else { 11729948SAli.Saidi@ARM.com ++commitNonSpecStalls; 11739948SAli.Saidi@ARM.com } 11742292SN/A 11759948SAli.Saidi@ARM.com return false; 11761060SN/A } 11771060SN/A 11782316SN/A if (head_inst->isThreadSync()) { 11792292SN/A // Not handled for now. 11802316SN/A panic("Thread sync instructions are not handled yet.\n"); 11812132SN/A } 11822132SN/A 11834035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 11844035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 11854035Sktlim@umich.edu 11862316SN/A // Stores mark themselves as completed. 11874035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 11882310SN/A head_inst->setCompleted(); 11892310SN/A } 11902310SN/A 11912112SN/A if (inst_fault != NoFault) { 11927720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 11937720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11942292SN/A 11955557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 11962316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 11972316SN/A return false; 11982316SN/A } 11992310SN/A 12004035Sktlim@umich.edu head_inst->setCompleted(); 12014035Sktlim@umich.edu 120210034SGeoffrey.Blake@arm.com // If instruction has faulted, let the checker execute it and 120310034SGeoffrey.Blake@arm.com // check if it sees the same fault and control flow. 12048733Sgeoffrey.blake@arm.com if (cpu->checker) { 12058733Sgeoffrey.blake@arm.com // Need to check the instruction before its fault is processed 12062732Sktlim@umich.edu cpu->checker->verify(head_inst); 12072316SN/A } 12082292SN/A 12099382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC); 12102292SN/A 12112316SN/A // Mark that we're in state update mode so that the trap's 12122316SN/A // execution doesn't generate extra squashes. 12139382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 12142292SN/A 12152316SN/A // Execute the trap. Although it's slightly unrealistic in 12162316SN/A // terms of timing (as it doesn't wait for the full timing of 12172316SN/A // the trap event to complete before updating state), it's 12182316SN/A // needed to update the state as soon as possible. This 12192316SN/A // prevents external agents from changing any specific state 12202316SN/A // that the trap need. 12217684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 12222292SN/A 12232316SN/A // Exit state update mode to avoid accidental updating. 12249382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 12252292SN/A 12262316SN/A commitStatus[tid] = TrapPending; 12272292SN/A 12288067SAli.Saidi@ARM.com DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 12298067SAli.Saidi@ARM.com head_inst->seqNum); 12304035Sktlim@umich.edu if (head_inst->traceData) { 12316667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 12326667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 12338834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12346667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 12356667Ssteve.reinhardt@amd.com } 12364288Sktlim@umich.edu delete head_inst->traceData; 12374035Sktlim@umich.edu head_inst->traceData = NULL; 12384035Sktlim@umich.edu } 12394035Sktlim@umich.edu 12402316SN/A // Generate trap squash event. 12412316SN/A generateTrapEvent(tid); 12422316SN/A return false; 12431060SN/A } 12441060SN/A 12452301SN/A updateComInstStats(head_inst); 12462132SN/A 12478793Sgblack@eecs.umich.edu if (FullSystem) { 12488793Sgblack@eecs.umich.edu if (thread[tid]->profile) { 12498793Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 12508793Sgblack@eecs.umich.edu ProfileNode *node = thread[tid]->profile->consume( 12518793Sgblack@eecs.umich.edu thread[tid]->getTC(), head_inst->staticInst); 12522362SN/A 12538793Sgblack@eecs.umich.edu if (node) 12548793Sgblack@eecs.umich.edu thread[tid]->profileNode = node; 12558793Sgblack@eecs.umich.edu } 12568793Sgblack@eecs.umich.edu if (CPA::available()) { 12578793Sgblack@eecs.umich.edu if (head_inst->isControl()) { 12588793Sgblack@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 12598793Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 12608793Sgblack@eecs.umich.edu } 12615953Ssaidi@eecs.umich.edu } 12625953Ssaidi@eecs.umich.edu } 12638516SMrinmoy.Ghosh@arm.com DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 12648516SMrinmoy.Ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12652132SN/A if (head_inst->traceData) { 12662292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 12678834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12684046Sbinkertn@umich.edu head_inst->traceData->dump(); 12694046Sbinkertn@umich.edu delete head_inst->traceData; 12702292SN/A head_inst->traceData = NULL; 12711060SN/A } 12728843Smrinmoy.ghosh@arm.com if (head_inst->isReturn()) { 12738843Smrinmoy.ghosh@arm.com DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 12748843Smrinmoy.ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12758843Smrinmoy.ghosh@arm.com } 12761060SN/A 12772292SN/A // Update the commit rename map 12782292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 12793771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 12802292SN/A head_inst->renamedDestRegIdx(i)); 12811060SN/A } 12821062SN/A 12832292SN/A // Finally clear the head ROB entry. 12842292SN/A rob->retireHead(tid); 12851060SN/A 12868471SGiacomo.Gabrielli@arm.com#if TRACING_ON 12879527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 12889527SMatt.Horsnell@arm.com head_inst->commitTick = curTick() - head_inst->fetchTick; 12899527SMatt.Horsnell@arm.com } 12908471SGiacomo.Gabrielli@arm.com#endif 12918471SGiacomo.Gabrielli@arm.com 12924035Sktlim@umich.edu // If this was a store, record it for this cycle. 12934035Sktlim@umich.edu if (head_inst->isStore()) 12944035Sktlim@umich.edu committedStores[tid] = true; 12954035Sktlim@umich.edu 12961060SN/A // Return true to indicate that we have committed an instruction. 12971060SN/A return true; 12981060SN/A} 12991060SN/A 13001061SN/Atemplate <class Impl> 13011060SN/Avoid 13022292SN/ADefaultCommit<Impl>::getInsts() 13031060SN/A{ 13042935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 13052935Sksewell@umich.edu 13063093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 13073093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 13082965Sksewell@umich.edu 13092965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 13102965Sksewell@umich.edu DynInstPtr inst; 13112965Sksewell@umich.edu 13123093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 13136221Snate@binkert.org ThreadID tid = inst->threadNumber; 13142292SN/A 13152292SN/A if (!inst->isSquashed() && 13164035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 13174035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 13182292SN/A changedROBNumEntries[tid] = true; 13192292SN/A 13207720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 13217720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13222292SN/A 13232292SN/A rob->insertInst(inst); 13242292SN/A 13252292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 13262292SN/A 13272292SN/A youngestSeqNum[tid] = inst->seqNum; 13281061SN/A } else { 13297720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 13301061SN/A "squashed, skipping.\n", 13317720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13321061SN/A } 13331060SN/A } 13342965Sksewell@umich.edu} 13352965Sksewell@umich.edu 13362965Sksewell@umich.edutemplate <class Impl> 13372965Sksewell@umich.eduvoid 13382965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 13392965Sksewell@umich.edu{ 13402965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 13412965Sksewell@umich.edu "skidBuffer.\n"); 13422965Sksewell@umich.edu 13432965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 13442965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 13452965Sksewell@umich.edu 13462965Sksewell@umich.edu if (!inst->isSquashed()) { 13477720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 13487720Sgblack@eecs.umich.edu "skidBuffer.\n", inst->pcState(), inst->seqNum, 13493221Sktlim@umich.edu inst->threadNumber); 13502965Sksewell@umich.edu skidBuffer.push(inst); 13512965Sksewell@umich.edu } else { 13527720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 13532965Sksewell@umich.edu "squashed, skipping.\n", 13547720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->threadNumber); 13552965Sksewell@umich.edu } 13562965Sksewell@umich.edu } 13571060SN/A} 13581060SN/A 13591061SN/Atemplate <class Impl> 13601060SN/Avoid 13612292SN/ADefaultCommit<Impl>::markCompletedInsts() 13621060SN/A{ 13631060SN/A // Grab completed insts out of the IEW instruction queue, and mark 13641060SN/A // instructions completed within the ROB. 13651060SN/A for (int inst_num = 0; 13661681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 13671060SN/A ++inst_num) 13681060SN/A { 13692292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 13707720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 13712316SN/A "within ROB.\n", 13722292SN/A fromIEW->insts[inst_num]->threadNumber, 13737720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 13742292SN/A fromIEW->insts[inst_num]->seqNum); 13751060SN/A 13762292SN/A // Mark the instruction as ready to commit. 13772292SN/A fromIEW->insts[inst_num]->setCanCommit(); 13782292SN/A } 13791060SN/A } 13801060SN/A} 13811060SN/A 13821061SN/Atemplate <class Impl> 13832292SN/Abool 13842292SN/ADefaultCommit<Impl>::robDoneSquashing() 13851060SN/A{ 13866221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 13876221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 13882292SN/A 13893867Sbinkertn@umich.edu while (threads != end) { 13906221Snate@binkert.org ThreadID tid = *threads++; 13912292SN/A 13922292SN/A if (!rob->isDoneSquashing(tid)) 13932292SN/A return false; 13942292SN/A } 13952292SN/A 13962292SN/A return true; 13971060SN/A} 13982292SN/A 13992301SN/Atemplate <class Impl> 14002301SN/Avoid 14012301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 14022301SN/A{ 14036221Snate@binkert.org ThreadID tid = inst->threadNumber; 14042301SN/A 14058834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) 14068834Satgutier@umich.edu instsCommitted[tid]++; 14078834Satgutier@umich.edu opsCommitted[tid]++; 14082301SN/A 14099218Satgutier@umich.edu // To match the old model, don't count nops and instruction 14109218Satgutier@umich.edu // prefetches towards the total commit count. 14119218Satgutier@umich.edu if (!inst->isNop() && !inst->isInstPrefetch()) { 14129218Satgutier@umich.edu cpu->instDone(tid, inst); 14139218Satgutier@umich.edu } 14149218Satgutier@umich.edu 14152301SN/A // 14162301SN/A // Control Instructions 14172301SN/A // 14182301SN/A if (inst->isControl()) 14196221Snate@binkert.org statComBranches[tid]++; 14202301SN/A 14212301SN/A // 14222301SN/A // Memory references 14232301SN/A // 14242301SN/A if (inst->isMemRef()) { 14256221Snate@binkert.org statComRefs[tid]++; 14262301SN/A 14272301SN/A if (inst->isLoad()) { 14286221Snate@binkert.org statComLoads[tid]++; 14292301SN/A } 14302301SN/A } 14312301SN/A 14322301SN/A if (inst->isMemBarrier()) { 14336221Snate@binkert.org statComMembars[tid]++; 14342301SN/A } 14357897Shestness@cs.utexas.edu 14367897Shestness@cs.utexas.edu // Integer Instruction 14377897Shestness@cs.utexas.edu if (inst->isInteger()) 14387897Shestness@cs.utexas.edu statComInteger[tid]++; 14397897Shestness@cs.utexas.edu 14407897Shestness@cs.utexas.edu // Floating Point Instruction 14417897Shestness@cs.utexas.edu if (inst->isFloating()) 14427897Shestness@cs.utexas.edu statComFloating[tid]++; 14437897Shestness@cs.utexas.edu 14447897Shestness@cs.utexas.edu // Function Calls 14457897Shestness@cs.utexas.edu if (inst->isCall()) 14467897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 14477897Shestness@cs.utexas.edu 14482301SN/A} 14492301SN/A 14502292SN/A//////////////////////////////////////// 14512292SN/A// // 14522316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 14532292SN/A// // 14542292SN/A//////////////////////////////////////// 14552292SN/Atemplate <class Impl> 14566221Snate@binkert.orgThreadID 14572292SN/ADefaultCommit<Impl>::getCommittingThread() 14582292SN/A{ 14592292SN/A if (numThreads > 1) { 14602292SN/A switch (commitPolicy) { 14612292SN/A 14622292SN/A case Aggressive: 14632292SN/A //If Policy is Aggressive, commit will call 14642292SN/A //this function multiple times per 14652292SN/A //cycle 14662292SN/A return oldestReady(); 14672292SN/A 14682292SN/A case RoundRobin: 14692292SN/A return roundRobin(); 14702292SN/A 14712292SN/A case OldestReady: 14722292SN/A return oldestReady(); 14732292SN/A 14742292SN/A default: 14756221Snate@binkert.org return InvalidThreadID; 14762292SN/A } 14772292SN/A } else { 14783867Sbinkertn@umich.edu assert(!activeThreads->empty()); 14796221Snate@binkert.org ThreadID tid = activeThreads->front(); 14802292SN/A 14812292SN/A if (commitStatus[tid] == Running || 14822292SN/A commitStatus[tid] == Idle || 14832292SN/A commitStatus[tid] == FetchTrapPending) { 14842292SN/A return tid; 14852292SN/A } else { 14866221Snate@binkert.org return InvalidThreadID; 14872292SN/A } 14882292SN/A } 14892292SN/A} 14902292SN/A 14912292SN/Atemplate<class Impl> 14926221Snate@binkert.orgThreadID 14932292SN/ADefaultCommit<Impl>::roundRobin() 14942292SN/A{ 14956221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14966221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14972292SN/A 14982292SN/A while (pri_iter != end) { 14996221Snate@binkert.org ThreadID tid = *pri_iter; 15002292SN/A 15012292SN/A if (commitStatus[tid] == Running || 15022831Sksewell@umich.edu commitStatus[tid] == Idle || 15032831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 15042292SN/A 15052292SN/A if (rob->isHeadReady(tid)) { 15062292SN/A priority_list.erase(pri_iter); 15072292SN/A priority_list.push_back(tid); 15082292SN/A 15092292SN/A return tid; 15102292SN/A } 15112292SN/A } 15122292SN/A 15132292SN/A pri_iter++; 15142292SN/A } 15152292SN/A 15166221Snate@binkert.org return InvalidThreadID; 15172292SN/A} 15182292SN/A 15192292SN/Atemplate<class Impl> 15206221Snate@binkert.orgThreadID 15212292SN/ADefaultCommit<Impl>::oldestReady() 15222292SN/A{ 15232292SN/A unsigned oldest = 0; 15242292SN/A bool first = true; 15252292SN/A 15266221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15276221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15282292SN/A 15293867Sbinkertn@umich.edu while (threads != end) { 15306221Snate@binkert.org ThreadID tid = *threads++; 15312292SN/A 15322292SN/A if (!rob->isEmpty(tid) && 15332292SN/A (commitStatus[tid] == Running || 15342292SN/A commitStatus[tid] == Idle || 15352292SN/A commitStatus[tid] == FetchTrapPending)) { 15362292SN/A 15372292SN/A if (rob->isHeadReady(tid)) { 15382292SN/A 15392292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 15402292SN/A 15412292SN/A if (first) { 15422292SN/A oldest = tid; 15432292SN/A first = false; 15442292SN/A } else if (head_inst->seqNum < oldest) { 15452292SN/A oldest = tid; 15462292SN/A } 15472292SN/A } 15482292SN/A } 15492292SN/A } 15502292SN/A 15512292SN/A if (!first) { 15522292SN/A return oldest; 15532292SN/A } else { 15546221Snate@binkert.org return InvalidThreadID; 15552292SN/A } 15562292SN/A} 15579944Smatt.horsnell@ARM.com 15589944Smatt.horsnell@ARM.com#endif//__CPU_O3_COMMIT_IMPL_HH__ 1559