commit_impl.hh revision 10172
11689SN/A/* 29948SAli.Saidi@ARM.com * Copyright (c) 2010-2013 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412965Sksewell@umich.edu * Korey Sewell 421689SN/A */ 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_COMMIT_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_COMMIT_IMPL_HH__ 451689SN/A 462292SN/A#include <algorithm> 479516SAli.Saidi@ARM.com#include <set> 482329SN/A#include <string> 492292SN/A 503577Sgblack@eecs.umich.edu#include "arch/utility.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 525953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 551717SN/A#include "cpu/o3/commit.hh" 562292SN/A#include "cpu/o3/thread_state.hh" 578662SAli.Saidi@ARM.com#include "cpu/base.hh" 588229Snate@binkert.org#include "cpu/exetrace.hh" 598229Snate@binkert.org#include "cpu/timebuf.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 618232Snate@binkert.org#include "debug/Commit.hh" 628232Snate@binkert.org#include "debug/CommitRate.hh" 639444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 648232Snate@binkert.org#include "debug/ExecFaulting.hh" 659527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 666221Snate@binkert.org#include "params/DerivO3CPU.hh" 678230Snate@binkert.org#include "sim/faults.hh" 688793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 692292SN/A 706221Snate@binkert.orgusing namespace std; 715529Snate@binkert.org 721061SN/Atemplate <class Impl> 732292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 746221Snate@binkert.org ThreadID _tid) 758581Ssteve.reinhardt@amd.com : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 761060SN/A{ 771060SN/A} 781060SN/A 791061SN/Atemplate <class Impl> 801060SN/Avoid 812292SN/ADefaultCommit<Impl>::TrapEvent::process() 821062SN/A{ 832316SN/A // This will get reset by commit if it was switched out at the 842316SN/A // time of this event processing. 852292SN/A commit->trapSquash[tid] = true; 862292SN/A} 872292SN/A 882292SN/Atemplate <class Impl> 892292SN/Aconst char * 905336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 912292SN/A{ 924873Sstever@eecs.umich.edu return "Trap"; 932292SN/A} 942292SN/A 952292SN/Atemplate <class Impl> 965529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 974329Sktlim@umich.edu : cpu(_cpu), 984329Sktlim@umich.edu squashCounter(0), 992292SN/A iewToCommitDelay(params->iewToCommitDelay), 1002292SN/A commitToIEWDelay(params->commitToIEWDelay), 1012292SN/A renameToROBDelay(params->renameToROBDelay), 1022292SN/A fetchToCommitDelay(params->commitToFetchDelay), 1032292SN/A renameWidth(params->renameWidth), 1042292SN/A commitWidth(params->commitWidth), 1055529Snate@binkert.org numThreads(params->numThreads), 1062843Sktlim@umich.edu drainPending(false), 1078823Snilay@cs.wisc.edu trapLatency(params->trapLatency), 1089513SAli.Saidi@ARM.com canHandleInterrupts(true), 1099513SAli.Saidi@ARM.com avoidQuiesceLiveLock(false) 1102292SN/A{ 11110172Sdam.sunwoo@arm.com if (commitWidth > Impl::MaxWidth) 11210172Sdam.sunwoo@arm.com fatal("commitWidth (%d) is larger than compiled limit (%d),\n" 11310172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 11410172Sdam.sunwoo@arm.com commitWidth, static_cast<int>(Impl::MaxWidth)); 11510172Sdam.sunwoo@arm.com 1162292SN/A _status = Active; 1172292SN/A _nextStatus = Inactive; 1182980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1192292SN/A 1202292SN/A //Convert string to lowercase 1212292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1222292SN/A (int(*)(int)) tolower); 1232292SN/A 1242292SN/A //Assign commit policy 1252292SN/A if (policy == "aggressive"){ 1262292SN/A commitPolicy = Aggressive; 1272292SN/A 1288346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 1292292SN/A } else if (policy == "roundrobin"){ 1302292SN/A commitPolicy = RoundRobin; 1312292SN/A 1322292SN/A //Set-Up Priority List 1336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1342292SN/A priority_list.push_back(tid); 1352292SN/A } 1362292SN/A 1378346Sksewell@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 1382292SN/A } else if (policy == "oldestready"){ 1392292SN/A commitPolicy = OldestReady; 1402292SN/A 1414329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1422292SN/A } else { 1432292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1442292SN/A "RoundRobin,OldestReady}"); 1452292SN/A } 1462292SN/A 1476221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1486221Snate@binkert.org commitStatus[tid] = Idle; 1496221Snate@binkert.org changedROBNumEntries[tid] = false; 1506221Snate@binkert.org checkEmptyROB[tid] = false; 1516221Snate@binkert.org trapInFlight[tid] = false; 1526221Snate@binkert.org committedStores[tid] = false; 1536221Snate@binkert.org trapSquash[tid] = false; 1546221Snate@binkert.org tcSquash[tid] = false; 1557720Sgblack@eecs.umich.edu pc[tid].set(0); 1567855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = 0; 1579437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 1582292SN/A } 1593640Sktlim@umich.edu interrupt = NoFault; 1602292SN/A} 1612292SN/A 1622292SN/Atemplate <class Impl> 1632292SN/Astd::string 1642292SN/ADefaultCommit<Impl>::name() const 1652292SN/A{ 1662292SN/A return cpu->name() + ".commit"; 1672292SN/A} 1682292SN/A 1692292SN/Atemplate <class Impl> 1702292SN/Avoid 17110023Smatt.horsnell@ARM.comDefaultCommit<Impl>::regProbePoints() 17210023Smatt.horsnell@ARM.com{ 17310023Smatt.horsnell@ARM.com ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); 17410023Smatt.horsnell@ARM.com ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); 17510023Smatt.horsnell@ARM.com} 17610023Smatt.horsnell@ARM.com 17710023Smatt.horsnell@ARM.comtemplate <class Impl> 17810023Smatt.horsnell@ARM.comvoid 1792292SN/ADefaultCommit<Impl>::regStats() 1802132SN/A{ 1812301SN/A using namespace Stats; 1821062SN/A commitSquashedInsts 1831062SN/A .name(name() + ".commitSquashedInsts") 1841062SN/A .desc("The number of squashed insts skipped by commit") 1851062SN/A .prereq(commitSquashedInsts); 1861062SN/A commitSquashEvents 1871062SN/A .name(name() + ".commitSquashEvents") 1881062SN/A .desc("The number of times commit is told to squash") 1891062SN/A .prereq(commitSquashEvents); 1901062SN/A commitNonSpecStalls 1911062SN/A .name(name() + ".commitNonSpecStalls") 1921062SN/A .desc("The number of times commit has been forced to stall to " 1931062SN/A "communicate backwards") 1941062SN/A .prereq(commitNonSpecStalls); 1951062SN/A branchMispredicts 1961062SN/A .name(name() + ".branchMispredicts") 1971062SN/A .desc("The number of times a branch was mispredicted") 1981062SN/A .prereq(branchMispredicts); 1992292SN/A numCommittedDist 2001062SN/A .init(0,commitWidth,1) 2018240Snate@binkert.org .name(name() + ".committed_per_cycle") 2021062SN/A .desc("Number of insts commited each cycle") 2031062SN/A .flags(Stats::pdf) 2041062SN/A ; 2052301SN/A 2068834Satgutier@umich.edu instsCommitted 2076221Snate@binkert.org .init(cpu->numThreads) 2088834Satgutier@umich.edu .name(name() + ".committedInsts") 2092301SN/A .desc("Number of instructions committed") 2102301SN/A .flags(total) 2112301SN/A ; 2122301SN/A 2138834Satgutier@umich.edu opsCommitted 2148834Satgutier@umich.edu .init(cpu->numThreads) 2158834Satgutier@umich.edu .name(name() + ".committedOps") 2168834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 2178834Satgutier@umich.edu .flags(total) 2188834Satgutier@umich.edu ; 2198834Satgutier@umich.edu 2202316SN/A statComSwp 2216221Snate@binkert.org .init(cpu->numThreads) 2228240Snate@binkert.org .name(name() + ".swp_count") 2232301SN/A .desc("Number of s/w prefetches committed") 2242301SN/A .flags(total) 2252301SN/A ; 2262301SN/A 2272316SN/A statComRefs 2286221Snate@binkert.org .init(cpu->numThreads) 2298240Snate@binkert.org .name(name() + ".refs") 2302301SN/A .desc("Number of memory references committed") 2312301SN/A .flags(total) 2322301SN/A ; 2332301SN/A 2342316SN/A statComLoads 2356221Snate@binkert.org .init(cpu->numThreads) 2368240Snate@binkert.org .name(name() + ".loads") 2372301SN/A .desc("Number of loads committed") 2382301SN/A .flags(total) 2392301SN/A ; 2402301SN/A 2412316SN/A statComMembars 2426221Snate@binkert.org .init(cpu->numThreads) 2438240Snate@binkert.org .name(name() + ".membars") 2442301SN/A .desc("Number of memory barriers committed") 2452301SN/A .flags(total) 2462301SN/A ; 2472301SN/A 2482316SN/A statComBranches 2496221Snate@binkert.org .init(cpu->numThreads) 2508240Snate@binkert.org .name(name() + ".branches") 2512301SN/A .desc("Number of branches committed") 2522301SN/A .flags(total) 2532301SN/A ; 2542301SN/A 2557897Shestness@cs.utexas.edu statComFloating 2567897Shestness@cs.utexas.edu .init(cpu->numThreads) 2578240Snate@binkert.org .name(name() + ".fp_insts") 2587897Shestness@cs.utexas.edu .desc("Number of committed floating point instructions.") 2597897Shestness@cs.utexas.edu .flags(total) 2607897Shestness@cs.utexas.edu ; 2617897Shestness@cs.utexas.edu 2627897Shestness@cs.utexas.edu statComInteger 2637897Shestness@cs.utexas.edu .init(cpu->numThreads) 2648240Snate@binkert.org .name(name()+".int_insts") 2657897Shestness@cs.utexas.edu .desc("Number of committed integer instructions.") 2667897Shestness@cs.utexas.edu .flags(total) 2677897Shestness@cs.utexas.edu ; 2687897Shestness@cs.utexas.edu 2697897Shestness@cs.utexas.edu statComFunctionCalls 2707897Shestness@cs.utexas.edu .init(cpu->numThreads) 2718240Snate@binkert.org .name(name()+".function_calls") 2727897Shestness@cs.utexas.edu .desc("Number of function calls committed.") 2737897Shestness@cs.utexas.edu .flags(total) 2747897Shestness@cs.utexas.edu ; 2757897Shestness@cs.utexas.edu 2762316SN/A commitEligible 2776221Snate@binkert.org .init(cpu->numThreads) 2788240Snate@binkert.org .name(name() + ".bw_limited") 2792301SN/A .desc("number of insts not committed due to BW limits") 2802301SN/A .flags(total) 2812301SN/A ; 2822301SN/A 2832316SN/A commitEligibleSamples 2848240Snate@binkert.org .name(name() + ".bw_lim_events") 2852301SN/A .desc("number cycles where commit BW limit reached") 2862301SN/A ; 2871062SN/A} 2881062SN/A 2891062SN/Atemplate <class Impl> 2901062SN/Avoid 2912980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2922292SN/A{ 2932292SN/A thread = threads; 2942292SN/A} 2952292SN/A 2962292SN/Atemplate <class Impl> 2972292SN/Avoid 2982292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2991060SN/A{ 3001060SN/A timeBuffer = tb_ptr; 3011060SN/A 3021060SN/A // Setup wire to send information back to IEW. 3031060SN/A toIEW = timeBuffer->getWire(0); 3041060SN/A 3051060SN/A // Setup wire to read data from IEW (for the ROB). 3061060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 3071060SN/A} 3081060SN/A 3091061SN/Atemplate <class Impl> 3101060SN/Avoid 3112292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 3122292SN/A{ 3132292SN/A fetchQueue = fq_ptr; 3142292SN/A 3152292SN/A // Setup wire to get instructions from rename (for the ROB). 3162292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 3172292SN/A} 3182292SN/A 3192292SN/Atemplate <class Impl> 3202292SN/Avoid 3212292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3221060SN/A{ 3231060SN/A renameQueue = rq_ptr; 3241060SN/A 3251060SN/A // Setup wire to get instructions from rename (for the ROB). 3261060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 3271060SN/A} 3281060SN/A 3291061SN/Atemplate <class Impl> 3301060SN/Avoid 3312292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3321060SN/A{ 3331060SN/A iewQueue = iq_ptr; 3341060SN/A 3351060SN/A // Setup wire to get instructions from IEW. 3361060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 3371060SN/A} 3381060SN/A 3391061SN/Atemplate <class Impl> 3401060SN/Avoid 3412292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 3422292SN/A{ 3432292SN/A iewStage = iew_stage; 3442292SN/A} 3452292SN/A 3462292SN/Atemplate<class Impl> 3472292SN/Avoid 3486221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3492292SN/A{ 3502292SN/A activeThreads = at_ptr; 3512292SN/A} 3522292SN/A 3532292SN/Atemplate <class Impl> 3542292SN/Avoid 3552292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3562292SN/A{ 3576221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3586221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3592292SN/A} 3602292SN/A 3612292SN/Atemplate <class Impl> 3622292SN/Avoid 3632292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3641060SN/A{ 3651060SN/A rob = rob_ptr; 3661060SN/A} 3671060SN/A 3681061SN/Atemplate <class Impl> 3691060SN/Avoid 3709427SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::startupStage() 3711060SN/A{ 3722292SN/A rob->setActiveThreads(activeThreads); 3732292SN/A rob->resetEntries(); 3741060SN/A 3752292SN/A // Broadcast the number of free entries. 3766221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3776221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3786221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3796221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3801060SN/A } 3811060SN/A 3824329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3834329Sktlim@umich.edu // start of the simulation, so it starts as active. 3844329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3854329Sktlim@umich.edu 3862292SN/A cpu->activityThisCycle(); 3871060SN/A} 3881060SN/A 3891061SN/Atemplate <class Impl> 3909444SAndreas.Sandberg@ARM.comvoid 3912843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3921060SN/A{ 3932843Sktlim@umich.edu drainPending = true; 3942316SN/A} 3952316SN/A 3962316SN/Atemplate <class Impl> 3972316SN/Avoid 3989444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainResume() 3992843Sktlim@umich.edu{ 4002864Sktlim@umich.edu drainPending = false; 4012843Sktlim@umich.edu} 4022843Sktlim@umich.edu 4032843Sktlim@umich.edutemplate <class Impl> 4042843Sktlim@umich.eduvoid 4059444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::drainSanityCheck() const 4069444SAndreas.Sandberg@ARM.com{ 4079444SAndreas.Sandberg@ARM.com assert(isDrained()); 4089444SAndreas.Sandberg@ARM.com rob->drainSanityCheck(); 4099444SAndreas.Sandberg@ARM.com} 4109444SAndreas.Sandberg@ARM.com 4119444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4129444SAndreas.Sandberg@ARM.combool 4139444SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::isDrained() const 4149444SAndreas.Sandberg@ARM.com{ 4159444SAndreas.Sandberg@ARM.com /* Make sure no one is executing microcode. There are two reasons 4169444SAndreas.Sandberg@ARM.com * for this: 4179444SAndreas.Sandberg@ARM.com * - Hardware virtualized CPUs can't switch into the middle of a 4189444SAndreas.Sandberg@ARM.com * microcode sequence. 4199444SAndreas.Sandberg@ARM.com * - The current fetch implementation will most likely get very 4209444SAndreas.Sandberg@ARM.com * confused if it tries to start fetching an instruction that 4219444SAndreas.Sandberg@ARM.com * is executing in the middle of a ucode sequence that changes 4229444SAndreas.Sandberg@ARM.com * address mappings. This can happen on for example x86. 4239444SAndreas.Sandberg@ARM.com */ 4249444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 4259444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() != 0) 4269444SAndreas.Sandberg@ARM.com return false; 4279444SAndreas.Sandberg@ARM.com } 4289444SAndreas.Sandberg@ARM.com 4299444SAndreas.Sandberg@ARM.com /* Make sure that all instructions have finished committing before 4309444SAndreas.Sandberg@ARM.com * declaring the system as drained. We want the pipeline to be 4319444SAndreas.Sandberg@ARM.com * completely empty when we declare the CPU to be drained. This 4329444SAndreas.Sandberg@ARM.com * makes debugging easier since CPU handover and restoring from a 4339444SAndreas.Sandberg@ARM.com * checkpoint with a different CPU should have the same timing. 4349444SAndreas.Sandberg@ARM.com */ 4359444SAndreas.Sandberg@ARM.com return rob->isEmpty() && 4369444SAndreas.Sandberg@ARM.com interrupt == NoFault; 4379444SAndreas.Sandberg@ARM.com} 4389444SAndreas.Sandberg@ARM.com 4399444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4409444SAndreas.Sandberg@ARM.comvoid 4412307SN/ADefaultCommit<Impl>::takeOverFrom() 4422307SN/A{ 4432307SN/A _status = Active; 4442307SN/A _nextStatus = Inactive; 4456221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4466221Snate@binkert.org commitStatus[tid] = Idle; 4476221Snate@binkert.org changedROBNumEntries[tid] = false; 4486221Snate@binkert.org trapSquash[tid] = false; 4496221Snate@binkert.org tcSquash[tid] = false; 4509437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 4512307SN/A } 4522307SN/A squashCounter = 0; 4532307SN/A rob->takeOverFrom(); 4542307SN/A} 4552307SN/A 4562307SN/Atemplate <class Impl> 4572307SN/Avoid 4582292SN/ADefaultCommit<Impl>::updateStatus() 4592132SN/A{ 4602316SN/A // reset ROB changed variable 4616221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4626221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4633867Sbinkertn@umich.edu 4643867Sbinkertn@umich.edu while (threads != end) { 4656221Snate@binkert.org ThreadID tid = *threads++; 4663867Sbinkertn@umich.edu 4672316SN/A changedROBNumEntries[tid] = false; 4682316SN/A 4692316SN/A // Also check if any of the threads has a trap pending 4702316SN/A if (commitStatus[tid] == TrapPending || 4712316SN/A commitStatus[tid] == FetchTrapPending) { 4722316SN/A _nextStatus = Active; 4732316SN/A } 4742292SN/A } 4752292SN/A 4762292SN/A if (_nextStatus == Inactive && _status == Active) { 4772292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4782733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4792292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4802292SN/A DPRINTF(Activity, "Activating stage.\n"); 4812733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4822292SN/A } 4832292SN/A 4842292SN/A _status = _nextStatus; 4852292SN/A} 4862292SN/A 4872292SN/Atemplate <class Impl> 4882292SN/Avoid 4892292SN/ADefaultCommit<Impl>::setNextStatus() 4902292SN/A{ 4912292SN/A int squashes = 0; 4922292SN/A 4936221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4946221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4952292SN/A 4963867Sbinkertn@umich.edu while (threads != end) { 4976221Snate@binkert.org ThreadID tid = *threads++; 4982292SN/A 4992292SN/A if (commitStatus[tid] == ROBSquashing) { 5002292SN/A squashes++; 5012292SN/A } 5022292SN/A } 5032292SN/A 5042702Sktlim@umich.edu squashCounter = squashes; 5052292SN/A 5062292SN/A // If commit is currently squashing, then it will have activity for the 5072292SN/A // next cycle. Set its next status as active. 5082292SN/A if (squashCounter) { 5092292SN/A _nextStatus = Active; 5102292SN/A } 5112292SN/A} 5122292SN/A 5132292SN/Atemplate <class Impl> 5142292SN/Abool 5152292SN/ADefaultCommit<Impl>::changedROBEntries() 5162292SN/A{ 5176221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5186221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5192292SN/A 5203867Sbinkertn@umich.edu while (threads != end) { 5216221Snate@binkert.org ThreadID tid = *threads++; 5222292SN/A 5232292SN/A if (changedROBNumEntries[tid]) { 5242292SN/A return true; 5252292SN/A } 5262292SN/A } 5272292SN/A 5282292SN/A return false; 5292292SN/A} 5302292SN/A 5312292SN/Atemplate <class Impl> 5326221Snate@binkert.orgsize_t 5336221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 5342292SN/A{ 5352292SN/A return rob->numFreeEntries(tid); 5362292SN/A} 5372292SN/A 5382292SN/Atemplate <class Impl> 5392292SN/Avoid 5406221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 5412292SN/A{ 5422292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 5432292SN/A 5442292SN/A TrapEvent *trap = new TrapEvent(this, tid); 5452292SN/A 5469179Sandreas.hansson@arm.com cpu->schedule(trap, cpu->clockEdge(trapLatency)); 5474035Sktlim@umich.edu trapInFlight[tid] = true; 5488518Sgeoffrey.blake@arm.com thread[tid]->trapPending = true; 5492292SN/A} 5502292SN/A 5512292SN/Atemplate <class Impl> 5522292SN/Avoid 5536221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 5542292SN/A{ 5554035Sktlim@umich.edu assert(!trapInFlight[tid]); 5562680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 5572292SN/A 5582680Sktlim@umich.edu tcSquash[tid] = true; 5592292SN/A} 5602292SN/A 5612292SN/Atemplate <class Impl> 5622292SN/Avoid 5636221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 5642292SN/A{ 5652292SN/A // If we want to include the squashing instruction in the squash, 5662292SN/A // then use one older sequence number. 5672292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 5682292SN/A // all instructions of this thread. 56910164Ssleimanf@umich.edu InstSeqNum squashed_inst = rob->isEmpty(tid) ? 5707855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 5712292SN/A 5722292SN/A // All younger instructions will be squashed. Set the sequence 5732292SN/A // number as the youngest instruction in the ROB (0 in this case. 5742292SN/A // Hopefully nothing breaks.) 5757855SAli.Saidi@ARM.com youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 5762292SN/A 5772292SN/A rob->squash(squashed_inst, tid); 5782292SN/A changedROBNumEntries[tid] = true; 5792292SN/A 5802292SN/A // Send back the sequence number of the squashed instruction. 5812292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5822292SN/A 5832292SN/A // Send back the squash signal to tell stages that they should 5842292SN/A // squash. 5852292SN/A toIEW->commitInfo[tid].squash = true; 5862292SN/A 5872292SN/A // Send back the rob squashing signal so other stages know that 5882292SN/A // the ROB is in the process of squashing. 5892292SN/A toIEW->commitInfo[tid].robSquashing = true; 5902292SN/A 5917851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = NULL; 5928137SAli.Saidi@ARM.com toIEW->commitInfo[tid].squashInst = NULL; 5932292SN/A 5947720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = pc[tid]; 5952316SN/A} 5962292SN/A 5972316SN/Atemplate <class Impl> 5982316SN/Avoid 5996221Snate@binkert.orgDefaultCommit<Impl>::squashFromTrap(ThreadID tid) 6002316SN/A{ 6012316SN/A squashAll(tid); 6022316SN/A 6037720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 6042316SN/A 6052316SN/A thread[tid]->trapPending = false; 6069382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6074035Sktlim@umich.edu trapInFlight[tid] = false; 6082316SN/A 6092316SN/A trapSquash[tid] = false; 6102316SN/A 6112316SN/A commitStatus[tid] = ROBSquashing; 6122316SN/A cpu->activityThisCycle(); 6132316SN/A} 6142316SN/A 6152316SN/Atemplate <class Impl> 6162316SN/Avoid 6176221Snate@binkert.orgDefaultCommit<Impl>::squashFromTC(ThreadID tid) 6182316SN/A{ 6192316SN/A squashAll(tid); 6202292SN/A 6217720Sgblack@eecs.umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 6222292SN/A 6239382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6242292SN/A assert(!thread[tid]->trapPending); 6252316SN/A 6262292SN/A commitStatus[tid] = ROBSquashing; 6272292SN/A cpu->activityThisCycle(); 6282292SN/A 6292680Sktlim@umich.edu tcSquash[tid] = false; 6302292SN/A} 6312292SN/A 6322292SN/Atemplate <class Impl> 6332292SN/Avoid 6349437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid) 6357784SAli.Saidi@ARM.com{ 6369437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Squashing after squash after request, " 6379437SAndreas.Sandberg@ARM.com "restarting at PC %s\n", pc[tid]); 6387784SAli.Saidi@ARM.com 6399437SAndreas.Sandberg@ARM.com squashAll(tid); 6409437SAndreas.Sandberg@ARM.com // Make sure to inform the fetch stage of which instruction caused 6419437SAndreas.Sandberg@ARM.com // the squash. It'll try to re-fetch an instruction executing in 6429437SAndreas.Sandberg@ARM.com // microcode unless this is set. 6439437SAndreas.Sandberg@ARM.com toIEW->commitInfo[tid].squashInst = squashAfterInst[tid]; 6449437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = NULL; 6457784SAli.Saidi@ARM.com 6469437SAndreas.Sandberg@ARM.com commitStatus[tid] = ROBSquashing; 6479437SAndreas.Sandberg@ARM.com cpu->activityThisCycle(); 6489437SAndreas.Sandberg@ARM.com} 6497784SAli.Saidi@ARM.com 6509437SAndreas.Sandberg@ARM.comtemplate <class Impl> 6519437SAndreas.Sandberg@ARM.comvoid 6529437SAndreas.Sandberg@ARM.comDefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst) 6539437SAndreas.Sandberg@ARM.com{ 6549437SAndreas.Sandberg@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 6559437SAndreas.Sandberg@ARM.com tid, head_inst->seqNum); 6567784SAli.Saidi@ARM.com 6579437SAndreas.Sandberg@ARM.com assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); 6589437SAndreas.Sandberg@ARM.com commitStatus[tid] = SquashAfterPending; 6599437SAndreas.Sandberg@ARM.com squashAfterInst[tid] = head_inst; 6607784SAli.Saidi@ARM.com} 6617784SAli.Saidi@ARM.com 6627784SAli.Saidi@ARM.comtemplate <class Impl> 6637784SAli.Saidi@ARM.comvoid 6642292SN/ADefaultCommit<Impl>::tick() 6652292SN/A{ 6662292SN/A wroteToTimeBuffer = false; 6672292SN/A _nextStatus = Inactive; 6682292SN/A 6693867Sbinkertn@umich.edu if (activeThreads->empty()) 6702875Sksewell@umich.edu return; 6712875Sksewell@umich.edu 6726221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6736221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6742292SN/A 6752316SN/A // Check if any of the threads are done squashing. Change the 6762316SN/A // status if they are done. 6773867Sbinkertn@umich.edu while (threads != end) { 6786221Snate@binkert.org ThreadID tid = *threads++; 6792292SN/A 6804035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6814035Sktlim@umich.edu // this cycle. 6824035Sktlim@umich.edu committedStores[tid] = false; 6834035Sktlim@umich.edu 6842292SN/A if (commitStatus[tid] == ROBSquashing) { 6852292SN/A 6862292SN/A if (rob->isDoneSquashing(tid)) { 6872292SN/A commitStatus[tid] = Running; 6882292SN/A } else { 6892292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6902877Sksewell@umich.edu " insts this cycle.\n", tid); 6912702Sktlim@umich.edu rob->doSquash(tid); 6922702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6932702Sktlim@umich.edu wroteToTimeBuffer = true; 6942292SN/A } 6952292SN/A } 6962292SN/A } 6972292SN/A 6982292SN/A commit(); 6992292SN/A 7002292SN/A markCompletedInsts(); 7012292SN/A 7023867Sbinkertn@umich.edu threads = activeThreads->begin(); 7032292SN/A 7043867Sbinkertn@umich.edu while (threads != end) { 7056221Snate@binkert.org ThreadID tid = *threads++; 7062292SN/A 7072292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 7082292SN/A // The ROB has more instructions it can commit. Its next status 7092292SN/A // will be active. 7102292SN/A _nextStatus = Active; 7112292SN/A 7122292SN/A DynInstPtr inst = rob->readHeadInst(tid); 7132292SN/A 7147720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 7152292SN/A " ROB and ready to commit\n", 7167720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7172292SN/A 7182292SN/A } else if (!rob->isEmpty(tid)) { 7192292SN/A DynInstPtr inst = rob->readHeadInst(tid); 7202292SN/A 72110023Smatt.horsnell@ARM.com ppCommitStall->notify(inst); 72210023Smatt.horsnell@ARM.com 7232292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 7247720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 7257720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 7262292SN/A } 7272292SN/A 7282292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 7292292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 7302292SN/A } 7312292SN/A 7322292SN/A 7332292SN/A if (wroteToTimeBuffer) { 7342316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 7352292SN/A cpu->activityThisCycle(); 7362292SN/A } 7372292SN/A 7382292SN/A updateStatus(); 7392292SN/A} 7402292SN/A 7412292SN/Atemplate <class Impl> 7422292SN/Avoid 7434035Sktlim@umich.eduDefaultCommit<Impl>::handleInterrupt() 7442292SN/A{ 7457847Sminkyu.jeong@arm.com // Verify that we still have an interrupt to handle 7467847Sminkyu.jeong@arm.com if (!cpu->checkInterrupts(cpu->tcBase(0))) { 7477847Sminkyu.jeong@arm.com DPRINTF(Commit, "Pending interrupt is cleared by master before " 7487847Sminkyu.jeong@arm.com "it got handled. Restart fetching from the orig path.\n"); 7497847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7507847Sminkyu.jeong@arm.com interrupt = NoFault; 7519513SAli.Saidi@ARM.com avoidQuiesceLiveLock = true; 7527847Sminkyu.jeong@arm.com return; 7537847Sminkyu.jeong@arm.com } 7543633Sktlim@umich.edu 7558493Sgblack@eecs.umich.edu // Wait until all in flight instructions are finished before enterring 7568493Sgblack@eecs.umich.edu // the interrupt. 7578823Snilay@cs.wisc.edu if (canHandleInterrupts && cpu->instList.empty()) { 7587847Sminkyu.jeong@arm.com // Squash or record that I need to squash this cycle if 7597847Sminkyu.jeong@arm.com // an interrupt needed to be handled. 7607847Sminkyu.jeong@arm.com DPRINTF(Commit, "Interrupt detected.\n"); 7614035Sktlim@umich.edu 7627847Sminkyu.jeong@arm.com // Clear the interrupt now that it's going to be handled 7637847Sminkyu.jeong@arm.com toIEW->commitInfo[0].clearInterrupt = true; 7642292SN/A 7659382SAli.Saidi@ARM.com assert(!thread[0]->noSquashFromTC); 7669382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = true; 7672292SN/A 7688733Sgeoffrey.blake@arm.com if (cpu->checker) { 7698733Sgeoffrey.blake@arm.com cpu->checker->handlePendingInt(); 7708733Sgeoffrey.blake@arm.com } 7718733Sgeoffrey.blake@arm.com 7729624Snilay@cs.wisc.edu // CPU will handle interrupt. Note that we ignore the local copy of 7739624Snilay@cs.wisc.edu // interrupt. This is because the local copy may no longer be the 7749624Snilay@cs.wisc.edu // interrupt that the interrupt controller thinks is being handled. 7759624Snilay@cs.wisc.edu cpu->processInterrupts(cpu->getInterrupts()); 7763633Sktlim@umich.edu 7779382SAli.Saidi@ARM.com thread[0]->noSquashFromTC = false; 7782292SN/A 7797847Sminkyu.jeong@arm.com commitStatus[0] = TrapPending; 7802292SN/A 7817847Sminkyu.jeong@arm.com // Generate trap squash event. 7827847Sminkyu.jeong@arm.com generateTrapEvent(0); 7833640Sktlim@umich.edu 7847847Sminkyu.jeong@arm.com interrupt = NoFault; 7859513SAli.Saidi@ARM.com avoidQuiesceLiveLock = false; 7867847Sminkyu.jeong@arm.com } else { 7878823Snilay@cs.wisc.edu DPRINTF(Commit, "Interrupt pending: instruction is %sin " 7888823Snilay@cs.wisc.edu "flight, ROB is %sempty\n", 7898823Snilay@cs.wisc.edu canHandleInterrupts ? "not " : "", 7908823Snilay@cs.wisc.edu cpu->instList.empty() ? "" : "not " ); 7911060SN/A } 7924035Sktlim@umich.edu} 7937847Sminkyu.jeong@arm.com 7947847Sminkyu.jeong@arm.comtemplate <class Impl> 7957847Sminkyu.jeong@arm.comvoid 7967847Sminkyu.jeong@arm.comDefaultCommit<Impl>::propagateInterrupt() 7977847Sminkyu.jeong@arm.com{ 7987847Sminkyu.jeong@arm.com if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 7997847Sminkyu.jeong@arm.com tcSquash[0]) 8007847Sminkyu.jeong@arm.com return; 8017847Sminkyu.jeong@arm.com 8027847Sminkyu.jeong@arm.com // Process interrupts if interrupts are enabled, not in PAL 8037847Sminkyu.jeong@arm.com // mode, and no other traps or external squashes are currently 8047847Sminkyu.jeong@arm.com // pending. 8057847Sminkyu.jeong@arm.com // @todo: Allow other threads to handle interrupts. 8067847Sminkyu.jeong@arm.com 8077847Sminkyu.jeong@arm.com // Get any interrupt that happened 8087847Sminkyu.jeong@arm.com interrupt = cpu->getInterrupts(); 8097847Sminkyu.jeong@arm.com 8107847Sminkyu.jeong@arm.com // Tell fetch that there is an interrupt pending. This 8117847Sminkyu.jeong@arm.com // will make fetch wait until it sees a non PAL-mode PC, 8127847Sminkyu.jeong@arm.com // at which point it stops fetching instructions. 8137847Sminkyu.jeong@arm.com if (interrupt != NoFault) 8147847Sminkyu.jeong@arm.com toIEW->commitInfo[0].interruptPending = true; 8157847Sminkyu.jeong@arm.com} 8167847Sminkyu.jeong@arm.com 8174035Sktlim@umich.edutemplate <class Impl> 8184035Sktlim@umich.eduvoid 8194035Sktlim@umich.eduDefaultCommit<Impl>::commit() 8204035Sktlim@umich.edu{ 8218793Sgblack@eecs.umich.edu if (FullSystem) { 8228793Sgblack@eecs.umich.edu // Check if we have a interrupt and get read to handle it 8238793Sgblack@eecs.umich.edu if (cpu->checkInterrupts(cpu->tcBase(0))) 8248793Sgblack@eecs.umich.edu propagateInterrupt(); 8258793Sgblack@eecs.umich.edu } 8261060SN/A 8271060SN/A //////////////////////////////////// 8282316SN/A // Check for any possible squashes, handle them first 8291060SN/A //////////////////////////////////// 8306221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8316221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8321060SN/A 8333867Sbinkertn@umich.edu while (threads != end) { 8346221Snate@binkert.org ThreadID tid = *threads++; 8351060SN/A 8362292SN/A // Not sure which one takes priority. I think if we have 8372292SN/A // both, that's a bad sign. 8382292SN/A if (trapSquash[tid] == true) { 8392680Sktlim@umich.edu assert(!tcSquash[tid]); 8402292SN/A squashFromTrap(tid); 8412680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 8424035Sktlim@umich.edu assert(commitStatus[tid] != TrapPending); 8432680Sktlim@umich.edu squashFromTC(tid); 8449437SAndreas.Sandberg@ARM.com } else if (commitStatus[tid] == SquashAfterPending) { 8459437SAndreas.Sandberg@ARM.com // A squash from the previous cycle of the commit stage (i.e., 8469437SAndreas.Sandberg@ARM.com // commitInsts() called squashAfter) is pending. Squash the 8479437SAndreas.Sandberg@ARM.com // thread now. 8489437SAndreas.Sandberg@ARM.com squashFromSquashAfter(tid); 8492292SN/A } 8501061SN/A 8512292SN/A // Squashed sequence number must be older than youngest valid 8522292SN/A // instruction in the ROB. This prevents squashes from younger 8532292SN/A // instructions overriding squashes from older instructions. 8542292SN/A if (fromIEW->squash[tid] && 8552292SN/A commitStatus[tid] != TrapPending && 8562292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 8571061SN/A 8588137SAli.Saidi@ARM.com if (fromIEW->mispredictInst[tid]) { 8598137SAli.Saidi@ARM.com DPRINTF(Commit, 8608137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 8612292SN/A tid, 8628137SAli.Saidi@ARM.com fromIEW->mispredictInst[tid]->instAddr(), 8632292SN/A fromIEW->squashedSeqNum[tid]); 8648137SAli.Saidi@ARM.com } else { 8658137SAli.Saidi@ARM.com DPRINTF(Commit, 8668137SAli.Saidi@ARM.com "[tid:%i]: Squashing due to order violation [sn:%i]\n", 8678137SAli.Saidi@ARM.com tid, fromIEW->squashedSeqNum[tid]); 8688137SAli.Saidi@ARM.com } 8691061SN/A 8702292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 8712292SN/A tid, 8727720Sgblack@eecs.umich.edu fromIEW->pc[tid].nextInstAddr()); 8731061SN/A 8742292SN/A commitStatus[tid] = ROBSquashing; 8751061SN/A 8762292SN/A // If we want to include the squashing instruction in the squash, 8772292SN/A // then use one older sequence number. 8782292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 8791062SN/A 8802935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 8812292SN/A squashed_inst--; 8822935Sksewell@umich.edu } 8834035Sktlim@umich.edu 8842292SN/A // All younger instructions will be squashed. Set the sequence 8852292SN/A // number as the youngest instruction in the ROB. 8862292SN/A youngestSeqNum[tid] = squashed_inst; 8872292SN/A 8883093Sksewell@umich.edu rob->squash(squashed_inst, tid); 8892292SN/A changedROBNumEntries[tid] = true; 8902292SN/A 8912292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8922292SN/A 8932292SN/A toIEW->commitInfo[tid].squash = true; 8942292SN/A 8952292SN/A // Send back the rob squashing signal so other stages know that 8962292SN/A // the ROB is in the process of squashing. 8972292SN/A toIEW->commitInfo[tid].robSquashing = true; 8982292SN/A 8997851SMatt.Horsnell@arm.com toIEW->commitInfo[tid].mispredictInst = 9007851SMatt.Horsnell@arm.com fromIEW->mispredictInst[tid]; 9012292SN/A toIEW->commitInfo[tid].branchTaken = 9022292SN/A fromIEW->branchTaken[tid]; 9038822Snilay@cs.wisc.edu toIEW->commitInfo[tid].squashInst = 9048822Snilay@cs.wisc.edu rob->findInst(tid, squashed_inst); 9058842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst) { 9068842Smrinmoy.ghosh@arm.com if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 9078842Smrinmoy.ghosh@arm.com toIEW->commitInfo[tid].branchTaken = true; 9088842Smrinmoy.ghosh@arm.com } 9098842Smrinmoy.ghosh@arm.com } 9102292SN/A 9117720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 9122292SN/A 9138137SAli.Saidi@ARM.com if (toIEW->commitInfo[tid].mispredictInst) { 9142292SN/A ++branchMispredicts; 9152292SN/A } 9161062SN/A } 9172292SN/A 9181060SN/A } 9191060SN/A 9202292SN/A setNextStatus(); 9212292SN/A 9222292SN/A if (squashCounter != numThreads) { 9231061SN/A // If we're not currently squashing, then get instructions. 9241060SN/A getInsts(); 9251060SN/A 9261061SN/A // Try to commit any instructions. 9271060SN/A commitInsts(); 9281060SN/A } 9291060SN/A 9302292SN/A //Check for any activity 9313867Sbinkertn@umich.edu threads = activeThreads->begin(); 9322292SN/A 9333867Sbinkertn@umich.edu while (threads != end) { 9346221Snate@binkert.org ThreadID tid = *threads++; 9352292SN/A 9362292SN/A if (changedROBNumEntries[tid]) { 9372292SN/A toIEW->commitInfo[tid].usedROB = true; 9382292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9392292SN/A 9402292SN/A wroteToTimeBuffer = true; 9412292SN/A changedROBNumEntries[tid] = false; 9424035Sktlim@umich.edu if (rob->isEmpty(tid)) 9434035Sktlim@umich.edu checkEmptyROB[tid] = true; 9442292SN/A } 9454035Sktlim@umich.edu 9464035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 9474035Sktlim@umich.edu // ROB is empty, b) there are no outstanding stores, c) IEW 9484035Sktlim@umich.edu // stage has received any information regarding stores that 9494035Sktlim@umich.edu // committed. 9504035Sktlim@umich.edu // c) is checked by making sure to not consider the ROB empty 9514035Sktlim@umich.edu // on the same cycle as when stores have been committed. 9524035Sktlim@umich.edu // @todo: Make this handle multi-cycle communication between 9534035Sktlim@umich.edu // commit and IEW. 9544035Sktlim@umich.edu if (checkEmptyROB[tid] && rob->isEmpty(tid) && 9555557Sktlim@umich.edu !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 9564035Sktlim@umich.edu checkEmptyROB[tid] = false; 9574035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 9584035Sktlim@umich.edu toIEW->commitInfo[tid].emptyROB = true; 9594035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 9604035Sktlim@umich.edu wroteToTimeBuffer = true; 9614035Sktlim@umich.edu } 9624035Sktlim@umich.edu 9631060SN/A } 9641060SN/A} 9651060SN/A 9661061SN/Atemplate <class Impl> 9671060SN/Avoid 9682292SN/ADefaultCommit<Impl>::commitInsts() 9691060SN/A{ 9701060SN/A //////////////////////////////////// 9711060SN/A // Handle commit 9722316SN/A // Note that commit will be handled prior to putting new 9732316SN/A // instructions in the ROB so that the ROB only tries to commit 9742316SN/A // instructions it has in this current cycle, and not instructions 9752316SN/A // it is writing in during this cycle. Can't commit and squash 9762316SN/A // things at the same time... 9771060SN/A //////////////////////////////////// 9781060SN/A 9792292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 9801060SN/A 9811060SN/A unsigned num_committed = 0; 9821060SN/A 9832292SN/A DynInstPtr head_inst; 9842316SN/A 9851060SN/A // Commit as many instructions as possible until the commit bandwidth 9861060SN/A // limit is reached, or it becomes impossible to commit any more. 9872292SN/A while (num_committed < commitWidth) { 9888823Snilay@cs.wisc.edu // Check for any interrupt that we've already squashed for 9898823Snilay@cs.wisc.edu // and start processing it. 9908823Snilay@cs.wisc.edu if (interrupt != NoFault) 9918823Snilay@cs.wisc.edu handleInterrupt(); 9928823Snilay@cs.wisc.edu 9932292SN/A int commit_thread = getCommittingThread(); 9941060SN/A 9952292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9962292SN/A break; 9972292SN/A 9982292SN/A head_inst = rob->readHeadInst(commit_thread); 9992292SN/A 10006221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 10012292SN/A 10022292SN/A assert(tid == commit_thread); 10032292SN/A 10042292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 10052292SN/A head_inst->seqNum, tid); 10062132SN/A 10072316SN/A // If the head instruction is squashed, it is ready to retire 10082316SN/A // (be removed from the ROB) at any time. 10091060SN/A if (head_inst->isSquashed()) { 10101060SN/A 10112292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 10121060SN/A "ROB.\n"); 10131060SN/A 10142292SN/A rob->retireHead(commit_thread); 10151060SN/A 10161062SN/A ++commitSquashedInsts; 10171062SN/A 10182292SN/A // Record that the number of ROB entries has changed. 10192292SN/A changedROBNumEntries[tid] = true; 10201060SN/A } else { 10217720Sgblack@eecs.umich.edu pc[tid] = head_inst->pcState(); 10222292SN/A 10231060SN/A // Increment the total number of non-speculative instructions 10241060SN/A // executed. 10251060SN/A // Hack for now: it really shouldn't happen until after the 10261061SN/A // commit is deemed to be successful, but this count is needed 10271061SN/A // for syscalls. 10282292SN/A thread[tid]->funcExeInst++; 10291060SN/A 10301060SN/A // Try to commit the head instruction. 10311060SN/A bool commit_success = commitHead(head_inst, num_committed); 10321060SN/A 10331062SN/A if (commit_success) { 10341060SN/A ++num_committed; 103510023Smatt.horsnell@ARM.com ppCommit->notify(head_inst); 10361060SN/A 10372292SN/A changedROBNumEntries[tid] = true; 10382292SN/A 10392292SN/A // Set the doneSeqNum to the youngest committed instruction. 10402292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 10411060SN/A 10428823Snilay@cs.wisc.edu if (tid == 0) { 10438823Snilay@cs.wisc.edu canHandleInterrupts = (!head_inst->isDelayedCommit()) && 10448823Snilay@cs.wisc.edu ((THE_ISA != ALPHA_ISA) || 10458823Snilay@cs.wisc.edu (!(pc[0].instAddr() & 0x3))); 10468823Snilay@cs.wisc.edu } 10478823Snilay@cs.wisc.edu 10487783SGiacomo.Gabrielli@arm.com // Updates misc. registers. 10497783SGiacomo.Gabrielli@arm.com head_inst->updateMiscRegs(); 10507783SGiacomo.Gabrielli@arm.com 105110034SGeoffrey.Blake@arm.com // Check instruction execution if it successfully commits and 105210034SGeoffrey.Blake@arm.com // is not carrying a fault. 105310034SGeoffrey.Blake@arm.com if (cpu->checker) { 105410034SGeoffrey.Blake@arm.com cpu->checker->verify(head_inst); 105510034SGeoffrey.Blake@arm.com } 105610034SGeoffrey.Blake@arm.com 10578662SAli.Saidi@ARM.com cpu->traceFunctions(pc[tid].instAddr()); 10588662SAli.Saidi@ARM.com 10597720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 10602935Sksewell@umich.edu 10617855SAli.Saidi@ARM.com // Keep track of the last sequence number commited 10627855SAli.Saidi@ARM.com lastCommitedSeqNum[tid] = head_inst->seqNum; 10637855SAli.Saidi@ARM.com 10647784SAli.Saidi@ARM.com // If this is an instruction that doesn't play nicely with 10657784SAli.Saidi@ARM.com // others squash everything and restart fetch 10667784SAli.Saidi@ARM.com if (head_inst->isSquashAfter()) 10679437SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10687784SAli.Saidi@ARM.com 10699444SAndreas.Sandberg@ARM.com if (drainPending) { 10709444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 10719444SAndreas.Sandberg@ARM.com if (pc[tid].microPC() == 0 && interrupt == NoFault) { 10729444SAndreas.Sandberg@ARM.com squashAfter(tid, head_inst); 10739444SAndreas.Sandberg@ARM.com cpu->commitDrained(tid); 10749444SAndreas.Sandberg@ARM.com } 10759444SAndreas.Sandberg@ARM.com } 10769444SAndreas.Sandberg@ARM.com 10772292SN/A int count = 0; 10782292SN/A Addr oldpc; 10795108Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 10805108Sgblack@eecs.umich.edu // currently updating state while handling PC events. 10819382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending); 10822292SN/A do { 10837720Sgblack@eecs.umich.edu oldpc = pc[tid].instAddr(); 10845108Sgblack@eecs.umich.edu cpu->system->pcEventQueue.service(thread[tid]->getTC()); 10852292SN/A count++; 10867720Sgblack@eecs.umich.edu } while (oldpc != pc[tid].instAddr()); 10872292SN/A if (count > 1) { 10885108Sgblack@eecs.umich.edu DPRINTF(Commit, 10895108Sgblack@eecs.umich.edu "PC skip function event, stopping commit\n"); 10902292SN/A break; 10912292SN/A } 10929513SAli.Saidi@ARM.com 10939513SAli.Saidi@ARM.com // Check if an instruction just enabled interrupts and we've 10949513SAli.Saidi@ARM.com // previously had an interrupt pending that was not handled 10959513SAli.Saidi@ARM.com // because interrupts were subsequently disabled before the 10969513SAli.Saidi@ARM.com // pipeline reached a place to handle the interrupt. In that 10979513SAli.Saidi@ARM.com // case squash now to make sure the interrupt is handled. 10989513SAli.Saidi@ARM.com // 10999513SAli.Saidi@ARM.com // If we don't do this, we might end up in a live lock situation 11009513SAli.Saidi@ARM.com if (!interrupt && avoidQuiesceLiveLock && 11019513SAli.Saidi@ARM.com (!head_inst->isMicroop() || head_inst->isLastMicroop()) && 11029513SAli.Saidi@ARM.com cpu->checkInterrupts(cpu->tcBase(0))) 11039513SAli.Saidi@ARM.com squashAfter(tid, head_inst); 11041060SN/A } else { 11057720Sgblack@eecs.umich.edu DPRINTF(Commit, "Unable to commit head instruction PC:%s " 11062292SN/A "[tid:%i] [sn:%i].\n", 11077720Sgblack@eecs.umich.edu head_inst->pcState(), tid ,head_inst->seqNum); 11081060SN/A break; 11091060SN/A } 11101060SN/A } 11111060SN/A } 11121062SN/A 11131063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 11142292SN/A numCommittedDist.sample(num_committed); 11152307SN/A 11162307SN/A if (num_committed == commitWidth) { 11172349SN/A commitEligibleSamples++; 11182307SN/A } 11191060SN/A} 11201060SN/A 11211061SN/Atemplate <class Impl> 11221060SN/Abool 11232292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 11241060SN/A{ 11251060SN/A assert(head_inst); 11261060SN/A 11276221Snate@binkert.org ThreadID tid = head_inst->threadNumber; 11282292SN/A 11292316SN/A // If the instruction is not executed yet, then it will need extra 11302316SN/A // handling. Signal backwards that it should be executed. 11311061SN/A if (!head_inst->isExecuted()) { 11321061SN/A // Keep this number correct. We have not yet actually executed 11331061SN/A // and committed this instruction. 11342292SN/A thread[tid]->funcExeInst--; 11351062SN/A 11369948SAli.Saidi@ARM.com // Make sure we are only trying to commit un-executed instructions we 11379948SAli.Saidi@ARM.com // think are possible. 11389948SAli.Saidi@ARM.com assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() 11399948SAli.Saidi@ARM.com || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 11409948SAli.Saidi@ARM.com (head_inst->isLoad() && head_inst->uncacheable())); 11412316SN/A 11429948SAli.Saidi@ARM.com DPRINTF(Commit, "Encountered a barrier or non-speculative " 11439948SAli.Saidi@ARM.com "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 11449948SAli.Saidi@ARM.com head_inst->seqNum, head_inst->pcState()); 11452316SN/A 11469948SAli.Saidi@ARM.com if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 11479948SAli.Saidi@ARM.com DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 11489948SAli.Saidi@ARM.com return false; 11499948SAli.Saidi@ARM.com } 11502292SN/A 11519948SAli.Saidi@ARM.com toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 11521061SN/A 11539948SAli.Saidi@ARM.com // Change the instruction so it won't try to commit again until 11549948SAli.Saidi@ARM.com // it is executed. 11559948SAli.Saidi@ARM.com head_inst->clearCanCommit(); 11561061SN/A 11579948SAli.Saidi@ARM.com if (head_inst->isLoad() && head_inst->uncacheable()) { 11587720Sgblack@eecs.umich.edu DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 11597720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11602292SN/A toIEW->commitInfo[tid].uncached = true; 11612292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 11629948SAli.Saidi@ARM.com } else { 11639948SAli.Saidi@ARM.com ++commitNonSpecStalls; 11649948SAli.Saidi@ARM.com } 11652292SN/A 11669948SAli.Saidi@ARM.com return false; 11671060SN/A } 11681060SN/A 11692316SN/A if (head_inst->isThreadSync()) { 11702292SN/A // Not handled for now. 11712316SN/A panic("Thread sync instructions are not handled yet.\n"); 11722132SN/A } 11732132SN/A 11744035Sktlim@umich.edu // Check if the instruction caused a fault. If so, trap. 11754035Sktlim@umich.edu Fault inst_fault = head_inst->getFault(); 11764035Sktlim@umich.edu 11772316SN/A // Stores mark themselves as completed. 11784035Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 11792310SN/A head_inst->setCompleted(); 11802310SN/A } 11812310SN/A 11822112SN/A if (inst_fault != NoFault) { 11837720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 11847720Sgblack@eecs.umich.edu head_inst->seqNum, head_inst->pcState()); 11852292SN/A 11865557Sktlim@umich.edu if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 11872316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 11882316SN/A return false; 11892316SN/A } 11902310SN/A 11914035Sktlim@umich.edu head_inst->setCompleted(); 11924035Sktlim@umich.edu 119310034SGeoffrey.Blake@arm.com // If instruction has faulted, let the checker execute it and 119410034SGeoffrey.Blake@arm.com // check if it sees the same fault and control flow. 11958733Sgeoffrey.blake@arm.com if (cpu->checker) { 11968733Sgeoffrey.blake@arm.com // Need to check the instruction before its fault is processed 11972732Sktlim@umich.edu cpu->checker->verify(head_inst); 11982316SN/A } 11992292SN/A 12009382SAli.Saidi@ARM.com assert(!thread[tid]->noSquashFromTC); 12012292SN/A 12022316SN/A // Mark that we're in state update mode so that the trap's 12032316SN/A // execution doesn't generate extra squashes. 12049382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 12052292SN/A 12062316SN/A // Execute the trap. Although it's slightly unrealistic in 12072316SN/A // terms of timing (as it doesn't wait for the full timing of 12082316SN/A // the trap event to complete before updating state), it's 12092316SN/A // needed to update the state as soon as possible. This 12102316SN/A // prevents external agents from changing any specific state 12112316SN/A // that the trap need. 12127684Sgblack@eecs.umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 12132292SN/A 12142316SN/A // Exit state update mode to avoid accidental updating. 12159382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 12162292SN/A 12172316SN/A commitStatus[tid] = TrapPending; 12182292SN/A 12198067SAli.Saidi@ARM.com DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 12208067SAli.Saidi@ARM.com head_inst->seqNum); 12214035Sktlim@umich.edu if (head_inst->traceData) { 12226667Ssteve.reinhardt@amd.com if (DTRACE(ExecFaulting)) { 12236667Ssteve.reinhardt@amd.com head_inst->traceData->setFetchSeq(head_inst->seqNum); 12248834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12256667Ssteve.reinhardt@amd.com head_inst->traceData->dump(); 12266667Ssteve.reinhardt@amd.com } 12274288Sktlim@umich.edu delete head_inst->traceData; 12284035Sktlim@umich.edu head_inst->traceData = NULL; 12294035Sktlim@umich.edu } 12304035Sktlim@umich.edu 12312316SN/A // Generate trap squash event. 12322316SN/A generateTrapEvent(tid); 12332316SN/A return false; 12341060SN/A } 12351060SN/A 12362301SN/A updateComInstStats(head_inst); 12372132SN/A 12388793Sgblack@eecs.umich.edu if (FullSystem) { 12398793Sgblack@eecs.umich.edu if (thread[tid]->profile) { 12408793Sgblack@eecs.umich.edu thread[tid]->profilePC = head_inst->instAddr(); 12418793Sgblack@eecs.umich.edu ProfileNode *node = thread[tid]->profile->consume( 12428793Sgblack@eecs.umich.edu thread[tid]->getTC(), head_inst->staticInst); 12432362SN/A 12448793Sgblack@eecs.umich.edu if (node) 12458793Sgblack@eecs.umich.edu thread[tid]->profileNode = node; 12468793Sgblack@eecs.umich.edu } 12478793Sgblack@eecs.umich.edu if (CPA::available()) { 12488793Sgblack@eecs.umich.edu if (head_inst->isControl()) { 12498793Sgblack@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 12508793Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 12518793Sgblack@eecs.umich.edu } 12525953Ssaidi@eecs.umich.edu } 12535953Ssaidi@eecs.umich.edu } 12548516SMrinmoy.Ghosh@arm.com DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 12558516SMrinmoy.Ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12562132SN/A if (head_inst->traceData) { 12572292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 12588834Satgutier@umich.edu head_inst->traceData->setCPSeq(thread[tid]->numOp); 12594046Sbinkertn@umich.edu head_inst->traceData->dump(); 12604046Sbinkertn@umich.edu delete head_inst->traceData; 12612292SN/A head_inst->traceData = NULL; 12621060SN/A } 12638843Smrinmoy.ghosh@arm.com if (head_inst->isReturn()) { 12648843Smrinmoy.ghosh@arm.com DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 12658843Smrinmoy.ghosh@arm.com head_inst->seqNum, head_inst->pcState()); 12668843Smrinmoy.ghosh@arm.com } 12671060SN/A 12682292SN/A // Update the commit rename map 12692292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 12703771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 12712292SN/A head_inst->renamedDestRegIdx(i)); 12721060SN/A } 12731062SN/A 12742292SN/A // Finally clear the head ROB entry. 12752292SN/A rob->retireHead(tid); 12761060SN/A 12778471SGiacomo.Gabrielli@arm.com#if TRACING_ON 12789527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 12799527SMatt.Horsnell@arm.com head_inst->commitTick = curTick() - head_inst->fetchTick; 12809527SMatt.Horsnell@arm.com } 12818471SGiacomo.Gabrielli@arm.com#endif 12828471SGiacomo.Gabrielli@arm.com 12834035Sktlim@umich.edu // If this was a store, record it for this cycle. 12844035Sktlim@umich.edu if (head_inst->isStore()) 12854035Sktlim@umich.edu committedStores[tid] = true; 12864035Sktlim@umich.edu 12871060SN/A // Return true to indicate that we have committed an instruction. 12881060SN/A return true; 12891060SN/A} 12901060SN/A 12911061SN/Atemplate <class Impl> 12921060SN/Avoid 12932292SN/ADefaultCommit<Impl>::getInsts() 12941060SN/A{ 12952935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 12962935Sksewell@umich.edu 12973093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 12983093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 12992965Sksewell@umich.edu 13002965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 13012965Sksewell@umich.edu DynInstPtr inst; 13022965Sksewell@umich.edu 13033093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 13046221Snate@binkert.org ThreadID tid = inst->threadNumber; 13052292SN/A 13062292SN/A if (!inst->isSquashed() && 13074035Sktlim@umich.edu commitStatus[tid] != ROBSquashing && 13084035Sktlim@umich.edu commitStatus[tid] != TrapPending) { 13092292SN/A changedROBNumEntries[tid] = true; 13102292SN/A 13117720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 13127720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13132292SN/A 13142292SN/A rob->insertInst(inst); 13152292SN/A 13162292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 13172292SN/A 13182292SN/A youngestSeqNum[tid] = inst->seqNum; 13191061SN/A } else { 13207720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 13211061SN/A "squashed, skipping.\n", 13227720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 13231061SN/A } 13241060SN/A } 13252965Sksewell@umich.edu} 13262965Sksewell@umich.edu 13272965Sksewell@umich.edutemplate <class Impl> 13282965Sksewell@umich.eduvoid 13292965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 13302965Sksewell@umich.edu{ 13312965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 13322965Sksewell@umich.edu "skidBuffer.\n"); 13332965Sksewell@umich.edu 13342965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 13352965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 13362965Sksewell@umich.edu 13372965Sksewell@umich.edu if (!inst->isSquashed()) { 13387720Sgblack@eecs.umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 13397720Sgblack@eecs.umich.edu "skidBuffer.\n", inst->pcState(), inst->seqNum, 13403221Sktlim@umich.edu inst->threadNumber); 13412965Sksewell@umich.edu skidBuffer.push(inst); 13422965Sksewell@umich.edu } else { 13437720Sgblack@eecs.umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 13442965Sksewell@umich.edu "squashed, skipping.\n", 13457720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->threadNumber); 13462965Sksewell@umich.edu } 13472965Sksewell@umich.edu } 13481060SN/A} 13491060SN/A 13501061SN/Atemplate <class Impl> 13511060SN/Avoid 13522292SN/ADefaultCommit<Impl>::markCompletedInsts() 13531060SN/A{ 13541060SN/A // Grab completed insts out of the IEW instruction queue, and mark 13551060SN/A // instructions completed within the ROB. 13561060SN/A for (int inst_num = 0; 13571681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 13581060SN/A ++inst_num) 13591060SN/A { 13602292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 13617720Sgblack@eecs.umich.edu DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 13622316SN/A "within ROB.\n", 13632292SN/A fromIEW->insts[inst_num]->threadNumber, 13647720Sgblack@eecs.umich.edu fromIEW->insts[inst_num]->pcState(), 13652292SN/A fromIEW->insts[inst_num]->seqNum); 13661060SN/A 13672292SN/A // Mark the instruction as ready to commit. 13682292SN/A fromIEW->insts[inst_num]->setCanCommit(); 13692292SN/A } 13701060SN/A } 13711060SN/A} 13721060SN/A 13731061SN/Atemplate <class Impl> 13742292SN/Abool 13752292SN/ADefaultCommit<Impl>::robDoneSquashing() 13761060SN/A{ 13776221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 13786221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 13792292SN/A 13803867Sbinkertn@umich.edu while (threads != end) { 13816221Snate@binkert.org ThreadID tid = *threads++; 13822292SN/A 13832292SN/A if (!rob->isDoneSquashing(tid)) 13842292SN/A return false; 13852292SN/A } 13862292SN/A 13872292SN/A return true; 13881060SN/A} 13892292SN/A 13902301SN/Atemplate <class Impl> 13912301SN/Avoid 13922301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 13932301SN/A{ 13946221Snate@binkert.org ThreadID tid = inst->threadNumber; 13952301SN/A 13968834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) 13978834Satgutier@umich.edu instsCommitted[tid]++; 13988834Satgutier@umich.edu opsCommitted[tid]++; 13992301SN/A 14009218Satgutier@umich.edu // To match the old model, don't count nops and instruction 14019218Satgutier@umich.edu // prefetches towards the total commit count. 14029218Satgutier@umich.edu if (!inst->isNop() && !inst->isInstPrefetch()) { 14039218Satgutier@umich.edu cpu->instDone(tid, inst); 14049218Satgutier@umich.edu } 14059218Satgutier@umich.edu 14062301SN/A // 14072301SN/A // Control Instructions 14082301SN/A // 14092301SN/A if (inst->isControl()) 14106221Snate@binkert.org statComBranches[tid]++; 14112301SN/A 14122301SN/A // 14132301SN/A // Memory references 14142301SN/A // 14152301SN/A if (inst->isMemRef()) { 14166221Snate@binkert.org statComRefs[tid]++; 14172301SN/A 14182301SN/A if (inst->isLoad()) { 14196221Snate@binkert.org statComLoads[tid]++; 14202301SN/A } 14212301SN/A } 14222301SN/A 14232301SN/A if (inst->isMemBarrier()) { 14246221Snate@binkert.org statComMembars[tid]++; 14252301SN/A } 14267897Shestness@cs.utexas.edu 14277897Shestness@cs.utexas.edu // Integer Instruction 14287897Shestness@cs.utexas.edu if (inst->isInteger()) 14297897Shestness@cs.utexas.edu statComInteger[tid]++; 14307897Shestness@cs.utexas.edu 14317897Shestness@cs.utexas.edu // Floating Point Instruction 14327897Shestness@cs.utexas.edu if (inst->isFloating()) 14337897Shestness@cs.utexas.edu statComFloating[tid]++; 14347897Shestness@cs.utexas.edu 14357897Shestness@cs.utexas.edu // Function Calls 14367897Shestness@cs.utexas.edu if (inst->isCall()) 14377897Shestness@cs.utexas.edu statComFunctionCalls[tid]++; 14387897Shestness@cs.utexas.edu 14392301SN/A} 14402301SN/A 14412292SN/A//////////////////////////////////////// 14422292SN/A// // 14432316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 14442292SN/A// // 14452292SN/A//////////////////////////////////////// 14462292SN/Atemplate <class Impl> 14476221Snate@binkert.orgThreadID 14482292SN/ADefaultCommit<Impl>::getCommittingThread() 14492292SN/A{ 14502292SN/A if (numThreads > 1) { 14512292SN/A switch (commitPolicy) { 14522292SN/A 14532292SN/A case Aggressive: 14542292SN/A //If Policy is Aggressive, commit will call 14552292SN/A //this function multiple times per 14562292SN/A //cycle 14572292SN/A return oldestReady(); 14582292SN/A 14592292SN/A case RoundRobin: 14602292SN/A return roundRobin(); 14612292SN/A 14622292SN/A case OldestReady: 14632292SN/A return oldestReady(); 14642292SN/A 14652292SN/A default: 14666221Snate@binkert.org return InvalidThreadID; 14672292SN/A } 14682292SN/A } else { 14693867Sbinkertn@umich.edu assert(!activeThreads->empty()); 14706221Snate@binkert.org ThreadID tid = activeThreads->front(); 14712292SN/A 14722292SN/A if (commitStatus[tid] == Running || 14732292SN/A commitStatus[tid] == Idle || 14742292SN/A commitStatus[tid] == FetchTrapPending) { 14752292SN/A return tid; 14762292SN/A } else { 14776221Snate@binkert.org return InvalidThreadID; 14782292SN/A } 14792292SN/A } 14802292SN/A} 14812292SN/A 14822292SN/Atemplate<class Impl> 14836221Snate@binkert.orgThreadID 14842292SN/ADefaultCommit<Impl>::roundRobin() 14852292SN/A{ 14866221Snate@binkert.org list<ThreadID>::iterator pri_iter = priority_list.begin(); 14876221Snate@binkert.org list<ThreadID>::iterator end = priority_list.end(); 14882292SN/A 14892292SN/A while (pri_iter != end) { 14906221Snate@binkert.org ThreadID tid = *pri_iter; 14912292SN/A 14922292SN/A if (commitStatus[tid] == Running || 14932831Sksewell@umich.edu commitStatus[tid] == Idle || 14942831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 14952292SN/A 14962292SN/A if (rob->isHeadReady(tid)) { 14972292SN/A priority_list.erase(pri_iter); 14982292SN/A priority_list.push_back(tid); 14992292SN/A 15002292SN/A return tid; 15012292SN/A } 15022292SN/A } 15032292SN/A 15042292SN/A pri_iter++; 15052292SN/A } 15062292SN/A 15076221Snate@binkert.org return InvalidThreadID; 15082292SN/A} 15092292SN/A 15102292SN/Atemplate<class Impl> 15116221Snate@binkert.orgThreadID 15122292SN/ADefaultCommit<Impl>::oldestReady() 15132292SN/A{ 15142292SN/A unsigned oldest = 0; 15152292SN/A bool first = true; 15162292SN/A 15176221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15186221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15192292SN/A 15203867Sbinkertn@umich.edu while (threads != end) { 15216221Snate@binkert.org ThreadID tid = *threads++; 15222292SN/A 15232292SN/A if (!rob->isEmpty(tid) && 15242292SN/A (commitStatus[tid] == Running || 15252292SN/A commitStatus[tid] == Idle || 15262292SN/A commitStatus[tid] == FetchTrapPending)) { 15272292SN/A 15282292SN/A if (rob->isHeadReady(tid)) { 15292292SN/A 15302292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 15312292SN/A 15322292SN/A if (first) { 15332292SN/A oldest = tid; 15342292SN/A first = false; 15352292SN/A } else if (head_inst->seqNum < oldest) { 15362292SN/A oldest = tid; 15372292SN/A } 15382292SN/A } 15392292SN/A } 15402292SN/A } 15412292SN/A 15422292SN/A if (!first) { 15432292SN/A return oldest; 15442292SN/A } else { 15456221Snate@binkert.org return InvalidThreadID; 15462292SN/A } 15472292SN/A} 15489944Smatt.horsnell@ARM.com 15499944Smatt.horsnell@ARM.com#endif//__CPU_O3_COMMIT_IMPL_HH__ 1550