commit.hh revision 8137:48371b9fb929
12SN/A/* 212276Sanouk.vanlaer@arm.com * Copyright (c) 2010 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved. 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * All rights reserved. 169983Sstever@gmail.com * 179983Sstever@gmail.com * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392SN/A * 402SN/A * Authors: Kevin Lim 412SN/A * Korey Sewell 422665Ssaidi@eecs.umich.edu */ 432665Ssaidi@eecs.umich.edu 442665Ssaidi@eecs.umich.edu#ifndef __CPU_O3_COMMIT_HH__ 457897Shestness@cs.utexas.edu#define __CPU_O3_COMMIT_HH__ 462SN/A 472SN/A#include "base/statistics.hh" 4811793Sbrandon.potter@amd.com#include "cpu/timebuf.hh" 4911793Sbrandon.potter@amd.com#include "cpu/exetrace.hh" 501388SN/A#include "cpu/inst_seq.hh" 518229Snate@binkert.org 522SN/Aclass DerivO3CPUParams; 532SN/A 5412406Sgabeblack@google.comtemplate <class> 5511793Sbrandon.potter@amd.comclass O3ThreadState; 568229Snate@binkert.org 5712334Sgabeblack@google.com/** 581388SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 595529Snate@binkert.org * specified by the parameters; each cycle it tries to commit that 6010529Smorr@cs.wisc.edu * many instructions. The SMT policy decides which thread it tries to 612651Ssaidi@eecs.umich.edu * commit instructions from. Non- speculative instructions must reach 628229Snate@binkert.org * the head of the ROB before they are ready to execute; once they 632680Sktlim@umich.edu * reach the head, commit will broadcast the instruction's sequence 6410529Smorr@cs.wisc.edu * number to the previous stages so that they can issue/ execute the 658232Snate@binkert.org * instruction. Only one non-speculative instruction is handled per 6610529Smorr@cs.wisc.edu * cycle. Commit is responsible for handling all back-end initiated 675529Snate@binkert.org * redirects. It receives the redirect, and then broadcasts it to all 6811526Sdavid.guillen@arm.com * stages, indicating the sequence number they should squash until, 698779Sgblack@eecs.umich.edu * and any necessary branch misprediction information as well. It 702190SN/A * priortizes redirects by instruction's age, only broadcasting a 7156SN/A * redirect if it corresponds to an instruction that should currently 728229Snate@binkert.org * be in the ROB. This is done by tracking the sequence number of the 732190SN/A * youngest instruction in the ROB, which gets updated to any 742SN/A * squashing instruction's sequence number, and only broadcasting a 752359SN/A * redirect if it corresponds to an older instruction. Commit also 762359SN/A * supports multiple cycle squashing, to model a ROB that can only 772359SN/A * remove a certain number of instructions per cycle. 782SN/A */ 792SN/Atemplate<class Impl> 802SN/Aclass DefaultCommit 812SN/A{ 822SN/A public: 832SN/A // Typedefs from the Impl. 842SN/A typedef typename Impl::O3CPU O3CPU; 852SN/A typedef typename Impl::DynInstPtr DynInstPtr; 862SN/A typedef typename Impl::CPUPol CPUPol; 875606Snate@binkert.org 886144Sksewell@umich.edu typedef typename CPUPol::RenameMap RenameMap; 896144Sksewell@umich.edu typedef typename CPUPol::ROB ROB; 903126Sktlim@umich.edu 916144Sksewell@umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 927823Ssteve.reinhardt@amd.com typedef typename CPUPol::FetchStruct FetchStruct; 933126Sktlim@umich.edu typedef typename CPUPol::IEWStruct IEWStruct; 943126Sktlim@umich.edu typedef typename CPUPol::RenameStruct RenameStruct; 952356SN/A 962356SN/A typedef typename CPUPol::Fetch Fetch; 972356SN/A typedef typename CPUPol::IEW IEW; 988834Satgutier@umich.edu 9910786Smalek.musleh@gmail.com typedef O3ThreadState<Impl> Thread; 10010786Smalek.musleh@gmail.com 10110786Smalek.musleh@gmail.com /** Event class used to schedule a squash due to a trap (fault or 10210786Smalek.musleh@gmail.com * interrupt) to happen on a specific cycle. 10311321Ssteve.reinhardt@amd.com */ 10410786Smalek.musleh@gmail.com class TrapEvent : public Event { 10510786Smalek.musleh@gmail.com private: 10610786Smalek.musleh@gmail.com DefaultCommit<Impl> *commit; 1072356SN/A ThreadID tid; 1089179Sandreas.hansson@arm.com 1092367SN/A public: 1106144Sksewell@umich.edu TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 1116144Sksewell@umich.edu 1126144Sksewell@umich.edu void process(); 1132356SN/A const char *description() const; 1142367SN/A }; 1156144Sksewell@umich.edu 1167823Ssteve.reinhardt@amd.com /** Overall commit status. Used to determine if the CPU can deschedule 1176144Sksewell@umich.edu * itself due to a lack of activity. 1182367SN/A */ 1192356SN/A enum CommitStatus{ 1202356SN/A Active, 1212356SN/A Inactive 1222356SN/A }; 1235336Shines@cs.fsu.edu 1242356SN/A /** Individual thread status. */ 1254873Sstever@eecs.umich.edu enum ThreadStatus { 1262356SN/A Running, 1272356SN/A Idle, 1288876Sandreas.hansson@arm.com ROBSquashing, 12910190Sakash.bagdia@arm.com TrapPending, 13012680Sgiacomo.travaglini@arm.com FetchTrapPending 13112680Sgiacomo.travaglini@arm.com }; 13211050Sandreas.hansson@arm.com 1339814Sandreas.hansson@arm.com /** Commit policy for SMT mode. */ 1349220Shestness@cs.wisc.edu enum CommitPolicy { 13510529Smorr@cs.wisc.edu Aggressive, 13612284Sjose.marinho@arm.com RoundRobin, 13710537Sandreas.hansson@arm.com OldestReady 13810537Sandreas.hansson@arm.com }; 13911877Sbrandon.potter@amd.com 14012276Sanouk.vanlaer@arm.com private: 14112276Sanouk.vanlaer@arm.com /** Overall commit status. */ 14212277Sjose.marinho@arm.com CommitStatus _status; 14312276Sanouk.vanlaer@arm.com /** Next commit status, to be set at the end of the cycle. */ 1442SN/A CommitStatus _nextStatus; 1455712Shsul@eecs.umich.edu /** Per-thread status. */ 1465712Shsul@eecs.umich.edu ThreadStatus commitStatus[Impl::MaxThreads]; 1475712Shsul@eecs.umich.edu /** Commit policy used in SMT mode. */ 1485712Shsul@eecs.umich.edu CommitPolicy commitPolicy; 1495712Shsul@eecs.umich.edu 1502SN/A public: 1512SN/A /** Construct a DefaultCommit with the given parameters. */ 1522SN/A DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 15310190Sakash.bagdia@arm.com 15410190Sakash.bagdia@arm.com /** Returns the name of the DefaultCommit. */ 1555712Shsul@eecs.umich.edu std::string name() const; 1566221Snate@binkert.org 1576221Snate@binkert.org /** Registers statistics. */ 1582SN/A void regStats(); 1592SN/A 1606221Snate@binkert.org /** Sets the list of threads. */ 1616221Snate@binkert.org void setThreads(std::vector<Thread *> &threads); 1626221Snate@binkert.org 1636221Snate@binkert.org /** Sets the main time buffer pointer, used for backwards communication. */ 1642SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1652SN/A 1662SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1672SN/A 1685606Snate@binkert.org /** Sets the pointer to the queue coming from rename. */ 1695606Snate@binkert.org void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1709749Sandreas@sandberg.pp.se 1719749Sandreas@sandberg.pp.se /** Sets the pointer to the queue coming from IEW. */ 1725606Snate@binkert.org void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1732SN/A 1749647Sdam.sunwoo@arm.com /** Sets the pointer to the IEW stage. */ 1759647Sdam.sunwoo@arm.com void setIEWStage(IEW *iew_stage); 1769647Sdam.sunwoo@arm.com 1779647Sdam.sunwoo@arm.com /** Skid buffer between rename and commit. */ 1789647Sdam.sunwoo@arm.com std::queue<DynInstPtr> skidBuffer; 1799647Sdam.sunwoo@arm.com 1809749Sandreas@sandberg.pp.se /** The pointer to the IEW stage. Used solely to ensure that 1819749Sandreas@sandberg.pp.se * various events (traps, interrupts, syscalls) do not occur until 1829647Sdam.sunwoo@arm.com * all stores have written back. 1839647Sdam.sunwoo@arm.com */ 1841400SN/A IEW *iewStage; 1855606Snate@binkert.org 1865606Snate@binkert.org /** Sets pointer to list of active threads. */ 1872SN/A void setActiveThreads(std::list<ThreadID> *at_ptr); 1882SN/A 1892SN/A /** Sets pointer to the commited state rename map. */ 1902SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1916221Snate@binkert.org 1926221Snate@binkert.org /** Sets pointer to the ROB. */ 1935606Snate@binkert.org void setROB(ROB *rob_ptr); 1946670Shsul@eecs.umich.edu 1955606Snate@binkert.org /** Initializes stage by sending back the number of free entries. */ 1962SN/A void initStage(); 1972SN/A 198124SN/A /** Initializes the draining of commit. */ 1996221Snate@binkert.org bool drain(); 2006221Snate@binkert.org 2016221Snate@binkert.org /** Resumes execution after draining. */ 202124SN/A void resume(); 203124SN/A 204124SN/A /** Completes the switch out of commit. */ 205124SN/A void switchOut(); 2065606Snate@binkert.org 2075606Snate@binkert.org /** Takes over from another CPU's thread. */ 2089749Sandreas@sandberg.pp.se void takeOverFrom(); 2099749Sandreas@sandberg.pp.se 2105606Snate@binkert.org /** Ticks the commit stage, which tries to commit instructions. */ 211124SN/A void tick(); 2121400SN/A 2135606Snate@binkert.org /** Handles any squashes that are sent from IEW, and adds instructions 214124SN/A * to the ROB and tries to commit instructions. 215124SN/A */ 216124SN/A void commit(); 217124SN/A 2186221Snate@binkert.org /** Returns the number of free ROB entries for a specific thread. */ 2196221Snate@binkert.org size_t numROBFreeEntries(ThreadID tid); 2205606Snate@binkert.org 2216221Snate@binkert.org /** Generates an event to schedule a squash due to a trap. */ 2225606Snate@binkert.org void generateTrapEvent(ThreadID tid); 223124SN/A 224124SN/A /** Records that commit needs to initiate a squash due to an 2251191SN/A * external state update through the TC. 2265529Snate@binkert.org */ 2278634Schris.emmons@arm.com void generateTCEvent(ThreadID tid); 22811359Sandreas@sandberg.pp.se 2298634Schris.emmons@arm.com private: 2301191SN/A /** Updates the overall status of commit with the nextStatus, and 2315529Snate@binkert.org * tell the CPU if commit is active/inactive. 2321191SN/A */ 2335529Snate@binkert.org void updateStatus(); 2341191SN/A 2351191SN/A /** Sets the next status based on threads' statuses, which becomes the 23612085Sspwilson2@wisc.edu * current status at the end of the cycle. 23712085Sspwilson2@wisc.edu */ 2385606Snate@binkert.org void setNextStatus(); 2391191SN/A 2401191SN/A /** Checks if the ROB is completed with squashing. This is for the case 2418876Sandreas.hansson@arm.com * where the ROB can take multiple cycles to complete squashing. 2428876Sandreas.hansson@arm.com */ 2438876Sandreas.hansson@arm.com bool robDoneSquashing(); 2449433SAndreas.Sandberg@ARM.com 24511221Sandreas.sandberg@arm.com /** Returns if any of the threads have the number of ROB entries changed 24611221Sandreas.sandberg@arm.com * on this cycle. Used to determine if the number of free ROB entries needs 24711221Sandreas.sandberg@arm.com * to be sent back to previous stages. 24811221Sandreas.sandberg@arm.com */ 24911221Sandreas.sandberg@arm.com bool changedROBEntries(); 25011221Sandreas.sandberg@arm.com 2518876Sandreas.hansson@arm.com /** Squashes all in flight instructions. */ 2525810Sgblack@eecs.umich.edu void squashAll(ThreadID tid); 2538779Sgblack@eecs.umich.edu 2548779Sgblack@eecs.umich.edu /** Handles squashing due to a trap. */ 25512127Sspwilson2@wisc.edu void squashFromTrap(ThreadID tid); 25612127Sspwilson2@wisc.edu 25712127Sspwilson2@wisc.edu /** Handles squashing due to an TC write. */ 2588779Sgblack@eecs.umich.edu void squashFromTC(ThreadID tid); 2595529Snate@binkert.org 2609384SAndreas.Sandberg@arm.com /** Handles squashing from instruction with SquashAfter set. 2619384SAndreas.Sandberg@arm.com * This differs from the other squashes as it squashes following 2629384SAndreas.Sandberg@arm.com * instructions instead of the current instruction and doesn't 2639384SAndreas.Sandberg@arm.com * clean up various status bits about traps/tc writes pending. 2649384SAndreas.Sandberg@arm.com */ 2651917SN/A void squashAfter(ThreadID tid, DynInstPtr &head_inst, 2661191SN/A uint64_t squash_after_seq_num); 2671191SN/A 2681191SN/A#if FULL_SYSTEM 2691191SN/A /** Handles processing an interrupt. */ 2701191SN/A void handleInterrupt(); 2711191SN/A 2721191SN/A /** Get fetch redirecting so we can handle an interrupt */ 2731191SN/A void propagateInterrupt(); 2741191SN/A#endif // FULL_SYSTEM 2759086Sandreas.hansson@arm.com 2769086Sandreas.hansson@arm.com /** Commits as many instructions as possible. */ 2779086Sandreas.hansson@arm.com void commitInsts(); 2781191SN/A 2791191SN/A /** Tries to commit the head ROB instruction passed in. 2801129SN/A * @param head_inst The instruction to be committed. 28111148Smitch.hayenga@arm.com */ 28210529Smorr@cs.wisc.edu bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 28311148Smitch.hayenga@arm.com 28411148Smitch.hayenga@arm.com /** Gets instructions from rename and inserts them into the ROB. */ 28511148Smitch.hayenga@arm.com void getInsts(); 28611148Smitch.hayenga@arm.com 28711148Smitch.hayenga@arm.com /** Insert all instructions from rename into skidBuffer */ 28811148Smitch.hayenga@arm.com void skidInsert(); 28911148Smitch.hayenga@arm.com 29010529Smorr@cs.wisc.edu /** Marks completed instructions using information sent from IEW. */ 29110529Smorr@cs.wisc.edu void markCompletedInsts(); 29210529Smorr@cs.wisc.edu 29311148Smitch.hayenga@arm.com /** Gets the thread to commit, based on the SMT policy. */ 29410529Smorr@cs.wisc.edu ThreadID getCommittingThread(); 29511148Smitch.hayenga@arm.com 29611148Smitch.hayenga@arm.com /** Returns the thread ID to use based on a round robin policy. */ 29711148Smitch.hayenga@arm.com ThreadID roundRobin(); 29811325Ssteve.reinhardt@amd.com 29910529Smorr@cs.wisc.edu /** Returns the thread ID to use based on an oldest instruction policy. */ 30010529Smorr@cs.wisc.edu ThreadID oldestReady(); 30110529Smorr@cs.wisc.edu 30210529Smorr@cs.wisc.edu public: 30311148Smitch.hayenga@arm.com /** Reads the PC of a specific thread. */ 30411148Smitch.hayenga@arm.com TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 30510529Smorr@cs.wisc.edu 30611148Smitch.hayenga@arm.com /** Sets the PC of a specific thread. */ 30711148Smitch.hayenga@arm.com void pcState(const TheISA::PCState &val, ThreadID tid) 30810529Smorr@cs.wisc.edu { pc[tid] = val; } 30910529Smorr@cs.wisc.edu 31011148Smitch.hayenga@arm.com /** Returns the PC of a specific thread. */ 31110529Smorr@cs.wisc.edu Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 31210529Smorr@cs.wisc.edu 31310529Smorr@cs.wisc.edu /** Returns the next PC of a specific thread. */ 31410529Smorr@cs.wisc.edu Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 31510529Smorr@cs.wisc.edu 31612406Sgabeblack@google.com /** Reads the micro PC of a specific thread. */ 31710529Smorr@cs.wisc.edu Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 31811148Smitch.hayenga@arm.com 31911148Smitch.hayenga@arm.com private: 32011148Smitch.hayenga@arm.com /** Time buffer interface. */ 32112784Sgiacomo.travaglini@arm.com TimeBuffer<TimeStruct> *timeBuffer; 32212784Sgiacomo.travaglini@arm.com 32311148Smitch.hayenga@arm.com /** Wire to write information heading to previous stages. */ 32410529Smorr@cs.wisc.edu typename TimeBuffer<TimeStruct>::wire toIEW; 32510529Smorr@cs.wisc.edu 32610529Smorr@cs.wisc.edu /** Wire to read information from IEW (for ROB). */ 32710529Smorr@cs.wisc.edu typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 32810529Smorr@cs.wisc.edu 32910529Smorr@cs.wisc.edu TimeBuffer<FetchStruct> *fetchQueue; 33010529Smorr@cs.wisc.edu 33110529Smorr@cs.wisc.edu typename TimeBuffer<FetchStruct>::wire fromFetch; 33210529Smorr@cs.wisc.edu 33310529Smorr@cs.wisc.edu /** IEW instruction queue interface. */ 33412749Sgiacomo.travaglini@arm.com TimeBuffer<IEWStruct> *iewQueue; 33510529Smorr@cs.wisc.edu 33610529Smorr@cs.wisc.edu /** Wire to read information from IEW queue. */ 33712749Sgiacomo.travaglini@arm.com typename TimeBuffer<IEWStruct>::wire fromIEW; 33810529Smorr@cs.wisc.edu 33910529Smorr@cs.wisc.edu /** Rename instruction queue interface, for ROB. */ 34012749Sgiacomo.travaglini@arm.com TimeBuffer<RenameStruct> *renameQueue; 34111148Smitch.hayenga@arm.com 34210529Smorr@cs.wisc.edu /** Wire to read information from rename queue. */ 34311148Smitch.hayenga@arm.com typename TimeBuffer<RenameStruct>::wire fromRename; 34411148Smitch.hayenga@arm.com 34510529Smorr@cs.wisc.edu public: 34610529Smorr@cs.wisc.edu /** ROB interface. */ 34710529Smorr@cs.wisc.edu ROB *rob; 3481129SN/A 3491129SN/A private: 3509523SAndreas.Sandberg@ARM.com /** Pointer to O3CPU. */ 3512680Sktlim@umich.edu O3CPU *cpu; 3529523SAndreas.Sandberg@ARM.com 3539523SAndreas.Sandberg@ARM.com /** Vector of all of the threads. */ 3549523SAndreas.Sandberg@ARM.com std::vector<Thread *> thread; 3551129SN/A 356180SN/A /** Records that commit has written to the time buffer this cycle. Used for 3572SN/A * the CPU to determine if it can deschedule itself if there is no activity. 3581917SN/A */ 3591917SN/A bool wroteToTimeBuffer; 3608779Sgblack@eecs.umich.edu 3619433SAndreas.Sandberg@ARM.com /** Records if the number of ROB entries has changed this cycle. If it has, 3628779Sgblack@eecs.umich.edu * then the number of free entries must be re-broadcast. 3638779Sgblack@eecs.umich.edu */ 3642356SN/A bool changedROBNumEntries[Impl::MaxThreads]; 3655529Snate@binkert.org 3669179Sandreas.hansson@arm.com /** A counter of how many threads are currently squashing. */ 3672356SN/A ThreadID squashCounter; 36811526Sdavid.guillen@arm.com 36912276Sanouk.vanlaer@arm.com /** Records if a thread has to squash this cycle due to a trap. */ 37012276Sanouk.vanlaer@arm.com bool trapSquash[Impl::MaxThreads]; 37112276Sanouk.vanlaer@arm.com 37211526Sdavid.guillen@arm.com /** Records if a thread has to squash this cycle due to an XC write. */ 37311526Sdavid.guillen@arm.com bool tcSquash[Impl::MaxThreads]; 37411526Sdavid.guillen@arm.com 37511526Sdavid.guillen@arm.com /** Priority List used for Commit Policy */ 3761917SN/A std::list<ThreadID> priority_list; 3771917SN/A 37810464SAndreas.Sandberg@ARM.com /** IEW to Commit delay, in ticks. */ 37910464SAndreas.Sandberg@ARM.com unsigned iewToCommitDelay; 38010464SAndreas.Sandberg@ARM.com 38110464SAndreas.Sandberg@ARM.com /** Commit to IEW delay, in ticks. */ 38210464SAndreas.Sandberg@ARM.com unsigned commitToIEWDelay; 38310464SAndreas.Sandberg@ARM.com 38410464SAndreas.Sandberg@ARM.com /** Rename to ROB delay, in ticks. */ 38510464SAndreas.Sandberg@ARM.com unsigned renameToROBDelay; 38610464SAndreas.Sandberg@ARM.com 38710464SAndreas.Sandberg@ARM.com unsigned fetchToCommitDelay; 38810464SAndreas.Sandberg@ARM.com 38910464SAndreas.Sandberg@ARM.com /** Rename width, in instructions. Used so ROB knows how many 39012284Sjose.marinho@arm.com * instructions to get from the rename instruction queue. 39112284Sjose.marinho@arm.com */ 39210464SAndreas.Sandberg@ARM.com unsigned renameWidth; 39310464SAndreas.Sandberg@ARM.com 39410464SAndreas.Sandberg@ARM.com /** Commit width, in instructions. */ 39510464SAndreas.Sandberg@ARM.com unsigned commitWidth; 39610464SAndreas.Sandberg@ARM.com 39712284Sjose.marinho@arm.com /** Number of Reorder Buffers */ 39812284Sjose.marinho@arm.com unsigned numRobs; 39912284Sjose.marinho@arm.com 40010464SAndreas.Sandberg@ARM.com /** Number of Active Threads */ 40110464SAndreas.Sandberg@ARM.com ThreadID numThreads; 40210464SAndreas.Sandberg@ARM.com 40310464SAndreas.Sandberg@ARM.com /** Is a drain pending. */ 40410464SAndreas.Sandberg@ARM.com bool drainPending; 40510464SAndreas.Sandberg@ARM.com 40610464SAndreas.Sandberg@ARM.com /** Is commit switched out. */ 40710464SAndreas.Sandberg@ARM.com bool switchedOut; 40810464SAndreas.Sandberg@ARM.com 40910464SAndreas.Sandberg@ARM.com /** The latency to handle a trap. Used when scheduling trap 41010464SAndreas.Sandberg@ARM.com * squash event. 41110464SAndreas.Sandberg@ARM.com */ 41210464SAndreas.Sandberg@ARM.com Tick trapLatency; 41310643Snikos.nikoleris@gmail.com 41410464SAndreas.Sandberg@ARM.com /** The interrupt fault. */ 41510464SAndreas.Sandberg@ARM.com Fault interrupt; 41610464SAndreas.Sandberg@ARM.com 41710464SAndreas.Sandberg@ARM.com /** The commit PC state of each thread. Refers to the instruction that 4181917SN/A * is currently being processed/committed. 4191917SN/A */ 4202SN/A TheISA::PCState pc[Impl::MaxThreads]; 4212SN/A 42211522Sstephan.diestelhorst@arm.com /** The sequence number of the youngest valid instruction in the ROB. */ 42311522Sstephan.diestelhorst@arm.com InstSeqNum youngestSeqNum[Impl::MaxThreads]; 424729SN/A 425707SN/A /** The sequence number of the last commited instruction. */ 426707SN/A InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 427707SN/A 428707SN/A /** Records if there is a trap currently in flight. */ 429707SN/A bool trapInFlight[Impl::MaxThreads]; 430707SN/A 4317914SBrad.Beckmann@amd.com /** Records if there were any stores committed this cycle. */ 4327914SBrad.Beckmann@amd.com bool committedStores[Impl::MaxThreads]; 4337914SBrad.Beckmann@amd.com 4347914SBrad.Beckmann@amd.com /** Records if commit should check if the ROB is truly empty (see 4357914SBrad.Beckmann@amd.com commit_impl.hh). */ 4367914SBrad.Beckmann@amd.com bool checkEmptyROB[Impl::MaxThreads]; 4377914SBrad.Beckmann@amd.com 4387914SBrad.Beckmann@amd.com /** Pointer to the list of active threads. */ 4397914SBrad.Beckmann@amd.com std::list<ThreadID> *activeThreads; 4407914SBrad.Beckmann@amd.com 4412680Sktlim@umich.edu /** Rename map interface. */ 4422SN/A RenameMap *renameMap[Impl::MaxThreads]; 4432SN/A 4442SN/A /** Updates commit stats based on this instruction. */ 4452SN/A void updateComInstStats(DynInstPtr &inst); 4462680Sktlim@umich.edu 4472SN/A /** Stat for the total number of committed instructions. */ 4482SN/A Stats::Scalar commitCommittedInsts; 4492680Sktlim@umich.edu /** Stat for the total number of squashed instructions discarded by commit. 4502SN/A */ 4512SN/A Stats::Scalar commitSquashedInsts; 4529294Sandreas.hansson@arm.com /** Stat for the total number of times commit is told to squash. 4539294Sandreas.hansson@arm.com * @todo: Actually increment this stat. 4548850Sandreas.hansson@arm.com */ 4558850Sandreas.hansson@arm.com Stats::Scalar commitSquashEvents; 4568850Sandreas.hansson@arm.com /** Stat for the total number of times commit has had to stall due to a non- 4578850Sandreas.hansson@arm.com * speculative instruction reaching the head of the ROB. 4589608Sandreas.hansson@arm.com */ 4598850Sandreas.hansson@arm.com Stats::Scalar commitNonSpecStalls; 4608922Swilliam.wang@arm.com /** Stat for the total number of branch mispredicts that caused a squash. */ 4618850Sandreas.hansson@arm.com Stats::Scalar branchMispredicts; 4628922Swilliam.wang@arm.com /** Distribution of the number of committed instructions each cycle. */ 4638850Sandreas.hansson@arm.com Stats::Distribution numCommittedDist; 4648922Swilliam.wang@arm.com 4658850Sandreas.hansson@arm.com /** Total number of instructions committed. */ 4668850Sandreas.hansson@arm.com Stats::Vector statComInst; 467180SN/A /** Total number of software prefetches committed. */ 4682680Sktlim@umich.edu Stats::Vector statComSwp; 469180SN/A /** Stat for the total number of committed memory references. */ 47011146Smitch.hayenga@arm.com Stats::Vector statComRefs; 47111146Smitch.hayenga@arm.com /** Stat for the total number of committed loads. */ 4726221Snate@binkert.org Stats::Vector statComLoads; 4736221Snate@binkert.org /** Total number of committed memory barriers. */ 4746221Snate@binkert.org Stats::Vector statComMembars; 4752378SN/A /** Total number of committed branches. */ 47611146Smitch.hayenga@arm.com Stats::Vector statComBranches; 47711146Smitch.hayenga@arm.com /** Total number of floating point instructions */ 47811146Smitch.hayenga@arm.com Stats::Vector statComFloating; 4795718Shsul@eecs.umich.edu /** Total number of integer instructions */ 48011146Smitch.hayenga@arm.com Stats::Vector statComInteger; 4818779Sgblack@eecs.umich.edu /** Total number of function calls */ 4828779Sgblack@eecs.umich.edu Stats::Vector statComFunctionCalls; 4838779Sgblack@eecs.umich.edu 484180SN/A /** Number of cycles where the commit bandwidth limit is reached. */ 485180SN/A Stats::Scalar commitEligibleSamples; 486180SN/A /** Number of instructions not committed due to bandwidth limits. */ 48712276Sanouk.vanlaer@arm.com Stats::Vector commitEligible; 48812276Sanouk.vanlaer@arm.com}; 48912276Sanouk.vanlaer@arm.com 49012276Sanouk.vanlaer@arm.com#endif // __CPU_O3_COMMIT_HH__ 49112276Sanouk.vanlaer@arm.com