commit.hh revision 7847:0c6613ad8f18
1955SN/A/* 2955SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31762SN/A * All rights reserved. 4955SN/A * 5955SN/A * Redistribution and use in source and binary forms, with or without 6955SN/A * modification, are permitted provided that the following conditions are 7955SN/A * met: redistributions of source code must retain the above copyright 8955SN/A * notice, this list of conditions and the following disclaimer; 9955SN/A * redistributions in binary form must reproduce the above copyright 10955SN/A * notice, this list of conditions and the following disclaimer in the 11955SN/A * documentation and/or other materials provided with the distribution; 12955SN/A * neither the name of the copyright holders nor the names of its 13955SN/A * contributors may be used to endorse or promote products derived from 14955SN/A * this software without specific prior written permission. 15955SN/A * 16955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 294762Snate@binkert.org * Korey Sewell 30955SN/A */ 315522Snate@binkert.org 326143Snate@binkert.org#ifndef __CPU_O3_COMMIT_HH__ 334762Snate@binkert.org#define __CPU_O3_COMMIT_HH__ 345522Snate@binkert.org 35955SN/A#include "base/statistics.hh" 365522Snate@binkert.org#include "cpu/timebuf.hh" 37955SN/A#include "cpu/exetrace.hh" 385522Snate@binkert.org#include "cpu/inst_seq.hh" 394202Sbinkertn@umich.edu 405742Snate@binkert.orgclass DerivO3CPUParams; 41955SN/A 424381Sbinkertn@umich.edutemplate <class> 434381Sbinkertn@umich.educlass O3ThreadState; 448334Snate@binkert.org 45955SN/A/** 46955SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 474202Sbinkertn@umich.edu * specified by the parameters; each cycle it tries to commit that 48955SN/A * many instructions. The SMT policy decides which thread it tries to 494382Sbinkertn@umich.edu * commit instructions from. Non- speculative instructions must reach 504382Sbinkertn@umich.edu * the head of the ROB before they are ready to execute; once they 514382Sbinkertn@umich.edu * reach the head, commit will broadcast the instruction's sequence 526654Snate@binkert.org * number to the previous stages so that they can issue/ execute the 535517Snate@binkert.org * instruction. Only one non-speculative instruction is handled per 548614Sgblack@eecs.umich.edu * cycle. Commit is responsible for handling all back-end initiated 557674Snate@binkert.org * redirects. It receives the redirect, and then broadcasts it to all 566143Snate@binkert.org * stages, indicating the sequence number they should squash until, 576143Snate@binkert.org * and any necessary branch misprediction information as well. It 586143Snate@binkert.org * priortizes redirects by instruction's age, only broadcasting a 598233Snate@binkert.org * redirect if it corresponds to an instruction that should currently 608233Snate@binkert.org * be in the ROB. This is done by tracking the sequence number of the 618233Snate@binkert.org * youngest instruction in the ROB, which gets updated to any 628233Snate@binkert.org * squashing instruction's sequence number, and only broadcasting a 638233Snate@binkert.org * redirect if it corresponds to an older instruction. Commit also 648334Snate@binkert.org * supports multiple cycle squashing, to model a ROB that can only 658334Snate@binkert.org * remove a certain number of instructions per cycle. 6610453SAndrew.Bardsley@arm.com */ 6710453SAndrew.Bardsley@arm.comtemplate<class Impl> 688233Snate@binkert.orgclass DefaultCommit 698233Snate@binkert.org{ 708233Snate@binkert.org public: 718233Snate@binkert.org // Typedefs from the Impl. 728233Snate@binkert.org typedef typename Impl::O3CPU O3CPU; 738233Snate@binkert.org typedef typename Impl::DynInstPtr DynInstPtr; 746143Snate@binkert.org typedef typename Impl::CPUPol CPUPol; 758233Snate@binkert.org 768233Snate@binkert.org typedef typename CPUPol::RenameMap RenameMap; 778233Snate@binkert.org typedef typename CPUPol::ROB ROB; 786143Snate@binkert.org 796143Snate@binkert.org typedef typename CPUPol::TimeStruct TimeStruct; 806143Snate@binkert.org typedef typename CPUPol::FetchStruct FetchStruct; 8111308Santhony.gutierrez@amd.com typedef typename CPUPol::IEWStruct IEWStruct; 828233Snate@binkert.org typedef typename CPUPol::RenameStruct RenameStruct; 838233Snate@binkert.org 848233Snate@binkert.org typedef typename CPUPol::Fetch Fetch; 856143Snate@binkert.org typedef typename CPUPol::IEW IEW; 868233Snate@binkert.org 878233Snate@binkert.org typedef O3ThreadState<Impl> Thread; 888233Snate@binkert.org 898233Snate@binkert.org /** Event class used to schedule a squash due to a trap (fault or 906143Snate@binkert.org * interrupt) to happen on a specific cycle. 916143Snate@binkert.org */ 926143Snate@binkert.org class TrapEvent : public Event { 934762Snate@binkert.org private: 946143Snate@binkert.org DefaultCommit<Impl> *commit; 958233Snate@binkert.org ThreadID tid; 968233Snate@binkert.org 978233Snate@binkert.org public: 988233Snate@binkert.org TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 998233Snate@binkert.org 1006143Snate@binkert.org void process(); 1018233Snate@binkert.org const char *description() const; 1028233Snate@binkert.org }; 1038233Snate@binkert.org 1048233Snate@binkert.org /** Overall commit status. Used to determine if the CPU can deschedule 1056143Snate@binkert.org * itself due to a lack of activity. 1066143Snate@binkert.org */ 1076143Snate@binkert.org enum CommitStatus{ 1086143Snate@binkert.org Active, 1096143Snate@binkert.org Inactive 1106143Snate@binkert.org }; 1116143Snate@binkert.org 1126143Snate@binkert.org /** Individual thread status. */ 1136143Snate@binkert.org enum ThreadStatus { 1147065Snate@binkert.org Running, 1156143Snate@binkert.org Idle, 1168233Snate@binkert.org ROBSquashing, 1178233Snate@binkert.org TrapPending, 1188233Snate@binkert.org FetchTrapPending 1198233Snate@binkert.org }; 1208233Snate@binkert.org 1218233Snate@binkert.org /** Commit policy for SMT mode. */ 1228233Snate@binkert.org enum CommitPolicy { 1238233Snate@binkert.org Aggressive, 1248233Snate@binkert.org RoundRobin, 1258233Snate@binkert.org OldestReady 1268233Snate@binkert.org }; 1278233Snate@binkert.org 1288233Snate@binkert.org private: 1298233Snate@binkert.org /** Overall commit status. */ 1308233Snate@binkert.org CommitStatus _status; 1318233Snate@binkert.org /** Next commit status, to be set at the end of the cycle. */ 1328233Snate@binkert.org CommitStatus _nextStatus; 1338233Snate@binkert.org /** Per-thread status. */ 1348233Snate@binkert.org ThreadStatus commitStatus[Impl::MaxThreads]; 1358233Snate@binkert.org /** Commit policy used in SMT mode. */ 1368233Snate@binkert.org CommitPolicy commitPolicy; 1378233Snate@binkert.org 1388233Snate@binkert.org public: 1398233Snate@binkert.org /** Construct a DefaultCommit with the given parameters. */ 1408233Snate@binkert.org DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 1418233Snate@binkert.org 1428233Snate@binkert.org /** Returns the name of the DefaultCommit. */ 1438233Snate@binkert.org std::string name() const; 1448233Snate@binkert.org 1458233Snate@binkert.org /** Registers statistics. */ 1468233Snate@binkert.org void regStats(); 1476143Snate@binkert.org 1486143Snate@binkert.org /** Sets the list of threads. */ 1496143Snate@binkert.org void setThreads(std::vector<Thread *> &threads); 1506143Snate@binkert.org 1516143Snate@binkert.org /** Sets the main time buffer pointer, used for backwards communication. */ 1526143Snate@binkert.org void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1539982Satgutier@umich.edu 15410196SCurtis.Dunham@arm.com void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 15510196SCurtis.Dunham@arm.com 15610196SCurtis.Dunham@arm.com /** Sets the pointer to the queue coming from rename. */ 15710196SCurtis.Dunham@arm.com void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 15810196SCurtis.Dunham@arm.com 15910196SCurtis.Dunham@arm.com /** Sets the pointer to the queue coming from IEW. */ 16010196SCurtis.Dunham@arm.com void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 16110196SCurtis.Dunham@arm.com 1626143Snate@binkert.org /** Sets the pointer to the IEW stage. */ 1636143Snate@binkert.org void setIEWStage(IEW *iew_stage); 1648945Ssteve.reinhardt@amd.com 1658233Snate@binkert.org /** Skid buffer between rename and commit. */ 1668233Snate@binkert.org std::queue<DynInstPtr> skidBuffer; 1676143Snate@binkert.org 1688945Ssteve.reinhardt@amd.com /** The pointer to the IEW stage. Used solely to ensure that 1696143Snate@binkert.org * various events (traps, interrupts, syscalls) do not occur until 1706143Snate@binkert.org * all stores have written back. 1716143Snate@binkert.org */ 1726143Snate@binkert.org IEW *iewStage; 1735522Snate@binkert.org 1746143Snate@binkert.org /** Sets pointer to list of active threads. */ 1756143Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1766143Snate@binkert.org 1779982Satgutier@umich.edu /** Sets pointer to the commited state rename map. */ 1788233Snate@binkert.org void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1798233Snate@binkert.org 1808233Snate@binkert.org /** Sets pointer to the ROB. */ 1816143Snate@binkert.org void setROB(ROB *rob_ptr); 1826143Snate@binkert.org 1836143Snate@binkert.org /** Initializes stage by sending back the number of free entries. */ 1846143Snate@binkert.org void initStage(); 1855522Snate@binkert.org 1865522Snate@binkert.org /** Initializes the draining of commit. */ 1875522Snate@binkert.org bool drain(); 1885522Snate@binkert.org 1895604Snate@binkert.org /** Resumes execution after draining. */ 1905604Snate@binkert.org void resume(); 1916143Snate@binkert.org 1926143Snate@binkert.org /** Completes the switch out of commit. */ 1934762Snate@binkert.org void switchOut(); 1944762Snate@binkert.org 1956143Snate@binkert.org /** Takes over from another CPU's thread. */ 1966727Ssteve.reinhardt@amd.com void takeOverFrom(); 1976727Ssteve.reinhardt@amd.com 1986727Ssteve.reinhardt@amd.com /** Ticks the commit stage, which tries to commit instructions. */ 1994762Snate@binkert.org void tick(); 2006143Snate@binkert.org 2016143Snate@binkert.org /** Handles any squashes that are sent from IEW, and adds instructions 2026143Snate@binkert.org * to the ROB and tries to commit instructions. 2036143Snate@binkert.org */ 2046727Ssteve.reinhardt@amd.com void commit(); 2056143Snate@binkert.org 2067674Snate@binkert.org /** Returns the number of free ROB entries for a specific thread. */ 2077674Snate@binkert.org size_t numROBFreeEntries(ThreadID tid); 2085604Snate@binkert.org 2096143Snate@binkert.org /** Generates an event to schedule a squash due to a trap. */ 2106143Snate@binkert.org void generateTrapEvent(ThreadID tid); 2116143Snate@binkert.org 2124762Snate@binkert.org /** Records that commit needs to initiate a squash due to an 2136143Snate@binkert.org * external state update through the TC. 2144762Snate@binkert.org */ 2154762Snate@binkert.org void generateTCEvent(ThreadID tid); 2164762Snate@binkert.org 2176143Snate@binkert.org private: 2186143Snate@binkert.org /** Updates the overall status of commit with the nextStatus, and 2194762Snate@binkert.org * tell the CPU if commit is active/inactive. 2208233Snate@binkert.org */ 2218233Snate@binkert.org void updateStatus(); 2228233Snate@binkert.org 2238233Snate@binkert.org /** Sets the next status based on threads' statuses, which becomes the 2246143Snate@binkert.org * current status at the end of the cycle. 2256143Snate@binkert.org */ 2264762Snate@binkert.org void setNextStatus(); 2276143Snate@binkert.org 2284762Snate@binkert.org /** Checks if the ROB is completed with squashing. This is for the case 2296143Snate@binkert.org * where the ROB can take multiple cycles to complete squashing. 2304762Snate@binkert.org */ 2316143Snate@binkert.org bool robDoneSquashing(); 2328233Snate@binkert.org 2338233Snate@binkert.org /** Returns if any of the threads have the number of ROB entries changed 23410453SAndrew.Bardsley@arm.com * on this cycle. Used to determine if the number of free ROB entries needs 2356143Snate@binkert.org * to be sent back to previous stages. 2366143Snate@binkert.org */ 2376143Snate@binkert.org bool changedROBEntries(); 2386143Snate@binkert.org 2396143Snate@binkert.org /** Squashes all in flight instructions. */ 2406143Snate@binkert.org void squashAll(ThreadID tid); 2416143Snate@binkert.org 2426143Snate@binkert.org /** Handles squashing due to a trap. */ 24310453SAndrew.Bardsley@arm.com void squashFromTrap(ThreadID tid); 24410453SAndrew.Bardsley@arm.com 245955SN/A /** Handles squashing due to an TC write. */ 2469396Sandreas.hansson@arm.com void squashFromTC(ThreadID tid); 2479396Sandreas.hansson@arm.com 2489396Sandreas.hansson@arm.com /** Handles squashing from instruction with SquashAfter set. 2499396Sandreas.hansson@arm.com * This differs from the other squashes as it squashes following 2509396Sandreas.hansson@arm.com * instructions instead of the current instruction and doesn't 2519396Sandreas.hansson@arm.com * clean up various status bits about traps/tc writes pending. 2529396Sandreas.hansson@arm.com */ 2539396Sandreas.hansson@arm.com void squashAfter(ThreadID tid, uint64_t squash_after_seq_num); 2549396Sandreas.hansson@arm.com 2559396Sandreas.hansson@arm.com#if FULL_SYSTEM 2569396Sandreas.hansson@arm.com /** Handles processing an interrupt. */ 2579396Sandreas.hansson@arm.com void handleInterrupt(); 2589396Sandreas.hansson@arm.com 2599930Sandreas.hansson@arm.com /** Get fetch redirecting so we can handle an interrupt */ 2609930Sandreas.hansson@arm.com void propagateInterrupt(); 2619396Sandreas.hansson@arm.com#endif // FULL_SYSTEM 2628235Snate@binkert.org 2638235Snate@binkert.org /** Commits as many instructions as possible. */ 2646143Snate@binkert.org void commitInsts(); 2658235Snate@binkert.org 2669003SAli.Saidi@ARM.com /** Tries to commit the head ROB instruction passed in. 2678235Snate@binkert.org * @param head_inst The instruction to be committed. 2688235Snate@binkert.org */ 2698235Snate@binkert.org bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 2708235Snate@binkert.org 2718235Snate@binkert.org /** Gets instructions from rename and inserts them into the ROB. */ 2728235Snate@binkert.org void getInsts(); 2738235Snate@binkert.org 2748235Snate@binkert.org /** Insert all instructions from rename into skidBuffer */ 2758235Snate@binkert.org void skidInsert(); 2768235Snate@binkert.org 2778235Snate@binkert.org /** Marks completed instructions using information sent from IEW. */ 2788235Snate@binkert.org void markCompletedInsts(); 2798235Snate@binkert.org 2808235Snate@binkert.org /** Gets the thread to commit, based on the SMT policy. */ 2819003SAli.Saidi@ARM.com ThreadID getCommittingThread(); 2828235Snate@binkert.org 2835584Snate@binkert.org /** Returns the thread ID to use based on a round robin policy. */ 2844382Sbinkertn@umich.edu ThreadID roundRobin(); 2854202Sbinkertn@umich.edu 2864382Sbinkertn@umich.edu /** Returns the thread ID to use based on an oldest instruction policy. */ 2874382Sbinkertn@umich.edu ThreadID oldestReady(); 2884382Sbinkertn@umich.edu 2899396Sandreas.hansson@arm.com public: 2905584Snate@binkert.org /** Reads the PC of a specific thread. */ 2914382Sbinkertn@umich.edu TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 2924382Sbinkertn@umich.edu 2934382Sbinkertn@umich.edu /** Sets the PC of a specific thread. */ 2948232Snate@binkert.org void pcState(const TheISA::PCState &val, ThreadID tid) 2955192Ssaidi@eecs.umich.edu { pc[tid] = val; } 2968232Snate@binkert.org 2978232Snate@binkert.org /** Returns the PC of a specific thread. */ 2988232Snate@binkert.org Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 2995192Ssaidi@eecs.umich.edu 3008232Snate@binkert.org /** Returns the next PC of a specific thread. */ 3015192Ssaidi@eecs.umich.edu Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 3025799Snate@binkert.org 3038232Snate@binkert.org /** Reads the micro PC of a specific thread. */ 3045192Ssaidi@eecs.umich.edu Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 3055192Ssaidi@eecs.umich.edu 3065192Ssaidi@eecs.umich.edu private: 3078232Snate@binkert.org /** Time buffer interface. */ 3085192Ssaidi@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 3098232Snate@binkert.org 3105192Ssaidi@eecs.umich.edu /** Wire to write information heading to previous stages. */ 3115192Ssaidi@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire toIEW; 3125192Ssaidi@eecs.umich.edu 3135192Ssaidi@eecs.umich.edu /** Wire to read information from IEW (for ROB). */ 3144382Sbinkertn@umich.edu typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 3154382Sbinkertn@umich.edu 3164382Sbinkertn@umich.edu TimeBuffer<FetchStruct> *fetchQueue; 3172667Sstever@eecs.umich.edu 3182667Sstever@eecs.umich.edu typename TimeBuffer<FetchStruct>::wire fromFetch; 3192667Sstever@eecs.umich.edu 3202667Sstever@eecs.umich.edu /** IEW instruction queue interface. */ 3212667Sstever@eecs.umich.edu TimeBuffer<IEWStruct> *iewQueue; 3222667Sstever@eecs.umich.edu 3235742Snate@binkert.org /** Wire to read information from IEW queue. */ 3245742Snate@binkert.org typename TimeBuffer<IEWStruct>::wire fromIEW; 3255742Snate@binkert.org 3265793Snate@binkert.org /** Rename instruction queue interface, for ROB. */ 3278334Snate@binkert.org TimeBuffer<RenameStruct> *renameQueue; 3285793Snate@binkert.org 3295793Snate@binkert.org /** Wire to read information from rename queue. */ 3305793Snate@binkert.org typename TimeBuffer<RenameStruct>::wire fromRename; 3314382Sbinkertn@umich.edu 3324762Snate@binkert.org public: 3335344Sstever@gmail.com /** ROB interface. */ 3344382Sbinkertn@umich.edu ROB *rob; 3355341Sstever@gmail.com 3365742Snate@binkert.org private: 3375742Snate@binkert.org /** Pointer to O3CPU. */ 3385742Snate@binkert.org O3CPU *cpu; 3395742Snate@binkert.org 3405742Snate@binkert.org /** Vector of all of the threads. */ 3414762Snate@binkert.org std::vector<Thread *> thread; 3425742Snate@binkert.org 3435742Snate@binkert.org /** Records that commit has written to the time buffer this cycle. Used for 3447722Sgblack@eecs.umich.edu * the CPU to determine if it can deschedule itself if there is no activity. 3455742Snate@binkert.org */ 3465742Snate@binkert.org bool wroteToTimeBuffer; 3475742Snate@binkert.org 3489930Sandreas.hansson@arm.com /** Records if the number of ROB entries has changed this cycle. If it has, 3499930Sandreas.hansson@arm.com * then the number of free entries must be re-broadcast. 3509930Sandreas.hansson@arm.com */ 3519930Sandreas.hansson@arm.com bool changedROBNumEntries[Impl::MaxThreads]; 3529930Sandreas.hansson@arm.com 3535742Snate@binkert.org /** A counter of how many threads are currently squashing. */ 3548242Sbradley.danofsky@amd.com ThreadID squashCounter; 3558242Sbradley.danofsky@amd.com 3568242Sbradley.danofsky@amd.com /** Records if a thread has to squash this cycle due to a trap. */ 3578242Sbradley.danofsky@amd.com bool trapSquash[Impl::MaxThreads]; 3585341Sstever@gmail.com 3595742Snate@binkert.org /** Records if a thread has to squash this cycle due to an XC write. */ 3607722Sgblack@eecs.umich.edu bool tcSquash[Impl::MaxThreads]; 3614773Snate@binkert.org 3626108Snate@binkert.org /** Priority List used for Commit Policy */ 3631858SN/A std::list<ThreadID> priority_list; 3641085SN/A 3656658Snate@binkert.org /** IEW to Commit delay, in ticks. */ 3666658Snate@binkert.org unsigned iewToCommitDelay; 3677673Snate@binkert.org 3686658Snate@binkert.org /** Commit to IEW delay, in ticks. */ 3696658Snate@binkert.org unsigned commitToIEWDelay; 37011308Santhony.gutierrez@amd.com 3716658Snate@binkert.org /** Rename to ROB delay, in ticks. */ 37211308Santhony.gutierrez@amd.com unsigned renameToROBDelay; 3736658Snate@binkert.org 3746658Snate@binkert.org unsigned fetchToCommitDelay; 3757673Snate@binkert.org 3767673Snate@binkert.org /** Rename width, in instructions. Used so ROB knows how many 3777673Snate@binkert.org * instructions to get from the rename instruction queue. 3787673Snate@binkert.org */ 3797673Snate@binkert.org unsigned renameWidth; 3807673Snate@binkert.org 3817673Snate@binkert.org /** Commit width, in instructions. */ 38210467Sandreas.hansson@arm.com unsigned commitWidth; 3836658Snate@binkert.org 3847673Snate@binkert.org /** Number of Reorder Buffers */ 38510467Sandreas.hansson@arm.com unsigned numRobs; 38610467Sandreas.hansson@arm.com 38710467Sandreas.hansson@arm.com /** Number of Active Threads */ 38810467Sandreas.hansson@arm.com ThreadID numThreads; 38910467Sandreas.hansson@arm.com 39010467Sandreas.hansson@arm.com /** Is a drain pending. */ 39110467Sandreas.hansson@arm.com bool drainPending; 39210467Sandreas.hansson@arm.com 39310467Sandreas.hansson@arm.com /** Is commit switched out. */ 39410467Sandreas.hansson@arm.com bool switchedOut; 39510467Sandreas.hansson@arm.com 3967673Snate@binkert.org /** The latency to handle a trap. Used when scheduling trap 3977673Snate@binkert.org * squash event. 3987673Snate@binkert.org */ 3997673Snate@binkert.org Tick trapLatency; 4007673Snate@binkert.org 4019048SAli.Saidi@ARM.com /** The interrupt fault. */ 4027673Snate@binkert.org Fault interrupt; 4037673Snate@binkert.org 4047673Snate@binkert.org /** The commit PC state of each thread. Refers to the instruction that 4057673Snate@binkert.org * is currently being processed/committed. 4066658Snate@binkert.org */ 4077756SAli.Saidi@ARM.com TheISA::PCState pc[Impl::MaxThreads]; 4087816Ssteve.reinhardt@amd.com 4096658Snate@binkert.org /** The sequence number of the youngest valid instruction in the ROB. */ 41011308Santhony.gutierrez@amd.com InstSeqNum youngestSeqNum[Impl::MaxThreads]; 41111308Santhony.gutierrez@amd.com 41211308Santhony.gutierrez@amd.com /** Records if there is a trap currently in flight. */ 41311308Santhony.gutierrez@amd.com bool trapInFlight[Impl::MaxThreads]; 41411308Santhony.gutierrez@amd.com 41511308Santhony.gutierrez@amd.com /** Records if there were any stores committed this cycle. */ 41611308Santhony.gutierrez@amd.com bool committedStores[Impl::MaxThreads]; 41711308Santhony.gutierrez@amd.com 41811308Santhony.gutierrez@amd.com /** Records if commit should check if the ROB is truly empty (see 41911308Santhony.gutierrez@amd.com commit_impl.hh). */ 42011308Santhony.gutierrez@amd.com bool checkEmptyROB[Impl::MaxThreads]; 42111308Santhony.gutierrez@amd.com 42211308Santhony.gutierrez@amd.com /** Pointer to the list of active threads. */ 42311308Santhony.gutierrez@amd.com std::list<ThreadID> *activeThreads; 42411308Santhony.gutierrez@amd.com 42511308Santhony.gutierrez@amd.com /** Rename map interface. */ 42611308Santhony.gutierrez@amd.com RenameMap *renameMap[Impl::MaxThreads]; 42711308Santhony.gutierrez@amd.com 42811308Santhony.gutierrez@amd.com /** Updates commit stats based on this instruction. */ 42911308Santhony.gutierrez@amd.com void updateComInstStats(DynInstPtr &inst); 43011308Santhony.gutierrez@amd.com 43111308Santhony.gutierrez@amd.com /** Stat for the total number of committed instructions. */ 43211308Santhony.gutierrez@amd.com Stats::Scalar commitCommittedInsts; 43311308Santhony.gutierrez@amd.com /** Stat for the total number of squashed instructions discarded by commit. 43411308Santhony.gutierrez@amd.com */ 43511308Santhony.gutierrez@amd.com Stats::Scalar commitSquashedInsts; 43611308Santhony.gutierrez@amd.com /** Stat for the total number of times commit is told to squash. 43711308Santhony.gutierrez@amd.com * @todo: Actually increment this stat. 43811308Santhony.gutierrez@amd.com */ 43911308Santhony.gutierrez@amd.com Stats::Scalar commitSquashEvents; 44011308Santhony.gutierrez@amd.com /** Stat for the total number of times commit has had to stall due to a non- 44111308Santhony.gutierrez@amd.com * speculative instruction reaching the head of the ROB. 44211308Santhony.gutierrez@amd.com */ 44311308Santhony.gutierrez@amd.com Stats::Scalar commitNonSpecStalls; 44411308Santhony.gutierrez@amd.com /** Stat for the total number of branch mispredicts that caused a squash. */ 44511308Santhony.gutierrez@amd.com Stats::Scalar branchMispredicts; 44611308Santhony.gutierrez@amd.com /** Distribution of the number of committed instructions each cycle. */ 44711308Santhony.gutierrez@amd.com Stats::Distribution numCommittedDist; 44811308Santhony.gutierrez@amd.com 44911308Santhony.gutierrez@amd.com /** Total number of instructions committed. */ 45011308Santhony.gutierrez@amd.com Stats::Vector statComInst; 45111308Santhony.gutierrez@amd.com /** Total number of software prefetches committed. */ 45211308Santhony.gutierrez@amd.com Stats::Vector statComSwp; 45311308Santhony.gutierrez@amd.com /** Stat for the total number of committed memory references. */ 45411308Santhony.gutierrez@amd.com Stats::Vector statComRefs; 4554382Sbinkertn@umich.edu /** Stat for the total number of committed loads. */ 4564382Sbinkertn@umich.edu Stats::Vector statComLoads; 4574762Snate@binkert.org /** Total number of committed memory barriers. */ 4584762Snate@binkert.org Stats::Vector statComMembars; 4594762Snate@binkert.org /** Total number of committed branches. */ 4606654Snate@binkert.org Stats::Vector statComBranches; 4616654Snate@binkert.org 4625517Snate@binkert.org /** Number of cycles where the commit bandwidth limit is reached. */ 4635517Snate@binkert.org Stats::Scalar commitEligibleSamples; 4645517Snate@binkert.org /** Number of instructions not committed due to bandwidth limits. */ 4655517Snate@binkert.org Stats::Vector commitEligible; 4665517Snate@binkert.org}; 4675517Snate@binkert.org 4685517Snate@binkert.org#endif // __CPU_O3_COMMIT_HH__ 4695517Snate@binkert.org