commit.hh revision 6221:58a3c04e6344
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_COMMIT_HH__ 33#define __CPU_O3_COMMIT_HH__ 34 35#include "base/statistics.hh" 36#include "base/timebuf.hh" 37#include "cpu/exetrace.hh" 38#include "cpu/inst_seq.hh" 39 40class DerivO3CPUParams; 41 42template <class> 43class O3ThreadState; 44 45/** 46 * DefaultCommit handles single threaded and SMT commit. Its width is 47 * specified by the parameters; each cycle it tries to commit that 48 * many instructions. The SMT policy decides which thread it tries to 49 * commit instructions from. Non- speculative instructions must reach 50 * the head of the ROB before they are ready to execute; once they 51 * reach the head, commit will broadcast the instruction's sequence 52 * number to the previous stages so that they can issue/ execute the 53 * instruction. Only one non-speculative instruction is handled per 54 * cycle. Commit is responsible for handling all back-end initiated 55 * redirects. It receives the redirect, and then broadcasts it to all 56 * stages, indicating the sequence number they should squash until, 57 * and any necessary branch misprediction information as well. It 58 * priortizes redirects by instruction's age, only broadcasting a 59 * redirect if it corresponds to an instruction that should currently 60 * be in the ROB. This is done by tracking the sequence number of the 61 * youngest instruction in the ROB, which gets updated to any 62 * squashing instruction's sequence number, and only broadcasting a 63 * redirect if it corresponds to an older instruction. Commit also 64 * supports multiple cycle squashing, to model a ROB that can only 65 * remove a certain number of instructions per cycle. 66 */ 67template<class Impl> 68class DefaultCommit 69{ 70 public: 71 // Typedefs from the Impl. 72 typedef typename Impl::O3CPU O3CPU; 73 typedef typename Impl::DynInstPtr DynInstPtr; 74 typedef typename Impl::CPUPol CPUPol; 75 76 typedef typename CPUPol::RenameMap RenameMap; 77 typedef typename CPUPol::ROB ROB; 78 79 typedef typename CPUPol::TimeStruct TimeStruct; 80 typedef typename CPUPol::FetchStruct FetchStruct; 81 typedef typename CPUPol::IEWStruct IEWStruct; 82 typedef typename CPUPol::RenameStruct RenameStruct; 83 84 typedef typename CPUPol::Fetch Fetch; 85 typedef typename CPUPol::IEW IEW; 86 87 typedef O3ThreadState<Impl> Thread; 88 89 /** Event class used to schedule a squash due to a trap (fault or 90 * interrupt) to happen on a specific cycle. 91 */ 92 class TrapEvent : public Event { 93 private: 94 DefaultCommit<Impl> *commit; 95 ThreadID tid; 96 97 public: 98 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 99 100 void process(); 101 const char *description() const; 102 }; 103 104 /** Overall commit status. Used to determine if the CPU can deschedule 105 * itself due to a lack of activity. 106 */ 107 enum CommitStatus{ 108 Active, 109 Inactive 110 }; 111 112 /** Individual thread status. */ 113 enum ThreadStatus { 114 Running, 115 Idle, 116 ROBSquashing, 117 TrapPending, 118 FetchTrapPending 119 }; 120 121 /** Commit policy for SMT mode. */ 122 enum CommitPolicy { 123 Aggressive, 124 RoundRobin, 125 OldestReady 126 }; 127 128 private: 129 /** Overall commit status. */ 130 CommitStatus _status; 131 /** Next commit status, to be set at the end of the cycle. */ 132 CommitStatus _nextStatus; 133 /** Per-thread status. */ 134 ThreadStatus commitStatus[Impl::MaxThreads]; 135 /** Commit policy used in SMT mode. */ 136 CommitPolicy commitPolicy; 137 138 public: 139 /** Construct a DefaultCommit with the given parameters. */ 140 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 141 142 /** Returns the name of the DefaultCommit. */ 143 std::string name() const; 144 145 /** Registers statistics. */ 146 void regStats(); 147 148 /** Sets the list of threads. */ 149 void setThreads(std::vector<Thread *> &threads); 150 151 /** Sets the main time buffer pointer, used for backwards communication. */ 152 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 153 154 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 155 156 /** Sets the pointer to the queue coming from rename. */ 157 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 158 159 /** Sets the pointer to the queue coming from IEW. */ 160 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 161 162 /** Sets the pointer to the IEW stage. */ 163 void setIEWStage(IEW *iew_stage); 164 165 /** Skid buffer between rename and commit. */ 166 std::queue<DynInstPtr> skidBuffer; 167 168 /** The pointer to the IEW stage. Used solely to ensure that 169 * various events (traps, interrupts, syscalls) do not occur until 170 * all stores have written back. 171 */ 172 IEW *iewStage; 173 174 /** Sets pointer to list of active threads. */ 175 void setActiveThreads(std::list<ThreadID> *at_ptr); 176 177 /** Sets pointer to the commited state rename map. */ 178 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 179 180 /** Sets pointer to the ROB. */ 181 void setROB(ROB *rob_ptr); 182 183 /** Initializes stage by sending back the number of free entries. */ 184 void initStage(); 185 186 /** Initializes the draining of commit. */ 187 bool drain(); 188 189 /** Resumes execution after draining. */ 190 void resume(); 191 192 /** Completes the switch out of commit. */ 193 void switchOut(); 194 195 /** Takes over from another CPU's thread. */ 196 void takeOverFrom(); 197 198 /** Ticks the commit stage, which tries to commit instructions. */ 199 void tick(); 200 201 /** Handles any squashes that are sent from IEW, and adds instructions 202 * to the ROB and tries to commit instructions. 203 */ 204 void commit(); 205 206 /** Returns the number of free ROB entries for a specific thread. */ 207 size_t numROBFreeEntries(ThreadID tid); 208 209 /** Generates an event to schedule a squash due to a trap. */ 210 void generateTrapEvent(ThreadID tid); 211 212 /** Records that commit needs to initiate a squash due to an 213 * external state update through the TC. 214 */ 215 void generateTCEvent(ThreadID tid); 216 217 private: 218 /** Updates the overall status of commit with the nextStatus, and 219 * tell the CPU if commit is active/inactive. 220 */ 221 void updateStatus(); 222 223 /** Sets the next status based on threads' statuses, which becomes the 224 * current status at the end of the cycle. 225 */ 226 void setNextStatus(); 227 228 /** Checks if the ROB is completed with squashing. This is for the case 229 * where the ROB can take multiple cycles to complete squashing. 230 */ 231 bool robDoneSquashing(); 232 233 /** Returns if any of the threads have the number of ROB entries changed 234 * on this cycle. Used to determine if the number of free ROB entries needs 235 * to be sent back to previous stages. 236 */ 237 bool changedROBEntries(); 238 239 /** Squashes all in flight instructions. */ 240 void squashAll(ThreadID tid); 241 242 /** Handles squashing due to a trap. */ 243 void squashFromTrap(ThreadID tid); 244 245 /** Handles squashing due to an TC write. */ 246 void squashFromTC(ThreadID tid); 247 248#if FULL_SYSTEM 249 /** Handles processing an interrupt. */ 250 void handleInterrupt(); 251#endif // FULL_SYSTEM 252 253 /** Commits as many instructions as possible. */ 254 void commitInsts(); 255 256 /** Tries to commit the head ROB instruction passed in. 257 * @param head_inst The instruction to be committed. 258 */ 259 bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 260 261 /** Gets instructions from rename and inserts them into the ROB. */ 262 void getInsts(); 263 264 /** Insert all instructions from rename into skidBuffer */ 265 void skidInsert(); 266 267 /** Marks completed instructions using information sent from IEW. */ 268 void markCompletedInsts(); 269 270 /** Gets the thread to commit, based on the SMT policy. */ 271 ThreadID getCommittingThread(); 272 273 /** Returns the thread ID to use based on a round robin policy. */ 274 ThreadID roundRobin(); 275 276 /** Returns the thread ID to use based on an oldest instruction policy. */ 277 ThreadID oldestReady(); 278 279 public: 280 /** Returns the PC of the head instruction of the ROB. 281 * @todo: Probably remove this function as it returns only thread 0. 282 */ 283 Addr readPC() { return PC[0]; } 284 285 /** Returns the PC of a specific thread. */ 286 Addr readPC(ThreadID tid) { return PC[tid]; } 287 288 /** Sets the PC of a specific thread. */ 289 void setPC(Addr val, ThreadID tid) { PC[tid] = val; } 290 291 /** Reads the micro PC of a specific thread. */ 292 Addr readMicroPC(ThreadID tid) { return microPC[tid]; } 293 294 /** Sets the micro PC of a specific thread */ 295 void setMicroPC(Addr val, ThreadID tid) { microPC[tid] = val; } 296 297 /** Reads the next PC of a specific thread. */ 298 Addr readNextPC(ThreadID tid) { return nextPC[tid]; } 299 300 /** Sets the next PC of a specific thread. */ 301 void setNextPC(Addr val, ThreadID tid) { nextPC[tid] = val; } 302 303 /** Reads the next NPC of a specific thread. */ 304 Addr readNextNPC(ThreadID tid) { return nextNPC[tid]; } 305 306 /** Sets the next NPC of a specific thread. */ 307 void setNextNPC(Addr val, ThreadID tid) { nextNPC[tid] = val; } 308 309 /** Reads the micro PC of a specific thread. */ 310 Addr readNextMicroPC(ThreadID tid) { return nextMicroPC[tid]; } 311 312 /** Sets the micro PC of a specific thread */ 313 void setNextMicroPC(Addr val, ThreadID tid) { nextMicroPC[tid] = val; } 314 315 private: 316 /** Time buffer interface. */ 317 TimeBuffer<TimeStruct> *timeBuffer; 318 319 /** Wire to write information heading to previous stages. */ 320 typename TimeBuffer<TimeStruct>::wire toIEW; 321 322 /** Wire to read information from IEW (for ROB). */ 323 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 324 325 TimeBuffer<FetchStruct> *fetchQueue; 326 327 typename TimeBuffer<FetchStruct>::wire fromFetch; 328 329 /** IEW instruction queue interface. */ 330 TimeBuffer<IEWStruct> *iewQueue; 331 332 /** Wire to read information from IEW queue. */ 333 typename TimeBuffer<IEWStruct>::wire fromIEW; 334 335 /** Rename instruction queue interface, for ROB. */ 336 TimeBuffer<RenameStruct> *renameQueue; 337 338 /** Wire to read information from rename queue. */ 339 typename TimeBuffer<RenameStruct>::wire fromRename; 340 341 public: 342 /** ROB interface. */ 343 ROB *rob; 344 345 private: 346 /** Pointer to O3CPU. */ 347 O3CPU *cpu; 348 349 /** Vector of all of the threads. */ 350 std::vector<Thread *> thread; 351 352 /** Records that commit has written to the time buffer this cycle. Used for 353 * the CPU to determine if it can deschedule itself if there is no activity. 354 */ 355 bool wroteToTimeBuffer; 356 357 /** Records if the number of ROB entries has changed this cycle. If it has, 358 * then the number of free entries must be re-broadcast. 359 */ 360 bool changedROBNumEntries[Impl::MaxThreads]; 361 362 /** A counter of how many threads are currently squashing. */ 363 ThreadID squashCounter; 364 365 /** Records if a thread has to squash this cycle due to a trap. */ 366 bool trapSquash[Impl::MaxThreads]; 367 368 /** Records if a thread has to squash this cycle due to an XC write. */ 369 bool tcSquash[Impl::MaxThreads]; 370 371 /** Priority List used for Commit Policy */ 372 std::list<ThreadID> priority_list; 373 374 /** IEW to Commit delay, in ticks. */ 375 unsigned iewToCommitDelay; 376 377 /** Commit to IEW delay, in ticks. */ 378 unsigned commitToIEWDelay; 379 380 /** Rename to ROB delay, in ticks. */ 381 unsigned renameToROBDelay; 382 383 unsigned fetchToCommitDelay; 384 385 /** Rename width, in instructions. Used so ROB knows how many 386 * instructions to get from the rename instruction queue. 387 */ 388 unsigned renameWidth; 389 390 /** Commit width, in instructions. */ 391 unsigned commitWidth; 392 393 /** Number of Reorder Buffers */ 394 unsigned numRobs; 395 396 /** Number of Active Threads */ 397 ThreadID numThreads; 398 399 /** Is a drain pending. */ 400 bool drainPending; 401 402 /** Is commit switched out. */ 403 bool switchedOut; 404 405 /** The latency to handle a trap. Used when scheduling trap 406 * squash event. 407 */ 408 Tick trapLatency; 409 410 /** The interrupt fault. */ 411 Fault interrupt; 412 413 /** The commit PC of each thread. Refers to the instruction that 414 * is currently being processed/committed. 415 */ 416 Addr PC[Impl::MaxThreads]; 417 418 /** The commit micro PC of each thread. Refers to the instruction that 419 * is currently being processed/committed. 420 */ 421 Addr microPC[Impl::MaxThreads]; 422 423 /** The next PC of each thread. */ 424 Addr nextPC[Impl::MaxThreads]; 425 426 /** The next NPC of each thread. */ 427 Addr nextNPC[Impl::MaxThreads]; 428 429 /** The next micro PC of each thread. */ 430 Addr nextMicroPC[Impl::MaxThreads]; 431 432 /** The sequence number of the youngest valid instruction in the ROB. */ 433 InstSeqNum youngestSeqNum[Impl::MaxThreads]; 434 435 /** Records if there is a trap currently in flight. */ 436 bool trapInFlight[Impl::MaxThreads]; 437 438 /** Records if there were any stores committed this cycle. */ 439 bool committedStores[Impl::MaxThreads]; 440 441 /** Records if commit should check if the ROB is truly empty (see 442 commit_impl.hh). */ 443 bool checkEmptyROB[Impl::MaxThreads]; 444 445 /** Pointer to the list of active threads. */ 446 std::list<ThreadID> *activeThreads; 447 448 /** Rename map interface. */ 449 RenameMap *renameMap[Impl::MaxThreads]; 450 451 /** Updates commit stats based on this instruction. */ 452 void updateComInstStats(DynInstPtr &inst); 453 454 /** Stat for the total number of committed instructions. */ 455 Stats::Scalar commitCommittedInsts; 456 /** Stat for the total number of squashed instructions discarded by commit. 457 */ 458 Stats::Scalar commitSquashedInsts; 459 /** Stat for the total number of times commit is told to squash. 460 * @todo: Actually increment this stat. 461 */ 462 Stats::Scalar commitSquashEvents; 463 /** Stat for the total number of times commit has had to stall due to a non- 464 * speculative instruction reaching the head of the ROB. 465 */ 466 Stats::Scalar commitNonSpecStalls; 467 /** Stat for the total number of branch mispredicts that caused a squash. */ 468 Stats::Scalar branchMispredicts; 469 /** Distribution of the number of committed instructions each cycle. */ 470 Stats::Distribution numCommittedDist; 471 472 /** Total number of instructions committed. */ 473 Stats::Vector statComInst; 474 /** Total number of software prefetches committed. */ 475 Stats::Vector statComSwp; 476 /** Stat for the total number of committed memory references. */ 477 Stats::Vector statComRefs; 478 /** Stat for the total number of committed loads. */ 479 Stats::Vector statComLoads; 480 /** Total number of committed memory barriers. */ 481 Stats::Vector statComMembars; 482 /** Total number of committed branches. */ 483 Stats::Vector statComBranches; 484 485 /** Number of cycles where the commit bandwidth limit is reached. */ 486 Stats::Scalar commitEligibleSamples; 487 /** Number of instructions not committed due to bandwidth limits. */ 488 Stats::Vector commitEligible; 489}; 490 491#endif // __CPU_O3_COMMIT_HH__ 492