commit.hh revision 4329
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_COMMIT_HH__ 33#define __CPU_O3_COMMIT_HH__ 34 35#include "base/statistics.hh" 36#include "base/timebuf.hh" 37#include "cpu/exetrace.hh" 38#include "cpu/inst_seq.hh" 39 40template <class> 41class O3ThreadState; 42 43/** 44 * DefaultCommit handles single threaded and SMT commit. Its width is 45 * specified by the parameters; each cycle it tries to commit that 46 * many instructions. The SMT policy decides which thread it tries to 47 * commit instructions from. Non- speculative instructions must reach 48 * the head of the ROB before they are ready to execute; once they 49 * reach the head, commit will broadcast the instruction's sequence 50 * number to the previous stages so that they can issue/ execute the 51 * instruction. Only one non-speculative instruction is handled per 52 * cycle. Commit is responsible for handling all back-end initiated 53 * redirects. It receives the redirect, and then broadcasts it to all 54 * stages, indicating the sequence number they should squash until, 55 * and any necessary branch misprediction information as well. It 56 * priortizes redirects by instruction's age, only broadcasting a 57 * redirect if it corresponds to an instruction that should currently 58 * be in the ROB. This is done by tracking the sequence number of the 59 * youngest instruction in the ROB, which gets updated to any 60 * squashing instruction's sequence number, and only broadcasting a 61 * redirect if it corresponds to an older instruction. Commit also 62 * supports multiple cycle squashing, to model a ROB that can only 63 * remove a certain number of instructions per cycle. 64 */ 65template<class Impl> 66class DefaultCommit 67{ 68 public: 69 // Typedefs from the Impl. 70 typedef typename Impl::O3CPU O3CPU; 71 typedef typename Impl::DynInstPtr DynInstPtr; 72 typedef typename Impl::Params Params; 73 typedef typename Impl::CPUPol CPUPol; 74 75 typedef typename CPUPol::RenameMap RenameMap; 76 typedef typename CPUPol::ROB ROB; 77 78 typedef typename CPUPol::TimeStruct TimeStruct; 79 typedef typename CPUPol::FetchStruct FetchStruct; 80 typedef typename CPUPol::IEWStruct IEWStruct; 81 typedef typename CPUPol::RenameStruct RenameStruct; 82 83 typedef typename CPUPol::Fetch Fetch; 84 typedef typename CPUPol::IEW IEW; 85 86 typedef O3ThreadState<Impl> Thread; 87 88 /** Event class used to schedule a squash due to a trap (fault or 89 * interrupt) to happen on a specific cycle. 90 */ 91 class TrapEvent : public Event { 92 private: 93 DefaultCommit<Impl> *commit; 94 unsigned tid; 95 96 public: 97 TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid); 98 99 void process(); 100 const char *description(); 101 }; 102 103 /** Overall commit status. Used to determine if the CPU can deschedule 104 * itself due to a lack of activity. 105 */ 106 enum CommitStatus{ 107 Active, 108 Inactive 109 }; 110 111 /** Individual thread status. */ 112 enum ThreadStatus { 113 Running, 114 Idle, 115 ROBSquashing, 116 TrapPending, 117 FetchTrapPending 118 }; 119 120 /** Commit policy for SMT mode. */ 121 enum CommitPolicy { 122 Aggressive, 123 RoundRobin, 124 OldestReady 125 }; 126 127 private: 128 /** Overall commit status. */ 129 CommitStatus _status; 130 /** Next commit status, to be set at the end of the cycle. */ 131 CommitStatus _nextStatus; 132 /** Per-thread status. */ 133 ThreadStatus commitStatus[Impl::MaxThreads]; 134 /** Commit policy used in SMT mode. */ 135 CommitPolicy commitPolicy; 136 137 public: 138 /** Construct a DefaultCommit with the given parameters. */ 139 DefaultCommit(O3CPU *_cpu, Params *params); 140 141 /** Returns the name of the DefaultCommit. */ 142 std::string name() const; 143 144 /** Registers statistics. */ 145 void regStats(); 146 147 /** Sets the list of threads. */ 148 void setThreads(std::vector<Thread *> &threads); 149 150 /** Sets the main time buffer pointer, used for backwards communication. */ 151 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 152 153 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 154 155 /** Sets the pointer to the queue coming from rename. */ 156 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 157 158 /** Sets the pointer to the queue coming from IEW. */ 159 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 160 161 /** Sets the pointer to the IEW stage. */ 162 void setIEWStage(IEW *iew_stage); 163 164 /** Skid buffer between rename and commit. */ 165 std::queue<DynInstPtr> skidBuffer; 166 167 /** The pointer to the IEW stage. Used solely to ensure that 168 * various events (traps, interrupts, syscalls) do not occur until 169 * all stores have written back. 170 */ 171 IEW *iewStage; 172 173 /** Sets pointer to list of active threads. */ 174 void setActiveThreads(std::list<unsigned> *at_ptr); 175 176 /** Sets pointer to the commited state rename map. */ 177 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 178 179 /** Sets pointer to the ROB. */ 180 void setROB(ROB *rob_ptr); 181 182 /** Initializes stage by sending back the number of free entries. */ 183 void initStage(); 184 185 /** Initializes the draining of commit. */ 186 bool drain(); 187 188 /** Resumes execution after draining. */ 189 void resume(); 190 191 /** Completes the switch out of commit. */ 192 void switchOut(); 193 194 /** Takes over from another CPU's thread. */ 195 void takeOverFrom(); 196 197 /** Ticks the commit stage, which tries to commit instructions. */ 198 void tick(); 199 200 /** Handles any squashes that are sent from IEW, and adds instructions 201 * to the ROB and tries to commit instructions. 202 */ 203 void commit(); 204 205 /** Returns the number of free ROB entries for a specific thread. */ 206 unsigned numROBFreeEntries(unsigned tid); 207 208 /** Generates an event to schedule a squash due to a trap. */ 209 void generateTrapEvent(unsigned tid); 210 211 /** Records that commit needs to initiate a squash due to an 212 * external state update through the TC. 213 */ 214 void generateTCEvent(unsigned tid); 215 216 private: 217 /** Updates the overall status of commit with the nextStatus, and 218 * tell the CPU if commit is active/inactive. 219 */ 220 void updateStatus(); 221 222 /** Sets the next status based on threads' statuses, which becomes the 223 * current status at the end of the cycle. 224 */ 225 void setNextStatus(); 226 227 /** Checks if the ROB is completed with squashing. This is for the case 228 * where the ROB can take multiple cycles to complete squashing. 229 */ 230 bool robDoneSquashing(); 231 232 /** Returns if any of the threads have the number of ROB entries changed 233 * on this cycle. Used to determine if the number of free ROB entries needs 234 * to be sent back to previous stages. 235 */ 236 bool changedROBEntries(); 237 238 /** Squashes all in flight instructions. */ 239 void squashAll(unsigned tid); 240 241 /** Handles squashing due to a trap. */ 242 void squashFromTrap(unsigned tid); 243 244 /** Handles squashing due to an TC write. */ 245 void squashFromTC(unsigned tid); 246 247#if FULL_SYSTEM 248 /** Handles processing an interrupt. */ 249 void handleInterrupt(); 250#endif // FULL_SYSTEM 251 252 /** Commits as many instructions as possible. */ 253 void commitInsts(); 254 255 /** Tries to commit the head ROB instruction passed in. 256 * @param head_inst The instruction to be committed. 257 */ 258 bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 259 260 /** Gets instructions from rename and inserts them into the ROB. */ 261 void getInsts(); 262 263 /** Insert all instructions from rename into skidBuffer */ 264 void skidInsert(); 265 266 /** Marks completed instructions using information sent from IEW. */ 267 void markCompletedInsts(); 268 269 /** Gets the thread to commit, based on the SMT policy. */ 270 int getCommittingThread(); 271 272 /** Returns the thread ID to use based on a round robin policy. */ 273 int roundRobin(); 274 275 /** Returns the thread ID to use based on an oldest instruction policy. */ 276 int oldestReady(); 277 278 public: 279 /** Returns the PC of the head instruction of the ROB. 280 * @todo: Probably remove this function as it returns only thread 0. 281 */ 282 uint64_t readPC() { return PC[0]; } 283 284 /** Returns the PC of a specific thread. */ 285 uint64_t readPC(unsigned tid) { return PC[tid]; } 286 287 /** Sets the PC of a specific thread. */ 288 void setPC(uint64_t val, unsigned tid) { PC[tid] = val; } 289 290 /** Reads the next PC of a specific thread. */ 291 uint64_t readNextPC(unsigned tid) { return nextPC[tid]; } 292 293 /** Sets the next PC of a specific thread. */ 294 void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; } 295 296 /** Reads the next NPC of a specific thread. */ 297 uint64_t readNextNPC(unsigned tid) { return nextNPC[tid]; } 298 299 /** Sets the next NPC of a specific thread. */ 300 void setNextNPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; } 301 302 private: 303 /** Time buffer interface. */ 304 TimeBuffer<TimeStruct> *timeBuffer; 305 306 /** Wire to write information heading to previous stages. */ 307 typename TimeBuffer<TimeStruct>::wire toIEW; 308 309 /** Wire to read information from IEW (for ROB). */ 310 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 311 312 TimeBuffer<FetchStruct> *fetchQueue; 313 314 typename TimeBuffer<FetchStruct>::wire fromFetch; 315 316 /** IEW instruction queue interface. */ 317 TimeBuffer<IEWStruct> *iewQueue; 318 319 /** Wire to read information from IEW queue. */ 320 typename TimeBuffer<IEWStruct>::wire fromIEW; 321 322 /** Rename instruction queue interface, for ROB. */ 323 TimeBuffer<RenameStruct> *renameQueue; 324 325 /** Wire to read information from rename queue. */ 326 typename TimeBuffer<RenameStruct>::wire fromRename; 327 328 public: 329 /** ROB interface. */ 330 ROB *rob; 331 332 private: 333 /** Pointer to O3CPU. */ 334 O3CPU *cpu; 335 336 /** Vector of all of the threads. */ 337 std::vector<Thread *> thread; 338 339 /** Records that commit has written to the time buffer this cycle. Used for 340 * the CPU to determine if it can deschedule itself if there is no activity. 341 */ 342 bool wroteToTimeBuffer; 343 344 /** Records if the number of ROB entries has changed this cycle. If it has, 345 * then the number of free entries must be re-broadcast. 346 */ 347 bool changedROBNumEntries[Impl::MaxThreads]; 348 349 /** A counter of how many threads are currently squashing. */ 350 int squashCounter; 351 352 /** Records if a thread has to squash this cycle due to a trap. */ 353 bool trapSquash[Impl::MaxThreads]; 354 355 /** Records if a thread has to squash this cycle due to an XC write. */ 356 bool tcSquash[Impl::MaxThreads]; 357 358 /** Priority List used for Commit Policy */ 359 std::list<unsigned> priority_list; 360 361 /** IEW to Commit delay, in ticks. */ 362 unsigned iewToCommitDelay; 363 364 /** Commit to IEW delay, in ticks. */ 365 unsigned commitToIEWDelay; 366 367 /** Rename to ROB delay, in ticks. */ 368 unsigned renameToROBDelay; 369 370 unsigned fetchToCommitDelay; 371 372 /** Rename width, in instructions. Used so ROB knows how many 373 * instructions to get from the rename instruction queue. 374 */ 375 unsigned renameWidth; 376 377 /** Commit width, in instructions. */ 378 unsigned commitWidth; 379 380 /** Number of Reorder Buffers */ 381 unsigned numRobs; 382 383 /** Number of Active Threads */ 384 unsigned numThreads; 385 386 /** Is a drain pending. */ 387 bool drainPending; 388 389 /** Is commit switched out. */ 390 bool switchedOut; 391 392 /** The latency to handle a trap. Used when scheduling trap 393 * squash event. 394 */ 395 Tick trapLatency; 396 397 /** The interrupt fault. */ 398 Fault interrupt; 399 400 /** The commit PC of each thread. Refers to the instruction that 401 * is currently being processed/committed. 402 */ 403 Addr PC[Impl::MaxThreads]; 404 405 /** The next PC of each thread. */ 406 Addr nextPC[Impl::MaxThreads]; 407 408 /** The next NPC of each thread. */ 409 Addr nextNPC[Impl::MaxThreads]; 410 411 /** The sequence number of the youngest valid instruction in the ROB. */ 412 InstSeqNum youngestSeqNum[Impl::MaxThreads]; 413 414 /** Records if there is a trap currently in flight. */ 415 bool trapInFlight[Impl::MaxThreads]; 416 417 /** Records if there were any stores committed this cycle. */ 418 bool committedStores[Impl::MaxThreads]; 419 420 /** Records if commit should check if the ROB is truly empty (see 421 commit_impl.hh). */ 422 bool checkEmptyROB[Impl::MaxThreads]; 423 424 /** Pointer to the list of active threads. */ 425 std::list<unsigned> *activeThreads; 426 427 /** Rename map interface. */ 428 RenameMap *renameMap[Impl::MaxThreads]; 429 430 /** Updates commit stats based on this instruction. */ 431 void updateComInstStats(DynInstPtr &inst); 432 433 /** Stat for the total number of committed instructions. */ 434 Stats::Scalar<> commitCommittedInsts; 435 /** Stat for the total number of squashed instructions discarded by commit. 436 */ 437 Stats::Scalar<> commitSquashedInsts; 438 /** Stat for the total number of times commit is told to squash. 439 * @todo: Actually increment this stat. 440 */ 441 Stats::Scalar<> commitSquashEvents; 442 /** Stat for the total number of times commit has had to stall due to a non- 443 * speculative instruction reaching the head of the ROB. 444 */ 445 Stats::Scalar<> commitNonSpecStalls; 446 /** Stat for the total number of branch mispredicts that caused a squash. */ 447 Stats::Scalar<> branchMispredicts; 448 /** Distribution of the number of committed instructions each cycle. */ 449 Stats::Distribution<> numCommittedDist; 450 451 /** Total number of instructions committed. */ 452 Stats::Vector<> statComInst; 453 /** Total number of software prefetches committed. */ 454 Stats::Vector<> statComSwp; 455 /** Stat for the total number of committed memory references. */ 456 Stats::Vector<> statComRefs; 457 /** Stat for the total number of committed loads. */ 458 Stats::Vector<> statComLoads; 459 /** Total number of committed memory barriers. */ 460 Stats::Vector<> statComMembars; 461 /** Total number of committed branches. */ 462 Stats::Vector<> statComBranches; 463 464 /** Number of cycles where the commit bandwidth limit is reached. */ 465 Stats::Scalar<> commitEligibleSamples; 466 /** Number of instructions not committed due to bandwidth limits. */ 467 Stats::Vector<> commitEligible; 468}; 469 470#endif // __CPU_O3_COMMIT_HH__ 471