commit.hh revision 2935:d1223a6c9156 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#ifndef __CPU_O3_COMMIT_HH__
33#define __CPU_O3_COMMIT_HH__
34
35#include "arch/faults.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/exetrace.hh"
39#include "cpu/inst_seq.hh"
40
41template <class>
42class O3ThreadState;
43
44/**
45 * DefaultCommit handles single threaded and SMT commit. Its width is
46 * specified by the parameters; each cycle it tries to commit that
47 * many instructions. The SMT policy decides which thread it tries to
48 * commit instructions from. Non- speculative instructions must reach
49 * the head of the ROB before they are ready to execute; once they
50 * reach the head, commit will broadcast the instruction's sequence
51 * number to the previous stages so that they can issue/ execute the
52 * instruction. Only one non-speculative instruction is handled per
53 * cycle. Commit is responsible for handling all back-end initiated
54 * redirects.  It receives the redirect, and then broadcasts it to all
55 * stages, indicating the sequence number they should squash until,
56 * and any necessary branch misprediction information as well. It
57 * priortizes redirects by instruction's age, only broadcasting a
58 * redirect if it corresponds to an instruction that should currently
59 * be in the ROB. This is done by tracking the sequence number of the
60 * youngest instruction in the ROB, which gets updated to any
61 * squashing instruction's sequence number, and only broadcasting a
62 * redirect if it corresponds to an older instruction. Commit also
63 * supports multiple cycle squashing, to model a ROB that can only
64 * remove a certain number of instructions per cycle.
65 */
66template<class Impl>
67class DefaultCommit
68{
69  public:
70    // Typedefs from the Impl.
71    typedef typename Impl::O3CPU O3CPU;
72    typedef typename Impl::DynInstPtr DynInstPtr;
73    typedef typename Impl::Params Params;
74    typedef typename Impl::CPUPol CPUPol;
75
76    typedef typename CPUPol::RenameMap RenameMap;
77    typedef typename CPUPol::ROB ROB;
78
79    typedef typename CPUPol::TimeStruct TimeStruct;
80    typedef typename CPUPol::FetchStruct FetchStruct;
81    typedef typename CPUPol::IEWStruct IEWStruct;
82    typedef typename CPUPol::RenameStruct RenameStruct;
83
84    typedef typename CPUPol::Fetch Fetch;
85    typedef typename CPUPol::IEW IEW;
86
87    typedef O3ThreadState<Impl> Thread;
88
89    /** Event class used to schedule a squash due to a trap (fault or
90     * interrupt) to happen on a specific cycle.
91     */
92    class TrapEvent : public Event {
93      private:
94        DefaultCommit<Impl> *commit;
95        unsigned tid;
96
97      public:
98        TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
99
100        void process();
101        const char *description();
102    };
103
104    /** Overall commit status. Used to determine if the CPU can deschedule
105     * itself due to a lack of activity.
106     */
107    enum CommitStatus{
108        Active,
109        Inactive
110    };
111
112    /** Individual thread status. */
113    enum ThreadStatus {
114        Running,
115        Idle,
116        ROBSquashing,
117        TrapPending,
118        FetchTrapPending
119    };
120
121    /** Commit policy for SMT mode. */
122    enum CommitPolicy {
123        Aggressive,
124        RoundRobin,
125        OldestReady
126    };
127
128  private:
129    /** Overall commit status. */
130    CommitStatus _status;
131    /** Next commit status, to be set at the end of the cycle. */
132    CommitStatus _nextStatus;
133    /** Per-thread status. */
134    ThreadStatus commitStatus[Impl::MaxThreads];
135    /** Commit policy used in SMT mode. */
136    CommitPolicy commitPolicy;
137
138  public:
139    /** Construct a DefaultCommit with the given parameters. */
140    DefaultCommit(Params *params);
141
142    /** Returns the name of the DefaultCommit. */
143    std::string name() const;
144
145    /** Registers statistics. */
146    void regStats();
147
148    /** Sets the CPU pointer. */
149    void setCPU(O3CPU *cpu_ptr);
150
151    /** Sets the list of threads. */
152    void setThreads(std::vector<Thread *> &threads);
153
154    /** Sets the main time buffer pointer, used for backwards communication. */
155    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
156
157    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
158
159    /** Sets the pointer to the queue coming from rename. */
160    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
161
162    /** Sets the pointer to the queue coming from IEW. */
163    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
164
165    /** Sets the pointer to the IEW stage. */
166    void setIEWStage(IEW *iew_stage);
167
168    /** The pointer to the IEW stage. Used solely to ensure that
169     * various events (traps, interrupts, syscalls) do not occur until
170     * all stores have written back.
171     */
172    IEW *iewStage;
173
174    /** Sets pointer to list of active threads. */
175    void setActiveThreads(std::list<unsigned> *at_ptr);
176
177    /** Sets pointer to the commited state rename map. */
178    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
179
180    /** Sets pointer to the ROB. */
181    void setROB(ROB *rob_ptr);
182
183    /** Initializes stage by sending back the number of free entries. */
184    void initStage();
185
186    /** Initializes the draining of commit. */
187    bool drain();
188
189    /** Resumes execution after draining. */
190    void resume();
191
192    /** Completes the switch out of commit. */
193    void switchOut();
194
195    /** Takes over from another CPU's thread. */
196    void takeOverFrom();
197
198    /** Ticks the commit stage, which tries to commit instructions. */
199    void tick();
200
201    /** Handles any squashes that are sent from IEW, and adds instructions
202     * to the ROB and tries to commit instructions.
203     */
204    void commit();
205
206    /** Returns the number of free ROB entries for a specific thread. */
207    unsigned numROBFreeEntries(unsigned tid);
208
209    /** Generates an event to schedule a squash due to a trap. */
210    void generateTrapEvent(unsigned tid);
211
212    /** Records that commit needs to initiate a squash due to an
213     * external state update through the TC.
214     */
215    void generateTCEvent(unsigned tid);
216
217  private:
218    /** Updates the overall status of commit with the nextStatus, and
219     * tell the CPU if commit is active/inactive.
220     */
221    void updateStatus();
222
223    /** Sets the next status based on threads' statuses, which becomes the
224     * current status at the end of the cycle.
225     */
226    void setNextStatus();
227
228    /** Checks if the ROB is completed with squashing. This is for the case
229     * where the ROB can take multiple cycles to complete squashing.
230     */
231    bool robDoneSquashing();
232
233    /** Returns if any of the threads have the number of ROB entries changed
234     * on this cycle. Used to determine if the number of free ROB entries needs
235     * to be sent back to previous stages.
236     */
237    bool changedROBEntries();
238
239    /** Squashes all in flight instructions. */
240    void squashAll(unsigned tid);
241
242    /** Handles squashing due to a trap. */
243    void squashFromTrap(unsigned tid);
244
245    /** Handles squashing due to an TC write. */
246    void squashFromTC(unsigned tid);
247
248    /** Commits as many instructions as possible. */
249    void commitInsts();
250
251    /** Tries to commit the head ROB instruction passed in.
252     * @param head_inst The instruction to be committed.
253     */
254    bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
255
256    /** Gets instructions from rename and inserts them into the ROB. */
257    void getInsts();
258
259    /** Marks completed instructions using information sent from IEW. */
260    void markCompletedInsts();
261
262    /** Gets the thread to commit, based on the SMT policy. */
263    int getCommittingThread();
264
265    /** Returns the thread ID to use based on a round robin policy. */
266    int roundRobin();
267
268    /** Returns the thread ID to use based on an oldest instruction policy. */
269    int oldestReady();
270
271  public:
272    /** Returns the PC of the head instruction of the ROB.
273     * @todo: Probably remove this function as it returns only thread 0.
274     */
275    uint64_t readPC() { return PC[0]; }
276
277    /** Returns the PC of a specific thread. */
278    uint64_t readPC(unsigned tid) { return PC[tid]; }
279
280    /** Sets the PC of a specific thread. */
281    void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
282
283    /** Reads the next PC of a specific thread. */
284    uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
285
286    /** Sets the next PC of a specific thread. */
287    void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
288
289    /** Reads the next NPC of a specific thread. */
290    uint64_t readNextNPC(unsigned tid) { return nextNPC[tid]; }
291
292    /** Sets the next NPC of a specific thread. */
293    void setNextNPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; }
294
295  private:
296    /** Time buffer interface. */
297    TimeBuffer<TimeStruct> *timeBuffer;
298
299    /** Wire to write information heading to previous stages. */
300    typename TimeBuffer<TimeStruct>::wire toIEW;
301
302    /** Wire to read information from IEW (for ROB). */
303    typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
304
305    TimeBuffer<FetchStruct> *fetchQueue;
306
307    typename TimeBuffer<FetchStruct>::wire fromFetch;
308
309    /** IEW instruction queue interface. */
310    TimeBuffer<IEWStruct> *iewQueue;
311
312    /** Wire to read information from IEW queue. */
313    typename TimeBuffer<IEWStruct>::wire fromIEW;
314
315    /** Rename instruction queue interface, for ROB. */
316    TimeBuffer<RenameStruct> *renameQueue;
317
318    /** Wire to read information from rename queue. */
319    typename TimeBuffer<RenameStruct>::wire fromRename;
320
321  public:
322    /** ROB interface. */
323    ROB *rob;
324
325  private:
326    /** Pointer to O3CPU. */
327    O3CPU *cpu;
328
329    /** Vector of all of the threads. */
330    std::vector<Thread *> thread;
331
332    /** Records that commit has written to the time buffer this cycle. Used for
333     * the CPU to determine if it can deschedule itself if there is no activity.
334     */
335    bool wroteToTimeBuffer;
336
337    /** Records if the number of ROB entries has changed this cycle. If it has,
338     * then the number of free entries must be re-broadcast.
339     */
340    bool changedROBNumEntries[Impl::MaxThreads];
341
342    /** A counter of how many threads are currently squashing. */
343    int squashCounter;
344
345    /** Records if a thread has to squash this cycle due to a trap. */
346    bool trapSquash[Impl::MaxThreads];
347
348    /** Records if a thread has to squash this cycle due to an XC write. */
349    bool tcSquash[Impl::MaxThreads];
350
351    /** Priority List used for Commit Policy */
352    std::list<unsigned> priority_list;
353
354    /** IEW to Commit delay, in ticks. */
355    unsigned iewToCommitDelay;
356
357    /** Commit to IEW delay, in ticks. */
358    unsigned commitToIEWDelay;
359
360    /** Rename to ROB delay, in ticks. */
361    unsigned renameToROBDelay;
362
363    unsigned fetchToCommitDelay;
364
365    /** Rename width, in instructions.  Used so ROB knows how many
366     *  instructions to get from the rename instruction queue.
367     */
368    unsigned renameWidth;
369
370    /** Commit width, in instructions. */
371    unsigned commitWidth;
372
373    /** Number of Reorder Buffers */
374    unsigned numRobs;
375
376    /** Number of Active Threads */
377    unsigned numThreads;
378
379    /** Is a drain pending. */
380    bool drainPending;
381
382    /** Is commit switched out. */
383    bool switchedOut;
384
385    /** The latency to handle a trap.  Used when scheduling trap
386     * squash event.
387     */
388    Tick trapLatency;
389
390    /** The commit PC of each thread.  Refers to the instruction that
391     * is currently being processed/committed.
392     */
393    Addr PC[Impl::MaxThreads];
394
395    /** The next PC of each thread. */
396    Addr nextPC[Impl::MaxThreads];
397
398    /** The next NPC of each thread. */
399    Addr nextNPC[Impl::MaxThreads];
400
401    /** The sequence number of the youngest valid instruction in the ROB. */
402    InstSeqNum youngestSeqNum[Impl::MaxThreads];
403
404    /** Pointer to the list of active threads. */
405    std::list<unsigned> *activeThreads;
406
407    /** Rename map interface. */
408    RenameMap *renameMap[Impl::MaxThreads];
409
410    /** Updates commit stats based on this instruction. */
411    void updateComInstStats(DynInstPtr &inst);
412
413    /** Stat for the total number of committed instructions. */
414    Stats::Scalar<> commitCommittedInsts;
415    /** Stat for the total number of squashed instructions discarded by commit.
416     */
417    Stats::Scalar<> commitSquashedInsts;
418    /** Stat for the total number of times commit is told to squash.
419     * @todo: Actually increment this stat.
420     */
421    Stats::Scalar<> commitSquashEvents;
422    /** Stat for the total number of times commit has had to stall due to a non-
423     * speculative instruction reaching the head of the ROB.
424     */
425    Stats::Scalar<> commitNonSpecStalls;
426    /** Stat for the total number of branch mispredicts that caused a squash. */
427    Stats::Scalar<> branchMispredicts;
428    /** Distribution of the number of committed instructions each cycle. */
429    Stats::Distribution<> numCommittedDist;
430
431    /** Total number of instructions committed. */
432    Stats::Vector<> statComInst;
433    /** Total number of software prefetches committed. */
434    Stats::Vector<> statComSwp;
435    /** Stat for the total number of committed memory references. */
436    Stats::Vector<> statComRefs;
437    /** Stat for the total number of committed loads. */
438    Stats::Vector<> statComLoads;
439    /** Total number of committed memory barriers. */
440    Stats::Vector<> statComMembars;
441    /** Total number of committed branches. */
442    Stats::Vector<> statComBranches;
443
444    /** Number of cycles where the commit bandwidth limit is reached. */
445    Stats::Scalar<> commitEligibleSamples;
446    /** Number of instructions not committed due to bandwidth limits. */
447    Stats::Vector<> commitEligible;
448};
449
450#endif // __CPU_O3_COMMIT_HH__
451