commit.hh revision 2665:a124942bacb8 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// Todo: Maybe have a special method for handling interrupts/traps.
32//
33// Traps:  Have IEW send a signal to commit saying that there's a trap to
34// be handled.  Have commit send the PC back to the fetch stage, along
35// with the current commit PC.  Fetch will directly access the IPR and save
36// off all the proper stuff.  Commit can send out a squash, or something
37// close to it.
38// Do the same for hwrei().  However, requires that commit be specifically
39// built to support that kind of stuff.  Probably not horrible to have
40// commit support having the CPU tell it to squash the other stages and
41// restart at a given address.  The IPR register does become an issue.
42// Probably not a big deal if the IPR stuff isn't cycle accurate.  Can just
43// have the original function handle writing to the IPR register.
44
45#ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__
46#define __CPU_O3_CPU_SIMPLE_COMMIT_HH__
47
48#include "base/statistics.hh"
49#include "base/timebuf.hh"
50#include "mem/memory_interface.hh"
51
52template<class Impl>
53class SimpleCommit
54{
55  public:
56    // Typedefs from the Impl.
57    typedef typename Impl::FullCPU FullCPU;
58    typedef typename Impl::DynInstPtr DynInstPtr;
59    typedef typename Impl::Params Params;
60    typedef typename Impl::CPUPol CPUPol;
61
62    typedef typename CPUPol::ROB ROB;
63
64    typedef typename CPUPol::TimeStruct TimeStruct;
65    typedef typename CPUPol::IEWStruct IEWStruct;
66    typedef typename CPUPol::RenameStruct RenameStruct;
67
68  public:
69    // I don't believe commit can block, so it will only have two
70    // statuses for now.
71    // Actually if there's a cache access that needs to block (ie
72    // uncachable load or just a mem access in commit) then the stage
73    // may have to wait.
74    enum Status {
75        Running,
76        Idle,
77        ROBSquashing,
78        DcacheMissStall,
79        DcacheMissComplete
80    };
81
82  private:
83    Status _status;
84
85  public:
86    SimpleCommit(Params &params);
87
88    void regStats();
89
90    void setCPU(FullCPU *cpu_ptr);
91
92    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
93
94    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
95
96    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
97
98    void setROB(ROB *rob_ptr);
99
100    void tick();
101
102    void commit();
103
104  private:
105
106    void commitInsts();
107
108    bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
109
110    void getInsts();
111
112    void markCompletedInsts();
113
114  public:
115    uint64_t readCommitPC();
116
117    void setSquashing() { _status = ROBSquashing; }
118
119  private:
120    /** Time buffer interface. */
121    TimeBuffer<TimeStruct> *timeBuffer;
122
123    /** Wire to write information heading to previous stages. */
124    typename TimeBuffer<TimeStruct>::wire toIEW;
125
126    /** Wire to read information from IEW (for ROB). */
127    typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
128
129    /** IEW instruction queue interface. */
130    TimeBuffer<IEWStruct> *iewQueue;
131
132    /** Wire to read information from IEW queue. */
133    typename TimeBuffer<IEWStruct>::wire fromIEW;
134
135    /** Rename instruction queue interface, for ROB. */
136    TimeBuffer<RenameStruct> *renameQueue;
137
138    /** Wire to read information from rename queue. */
139    typename TimeBuffer<RenameStruct>::wire fromRename;
140
141    /** ROB interface. */
142    ROB *rob;
143
144    /** Pointer to FullCPU. */
145    FullCPU *cpu;
146
147    /** Memory interface.  Used for d-cache accesses. */
148    MemInterface *dcacheInterface;
149
150  private:
151    /** IEW to Commit delay, in ticks. */
152    unsigned iewToCommitDelay;
153
154    /** Rename to ROB delay, in ticks. */
155    unsigned renameToROBDelay;
156
157    /** Rename width, in instructions.  Used so ROB knows how many
158     *  instructions to get from the rename instruction queue.
159     */
160    unsigned renameWidth;
161
162    /** IEW width, in instructions.  Used so ROB knows how many
163     *  instructions to get from the IEW instruction queue.
164     */
165    unsigned iewWidth;
166
167    /** Commit width, in instructions. */
168    unsigned commitWidth;
169
170    Stats::Scalar<> commitCommittedInsts;
171    Stats::Scalar<> commitSquashedInsts;
172    Stats::Scalar<> commitSquashEvents;
173    Stats::Scalar<> commitNonSpecStalls;
174    Stats::Scalar<> commitCommittedBranches;
175    Stats::Scalar<> commitCommittedLoads;
176    Stats::Scalar<> commitCommittedMemRefs;
177    Stats::Scalar<> branchMispredicts;
178
179    Stats::Distribution<> n_committed_dist;
180};
181
182#endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__
183