commit.hh revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29// Todo: Maybe have a special method for handling interrupts/traps.
30//
31// Traps:  Have IEW send a signal to commit saying that there's a trap to
32// be handled.  Have commit send the PC back to the fetch stage, along
33// with the current commit PC.  Fetch will directly access the IPR and save
34// off all the proper stuff.  Commit can send out a squash, or something
35// close to it.
36// Do the same for hwrei().  However, requires that commit be specifically
37// built to support that kind of stuff.  Probably not horrible to have
38// commit support having the CPU tell it to squash the other stages and
39// restart at a given address.  The IPR register does become an issue.
40// Probably not a big deal if the IPR stuff isn't cycle accurate.  Can just
41// have the original function handle writing to the IPR register.
42
43#ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__
44#define __CPU_O3_CPU_SIMPLE_COMMIT_HH__
45
46#include "base/statistics.hh"
47#include "base/timebuf.hh"
48#include "mem/memory_interface.hh"
49
50template<class Impl>
51class SimpleCommit
52{
53  public:
54    // Typedefs from the Impl.
55    typedef typename Impl::FullCPU FullCPU;
56    typedef typename Impl::DynInstPtr DynInstPtr;
57    typedef typename Impl::Params Params;
58    typedef typename Impl::CPUPol CPUPol;
59
60    typedef typename CPUPol::ROB ROB;
61
62    typedef typename CPUPol::TimeStruct TimeStruct;
63    typedef typename CPUPol::IEWStruct IEWStruct;
64    typedef typename CPUPol::RenameStruct RenameStruct;
65
66  public:
67    // I don't believe commit can block, so it will only have two
68    // statuses for now.
69    // Actually if there's a cache access that needs to block (ie
70    // uncachable load or just a mem access in commit) then the stage
71    // may have to wait.
72    enum Status {
73        Running,
74        Idle,
75        ROBSquashing,
76        DcacheMissStall,
77        DcacheMissComplete
78    };
79
80  private:
81    Status _status;
82
83  public:
84    SimpleCommit(Params &params);
85
86    void regStats();
87
88    void setCPU(FullCPU *cpu_ptr);
89
90    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
91
92    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
93
94    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
95
96    void setROB(ROB *rob_ptr);
97
98    void tick();
99
100    void commit();
101
102  private:
103
104    void commitInsts();
105
106    bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
107
108    void getInsts();
109
110    void markCompletedInsts();
111
112  public:
113    uint64_t readCommitPC();
114
115    void setSquashing() { _status = ROBSquashing; }
116
117  private:
118    /** Time buffer interface. */
119    TimeBuffer<TimeStruct> *timeBuffer;
120
121    /** Wire to write information heading to previous stages. */
122    typename TimeBuffer<TimeStruct>::wire toIEW;
123
124    /** Wire to read information from IEW (for ROB). */
125    typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
126
127    /** IEW instruction queue interface. */
128    TimeBuffer<IEWStruct> *iewQueue;
129
130    /** Wire to read information from IEW queue. */
131    typename TimeBuffer<IEWStruct>::wire fromIEW;
132
133    /** Rename instruction queue interface, for ROB. */
134    TimeBuffer<RenameStruct> *renameQueue;
135
136    /** Wire to read information from rename queue. */
137    typename TimeBuffer<RenameStruct>::wire fromRename;
138
139    /** ROB interface. */
140    ROB *rob;
141
142    /** Pointer to FullCPU. */
143    FullCPU *cpu;
144
145    /** Memory interface.  Used for d-cache accesses. */
146    MemInterface *dcacheInterface;
147
148  private:
149    /** IEW to Commit delay, in ticks. */
150    unsigned iewToCommitDelay;
151
152    /** Rename to ROB delay, in ticks. */
153    unsigned renameToROBDelay;
154
155    /** Rename width, in instructions.  Used so ROB knows how many
156     *  instructions to get from the rename instruction queue.
157     */
158    unsigned renameWidth;
159
160    /** IEW width, in instructions.  Used so ROB knows how many
161     *  instructions to get from the IEW instruction queue.
162     */
163    unsigned iewWidth;
164
165    /** Commit width, in instructions. */
166    unsigned commitWidth;
167
168    Stats::Scalar<> commitCommittedInsts;
169    Stats::Scalar<> commitSquashedInsts;
170    Stats::Scalar<> commitSquashEvents;
171    Stats::Scalar<> commitNonSpecStalls;
172    Stats::Scalar<> commitCommittedBranches;
173    Stats::Scalar<> commitCommittedLoads;
174    Stats::Scalar<> commitCommittedMemRefs;
175    Stats::Scalar<> branchMispredicts;
176
177    Stats::Distribution<> n_committed_dist;
178};
179
180#endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__
181