commit.hh revision 9437
1360SN/A/* 21458SN/A * Copyright (c) 2010-2012 ARM Limited 3360SN/A * All rights reserved. 4360SN/A * 5360SN/A * The license below extends only to copyright in the software and shall 6360SN/A * not be construed as granting a license to any other intellectual 7360SN/A * property including but not limited to intellectual property relating 8360SN/A * to a hardware implementation of the functionality of the software 9360SN/A * licensed hereunder. You may use the software subject to the license 10360SN/A * terms below provided that you ensure that this notice is replicated 11360SN/A * unmodified and in its entirety in all distributions of the software, 12360SN/A * modified or unmodified, in source code or in binary form. 13360SN/A * 14360SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 15360SN/A * All rights reserved. 16360SN/A * 17360SN/A * Redistribution and use in source and binary forms, with or without 18360SN/A * modification, are permitted provided that the following conditions are 19360SN/A * met: redistributions of source code must retain the above copyright 20360SN/A * notice, this list of conditions and the following disclaimer; 21360SN/A * redistributions in binary form must reproduce the above copyright 22360SN/A * notice, this list of conditions and the following disclaimer in the 23360SN/A * documentation and/or other materials provided with the distribution; 24360SN/A * neither the name of the copyright holders nor the names of its 25360SN/A * contributors may be used to endorse or promote products derived from 26360SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31360SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211793Sbrandon.potter@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311793Sbrandon.potter@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342093SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513479Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36360SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811911SBrandon.Potter@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396712Snate@binkert.org * 4013031Sbrandon.potter@amd.com * Authors: Kevin Lim 41360SN/A * Korey Sewell 42360SN/A */ 437680Sgblack@eecs.umich.edu 442474SN/A#ifndef __CPU_O3_COMMIT_HH__ 45360SN/A#define __CPU_O3_COMMIT_HH__ 466658Snate@binkert.org 472680Sktlim@umich.edu#include <queue> 4812716Smichael.lebeane@amd.com 492474SN/A#include "base/statistics.hh" 5013031Sbrandon.potter@amd.com#include "cpu/exetrace.hh" 51360SN/A#include "cpu/inst_seq.hh" 528229Snate@binkert.org#include "cpu/timebuf.hh" 5311794Sbrandon.potter@amd.com 5411794Sbrandon.potter@amd.comstruct DerivO3CPUParams; 556029Ssteve.reinhardt@amd.com 56360SN/Atemplate <class> 57360SN/Astruct O3ThreadState; 582107SN/A 59360SN/A/** 601450SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 6111851Sbrandon.potter@amd.com * specified by the parameters; each cycle it tries to commit that 622680Sktlim@umich.edu * many instructions. The SMT policy decides which thread it tries to 63360SN/A * commit instructions from. Non- speculative instructions must reach 6411794Sbrandon.potter@amd.com * the head of the ROB before they are ready to execute; once they 652484SN/A * reach the head, commit will broadcast the instruction's sequence 662484SN/A * number to the previous stages so that they can issue/ execute the 67360SN/A * instruction. Only one non-speculative instruction is handled per 68360SN/A * cycle. Commit is responsible for handling all back-end initiated 69360SN/A * redirects. It receives the redirect, and then broadcasts it to all 701450SN/A * stages, indicating the sequence number they should squash until, 7111851Sbrandon.potter@amd.com * and any necessary branch misprediction information as well. It 722680Sktlim@umich.edu * priortizes redirects by instruction's age, only broadcasting a 73360SN/A * redirect if it corresponds to an instruction that should currently 7411794Sbrandon.potter@amd.com * be in the ROB. This is done by tracking the sequence number of the 7511794Sbrandon.potter@amd.com * youngest instruction in the ROB, which gets updated to any 7611794Sbrandon.potter@amd.com * squashing instruction's sequence number, and only broadcasting a 7710831Ssteve.reinhardt@amd.com * redirect if it corresponds to an older instruction. Commit also 78360SN/A * supports multiple cycle squashing, to model a ROB that can only 798149SChris.Emmons@ARM.com * remove a certain number of instructions per cycle. 808149SChris.Emmons@ARM.com */ 818149SChris.Emmons@ARM.comtemplate<class Impl> 8211886Sbrandon.potter@amd.comclass DefaultCommit 8311911SBrandon.Potter@amd.com{ 8411886Sbrandon.potter@amd.com public: 8511911SBrandon.Potter@amd.com // Typedefs from the Impl. 8611911SBrandon.Potter@amd.com typedef typename Impl::O3CPU O3CPU; 8711911SBrandon.Potter@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 8811911SBrandon.Potter@amd.com typedef typename Impl::CPUPol CPUPol; 8911911SBrandon.Potter@amd.com 9011886Sbrandon.potter@amd.com typedef typename CPUPol::RenameMap RenameMap; 9111911SBrandon.Potter@amd.com typedef typename CPUPol::ROB ROB; 9211911SBrandon.Potter@amd.com 9311911SBrandon.Potter@amd.com typedef typename CPUPol::TimeStruct TimeStruct; 9411911SBrandon.Potter@amd.com typedef typename CPUPol::FetchStruct FetchStruct; 9511911SBrandon.Potter@amd.com typedef typename CPUPol::IEWStruct IEWStruct; 9611911SBrandon.Potter@amd.com typedef typename CPUPol::RenameStruct RenameStruct; 9711911SBrandon.Potter@amd.com 9811911SBrandon.Potter@amd.com typedef typename CPUPol::Fetch Fetch; 9911911SBrandon.Potter@amd.com typedef typename CPUPol::IEW IEW; 10011911SBrandon.Potter@amd.com 10111911SBrandon.Potter@amd.com typedef O3ThreadState<Impl> Thread; 10211911SBrandon.Potter@amd.com 10311911SBrandon.Potter@amd.com /** Event class used to schedule a squash due to a trap (fault or 10411911SBrandon.Potter@amd.com * interrupt) to happen on a specific cycle. 10511911SBrandon.Potter@amd.com */ 10611911SBrandon.Potter@amd.com class TrapEvent : public Event { 10711911SBrandon.Potter@amd.com private: 10811911SBrandon.Potter@amd.com DefaultCommit<Impl> *commit; 10912716Smichael.lebeane@amd.com ThreadID tid; 11012716Smichael.lebeane@amd.com 11112716Smichael.lebeane@amd.com public: 11212716Smichael.lebeane@amd.com TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 11312716Smichael.lebeane@amd.com 11412716Smichael.lebeane@amd.com void process(); 11512716Smichael.lebeane@amd.com const char *description() const; 11612716Smichael.lebeane@amd.com }; 11712716Smichael.lebeane@amd.com 11812716Smichael.lebeane@amd.com /** Overall commit status. Used to determine if the CPU can deschedule 11912716Smichael.lebeane@amd.com * itself due to a lack of activity. 12012716Smichael.lebeane@amd.com */ 12112716Smichael.lebeane@amd.com enum CommitStatus{ 12212716Smichael.lebeane@amd.com Active, 12311911SBrandon.Potter@amd.com Inactive 12411911SBrandon.Potter@amd.com }; 12511911SBrandon.Potter@amd.com 12611911SBrandon.Potter@amd.com /** Individual thread status. */ 12711911SBrandon.Potter@amd.com enum ThreadStatus { 12811911SBrandon.Potter@amd.com Running, 12911911SBrandon.Potter@amd.com Idle, 13011911SBrandon.Potter@amd.com ROBSquashing, 13111911SBrandon.Potter@amd.com TrapPending, 13211911SBrandon.Potter@amd.com FetchTrapPending, 13311911SBrandon.Potter@amd.com SquashAfterPending, //< Committing instructions before a squash. 13411911SBrandon.Potter@amd.com }; 13511911SBrandon.Potter@amd.com 13611911SBrandon.Potter@amd.com /** Commit policy for SMT mode. */ 13711911SBrandon.Potter@amd.com enum CommitPolicy { 13811911SBrandon.Potter@amd.com Aggressive, 13911911SBrandon.Potter@amd.com RoundRobin, 14011911SBrandon.Potter@amd.com OldestReady 14111911SBrandon.Potter@amd.com }; 14211911SBrandon.Potter@amd.com 14311911SBrandon.Potter@amd.com private: 14411911SBrandon.Potter@amd.com /** Overall commit status. */ 14511911SBrandon.Potter@amd.com CommitStatus _status; 14611911SBrandon.Potter@amd.com /** Next commit status, to be set at the end of the cycle. */ 14711911SBrandon.Potter@amd.com CommitStatus _nextStatus; 14811911SBrandon.Potter@amd.com /** Per-thread status. */ 14911911SBrandon.Potter@amd.com ThreadStatus commitStatus[Impl::MaxThreads]; 15011911SBrandon.Potter@amd.com /** Commit policy used in SMT mode. */ 15111911SBrandon.Potter@amd.com CommitPolicy commitPolicy; 15211911SBrandon.Potter@amd.com 15311911SBrandon.Potter@amd.com public: 15411911SBrandon.Potter@amd.com /** Construct a DefaultCommit with the given parameters. */ 15511911SBrandon.Potter@amd.com DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 15611911SBrandon.Potter@amd.com 15711911SBrandon.Potter@amd.com /** Returns the name of the DefaultCommit. */ 15811911SBrandon.Potter@amd.com std::string name() const; 15911911SBrandon.Potter@amd.com 16011911SBrandon.Potter@amd.com /** Registers statistics. */ 16111911SBrandon.Potter@amd.com void regStats(); 16211911SBrandon.Potter@amd.com 16311911SBrandon.Potter@amd.com /** Sets the list of threads. */ 16411911SBrandon.Potter@amd.com void setThreads(std::vector<Thread *> &threads); 16511911SBrandon.Potter@amd.com 16611911SBrandon.Potter@amd.com /** Sets the main time buffer pointer, used for backwards communication. */ 16711911SBrandon.Potter@amd.com void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 16811911SBrandon.Potter@amd.com 16911911SBrandon.Potter@amd.com void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 17011911SBrandon.Potter@amd.com 17111886Sbrandon.potter@amd.com /** Sets the pointer to the queue coming from rename. */ 17211886Sbrandon.potter@amd.com void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 17311911SBrandon.Potter@amd.com 17411911SBrandon.Potter@amd.com /** Sets the pointer to the queue coming from IEW. */ 17511911SBrandon.Potter@amd.com void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 17611911SBrandon.Potter@amd.com 17711911SBrandon.Potter@amd.com /** Sets the pointer to the IEW stage. */ 17811911SBrandon.Potter@amd.com void setIEWStage(IEW *iew_stage); 17911911SBrandon.Potter@amd.com 18011911SBrandon.Potter@amd.com /** Skid buffer between rename and commit. */ 18111911SBrandon.Potter@amd.com std::queue<DynInstPtr> skidBuffer; 18211911SBrandon.Potter@amd.com 18311911SBrandon.Potter@amd.com /** The pointer to the IEW stage. Used solely to ensure that 18411911SBrandon.Potter@amd.com * various events (traps, interrupts, syscalls) do not occur until 18511911SBrandon.Potter@amd.com * all stores have written back. 18611911SBrandon.Potter@amd.com */ 18711911SBrandon.Potter@amd.com IEW *iewStage; 18811911SBrandon.Potter@amd.com 18911911SBrandon.Potter@amd.com /** Sets pointer to list of active threads. */ 19011911SBrandon.Potter@amd.com void setActiveThreads(std::list<ThreadID> *at_ptr); 19111911SBrandon.Potter@amd.com 19211911SBrandon.Potter@amd.com /** Sets pointer to the commited state rename map. */ 19311886Sbrandon.potter@amd.com void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1948149SChris.Emmons@ARM.com 1958149SChris.Emmons@ARM.com /** Sets pointer to the ROB. */ 19611886Sbrandon.potter@amd.com void setROB(ROB *rob_ptr); 197360SN/A 19811911SBrandon.Potter@amd.com /** Initializes stage by sending back the number of free entries. */ 199360SN/A void startupStage(); 200360SN/A 2011450SN/A /** Initializes the draining of commit. */ 20211911SBrandon.Potter@amd.com bool drain(); 2036109Ssanchezd@stanford.edu 20411911SBrandon.Potter@amd.com /** Resumes execution after draining. */ 2056109Ssanchezd@stanford.edu void resume(); 2066109Ssanchezd@stanford.edu 2076109Ssanchezd@stanford.edu /** Completes the switch out of commit. */ 20811851Sbrandon.potter@amd.com void switchOut(); 209360SN/A 21010318Sandreas.hansson@arm.com /** Takes over from another CPU's thread. */ 211360SN/A void takeOverFrom(); 212360SN/A 213360SN/A /** Ticks the commit stage, which tries to commit instructions. */ 2141450SN/A void tick(); 21511851Sbrandon.potter@amd.com 216360SN/A /** Handles any squashes that are sent from IEW, and adds instructions 217360SN/A * to the ROB and tries to commit instructions. 2186701Sgblack@eecs.umich.edu */ 2196701Sgblack@eecs.umich.edu void commit(); 2205748SSteve.Reinhardt@amd.com 22111905SBrandon.Potter@amd.com /** Returns the number of free ROB entries for a specific thread. */ 22211905SBrandon.Potter@amd.com size_t numROBFreeEntries(ThreadID tid); 22311905SBrandon.Potter@amd.com 2245748SSteve.Reinhardt@amd.com /** Generates an event to schedule a squash due to a trap. */ 2255748SSteve.Reinhardt@amd.com void generateTrapEvent(ThreadID tid); 2265748SSteve.Reinhardt@amd.com 22711905SBrandon.Potter@amd.com /** Records that commit needs to initiate a squash due to an 2285748SSteve.Reinhardt@amd.com * external state update through the TC. 22911905SBrandon.Potter@amd.com */ 2305748SSteve.Reinhardt@amd.com void generateTCEvent(ThreadID tid); 23111905SBrandon.Potter@amd.com 23211905SBrandon.Potter@amd.com private: 23310318Sandreas.hansson@arm.com /** Updates the overall status of commit with the nextStatus, and 2345748SSteve.Reinhardt@amd.com * tell the CPU if commit is active/inactive. 23510318Sandreas.hansson@arm.com */ 2366687Stjones1@inf.ed.ac.uk void updateStatus(); 2376687Stjones1@inf.ed.ac.uk 2386687Stjones1@inf.ed.ac.uk /** Sets the next status based on threads' statuses, which becomes the 23911905SBrandon.Potter@amd.com * current status at the end of the cycle. 2408852Sandreas.hansson@arm.com */ 2416687Stjones1@inf.ed.ac.uk void setNextStatus(); 2426687Stjones1@inf.ed.ac.uk 24310318Sandreas.hansson@arm.com /** Checks if the ROB is completed with squashing. This is for the case 2446687Stjones1@inf.ed.ac.uk * where the ROB can take multiple cycles to complete squashing. 2458852Sandreas.hansson@arm.com */ 24610318Sandreas.hansson@arm.com bool robDoneSquashing(); 2476687Stjones1@inf.ed.ac.uk 24811906SBrandon.Potter@amd.com /** Returns if any of the threads have the number of ROB entries changed 24910318Sandreas.hansson@arm.com * on this cycle. Used to determine if the number of free ROB entries needs 2508852Sandreas.hansson@arm.com * to be sent back to previous stages. 2516687Stjones1@inf.ed.ac.uk */ 2526687Stjones1@inf.ed.ac.uk bool changedROBEntries(); 2532474SN/A 2541450SN/A /** Squashes all in flight instructions. */ 2555748SSteve.Reinhardt@amd.com void squashAll(ThreadID tid); 25611905SBrandon.Potter@amd.com 25711380Salexandru.dutu@amd.com /** Handles squashing due to a trap. */ 25811905SBrandon.Potter@amd.com void squashFromTrap(ThreadID tid); 25911905SBrandon.Potter@amd.com 260360SN/A /** Handles squashing due to an TC write. */ 261360SN/A void squashFromTC(ThreadID tid); 26211886Sbrandon.potter@amd.com 26311886Sbrandon.potter@amd.com /** Handles a squash from a squashAfter() request. */ 26411886Sbrandon.potter@amd.com void squashFromSquashAfter(ThreadID tid); 26511886Sbrandon.potter@amd.com 26611886Sbrandon.potter@amd.com /** 26711886Sbrandon.potter@amd.com * Handle squashing from instruction with SquashAfter set. 26811886Sbrandon.potter@amd.com * 26911886Sbrandon.potter@amd.com * This differs from the other squashes as it squashes following 27011886Sbrandon.potter@amd.com * instructions instead of the current instruction and doesn't 27111886Sbrandon.potter@amd.com * clean up various status bits about traps/tc writes 272360SN/A * pending. Since there might have been instructions committed by 2731450SN/A * the commit stage before the squashing instruction was reached 27411851Sbrandon.potter@amd.com * and we can't commit and squash in the same cycle, we have to 275360SN/A * squash in two steps: 2766701Sgblack@eecs.umich.edu * 27710931Sbrandon.potter@amd.com * <ol> 27810931Sbrandon.potter@amd.com * <li>Immediately set the commit status of the thread of 27911856Sbrandon.potter@amd.com * SquashAfterPending. This forces the thread to stop 280360SN/A * committing instructions in this cycle. The last 281360SN/A * instruction to be committed in this cycle will be the 2821450SN/A * SquashAfter instruction. 28311851Sbrandon.potter@amd.com * <li>In the next cycle, commit() checks for the 284360SN/A * SquashAfterPending state and squashes <i>all</i> 2856701Sgblack@eecs.umich.edu * in-flight instructions. Since the SquashAfter instruction 28610931Sbrandon.potter@amd.com * was the last instruction to be committed in the previous 2876701Sgblack@eecs.umich.edu * cycle, this causes all subsequent instructions to be 2886701Sgblack@eecs.umich.edu * squashed. 289360SN/A * </ol> 29011856Sbrandon.potter@amd.com * 29111856Sbrandon.potter@amd.com * @param tid ID of the thread to squash. 29210931Sbrandon.potter@amd.com * @param head_inst Instruction that requested the squash. 29311856Sbrandon.potter@amd.com */ 29410931Sbrandon.potter@amd.com void squashAfter(ThreadID tid, DynInstPtr &head_inst); 29510931Sbrandon.potter@amd.com 296360SN/A /** Handles processing an interrupt. */ 2971458SN/A void handleInterrupt(); 298360SN/A 299360SN/A /** Get fetch redirecting so we can handle an interrupt */ 300360SN/A void propagateInterrupt(); 3011450SN/A 30211851Sbrandon.potter@amd.com /** Commits as many instructions as possible. */ 3034118Sgblack@eecs.umich.edu void commitInsts(); 3046701Sgblack@eecs.umich.edu 30510931Sbrandon.potter@amd.com /** Tries to commit the head ROB instruction passed in. 3066701Sgblack@eecs.umich.edu * @param head_inst The instruction to be committed. 3076701Sgblack@eecs.umich.edu */ 3086701Sgblack@eecs.umich.edu bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 3096701Sgblack@eecs.umich.edu 3104118Sgblack@eecs.umich.edu /** Gets instructions from rename and inserts them into the ROB. */ 31111856Sbrandon.potter@amd.com void getInsts(); 31211856Sbrandon.potter@amd.com 31310931Sbrandon.potter@amd.com /** Insert all instructions from rename into skidBuffer */ 31411856Sbrandon.potter@amd.com void skidInsert(); 31510931Sbrandon.potter@amd.com 3164118Sgblack@eecs.umich.edu /** Marks completed instructions using information sent from IEW. */ 3174118Sgblack@eecs.umich.edu void markCompletedInsts(); 31810931Sbrandon.potter@amd.com 3194118Sgblack@eecs.umich.edu /** Gets the thread to commit, based on the SMT policy. */ 3204118Sgblack@eecs.umich.edu ThreadID getCommittingThread(); 32111379Sbrandon.potter@amd.com 3224118Sgblack@eecs.umich.edu /** Returns the thread ID to use based on a round robin policy. */ 32311379Sbrandon.potter@amd.com ThreadID roundRobin(); 32411379Sbrandon.potter@amd.com 32511379Sbrandon.potter@amd.com /** Returns the thread ID to use based on an oldest instruction policy. */ 32611379Sbrandon.potter@amd.com ThreadID oldestReady(); 32711379Sbrandon.potter@amd.com 3284118Sgblack@eecs.umich.edu public: 3294118Sgblack@eecs.umich.edu /** Reads the PC of a specific thread. */ 3304118Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 3314118Sgblack@eecs.umich.edu 33211851Sbrandon.potter@amd.com /** Sets the PC of a specific thread. */ 333360SN/A void pcState(const TheISA::PCState &val, ThreadID tid) 33411383Sbrandon.potter@amd.com { pc[tid] = val; } 33511383Sbrandon.potter@amd.com 33611383Sbrandon.potter@amd.com /** Returns the PC of a specific thread. */ 3371458SN/A Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 338360SN/A 339360SN/A /** Returns the next PC of a specific thread. */ 340360SN/A Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 341360SN/A 342360SN/A /** Reads the micro PC of a specific thread. */ 3431450SN/A Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 34411851Sbrandon.potter@amd.com 345360SN/A private: 3466701Sgblack@eecs.umich.edu /** Time buffer interface. */ 34711906SBrandon.Potter@amd.com TimeBuffer<TimeStruct> *timeBuffer; 3486701Sgblack@eecs.umich.edu 34911906SBrandon.Potter@amd.com /** Wire to write information heading to previous stages. */ 350360SN/A typename TimeBuffer<TimeStruct>::wire toIEW; 351360SN/A 352360SN/A /** Wire to read information from IEW (for ROB). */ 3538706Sandreas.hansson@arm.com typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 354360SN/A 3551458SN/A TimeBuffer<FetchStruct> *fetchQueue; 356360SN/A 357360SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 3581450SN/A 35911851Sbrandon.potter@amd.com /** IEW instruction queue interface. */ 3605513SMichael.Adler@intel.com TimeBuffer<IEWStruct> *iewQueue; 3615513SMichael.Adler@intel.com 3626731Svince@csl.cornell.edu /** Wire to read information from IEW queue. */ 36311906SBrandon.Potter@amd.com typename TimeBuffer<IEWStruct>::wire fromIEW; 3646701Sgblack@eecs.umich.edu 36511906SBrandon.Potter@amd.com /** Rename instruction queue interface, for ROB. */ 3665513SMichael.Adler@intel.com TimeBuffer<RenameStruct> *renameQueue; 3675513SMichael.Adler@intel.com 3685513SMichael.Adler@intel.com /** Wire to read information from rename queue. */ 3695513SMichael.Adler@intel.com typename TimeBuffer<RenameStruct>::wire fromRename; 3705513SMichael.Adler@intel.com 3715513SMichael.Adler@intel.com public: 3725513SMichael.Adler@intel.com /** ROB interface. */ 3735513SMichael.Adler@intel.com ROB *rob; 3745513SMichael.Adler@intel.com 3755513SMichael.Adler@intel.com private: 37610955Sdavid.hashe@amd.com /** Pointer to O3CPU. */ 37711856Sbrandon.potter@amd.com O3CPU *cpu; 3785513SMichael.Adler@intel.com 37910955Sdavid.hashe@amd.com /** Vector of all of the threads. */ 3805513SMichael.Adler@intel.com std::vector<Thread *> thread; 3815513SMichael.Adler@intel.com 3825513SMichael.Adler@intel.com /** Records that commit has written to the time buffer this cycle. Used for 3835513SMichael.Adler@intel.com * the CPU to determine if it can deschedule itself if there is no activity. 3848706Sandreas.hansson@arm.com */ 3855513SMichael.Adler@intel.com bool wroteToTimeBuffer; 3865513SMichael.Adler@intel.com 3875513SMichael.Adler@intel.com /** Records if the number of ROB entries has changed this cycle. If it has, 3885513SMichael.Adler@intel.com * then the number of free entries must be re-broadcast. 38910203SAli.Saidi@ARM.com */ 39011851Sbrandon.potter@amd.com bool changedROBNumEntries[Impl::MaxThreads]; 39111851Sbrandon.potter@amd.com 39210203SAli.Saidi@ARM.com /** A counter of how many threads are currently squashing. */ 39310203SAli.Saidi@ARM.com ThreadID squashCounter; 39410203SAli.Saidi@ARM.com 3955513SMichael.Adler@intel.com /** Records if a thread has to squash this cycle due to a trap. */ 3965513SMichael.Adler@intel.com bool trapSquash[Impl::MaxThreads]; 39711851Sbrandon.potter@amd.com 39811851Sbrandon.potter@amd.com /** Records if a thread has to squash this cycle due to an XC write. */ 3995513SMichael.Adler@intel.com bool tcSquash[Impl::MaxThreads]; 4005513SMichael.Adler@intel.com 4015513SMichael.Adler@intel.com /** 4028852Sandreas.hansson@arm.com * Instruction passed to squashAfter(). 40310223Ssteve.reinhardt@amd.com * 4045513SMichael.Adler@intel.com * The squash after implementation needs to buffer the instruction 4055513SMichael.Adler@intel.com * that caused a squash since this needs to be passed to the fetch 4065513SMichael.Adler@intel.com * stage once squashing starts. 4075513SMichael.Adler@intel.com */ 40811906SBrandon.Potter@amd.com DynInstPtr squashAfterInst[Impl::MaxThreads]; 4096701Sgblack@eecs.umich.edu 4106701Sgblack@eecs.umich.edu /** Priority List used for Commit Policy */ 41111906SBrandon.Potter@amd.com std::list<ThreadID> priority_list; 4125513SMichael.Adler@intel.com 41310955Sdavid.hashe@amd.com /** IEW to Commit delay. */ 41410955Sdavid.hashe@amd.com Cycles iewToCommitDelay; 41510955Sdavid.hashe@amd.com 41610955Sdavid.hashe@amd.com /** Commit to IEW delay. */ 41711140Sjthestness@gmail.com Cycles commitToIEWDelay; 41811140Sjthestness@gmail.com 41911851Sbrandon.potter@amd.com /** Rename to ROB delay. */ 42011140Sjthestness@gmail.com Cycles renameToROBDelay; 42111140Sjthestness@gmail.com 42211140Sjthestness@gmail.com Cycles fetchToCommitDelay; 42311140Sjthestness@gmail.com 42411140Sjthestness@gmail.com /** Rename width, in instructions. Used so ROB knows how many 42511140Sjthestness@gmail.com * instructions to get from the rename instruction queue. 42611140Sjthestness@gmail.com */ 42711140Sjthestness@gmail.com unsigned renameWidth; 42811140Sjthestness@gmail.com 42911140Sjthestness@gmail.com /** Commit width, in instructions. */ 43011140Sjthestness@gmail.com unsigned commitWidth; 43111140Sjthestness@gmail.com 43211140Sjthestness@gmail.com /** Number of Reorder Buffers */ 43311140Sjthestness@gmail.com unsigned numRobs; 43411140Sjthestness@gmail.com 43511140Sjthestness@gmail.com /** Number of Active Threads */ 43611140Sjthestness@gmail.com ThreadID numThreads; 43711140Sjthestness@gmail.com 43810955Sdavid.hashe@amd.com /** Is a drain pending. */ 43910955Sdavid.hashe@amd.com bool drainPending; 44010955Sdavid.hashe@amd.com 44110955Sdavid.hashe@amd.com /** Is commit switched out. */ 44211140Sjthestness@gmail.com bool switchedOut; 44310955Sdavid.hashe@amd.com 44411140Sjthestness@gmail.com /** The latency to handle a trap. Used when scheduling trap 44511140Sjthestness@gmail.com * squash event. 44611140Sjthestness@gmail.com */ 44711140Sjthestness@gmail.com Cycles trapLatency; 44811140Sjthestness@gmail.com 44910955Sdavid.hashe@amd.com /** The interrupt fault. */ 4505513SMichael.Adler@intel.com Fault interrupt; 4518706Sandreas.hansson@arm.com 4525513SMichael.Adler@intel.com /** The commit PC state of each thread. Refers to the instruction that 4535513SMichael.Adler@intel.com * is currently being processed/committed. 4545513SMichael.Adler@intel.com */ 4555513SMichael.Adler@intel.com TheISA::PCState pc[Impl::MaxThreads]; 4565513SMichael.Adler@intel.com 45711851Sbrandon.potter@amd.com /** The sequence number of the youngest valid instruction in the ROB. */ 458511SN/A InstSeqNum youngestSeqNum[Impl::MaxThreads]; 45910633Smichaelupton@gmail.com 46010633Smichaelupton@gmail.com /** The sequence number of the last commited instruction. */ 46110633Smichaelupton@gmail.com InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 46210633Smichaelupton@gmail.com 46311851Sbrandon.potter@amd.com /** Records if there is a trap currently in flight. */ 46411851Sbrandon.potter@amd.com bool trapInFlight[Impl::MaxThreads]; 46510633Smichaelupton@gmail.com 4661706SN/A /** Records if there were any stores committed this cycle. */ 467360SN/A bool committedStores[Impl::MaxThreads]; 4688852Sandreas.hansson@arm.com 46910223Ssteve.reinhardt@amd.com /** Records if commit should check if the ROB is truly empty (see 470511SN/A commit_impl.hh). */ 4713669Sbinkertn@umich.edu bool checkEmptyROB[Impl::MaxThreads]; 4723669Sbinkertn@umich.edu 473511SN/A /** Pointer to the list of active threads. */ 4741458SN/A std::list<ThreadID> *activeThreads; 475511SN/A 476511SN/A /** Rename map interface. */ 47712795Smattdsinclair@gmail.com RenameMap *renameMap[Impl::MaxThreads]; 47812795Smattdsinclair@gmail.com 47912795Smattdsinclair@gmail.com /** True if last committed microop can be followed by an interrupt */ 48012795Smattdsinclair@gmail.com bool canHandleInterrupts; 48112795Smattdsinclair@gmail.com 48212795Smattdsinclair@gmail.com /** Updates commit stats based on this instruction. */ 48312795Smattdsinclair@gmail.com void updateComInstStats(DynInstPtr &inst); 48412795Smattdsinclair@gmail.com 48512795Smattdsinclair@gmail.com /** Stat for the total number of squashed instructions discarded by commit. 48612795Smattdsinclair@gmail.com */ 48712795Smattdsinclair@gmail.com Stats::Scalar commitSquashedInsts; 48812795Smattdsinclair@gmail.com /** Stat for the total number of times commit is told to squash. 48912795Smattdsinclair@gmail.com * @todo: Actually increment this stat. 49012795Smattdsinclair@gmail.com */ 49112795Smattdsinclair@gmail.com Stats::Scalar commitSquashEvents; 49212795Smattdsinclair@gmail.com /** Stat for the total number of times commit has had to stall due to a non- 49312795Smattdsinclair@gmail.com * speculative instruction reaching the head of the ROB. 49412795Smattdsinclair@gmail.com */ 49512795Smattdsinclair@gmail.com Stats::Scalar commitNonSpecStalls; 4965513SMichael.Adler@intel.com /** Stat for the total number of branch mispredicts that caused a squash. */ 4975513SMichael.Adler@intel.com Stats::Scalar branchMispredicts; 49812796Smattdsinclair@gmail.com /** Distribution of the number of committed instructions each cycle. */ 49912796Smattdsinclair@gmail.com Stats::Distribution numCommittedDist; 50012796Smattdsinclair@gmail.com 50112796Smattdsinclair@gmail.com /** Total number of instructions committed. */ 50212796Smattdsinclair@gmail.com Stats::Vector instsCommitted; 50312796Smattdsinclair@gmail.com /** Total number of ops (including micro ops) committed. */ 50412796Smattdsinclair@gmail.com Stats::Vector opsCommitted; 50512796Smattdsinclair@gmail.com /** Total number of software prefetches committed. */ 50612796Smattdsinclair@gmail.com Stats::Vector statComSwp; 50712796Smattdsinclair@gmail.com /** Stat for the total number of committed memory references. */ 50812796Smattdsinclair@gmail.com Stats::Vector statComRefs; 50912796Smattdsinclair@gmail.com /** Stat for the total number of committed loads. */ 51012796Smattdsinclair@gmail.com Stats::Vector statComLoads; 51112796Smattdsinclair@gmail.com /** Total number of committed memory barriers. */ 51212796Smattdsinclair@gmail.com Stats::Vector statComMembars; 51312796Smattdsinclair@gmail.com /** Total number of committed branches. */ 51412796Smattdsinclair@gmail.com Stats::Vector statComBranches; 51512796Smattdsinclair@gmail.com /** Total number of floating point instructions */ 51612796Smattdsinclair@gmail.com Stats::Vector statComFloating; 51712796Smattdsinclair@gmail.com /** Total number of integer instructions */ 51811851Sbrandon.potter@amd.com Stats::Vector statComInteger; 5195513SMichael.Adler@intel.com /** Total number of function calls */ 5205513SMichael.Adler@intel.com Stats::Vector statComFunctionCalls; 5215513SMichael.Adler@intel.com 5226701Sgblack@eecs.umich.edu /** Number of cycles where the commit bandwidth limit is reached. */ 5238852Sandreas.hansson@arm.com Stats::Scalar commitEligibleSamples; 52410223Ssteve.reinhardt@amd.com /** Number of instructions not committed due to bandwidth limits. */ 5255513SMichael.Adler@intel.com Stats::Vector commitEligible; 5265513SMichael.Adler@intel.com}; 5275513SMichael.Adler@intel.com 5285513SMichael.Adler@intel.com#endif // __CPU_O3_COMMIT_HH__ 5296701Sgblack@eecs.umich.edu