commit.hh revision 9180
11689SN/A/* 27855SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37855SAli.Saidi@ARM.com * All rights reserved. 47855SAli.Saidi@ARM.com * 57855SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67855SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77855SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87855SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97855SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107855SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117855SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127855SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137855SAli.Saidi@ARM.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_COMMIT_HH__ 452292SN/A#define __CPU_O3_COMMIT_HH__ 461060SN/A 478230Snate@binkert.org#include <queue> 488230Snate@binkert.org 491461SN/A#include "base/statistics.hh" 502292SN/A#include "cpu/exetrace.hh" 512329SN/A#include "cpu/inst_seq.hh" 528229Snate@binkert.org#include "cpu/timebuf.hh" 531060SN/A 548737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 555529Snate@binkert.org 562292SN/Atemplate <class> 578737Skoansin.tan@gmail.comstruct O3ThreadState; 582292SN/A 592292SN/A/** 602316SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 612316SN/A * specified by the parameters; each cycle it tries to commit that 622316SN/A * many instructions. The SMT policy decides which thread it tries to 632316SN/A * commit instructions from. Non- speculative instructions must reach 642316SN/A * the head of the ROB before they are ready to execute; once they 652316SN/A * reach the head, commit will broadcast the instruction's sequence 662316SN/A * number to the previous stages so that they can issue/ execute the 672316SN/A * instruction. Only one non-speculative instruction is handled per 682316SN/A * cycle. Commit is responsible for handling all back-end initiated 692316SN/A * redirects. It receives the redirect, and then broadcasts it to all 702316SN/A * stages, indicating the sequence number they should squash until, 712316SN/A * and any necessary branch misprediction information as well. It 722316SN/A * priortizes redirects by instruction's age, only broadcasting a 732316SN/A * redirect if it corresponds to an instruction that should currently 742316SN/A * be in the ROB. This is done by tracking the sequence number of the 752316SN/A * youngest instruction in the ROB, which gets updated to any 762316SN/A * squashing instruction's sequence number, and only broadcasting a 772316SN/A * redirect if it corresponds to an older instruction. Commit also 782316SN/A * supports multiple cycle squashing, to model a ROB that can only 792329SN/A * remove a certain number of instructions per cycle. 802292SN/A */ 811060SN/Atemplate<class Impl> 822292SN/Aclass DefaultCommit 831060SN/A{ 841060SN/A public: 851060SN/A // Typedefs from the Impl. 862733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 871061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 881061SN/A typedef typename Impl::CPUPol CPUPol; 891060SN/A 902292SN/A typedef typename CPUPol::RenameMap RenameMap; 911061SN/A typedef typename CPUPol::ROB ROB; 921060SN/A 931061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 942292SN/A typedef typename CPUPol::FetchStruct FetchStruct; 951061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 961061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 971060SN/A 982316SN/A typedef typename CPUPol::Fetch Fetch; 992292SN/A typedef typename CPUPol::IEW IEW; 1002292SN/A 1012292SN/A typedef O3ThreadState<Impl> Thread; 1022292SN/A 1032348SN/A /** Event class used to schedule a squash due to a trap (fault or 1042348SN/A * interrupt) to happen on a specific cycle. 1052348SN/A */ 1062292SN/A class TrapEvent : public Event { 1072292SN/A private: 1082292SN/A DefaultCommit<Impl> *commit; 1096221Snate@binkert.org ThreadID tid; 1102292SN/A 1112292SN/A public: 1126221Snate@binkert.org TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 1132292SN/A 1142292SN/A void process(); 1155336Shines@cs.fsu.edu const char *description() const; 1162292SN/A }; 1172292SN/A 1182292SN/A /** Overall commit status. Used to determine if the CPU can deschedule 1192292SN/A * itself due to a lack of activity. 1202292SN/A */ 1212292SN/A enum CommitStatus{ 1222292SN/A Active, 1232292SN/A Inactive 1242292SN/A }; 1252292SN/A 1262292SN/A /** Individual thread status. */ 1272292SN/A enum ThreadStatus { 1281060SN/A Running, 1291060SN/A Idle, 1301060SN/A ROBSquashing, 1312292SN/A TrapPending, 1322292SN/A FetchTrapPending 1332292SN/A }; 1342292SN/A 1352292SN/A /** Commit policy for SMT mode. */ 1362292SN/A enum CommitPolicy { 1372292SN/A Aggressive, 1382292SN/A RoundRobin, 1392292SN/A OldestReady 1401060SN/A }; 1411060SN/A 1421060SN/A private: 1432292SN/A /** Overall commit status. */ 1442292SN/A CommitStatus _status; 1452292SN/A /** Next commit status, to be set at the end of the cycle. */ 1462292SN/A CommitStatus _nextStatus; 1472292SN/A /** Per-thread status. */ 1482292SN/A ThreadStatus commitStatus[Impl::MaxThreads]; 1492292SN/A /** Commit policy used in SMT mode. */ 1502292SN/A CommitPolicy commitPolicy; 1511060SN/A 1521060SN/A public: 1532292SN/A /** Construct a DefaultCommit with the given parameters. */ 1545529Snate@binkert.org DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 1551060SN/A 1562292SN/A /** Returns the name of the DefaultCommit. */ 1572292SN/A std::string name() const; 1582292SN/A 1592292SN/A /** Registers statistics. */ 1601062SN/A void regStats(); 1611062SN/A 1622292SN/A /** Sets the list of threads. */ 1632292SN/A void setThreads(std::vector<Thread *> &threads); 1642292SN/A 1652292SN/A /** Sets the main time buffer pointer, used for backwards communication. */ 1661060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1671060SN/A 1682292SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1692292SN/A 1702292SN/A /** Sets the pointer to the queue coming from rename. */ 1711060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1721060SN/A 1732292SN/A /** Sets the pointer to the queue coming from IEW. */ 1741060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1751060SN/A 1762348SN/A /** Sets the pointer to the IEW stage. */ 1772292SN/A void setIEWStage(IEW *iew_stage); 1782292SN/A 1792965Sksewell@umich.edu /** Skid buffer between rename and commit. */ 1802965Sksewell@umich.edu std::queue<DynInstPtr> skidBuffer; 1812965Sksewell@umich.edu 1822316SN/A /** The pointer to the IEW stage. Used solely to ensure that 1832316SN/A * various events (traps, interrupts, syscalls) do not occur until 1842316SN/A * all stores have written back. 1852292SN/A */ 1862292SN/A IEW *iewStage; 1872292SN/A 1882292SN/A /** Sets pointer to list of active threads. */ 1896221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1902292SN/A 1912292SN/A /** Sets pointer to the commited state rename map. */ 1922292SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1932292SN/A 1942292SN/A /** Sets pointer to the ROB. */ 1951060SN/A void setROB(ROB *rob_ptr); 1961060SN/A 1972292SN/A /** Initializes stage by sending back the number of free entries. */ 1982292SN/A void initStage(); 1992292SN/A 2002843Sktlim@umich.edu /** Initializes the draining of commit. */ 2012863Sktlim@umich.edu bool drain(); 2022843Sktlim@umich.edu 2032843Sktlim@umich.edu /** Resumes execution after draining. */ 2042843Sktlim@umich.edu void resume(); 2052307SN/A 2062348SN/A /** Completes the switch out of commit. */ 2072843Sktlim@umich.edu void switchOut(); 2082316SN/A 2092348SN/A /** Takes over from another CPU's thread. */ 2102307SN/A void takeOverFrom(); 2112307SN/A 2122292SN/A /** Ticks the commit stage, which tries to commit instructions. */ 2131060SN/A void tick(); 2141060SN/A 2152292SN/A /** Handles any squashes that are sent from IEW, and adds instructions 2162292SN/A * to the ROB and tries to commit instructions. 2172292SN/A */ 2181060SN/A void commit(); 2191060SN/A 2202292SN/A /** Returns the number of free ROB entries for a specific thread. */ 2216221Snate@binkert.org size_t numROBFreeEntries(ThreadID tid); 2222292SN/A 2232348SN/A /** Generates an event to schedule a squash due to a trap. */ 2246221Snate@binkert.org void generateTrapEvent(ThreadID tid); 2252348SN/A 2262348SN/A /** Records that commit needs to initiate a squash due to an 2272680Sktlim@umich.edu * external state update through the TC. 2282348SN/A */ 2296221Snate@binkert.org void generateTCEvent(ThreadID tid); 2302292SN/A 2311060SN/A private: 2322292SN/A /** Updates the overall status of commit with the nextStatus, and 2332348SN/A * tell the CPU if commit is active/inactive. 2342348SN/A */ 2352292SN/A void updateStatus(); 2361060SN/A 2372292SN/A /** Sets the next status based on threads' statuses, which becomes the 2382292SN/A * current status at the end of the cycle. 2392292SN/A */ 2402292SN/A void setNextStatus(); 2412292SN/A 2422292SN/A /** Checks if the ROB is completed with squashing. This is for the case 2432292SN/A * where the ROB can take multiple cycles to complete squashing. 2442292SN/A */ 2452292SN/A bool robDoneSquashing(); 2462292SN/A 2472292SN/A /** Returns if any of the threads have the number of ROB entries changed 2482292SN/A * on this cycle. Used to determine if the number of free ROB entries needs 2492292SN/A * to be sent back to previous stages. 2502292SN/A */ 2512292SN/A bool changedROBEntries(); 2522292SN/A 2532348SN/A /** Squashes all in flight instructions. */ 2546221Snate@binkert.org void squashAll(ThreadID tid); 2552316SN/A 2562348SN/A /** Handles squashing due to a trap. */ 2576221Snate@binkert.org void squashFromTrap(ThreadID tid); 2582292SN/A 2592680Sktlim@umich.edu /** Handles squashing due to an TC write. */ 2606221Snate@binkert.org void squashFromTC(ThreadID tid); 2612292SN/A 2627784SAli.Saidi@ARM.com /** Handles squashing from instruction with SquashAfter set. 2637784SAli.Saidi@ARM.com * This differs from the other squashes as it squashes following 2647784SAli.Saidi@ARM.com * instructions instead of the current instruction and doesn't 2657784SAli.Saidi@ARM.com * clean up various status bits about traps/tc writes pending. 2667784SAli.Saidi@ARM.com */ 2678137SAli.Saidi@ARM.com void squashAfter(ThreadID tid, DynInstPtr &head_inst, 2688137SAli.Saidi@ARM.com uint64_t squash_after_seq_num); 2697784SAli.Saidi@ARM.com 2704035Sktlim@umich.edu /** Handles processing an interrupt. */ 2714035Sktlim@umich.edu void handleInterrupt(); 2727847Sminkyu.jeong@arm.com 2737847Sminkyu.jeong@arm.com /** Get fetch redirecting so we can handle an interrupt */ 2747847Sminkyu.jeong@arm.com void propagateInterrupt(); 2754035Sktlim@umich.edu 2762292SN/A /** Commits as many instructions as possible. */ 2771060SN/A void commitInsts(); 2781060SN/A 2792292SN/A /** Tries to commit the head ROB instruction passed in. 2802292SN/A * @param head_inst The instruction to be committed. 2812292SN/A */ 2821061SN/A bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 2831060SN/A 2842292SN/A /** Gets instructions from rename and inserts them into the ROB. */ 2851060SN/A void getInsts(); 2861060SN/A 2872965Sksewell@umich.edu /** Insert all instructions from rename into skidBuffer */ 2882965Sksewell@umich.edu void skidInsert(); 2892965Sksewell@umich.edu 2902292SN/A /** Marks completed instructions using information sent from IEW. */ 2911060SN/A void markCompletedInsts(); 2921060SN/A 2932292SN/A /** Gets the thread to commit, based on the SMT policy. */ 2946221Snate@binkert.org ThreadID getCommittingThread(); 2952292SN/A 2962292SN/A /** Returns the thread ID to use based on a round robin policy. */ 2976221Snate@binkert.org ThreadID roundRobin(); 2982292SN/A 2992292SN/A /** Returns the thread ID to use based on an oldest instruction policy. */ 3006221Snate@binkert.org ThreadID oldestReady(); 3012292SN/A 3021684SN/A public: 3037720Sgblack@eecs.umich.edu /** Reads the PC of a specific thread. */ 3047720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 3057720Sgblack@eecs.umich.edu 3067720Sgblack@eecs.umich.edu /** Sets the PC of a specific thread. */ 3077720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val, ThreadID tid) 3087720Sgblack@eecs.umich.edu { pc[tid] = val; } 3091684SN/A 3102348SN/A /** Returns the PC of a specific thread. */ 3117720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 3122292SN/A 3137720Sgblack@eecs.umich.edu /** Returns the next PC of a specific thread. */ 3147720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 3154636Sgblack@eecs.umich.edu 3164636Sgblack@eecs.umich.edu /** Reads the micro PC of a specific thread. */ 3177720Sgblack@eecs.umich.edu Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 3182756Sksewell@umich.edu 3191684SN/A private: 3201060SN/A /** Time buffer interface. */ 3211060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3221060SN/A 3231060SN/A /** Wire to write information heading to previous stages. */ 3241060SN/A typename TimeBuffer<TimeStruct>::wire toIEW; 3251060SN/A 3261060SN/A /** Wire to read information from IEW (for ROB). */ 3271060SN/A typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 3281060SN/A 3292292SN/A TimeBuffer<FetchStruct> *fetchQueue; 3302292SN/A 3312292SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 3322292SN/A 3331060SN/A /** IEW instruction queue interface. */ 3341060SN/A TimeBuffer<IEWStruct> *iewQueue; 3351060SN/A 3361060SN/A /** Wire to read information from IEW queue. */ 3371060SN/A typename TimeBuffer<IEWStruct>::wire fromIEW; 3381060SN/A 3391060SN/A /** Rename instruction queue interface, for ROB. */ 3401060SN/A TimeBuffer<RenameStruct> *renameQueue; 3411060SN/A 3421060SN/A /** Wire to read information from rename queue. */ 3431060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3441060SN/A 3452292SN/A public: 3461060SN/A /** ROB interface. */ 3471060SN/A ROB *rob; 3481060SN/A 3492292SN/A private: 3502733Sktlim@umich.edu /** Pointer to O3CPU. */ 3512733Sktlim@umich.edu O3CPU *cpu; 3521060SN/A 3532348SN/A /** Vector of all of the threads. */ 3542292SN/A std::vector<Thread *> thread; 3551060SN/A 3562292SN/A /** Records that commit has written to the time buffer this cycle. Used for 3572292SN/A * the CPU to determine if it can deschedule itself if there is no activity. 3582292SN/A */ 3592292SN/A bool wroteToTimeBuffer; 3602292SN/A 3612292SN/A /** Records if the number of ROB entries has changed this cycle. If it has, 3622292SN/A * then the number of free entries must be re-broadcast. 3632292SN/A */ 3642292SN/A bool changedROBNumEntries[Impl::MaxThreads]; 3652292SN/A 3662292SN/A /** A counter of how many threads are currently squashing. */ 3676221Snate@binkert.org ThreadID squashCounter; 3682292SN/A 3692292SN/A /** Records if a thread has to squash this cycle due to a trap. */ 3702292SN/A bool trapSquash[Impl::MaxThreads]; 3712292SN/A 3722292SN/A /** Records if a thread has to squash this cycle due to an XC write. */ 3732680Sktlim@umich.edu bool tcSquash[Impl::MaxThreads]; 3742292SN/A 3752292SN/A /** Priority List used for Commit Policy */ 3766221Snate@binkert.org std::list<ThreadID> priority_list; 3772292SN/A 3781060SN/A /** IEW to Commit delay, in ticks. */ 3791060SN/A unsigned iewToCommitDelay; 3801060SN/A 3812292SN/A /** Commit to IEW delay, in ticks. */ 3822292SN/A unsigned commitToIEWDelay; 3832292SN/A 3841060SN/A /** Rename to ROB delay, in ticks. */ 3851060SN/A unsigned renameToROBDelay; 3861060SN/A 3872292SN/A unsigned fetchToCommitDelay; 3882292SN/A 3891060SN/A /** Rename width, in instructions. Used so ROB knows how many 3901060SN/A * instructions to get from the rename instruction queue. 3911060SN/A */ 3921060SN/A unsigned renameWidth; 3931060SN/A 3941060SN/A /** Commit width, in instructions. */ 3951060SN/A unsigned commitWidth; 3961062SN/A 3972292SN/A /** Number of Reorder Buffers */ 3982292SN/A unsigned numRobs; 3992292SN/A 4002292SN/A /** Number of Active Threads */ 4016221Snate@binkert.org ThreadID numThreads; 4022292SN/A 4032843Sktlim@umich.edu /** Is a drain pending. */ 4042843Sktlim@umich.edu bool drainPending; 4052348SN/A 4062348SN/A /** Is commit switched out. */ 4072307SN/A bool switchedOut; 4082307SN/A 4092348SN/A /** The latency to handle a trap. Used when scheduling trap 4102348SN/A * squash event. 4112348SN/A */ 4129180Sandreas.hansson@arm.com Cycles trapLatency; 4132292SN/A 4143640Sktlim@umich.edu /** The interrupt fault. */ 4153640Sktlim@umich.edu Fault interrupt; 4163640Sktlim@umich.edu 4177720Sgblack@eecs.umich.edu /** The commit PC state of each thread. Refers to the instruction that 4182348SN/A * is currently being processed/committed. 4192348SN/A */ 4207720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4214636Sgblack@eecs.umich.edu 4222292SN/A /** The sequence number of the youngest valid instruction in the ROB. */ 4232292SN/A InstSeqNum youngestSeqNum[Impl::MaxThreads]; 4242292SN/A 4257855SAli.Saidi@ARM.com /** The sequence number of the last commited instruction. */ 4267855SAli.Saidi@ARM.com InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 4277855SAli.Saidi@ARM.com 4284035Sktlim@umich.edu /** Records if there is a trap currently in flight. */ 4294035Sktlim@umich.edu bool trapInFlight[Impl::MaxThreads]; 4304035Sktlim@umich.edu 4314035Sktlim@umich.edu /** Records if there were any stores committed this cycle. */ 4324035Sktlim@umich.edu bool committedStores[Impl::MaxThreads]; 4334035Sktlim@umich.edu 4344035Sktlim@umich.edu /** Records if commit should check if the ROB is truly empty (see 4354035Sktlim@umich.edu commit_impl.hh). */ 4364035Sktlim@umich.edu bool checkEmptyROB[Impl::MaxThreads]; 4374035Sktlim@umich.edu 4382292SN/A /** Pointer to the list of active threads. */ 4396221Snate@binkert.org std::list<ThreadID> *activeThreads; 4402292SN/A 4412292SN/A /** Rename map interface. */ 4422292SN/A RenameMap *renameMap[Impl::MaxThreads]; 4432292SN/A 4448823Snilay@cs.wisc.edu /** True if last committed microop can be followed by an interrupt */ 4458823Snilay@cs.wisc.edu bool canHandleInterrupts; 4468823Snilay@cs.wisc.edu 4472348SN/A /** Updates commit stats based on this instruction. */ 4482301SN/A void updateComInstStats(DynInstPtr &inst); 4492301SN/A 4502292SN/A /** Stat for the total number of committed instructions. */ 4515999Snate@binkert.org Stats::Scalar commitCommittedInsts; 4528834Satgutier@umich.edu /** Stat for the total number of committed ops. */ 4538834Satgutier@umich.edu Stats::Scalar commitCommittedOps; 4542292SN/A /** Stat for the total number of squashed instructions discarded by commit. 4552292SN/A */ 4565999Snate@binkert.org Stats::Scalar commitSquashedInsts; 4572292SN/A /** Stat for the total number of times commit is told to squash. 4582292SN/A * @todo: Actually increment this stat. 4592292SN/A */ 4605999Snate@binkert.org Stats::Scalar commitSquashEvents; 4612292SN/A /** Stat for the total number of times commit has had to stall due to a non- 4622292SN/A * speculative instruction reaching the head of the ROB. 4632292SN/A */ 4645999Snate@binkert.org Stats::Scalar commitNonSpecStalls; 4652292SN/A /** Stat for the total number of branch mispredicts that caused a squash. */ 4665999Snate@binkert.org Stats::Scalar branchMispredicts; 4672292SN/A /** Distribution of the number of committed instructions each cycle. */ 4685999Snate@binkert.org Stats::Distribution numCommittedDist; 4691062SN/A 4702316SN/A /** Total number of instructions committed. */ 4718834Satgutier@umich.edu Stats::Vector instsCommitted; 4728834Satgutier@umich.edu /** Total number of ops (including micro ops) committed. */ 4738834Satgutier@umich.edu Stats::Vector opsCommitted; 4742316SN/A /** Total number of software prefetches committed. */ 4755999Snate@binkert.org Stats::Vector statComSwp; 4762316SN/A /** Stat for the total number of committed memory references. */ 4775999Snate@binkert.org Stats::Vector statComRefs; 4782316SN/A /** Stat for the total number of committed loads. */ 4795999Snate@binkert.org Stats::Vector statComLoads; 4802316SN/A /** Total number of committed memory barriers. */ 4815999Snate@binkert.org Stats::Vector statComMembars; 4822316SN/A /** Total number of committed branches. */ 4835999Snate@binkert.org Stats::Vector statComBranches; 4847897Shestness@cs.utexas.edu /** Total number of floating point instructions */ 4857897Shestness@cs.utexas.edu Stats::Vector statComFloating; 4867897Shestness@cs.utexas.edu /** Total number of integer instructions */ 4877897Shestness@cs.utexas.edu Stats::Vector statComInteger; 4887897Shestness@cs.utexas.edu /** Total number of function calls */ 4897897Shestness@cs.utexas.edu Stats::Vector statComFunctionCalls; 4902301SN/A 4912348SN/A /** Number of cycles where the commit bandwidth limit is reached. */ 4925999Snate@binkert.org Stats::Scalar commitEligibleSamples; 4932348SN/A /** Number of instructions not committed due to bandwidth limits. */ 4945999Snate@binkert.org Stats::Vector commitEligible; 4951060SN/A}; 4961060SN/A 4972292SN/A#endif // __CPU_O3_COMMIT_HH__ 498