commit.hh revision 7855
11689SN/A/* 27855SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37855SAli.Saidi@ARM.com * All rights reserved. 47855SAli.Saidi@ARM.com * 57855SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67855SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77855SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87855SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97855SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107855SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117855SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127855SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137855SAli.Saidi@ARM.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_COMMIT_HH__ 452292SN/A#define __CPU_O3_COMMIT_HH__ 461060SN/A 471461SN/A#include "base/statistics.hh" 487813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 492292SN/A#include "cpu/exetrace.hh" 502329SN/A#include "cpu/inst_seq.hh" 511060SN/A 525529Snate@binkert.orgclass DerivO3CPUParams; 535529Snate@binkert.org 542292SN/Atemplate <class> 552292SN/Aclass O3ThreadState; 562292SN/A 572292SN/A/** 582316SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 592316SN/A * specified by the parameters; each cycle it tries to commit that 602316SN/A * many instructions. The SMT policy decides which thread it tries to 612316SN/A * commit instructions from. Non- speculative instructions must reach 622316SN/A * the head of the ROB before they are ready to execute; once they 632316SN/A * reach the head, commit will broadcast the instruction's sequence 642316SN/A * number to the previous stages so that they can issue/ execute the 652316SN/A * instruction. Only one non-speculative instruction is handled per 662316SN/A * cycle. Commit is responsible for handling all back-end initiated 672316SN/A * redirects. It receives the redirect, and then broadcasts it to all 682316SN/A * stages, indicating the sequence number they should squash until, 692316SN/A * and any necessary branch misprediction information as well. It 702316SN/A * priortizes redirects by instruction's age, only broadcasting a 712316SN/A * redirect if it corresponds to an instruction that should currently 722316SN/A * be in the ROB. This is done by tracking the sequence number of the 732316SN/A * youngest instruction in the ROB, which gets updated to any 742316SN/A * squashing instruction's sequence number, and only broadcasting a 752316SN/A * redirect if it corresponds to an older instruction. Commit also 762316SN/A * supports multiple cycle squashing, to model a ROB that can only 772329SN/A * remove a certain number of instructions per cycle. 782292SN/A */ 791060SN/Atemplate<class Impl> 802292SN/Aclass DefaultCommit 811060SN/A{ 821060SN/A public: 831060SN/A // Typedefs from the Impl. 842733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 851061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 861061SN/A typedef typename Impl::CPUPol CPUPol; 871060SN/A 882292SN/A typedef typename CPUPol::RenameMap RenameMap; 891061SN/A typedef typename CPUPol::ROB ROB; 901060SN/A 911061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 922292SN/A typedef typename CPUPol::FetchStruct FetchStruct; 931061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 941061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 951060SN/A 962316SN/A typedef typename CPUPol::Fetch Fetch; 972292SN/A typedef typename CPUPol::IEW IEW; 982292SN/A 992292SN/A typedef O3ThreadState<Impl> Thread; 1002292SN/A 1012348SN/A /** Event class used to schedule a squash due to a trap (fault or 1022348SN/A * interrupt) to happen on a specific cycle. 1032348SN/A */ 1042292SN/A class TrapEvent : public Event { 1052292SN/A private: 1062292SN/A DefaultCommit<Impl> *commit; 1076221Snate@binkert.org ThreadID tid; 1082292SN/A 1092292SN/A public: 1106221Snate@binkert.org TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 1112292SN/A 1122292SN/A void process(); 1135336Shines@cs.fsu.edu const char *description() const; 1142292SN/A }; 1152292SN/A 1162292SN/A /** Overall commit status. Used to determine if the CPU can deschedule 1172292SN/A * itself due to a lack of activity. 1182292SN/A */ 1192292SN/A enum CommitStatus{ 1202292SN/A Active, 1212292SN/A Inactive 1222292SN/A }; 1232292SN/A 1242292SN/A /** Individual thread status. */ 1252292SN/A enum ThreadStatus { 1261060SN/A Running, 1271060SN/A Idle, 1281060SN/A ROBSquashing, 1292292SN/A TrapPending, 1302292SN/A FetchTrapPending 1312292SN/A }; 1322292SN/A 1332292SN/A /** Commit policy for SMT mode. */ 1342292SN/A enum CommitPolicy { 1352292SN/A Aggressive, 1362292SN/A RoundRobin, 1372292SN/A OldestReady 1381060SN/A }; 1391060SN/A 1401060SN/A private: 1412292SN/A /** Overall commit status. */ 1422292SN/A CommitStatus _status; 1432292SN/A /** Next commit status, to be set at the end of the cycle. */ 1442292SN/A CommitStatus _nextStatus; 1452292SN/A /** Per-thread status. */ 1462292SN/A ThreadStatus commitStatus[Impl::MaxThreads]; 1472292SN/A /** Commit policy used in SMT mode. */ 1482292SN/A CommitPolicy commitPolicy; 1491060SN/A 1501060SN/A public: 1512292SN/A /** Construct a DefaultCommit with the given parameters. */ 1525529Snate@binkert.org DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 1531060SN/A 1542292SN/A /** Returns the name of the DefaultCommit. */ 1552292SN/A std::string name() const; 1562292SN/A 1572292SN/A /** Registers statistics. */ 1581062SN/A void regStats(); 1591062SN/A 1602292SN/A /** Sets the list of threads. */ 1612292SN/A void setThreads(std::vector<Thread *> &threads); 1622292SN/A 1632292SN/A /** Sets the main time buffer pointer, used for backwards communication. */ 1641060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1651060SN/A 1662292SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1672292SN/A 1682292SN/A /** Sets the pointer to the queue coming from rename. */ 1691060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1701060SN/A 1712292SN/A /** Sets the pointer to the queue coming from IEW. */ 1721060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1731060SN/A 1742348SN/A /** Sets the pointer to the IEW stage. */ 1752292SN/A void setIEWStage(IEW *iew_stage); 1762292SN/A 1772965Sksewell@umich.edu /** Skid buffer between rename and commit. */ 1782965Sksewell@umich.edu std::queue<DynInstPtr> skidBuffer; 1792965Sksewell@umich.edu 1802316SN/A /** The pointer to the IEW stage. Used solely to ensure that 1812316SN/A * various events (traps, interrupts, syscalls) do not occur until 1822316SN/A * all stores have written back. 1832292SN/A */ 1842292SN/A IEW *iewStage; 1852292SN/A 1862292SN/A /** Sets pointer to list of active threads. */ 1876221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1882292SN/A 1892292SN/A /** Sets pointer to the commited state rename map. */ 1902292SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1912292SN/A 1922292SN/A /** Sets pointer to the ROB. */ 1931060SN/A void setROB(ROB *rob_ptr); 1941060SN/A 1952292SN/A /** Initializes stage by sending back the number of free entries. */ 1962292SN/A void initStage(); 1972292SN/A 1982843Sktlim@umich.edu /** Initializes the draining of commit. */ 1992863Sktlim@umich.edu bool drain(); 2002843Sktlim@umich.edu 2012843Sktlim@umich.edu /** Resumes execution after draining. */ 2022843Sktlim@umich.edu void resume(); 2032307SN/A 2042348SN/A /** Completes the switch out of commit. */ 2052843Sktlim@umich.edu void switchOut(); 2062316SN/A 2072348SN/A /** Takes over from another CPU's thread. */ 2082307SN/A void takeOverFrom(); 2092307SN/A 2102292SN/A /** Ticks the commit stage, which tries to commit instructions. */ 2111060SN/A void tick(); 2121060SN/A 2132292SN/A /** Handles any squashes that are sent from IEW, and adds instructions 2142292SN/A * to the ROB and tries to commit instructions. 2152292SN/A */ 2161060SN/A void commit(); 2171060SN/A 2182292SN/A /** Returns the number of free ROB entries for a specific thread. */ 2196221Snate@binkert.org size_t numROBFreeEntries(ThreadID tid); 2202292SN/A 2212348SN/A /** Generates an event to schedule a squash due to a trap. */ 2226221Snate@binkert.org void generateTrapEvent(ThreadID tid); 2232348SN/A 2242348SN/A /** Records that commit needs to initiate a squash due to an 2252680Sktlim@umich.edu * external state update through the TC. 2262348SN/A */ 2276221Snate@binkert.org void generateTCEvent(ThreadID tid); 2282292SN/A 2291060SN/A private: 2302292SN/A /** Updates the overall status of commit with the nextStatus, and 2312348SN/A * tell the CPU if commit is active/inactive. 2322348SN/A */ 2332292SN/A void updateStatus(); 2341060SN/A 2352292SN/A /** Sets the next status based on threads' statuses, which becomes the 2362292SN/A * current status at the end of the cycle. 2372292SN/A */ 2382292SN/A void setNextStatus(); 2392292SN/A 2402292SN/A /** Checks if the ROB is completed with squashing. This is for the case 2412292SN/A * where the ROB can take multiple cycles to complete squashing. 2422292SN/A */ 2432292SN/A bool robDoneSquashing(); 2442292SN/A 2452292SN/A /** Returns if any of the threads have the number of ROB entries changed 2462292SN/A * on this cycle. Used to determine if the number of free ROB entries needs 2472292SN/A * to be sent back to previous stages. 2482292SN/A */ 2492292SN/A bool changedROBEntries(); 2502292SN/A 2512348SN/A /** Squashes all in flight instructions. */ 2526221Snate@binkert.org void squashAll(ThreadID tid); 2532316SN/A 2542348SN/A /** Handles squashing due to a trap. */ 2556221Snate@binkert.org void squashFromTrap(ThreadID tid); 2562292SN/A 2572680Sktlim@umich.edu /** Handles squashing due to an TC write. */ 2586221Snate@binkert.org void squashFromTC(ThreadID tid); 2592292SN/A 2607784SAli.Saidi@ARM.com /** Handles squashing from instruction with SquashAfter set. 2617784SAli.Saidi@ARM.com * This differs from the other squashes as it squashes following 2627784SAli.Saidi@ARM.com * instructions instead of the current instruction and doesn't 2637784SAli.Saidi@ARM.com * clean up various status bits about traps/tc writes pending. 2647784SAli.Saidi@ARM.com */ 2657784SAli.Saidi@ARM.com void squashAfter(ThreadID tid, uint64_t squash_after_seq_num); 2667784SAli.Saidi@ARM.com 2674035Sktlim@umich.edu#if FULL_SYSTEM 2684035Sktlim@umich.edu /** Handles processing an interrupt. */ 2694035Sktlim@umich.edu void handleInterrupt(); 2707847Sminkyu.jeong@arm.com 2717847Sminkyu.jeong@arm.com /** Get fetch redirecting so we can handle an interrupt */ 2727847Sminkyu.jeong@arm.com void propagateInterrupt(); 2734035Sktlim@umich.edu#endif // FULL_SYSTEM 2744035Sktlim@umich.edu 2752292SN/A /** Commits as many instructions as possible. */ 2761060SN/A void commitInsts(); 2771060SN/A 2782292SN/A /** Tries to commit the head ROB instruction passed in. 2792292SN/A * @param head_inst The instruction to be committed. 2802292SN/A */ 2811061SN/A bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 2821060SN/A 2832292SN/A /** Gets instructions from rename and inserts them into the ROB. */ 2841060SN/A void getInsts(); 2851060SN/A 2862965Sksewell@umich.edu /** Insert all instructions from rename into skidBuffer */ 2872965Sksewell@umich.edu void skidInsert(); 2882965Sksewell@umich.edu 2892292SN/A /** Marks completed instructions using information sent from IEW. */ 2901060SN/A void markCompletedInsts(); 2911060SN/A 2922292SN/A /** Gets the thread to commit, based on the SMT policy. */ 2936221Snate@binkert.org ThreadID getCommittingThread(); 2942292SN/A 2952292SN/A /** Returns the thread ID to use based on a round robin policy. */ 2966221Snate@binkert.org ThreadID roundRobin(); 2972292SN/A 2982292SN/A /** Returns the thread ID to use based on an oldest instruction policy. */ 2996221Snate@binkert.org ThreadID oldestReady(); 3002292SN/A 3011684SN/A public: 3027720Sgblack@eecs.umich.edu /** Reads the PC of a specific thread. */ 3037720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 3047720Sgblack@eecs.umich.edu 3057720Sgblack@eecs.umich.edu /** Sets the PC of a specific thread. */ 3067720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val, ThreadID tid) 3077720Sgblack@eecs.umich.edu { pc[tid] = val; } 3081684SN/A 3092348SN/A /** Returns the PC of a specific thread. */ 3107720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 3112292SN/A 3127720Sgblack@eecs.umich.edu /** Returns the next PC of a specific thread. */ 3137720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 3144636Sgblack@eecs.umich.edu 3154636Sgblack@eecs.umich.edu /** Reads the micro PC of a specific thread. */ 3167720Sgblack@eecs.umich.edu Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 3172756Sksewell@umich.edu 3181684SN/A private: 3191060SN/A /** Time buffer interface. */ 3201060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3211060SN/A 3221060SN/A /** Wire to write information heading to previous stages. */ 3231060SN/A typename TimeBuffer<TimeStruct>::wire toIEW; 3241060SN/A 3251060SN/A /** Wire to read information from IEW (for ROB). */ 3261060SN/A typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 3271060SN/A 3282292SN/A TimeBuffer<FetchStruct> *fetchQueue; 3292292SN/A 3302292SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 3312292SN/A 3321060SN/A /** IEW instruction queue interface. */ 3331060SN/A TimeBuffer<IEWStruct> *iewQueue; 3341060SN/A 3351060SN/A /** Wire to read information from IEW queue. */ 3361060SN/A typename TimeBuffer<IEWStruct>::wire fromIEW; 3371060SN/A 3381060SN/A /** Rename instruction queue interface, for ROB. */ 3391060SN/A TimeBuffer<RenameStruct> *renameQueue; 3401060SN/A 3411060SN/A /** Wire to read information from rename queue. */ 3421060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3431060SN/A 3442292SN/A public: 3451060SN/A /** ROB interface. */ 3461060SN/A ROB *rob; 3471060SN/A 3482292SN/A private: 3492733Sktlim@umich.edu /** Pointer to O3CPU. */ 3502733Sktlim@umich.edu O3CPU *cpu; 3511060SN/A 3522348SN/A /** Vector of all of the threads. */ 3532292SN/A std::vector<Thread *> thread; 3541060SN/A 3552292SN/A /** Records that commit has written to the time buffer this cycle. Used for 3562292SN/A * the CPU to determine if it can deschedule itself if there is no activity. 3572292SN/A */ 3582292SN/A bool wroteToTimeBuffer; 3592292SN/A 3602292SN/A /** Records if the number of ROB entries has changed this cycle. If it has, 3612292SN/A * then the number of free entries must be re-broadcast. 3622292SN/A */ 3632292SN/A bool changedROBNumEntries[Impl::MaxThreads]; 3642292SN/A 3652292SN/A /** A counter of how many threads are currently squashing. */ 3666221Snate@binkert.org ThreadID squashCounter; 3672292SN/A 3682292SN/A /** Records if a thread has to squash this cycle due to a trap. */ 3692292SN/A bool trapSquash[Impl::MaxThreads]; 3702292SN/A 3712292SN/A /** Records if a thread has to squash this cycle due to an XC write. */ 3722680Sktlim@umich.edu bool tcSquash[Impl::MaxThreads]; 3732292SN/A 3742292SN/A /** Priority List used for Commit Policy */ 3756221Snate@binkert.org std::list<ThreadID> priority_list; 3762292SN/A 3771060SN/A /** IEW to Commit delay, in ticks. */ 3781060SN/A unsigned iewToCommitDelay; 3791060SN/A 3802292SN/A /** Commit to IEW delay, in ticks. */ 3812292SN/A unsigned commitToIEWDelay; 3822292SN/A 3831060SN/A /** Rename to ROB delay, in ticks. */ 3841060SN/A unsigned renameToROBDelay; 3851060SN/A 3862292SN/A unsigned fetchToCommitDelay; 3872292SN/A 3881060SN/A /** Rename width, in instructions. Used so ROB knows how many 3891060SN/A * instructions to get from the rename instruction queue. 3901060SN/A */ 3911060SN/A unsigned renameWidth; 3921060SN/A 3931060SN/A /** Commit width, in instructions. */ 3941060SN/A unsigned commitWidth; 3951062SN/A 3962292SN/A /** Number of Reorder Buffers */ 3972292SN/A unsigned numRobs; 3982292SN/A 3992292SN/A /** Number of Active Threads */ 4006221Snate@binkert.org ThreadID numThreads; 4012292SN/A 4022843Sktlim@umich.edu /** Is a drain pending. */ 4032843Sktlim@umich.edu bool drainPending; 4042348SN/A 4052348SN/A /** Is commit switched out. */ 4062307SN/A bool switchedOut; 4072307SN/A 4082348SN/A /** The latency to handle a trap. Used when scheduling trap 4092348SN/A * squash event. 4102348SN/A */ 4112292SN/A Tick trapLatency; 4122292SN/A 4133640Sktlim@umich.edu /** The interrupt fault. */ 4143640Sktlim@umich.edu Fault interrupt; 4153640Sktlim@umich.edu 4167720Sgblack@eecs.umich.edu /** The commit PC state of each thread. Refers to the instruction that 4172348SN/A * is currently being processed/committed. 4182348SN/A */ 4197720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4204636Sgblack@eecs.umich.edu 4212292SN/A /** The sequence number of the youngest valid instruction in the ROB. */ 4222292SN/A InstSeqNum youngestSeqNum[Impl::MaxThreads]; 4232292SN/A 4247855SAli.Saidi@ARM.com /** The sequence number of the last commited instruction. */ 4257855SAli.Saidi@ARM.com InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 4267855SAli.Saidi@ARM.com 4274035Sktlim@umich.edu /** Records if there is a trap currently in flight. */ 4284035Sktlim@umich.edu bool trapInFlight[Impl::MaxThreads]; 4294035Sktlim@umich.edu 4304035Sktlim@umich.edu /** Records if there were any stores committed this cycle. */ 4314035Sktlim@umich.edu bool committedStores[Impl::MaxThreads]; 4324035Sktlim@umich.edu 4334035Sktlim@umich.edu /** Records if commit should check if the ROB is truly empty (see 4344035Sktlim@umich.edu commit_impl.hh). */ 4354035Sktlim@umich.edu bool checkEmptyROB[Impl::MaxThreads]; 4364035Sktlim@umich.edu 4372292SN/A /** Pointer to the list of active threads. */ 4386221Snate@binkert.org std::list<ThreadID> *activeThreads; 4392292SN/A 4402292SN/A /** Rename map interface. */ 4412292SN/A RenameMap *renameMap[Impl::MaxThreads]; 4422292SN/A 4432348SN/A /** Updates commit stats based on this instruction. */ 4442301SN/A void updateComInstStats(DynInstPtr &inst); 4452301SN/A 4462292SN/A /** Stat for the total number of committed instructions. */ 4475999Snate@binkert.org Stats::Scalar commitCommittedInsts; 4482292SN/A /** Stat for the total number of squashed instructions discarded by commit. 4492292SN/A */ 4505999Snate@binkert.org Stats::Scalar commitSquashedInsts; 4512292SN/A /** Stat for the total number of times commit is told to squash. 4522292SN/A * @todo: Actually increment this stat. 4532292SN/A */ 4545999Snate@binkert.org Stats::Scalar commitSquashEvents; 4552292SN/A /** Stat for the total number of times commit has had to stall due to a non- 4562292SN/A * speculative instruction reaching the head of the ROB. 4572292SN/A */ 4585999Snate@binkert.org Stats::Scalar commitNonSpecStalls; 4592292SN/A /** Stat for the total number of branch mispredicts that caused a squash. */ 4605999Snate@binkert.org Stats::Scalar branchMispredicts; 4612292SN/A /** Distribution of the number of committed instructions each cycle. */ 4625999Snate@binkert.org Stats::Distribution numCommittedDist; 4631062SN/A 4642316SN/A /** Total number of instructions committed. */ 4655999Snate@binkert.org Stats::Vector statComInst; 4662316SN/A /** Total number of software prefetches committed. */ 4675999Snate@binkert.org Stats::Vector statComSwp; 4682316SN/A /** Stat for the total number of committed memory references. */ 4695999Snate@binkert.org Stats::Vector statComRefs; 4702316SN/A /** Stat for the total number of committed loads. */ 4715999Snate@binkert.org Stats::Vector statComLoads; 4722316SN/A /** Total number of committed memory barriers. */ 4735999Snate@binkert.org Stats::Vector statComMembars; 4742316SN/A /** Total number of committed branches. */ 4755999Snate@binkert.org Stats::Vector statComBranches; 4762301SN/A 4772348SN/A /** Number of cycles where the commit bandwidth limit is reached. */ 4785999Snate@binkert.org Stats::Scalar commitEligibleSamples; 4792348SN/A /** Number of instructions not committed due to bandwidth limits. */ 4805999Snate@binkert.org Stats::Vector commitEligible; 4811060SN/A}; 4821060SN/A 4832292SN/A#endif // __CPU_O3_COMMIT_HH__ 484