commit.hh revision 7847
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_COMMIT_HH__ 332292SN/A#define __CPU_O3_COMMIT_HH__ 341060SN/A 351461SN/A#include "base/statistics.hh" 367813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 372292SN/A#include "cpu/exetrace.hh" 382329SN/A#include "cpu/inst_seq.hh" 391060SN/A 405529Snate@binkert.orgclass DerivO3CPUParams; 415529Snate@binkert.org 422292SN/Atemplate <class> 432292SN/Aclass O3ThreadState; 442292SN/A 452292SN/A/** 462316SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 472316SN/A * specified by the parameters; each cycle it tries to commit that 482316SN/A * many instructions. The SMT policy decides which thread it tries to 492316SN/A * commit instructions from. Non- speculative instructions must reach 502316SN/A * the head of the ROB before they are ready to execute; once they 512316SN/A * reach the head, commit will broadcast the instruction's sequence 522316SN/A * number to the previous stages so that they can issue/ execute the 532316SN/A * instruction. Only one non-speculative instruction is handled per 542316SN/A * cycle. Commit is responsible for handling all back-end initiated 552316SN/A * redirects. It receives the redirect, and then broadcasts it to all 562316SN/A * stages, indicating the sequence number they should squash until, 572316SN/A * and any necessary branch misprediction information as well. It 582316SN/A * priortizes redirects by instruction's age, only broadcasting a 592316SN/A * redirect if it corresponds to an instruction that should currently 602316SN/A * be in the ROB. This is done by tracking the sequence number of the 612316SN/A * youngest instruction in the ROB, which gets updated to any 622316SN/A * squashing instruction's sequence number, and only broadcasting a 632316SN/A * redirect if it corresponds to an older instruction. Commit also 642316SN/A * supports multiple cycle squashing, to model a ROB that can only 652329SN/A * remove a certain number of instructions per cycle. 662292SN/A */ 671060SN/Atemplate<class Impl> 682292SN/Aclass DefaultCommit 691060SN/A{ 701060SN/A public: 711060SN/A // Typedefs from the Impl. 722733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 731061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 741061SN/A typedef typename Impl::CPUPol CPUPol; 751060SN/A 762292SN/A typedef typename CPUPol::RenameMap RenameMap; 771061SN/A typedef typename CPUPol::ROB ROB; 781060SN/A 791061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 802292SN/A typedef typename CPUPol::FetchStruct FetchStruct; 811061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 821061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 831060SN/A 842316SN/A typedef typename CPUPol::Fetch Fetch; 852292SN/A typedef typename CPUPol::IEW IEW; 862292SN/A 872292SN/A typedef O3ThreadState<Impl> Thread; 882292SN/A 892348SN/A /** Event class used to schedule a squash due to a trap (fault or 902348SN/A * interrupt) to happen on a specific cycle. 912348SN/A */ 922292SN/A class TrapEvent : public Event { 932292SN/A private: 942292SN/A DefaultCommit<Impl> *commit; 956221Snate@binkert.org ThreadID tid; 962292SN/A 972292SN/A public: 986221Snate@binkert.org TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 992292SN/A 1002292SN/A void process(); 1015336Shines@cs.fsu.edu const char *description() const; 1022292SN/A }; 1032292SN/A 1042292SN/A /** Overall commit status. Used to determine if the CPU can deschedule 1052292SN/A * itself due to a lack of activity. 1062292SN/A */ 1072292SN/A enum CommitStatus{ 1082292SN/A Active, 1092292SN/A Inactive 1102292SN/A }; 1112292SN/A 1122292SN/A /** Individual thread status. */ 1132292SN/A enum ThreadStatus { 1141060SN/A Running, 1151060SN/A Idle, 1161060SN/A ROBSquashing, 1172292SN/A TrapPending, 1182292SN/A FetchTrapPending 1192292SN/A }; 1202292SN/A 1212292SN/A /** Commit policy for SMT mode. */ 1222292SN/A enum CommitPolicy { 1232292SN/A Aggressive, 1242292SN/A RoundRobin, 1252292SN/A OldestReady 1261060SN/A }; 1271060SN/A 1281060SN/A private: 1292292SN/A /** Overall commit status. */ 1302292SN/A CommitStatus _status; 1312292SN/A /** Next commit status, to be set at the end of the cycle. */ 1322292SN/A CommitStatus _nextStatus; 1332292SN/A /** Per-thread status. */ 1342292SN/A ThreadStatus commitStatus[Impl::MaxThreads]; 1352292SN/A /** Commit policy used in SMT mode. */ 1362292SN/A CommitPolicy commitPolicy; 1371060SN/A 1381060SN/A public: 1392292SN/A /** Construct a DefaultCommit with the given parameters. */ 1405529Snate@binkert.org DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 1411060SN/A 1422292SN/A /** Returns the name of the DefaultCommit. */ 1432292SN/A std::string name() const; 1442292SN/A 1452292SN/A /** Registers statistics. */ 1461062SN/A void regStats(); 1471062SN/A 1482292SN/A /** Sets the list of threads. */ 1492292SN/A void setThreads(std::vector<Thread *> &threads); 1502292SN/A 1512292SN/A /** Sets the main time buffer pointer, used for backwards communication. */ 1521060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1531060SN/A 1542292SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1552292SN/A 1562292SN/A /** Sets the pointer to the queue coming from rename. */ 1571060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1581060SN/A 1592292SN/A /** Sets the pointer to the queue coming from IEW. */ 1601060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1611060SN/A 1622348SN/A /** Sets the pointer to the IEW stage. */ 1632292SN/A void setIEWStage(IEW *iew_stage); 1642292SN/A 1652965Sksewell@umich.edu /** Skid buffer between rename and commit. */ 1662965Sksewell@umich.edu std::queue<DynInstPtr> skidBuffer; 1672965Sksewell@umich.edu 1682316SN/A /** The pointer to the IEW stage. Used solely to ensure that 1692316SN/A * various events (traps, interrupts, syscalls) do not occur until 1702316SN/A * all stores have written back. 1712292SN/A */ 1722292SN/A IEW *iewStage; 1732292SN/A 1742292SN/A /** Sets pointer to list of active threads. */ 1756221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1762292SN/A 1772292SN/A /** Sets pointer to the commited state rename map. */ 1782292SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1792292SN/A 1802292SN/A /** Sets pointer to the ROB. */ 1811060SN/A void setROB(ROB *rob_ptr); 1821060SN/A 1832292SN/A /** Initializes stage by sending back the number of free entries. */ 1842292SN/A void initStage(); 1852292SN/A 1862843Sktlim@umich.edu /** Initializes the draining of commit. */ 1872863Sktlim@umich.edu bool drain(); 1882843Sktlim@umich.edu 1892843Sktlim@umich.edu /** Resumes execution after draining. */ 1902843Sktlim@umich.edu void resume(); 1912307SN/A 1922348SN/A /** Completes the switch out of commit. */ 1932843Sktlim@umich.edu void switchOut(); 1942316SN/A 1952348SN/A /** Takes over from another CPU's thread. */ 1962307SN/A void takeOverFrom(); 1972307SN/A 1982292SN/A /** Ticks the commit stage, which tries to commit instructions. */ 1991060SN/A void tick(); 2001060SN/A 2012292SN/A /** Handles any squashes that are sent from IEW, and adds instructions 2022292SN/A * to the ROB and tries to commit instructions. 2032292SN/A */ 2041060SN/A void commit(); 2051060SN/A 2062292SN/A /** Returns the number of free ROB entries for a specific thread. */ 2076221Snate@binkert.org size_t numROBFreeEntries(ThreadID tid); 2082292SN/A 2092348SN/A /** Generates an event to schedule a squash due to a trap. */ 2106221Snate@binkert.org void generateTrapEvent(ThreadID tid); 2112348SN/A 2122348SN/A /** Records that commit needs to initiate a squash due to an 2132680Sktlim@umich.edu * external state update through the TC. 2142348SN/A */ 2156221Snate@binkert.org void generateTCEvent(ThreadID tid); 2162292SN/A 2171060SN/A private: 2182292SN/A /** Updates the overall status of commit with the nextStatus, and 2192348SN/A * tell the CPU if commit is active/inactive. 2202348SN/A */ 2212292SN/A void updateStatus(); 2221060SN/A 2232292SN/A /** Sets the next status based on threads' statuses, which becomes the 2242292SN/A * current status at the end of the cycle. 2252292SN/A */ 2262292SN/A void setNextStatus(); 2272292SN/A 2282292SN/A /** Checks if the ROB is completed with squashing. This is for the case 2292292SN/A * where the ROB can take multiple cycles to complete squashing. 2302292SN/A */ 2312292SN/A bool robDoneSquashing(); 2322292SN/A 2332292SN/A /** Returns if any of the threads have the number of ROB entries changed 2342292SN/A * on this cycle. Used to determine if the number of free ROB entries needs 2352292SN/A * to be sent back to previous stages. 2362292SN/A */ 2372292SN/A bool changedROBEntries(); 2382292SN/A 2392348SN/A /** Squashes all in flight instructions. */ 2406221Snate@binkert.org void squashAll(ThreadID tid); 2412316SN/A 2422348SN/A /** Handles squashing due to a trap. */ 2436221Snate@binkert.org void squashFromTrap(ThreadID tid); 2442292SN/A 2452680Sktlim@umich.edu /** Handles squashing due to an TC write. */ 2466221Snate@binkert.org void squashFromTC(ThreadID tid); 2472292SN/A 2487784SAli.Saidi@ARM.com /** Handles squashing from instruction with SquashAfter set. 2497784SAli.Saidi@ARM.com * This differs from the other squashes as it squashes following 2507784SAli.Saidi@ARM.com * instructions instead of the current instruction and doesn't 2517784SAli.Saidi@ARM.com * clean up various status bits about traps/tc writes pending. 2527784SAli.Saidi@ARM.com */ 2537784SAli.Saidi@ARM.com void squashAfter(ThreadID tid, uint64_t squash_after_seq_num); 2547784SAli.Saidi@ARM.com 2554035Sktlim@umich.edu#if FULL_SYSTEM 2564035Sktlim@umich.edu /** Handles processing an interrupt. */ 2574035Sktlim@umich.edu void handleInterrupt(); 2587847Sminkyu.jeong@arm.com 2597847Sminkyu.jeong@arm.com /** Get fetch redirecting so we can handle an interrupt */ 2607847Sminkyu.jeong@arm.com void propagateInterrupt(); 2614035Sktlim@umich.edu#endif // FULL_SYSTEM 2624035Sktlim@umich.edu 2632292SN/A /** Commits as many instructions as possible. */ 2641060SN/A void commitInsts(); 2651060SN/A 2662292SN/A /** Tries to commit the head ROB instruction passed in. 2672292SN/A * @param head_inst The instruction to be committed. 2682292SN/A */ 2691061SN/A bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 2701060SN/A 2712292SN/A /** Gets instructions from rename and inserts them into the ROB. */ 2721060SN/A void getInsts(); 2731060SN/A 2742965Sksewell@umich.edu /** Insert all instructions from rename into skidBuffer */ 2752965Sksewell@umich.edu void skidInsert(); 2762965Sksewell@umich.edu 2772292SN/A /** Marks completed instructions using information sent from IEW. */ 2781060SN/A void markCompletedInsts(); 2791060SN/A 2802292SN/A /** Gets the thread to commit, based on the SMT policy. */ 2816221Snate@binkert.org ThreadID getCommittingThread(); 2822292SN/A 2832292SN/A /** Returns the thread ID to use based on a round robin policy. */ 2846221Snate@binkert.org ThreadID roundRobin(); 2852292SN/A 2862292SN/A /** Returns the thread ID to use based on an oldest instruction policy. */ 2876221Snate@binkert.org ThreadID oldestReady(); 2882292SN/A 2891684SN/A public: 2907720Sgblack@eecs.umich.edu /** Reads the PC of a specific thread. */ 2917720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 2927720Sgblack@eecs.umich.edu 2937720Sgblack@eecs.umich.edu /** Sets the PC of a specific thread. */ 2947720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val, ThreadID tid) 2957720Sgblack@eecs.umich.edu { pc[tid] = val; } 2961684SN/A 2972348SN/A /** Returns the PC of a specific thread. */ 2987720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 2992292SN/A 3007720Sgblack@eecs.umich.edu /** Returns the next PC of a specific thread. */ 3017720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 3024636Sgblack@eecs.umich.edu 3034636Sgblack@eecs.umich.edu /** Reads the micro PC of a specific thread. */ 3047720Sgblack@eecs.umich.edu Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 3052756Sksewell@umich.edu 3061684SN/A private: 3071060SN/A /** Time buffer interface. */ 3081060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3091060SN/A 3101060SN/A /** Wire to write information heading to previous stages. */ 3111060SN/A typename TimeBuffer<TimeStruct>::wire toIEW; 3121060SN/A 3131060SN/A /** Wire to read information from IEW (for ROB). */ 3141060SN/A typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 3151060SN/A 3162292SN/A TimeBuffer<FetchStruct> *fetchQueue; 3172292SN/A 3182292SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 3192292SN/A 3201060SN/A /** IEW instruction queue interface. */ 3211060SN/A TimeBuffer<IEWStruct> *iewQueue; 3221060SN/A 3231060SN/A /** Wire to read information from IEW queue. */ 3241060SN/A typename TimeBuffer<IEWStruct>::wire fromIEW; 3251060SN/A 3261060SN/A /** Rename instruction queue interface, for ROB. */ 3271060SN/A TimeBuffer<RenameStruct> *renameQueue; 3281060SN/A 3291060SN/A /** Wire to read information from rename queue. */ 3301060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3311060SN/A 3322292SN/A public: 3331060SN/A /** ROB interface. */ 3341060SN/A ROB *rob; 3351060SN/A 3362292SN/A private: 3372733Sktlim@umich.edu /** Pointer to O3CPU. */ 3382733Sktlim@umich.edu O3CPU *cpu; 3391060SN/A 3402348SN/A /** Vector of all of the threads. */ 3412292SN/A std::vector<Thread *> thread; 3421060SN/A 3432292SN/A /** Records that commit has written to the time buffer this cycle. Used for 3442292SN/A * the CPU to determine if it can deschedule itself if there is no activity. 3452292SN/A */ 3462292SN/A bool wroteToTimeBuffer; 3472292SN/A 3482292SN/A /** Records if the number of ROB entries has changed this cycle. If it has, 3492292SN/A * then the number of free entries must be re-broadcast. 3502292SN/A */ 3512292SN/A bool changedROBNumEntries[Impl::MaxThreads]; 3522292SN/A 3532292SN/A /** A counter of how many threads are currently squashing. */ 3546221Snate@binkert.org ThreadID squashCounter; 3552292SN/A 3562292SN/A /** Records if a thread has to squash this cycle due to a trap. */ 3572292SN/A bool trapSquash[Impl::MaxThreads]; 3582292SN/A 3592292SN/A /** Records if a thread has to squash this cycle due to an XC write. */ 3602680Sktlim@umich.edu bool tcSquash[Impl::MaxThreads]; 3612292SN/A 3622292SN/A /** Priority List used for Commit Policy */ 3636221Snate@binkert.org std::list<ThreadID> priority_list; 3642292SN/A 3651060SN/A /** IEW to Commit delay, in ticks. */ 3661060SN/A unsigned iewToCommitDelay; 3671060SN/A 3682292SN/A /** Commit to IEW delay, in ticks. */ 3692292SN/A unsigned commitToIEWDelay; 3702292SN/A 3711060SN/A /** Rename to ROB delay, in ticks. */ 3721060SN/A unsigned renameToROBDelay; 3731060SN/A 3742292SN/A unsigned fetchToCommitDelay; 3752292SN/A 3761060SN/A /** Rename width, in instructions. Used so ROB knows how many 3771060SN/A * instructions to get from the rename instruction queue. 3781060SN/A */ 3791060SN/A unsigned renameWidth; 3801060SN/A 3811060SN/A /** Commit width, in instructions. */ 3821060SN/A unsigned commitWidth; 3831062SN/A 3842292SN/A /** Number of Reorder Buffers */ 3852292SN/A unsigned numRobs; 3862292SN/A 3872292SN/A /** Number of Active Threads */ 3886221Snate@binkert.org ThreadID numThreads; 3892292SN/A 3902843Sktlim@umich.edu /** Is a drain pending. */ 3912843Sktlim@umich.edu bool drainPending; 3922348SN/A 3932348SN/A /** Is commit switched out. */ 3942307SN/A bool switchedOut; 3952307SN/A 3962348SN/A /** The latency to handle a trap. Used when scheduling trap 3972348SN/A * squash event. 3982348SN/A */ 3992292SN/A Tick trapLatency; 4002292SN/A 4013640Sktlim@umich.edu /** The interrupt fault. */ 4023640Sktlim@umich.edu Fault interrupt; 4033640Sktlim@umich.edu 4047720Sgblack@eecs.umich.edu /** The commit PC state of each thread. Refers to the instruction that 4052348SN/A * is currently being processed/committed. 4062348SN/A */ 4077720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4084636Sgblack@eecs.umich.edu 4092292SN/A /** The sequence number of the youngest valid instruction in the ROB. */ 4102292SN/A InstSeqNum youngestSeqNum[Impl::MaxThreads]; 4112292SN/A 4124035Sktlim@umich.edu /** Records if there is a trap currently in flight. */ 4134035Sktlim@umich.edu bool trapInFlight[Impl::MaxThreads]; 4144035Sktlim@umich.edu 4154035Sktlim@umich.edu /** Records if there were any stores committed this cycle. */ 4164035Sktlim@umich.edu bool committedStores[Impl::MaxThreads]; 4174035Sktlim@umich.edu 4184035Sktlim@umich.edu /** Records if commit should check if the ROB is truly empty (see 4194035Sktlim@umich.edu commit_impl.hh). */ 4204035Sktlim@umich.edu bool checkEmptyROB[Impl::MaxThreads]; 4214035Sktlim@umich.edu 4222292SN/A /** Pointer to the list of active threads. */ 4236221Snate@binkert.org std::list<ThreadID> *activeThreads; 4242292SN/A 4252292SN/A /** Rename map interface. */ 4262292SN/A RenameMap *renameMap[Impl::MaxThreads]; 4272292SN/A 4282348SN/A /** Updates commit stats based on this instruction. */ 4292301SN/A void updateComInstStats(DynInstPtr &inst); 4302301SN/A 4312292SN/A /** Stat for the total number of committed instructions. */ 4325999Snate@binkert.org Stats::Scalar commitCommittedInsts; 4332292SN/A /** Stat for the total number of squashed instructions discarded by commit. 4342292SN/A */ 4355999Snate@binkert.org Stats::Scalar commitSquashedInsts; 4362292SN/A /** Stat for the total number of times commit is told to squash. 4372292SN/A * @todo: Actually increment this stat. 4382292SN/A */ 4395999Snate@binkert.org Stats::Scalar commitSquashEvents; 4402292SN/A /** Stat for the total number of times commit has had to stall due to a non- 4412292SN/A * speculative instruction reaching the head of the ROB. 4422292SN/A */ 4435999Snate@binkert.org Stats::Scalar commitNonSpecStalls; 4442292SN/A /** Stat for the total number of branch mispredicts that caused a squash. */ 4455999Snate@binkert.org Stats::Scalar branchMispredicts; 4462292SN/A /** Distribution of the number of committed instructions each cycle. */ 4475999Snate@binkert.org Stats::Distribution numCommittedDist; 4481062SN/A 4492316SN/A /** Total number of instructions committed. */ 4505999Snate@binkert.org Stats::Vector statComInst; 4512316SN/A /** Total number of software prefetches committed. */ 4525999Snate@binkert.org Stats::Vector statComSwp; 4532316SN/A /** Stat for the total number of committed memory references. */ 4545999Snate@binkert.org Stats::Vector statComRefs; 4552316SN/A /** Stat for the total number of committed loads. */ 4565999Snate@binkert.org Stats::Vector statComLoads; 4572316SN/A /** Total number of committed memory barriers. */ 4585999Snate@binkert.org Stats::Vector statComMembars; 4592316SN/A /** Total number of committed branches. */ 4605999Snate@binkert.org Stats::Vector statComBranches; 4612301SN/A 4622348SN/A /** Number of cycles where the commit bandwidth limit is reached. */ 4635999Snate@binkert.org Stats::Scalar commitEligibleSamples; 4642348SN/A /** Number of instructions not committed due to bandwidth limits. */ 4655999Snate@binkert.org Stats::Vector commitEligible; 4661060SN/A}; 4671060SN/A 4682292SN/A#endif // __CPU_O3_COMMIT_HH__ 469