commit.hh revision 4035
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_COMMIT_HH__ 332292SN/A#define __CPU_O3_COMMIT_HH__ 341060SN/A 351461SN/A#include "base/statistics.hh" 361060SN/A#include "base/timebuf.hh" 372292SN/A#include "cpu/exetrace.hh" 382329SN/A#include "cpu/inst_seq.hh" 391060SN/A 402292SN/Atemplate <class> 412292SN/Aclass O3ThreadState; 422292SN/A 432292SN/A/** 442316SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 452316SN/A * specified by the parameters; each cycle it tries to commit that 462316SN/A * many instructions. The SMT policy decides which thread it tries to 472316SN/A * commit instructions from. Non- speculative instructions must reach 482316SN/A * the head of the ROB before they are ready to execute; once they 492316SN/A * reach the head, commit will broadcast the instruction's sequence 502316SN/A * number to the previous stages so that they can issue/ execute the 512316SN/A * instruction. Only one non-speculative instruction is handled per 522316SN/A * cycle. Commit is responsible for handling all back-end initiated 532316SN/A * redirects. It receives the redirect, and then broadcasts it to all 542316SN/A * stages, indicating the sequence number they should squash until, 552316SN/A * and any necessary branch misprediction information as well. It 562316SN/A * priortizes redirects by instruction's age, only broadcasting a 572316SN/A * redirect if it corresponds to an instruction that should currently 582316SN/A * be in the ROB. This is done by tracking the sequence number of the 592316SN/A * youngest instruction in the ROB, which gets updated to any 602316SN/A * squashing instruction's sequence number, and only broadcasting a 612316SN/A * redirect if it corresponds to an older instruction. Commit also 622316SN/A * supports multiple cycle squashing, to model a ROB that can only 632329SN/A * remove a certain number of instructions per cycle. 642292SN/A */ 651060SN/Atemplate<class Impl> 662292SN/Aclass DefaultCommit 671060SN/A{ 681060SN/A public: 691060SN/A // Typedefs from the Impl. 702733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 711061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 721060SN/A typedef typename Impl::Params Params; 731061SN/A typedef typename Impl::CPUPol CPUPol; 741060SN/A 752292SN/A typedef typename CPUPol::RenameMap RenameMap; 761061SN/A typedef typename CPUPol::ROB ROB; 771060SN/A 781061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 792292SN/A typedef typename CPUPol::FetchStruct FetchStruct; 801061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 811061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 821060SN/A 832316SN/A typedef typename CPUPol::Fetch Fetch; 842292SN/A typedef typename CPUPol::IEW IEW; 852292SN/A 862292SN/A typedef O3ThreadState<Impl> Thread; 872292SN/A 882348SN/A /** Event class used to schedule a squash due to a trap (fault or 892348SN/A * interrupt) to happen on a specific cycle. 902348SN/A */ 912292SN/A class TrapEvent : public Event { 922292SN/A private: 932292SN/A DefaultCommit<Impl> *commit; 942292SN/A unsigned tid; 952292SN/A 962292SN/A public: 972292SN/A TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid); 982292SN/A 992292SN/A void process(); 1002292SN/A const char *description(); 1012292SN/A }; 1022292SN/A 1032292SN/A /** Overall commit status. Used to determine if the CPU can deschedule 1042292SN/A * itself due to a lack of activity. 1052292SN/A */ 1062292SN/A enum CommitStatus{ 1072292SN/A Active, 1082292SN/A Inactive 1092292SN/A }; 1102292SN/A 1112292SN/A /** Individual thread status. */ 1122292SN/A enum ThreadStatus { 1131060SN/A Running, 1141060SN/A Idle, 1151060SN/A ROBSquashing, 1162292SN/A TrapPending, 1172292SN/A FetchTrapPending 1182292SN/A }; 1192292SN/A 1202292SN/A /** Commit policy for SMT mode. */ 1212292SN/A enum CommitPolicy { 1222292SN/A Aggressive, 1232292SN/A RoundRobin, 1242292SN/A OldestReady 1251060SN/A }; 1261060SN/A 1271060SN/A private: 1282292SN/A /** Overall commit status. */ 1292292SN/A CommitStatus _status; 1302292SN/A /** Next commit status, to be set at the end of the cycle. */ 1312292SN/A CommitStatus _nextStatus; 1322292SN/A /** Per-thread status. */ 1332292SN/A ThreadStatus commitStatus[Impl::MaxThreads]; 1342292SN/A /** Commit policy used in SMT mode. */ 1352292SN/A CommitPolicy commitPolicy; 1361060SN/A 1371060SN/A public: 1382292SN/A /** Construct a DefaultCommit with the given parameters. */ 1392292SN/A DefaultCommit(Params *params); 1401060SN/A 1412292SN/A /** Returns the name of the DefaultCommit. */ 1422292SN/A std::string name() const; 1432292SN/A 1442292SN/A /** Registers statistics. */ 1451062SN/A void regStats(); 1461062SN/A 1472292SN/A /** Sets the CPU pointer. */ 1482733Sktlim@umich.edu void setCPU(O3CPU *cpu_ptr); 1491060SN/A 1502292SN/A /** Sets the list of threads. */ 1512292SN/A void setThreads(std::vector<Thread *> &threads); 1522292SN/A 1532292SN/A /** Sets the main time buffer pointer, used for backwards communication. */ 1541060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1551060SN/A 1562292SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1572292SN/A 1582292SN/A /** Sets the pointer to the queue coming from rename. */ 1591060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1601060SN/A 1612292SN/A /** Sets the pointer to the queue coming from IEW. */ 1621060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1631060SN/A 1642348SN/A /** Sets the pointer to the IEW stage. */ 1652292SN/A void setIEWStage(IEW *iew_stage); 1662292SN/A 1672965Sksewell@umich.edu /** Skid buffer between rename and commit. */ 1682965Sksewell@umich.edu std::queue<DynInstPtr> skidBuffer; 1692965Sksewell@umich.edu 1702316SN/A /** The pointer to the IEW stage. Used solely to ensure that 1712316SN/A * various events (traps, interrupts, syscalls) do not occur until 1722316SN/A * all stores have written back. 1732292SN/A */ 1742292SN/A IEW *iewStage; 1752292SN/A 1762292SN/A /** Sets pointer to list of active threads. */ 1772292SN/A void setActiveThreads(std::list<unsigned> *at_ptr); 1782292SN/A 1792292SN/A /** Sets pointer to the commited state rename map. */ 1802292SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1812292SN/A 1822292SN/A /** Sets pointer to the ROB. */ 1831060SN/A void setROB(ROB *rob_ptr); 1841060SN/A 1852292SN/A /** Initializes stage by sending back the number of free entries. */ 1862292SN/A void initStage(); 1872292SN/A 1882843Sktlim@umich.edu /** Initializes the draining of commit. */ 1892863Sktlim@umich.edu bool drain(); 1902843Sktlim@umich.edu 1912843Sktlim@umich.edu /** Resumes execution after draining. */ 1922843Sktlim@umich.edu void resume(); 1932307SN/A 1942348SN/A /** Completes the switch out of commit. */ 1952843Sktlim@umich.edu void switchOut(); 1962316SN/A 1972348SN/A /** Takes over from another CPU's thread. */ 1982307SN/A void takeOverFrom(); 1992307SN/A 2002292SN/A /** Ticks the commit stage, which tries to commit instructions. */ 2011060SN/A void tick(); 2021060SN/A 2032292SN/A /** Handles any squashes that are sent from IEW, and adds instructions 2042292SN/A * to the ROB and tries to commit instructions. 2052292SN/A */ 2061060SN/A void commit(); 2071060SN/A 2082292SN/A /** Returns the number of free ROB entries for a specific thread. */ 2092292SN/A unsigned numROBFreeEntries(unsigned tid); 2102292SN/A 2112348SN/A /** Generates an event to schedule a squash due to a trap. */ 2122348SN/A void generateTrapEvent(unsigned tid); 2132348SN/A 2142348SN/A /** Records that commit needs to initiate a squash due to an 2152680Sktlim@umich.edu * external state update through the TC. 2162348SN/A */ 2172680Sktlim@umich.edu void generateTCEvent(unsigned tid); 2182292SN/A 2191060SN/A private: 2202292SN/A /** Updates the overall status of commit with the nextStatus, and 2212348SN/A * tell the CPU if commit is active/inactive. 2222348SN/A */ 2232292SN/A void updateStatus(); 2241060SN/A 2252292SN/A /** Sets the next status based on threads' statuses, which becomes the 2262292SN/A * current status at the end of the cycle. 2272292SN/A */ 2282292SN/A void setNextStatus(); 2292292SN/A 2302292SN/A /** Checks if the ROB is completed with squashing. This is for the case 2312292SN/A * where the ROB can take multiple cycles to complete squashing. 2322292SN/A */ 2332292SN/A bool robDoneSquashing(); 2342292SN/A 2352292SN/A /** Returns if any of the threads have the number of ROB entries changed 2362292SN/A * on this cycle. Used to determine if the number of free ROB entries needs 2372292SN/A * to be sent back to previous stages. 2382292SN/A */ 2392292SN/A bool changedROBEntries(); 2402292SN/A 2412348SN/A /** Squashes all in flight instructions. */ 2422316SN/A void squashAll(unsigned tid); 2432316SN/A 2442348SN/A /** Handles squashing due to a trap. */ 2452292SN/A void squashFromTrap(unsigned tid); 2462292SN/A 2472680Sktlim@umich.edu /** Handles squashing due to an TC write. */ 2482680Sktlim@umich.edu void squashFromTC(unsigned tid); 2492292SN/A 2504035Sktlim@umich.edu#if FULL_SYSTEM 2514035Sktlim@umich.edu /** Handles processing an interrupt. */ 2524035Sktlim@umich.edu void handleInterrupt(); 2534035Sktlim@umich.edu#endif // FULL_SYSTEM 2544035Sktlim@umich.edu 2552292SN/A /** Commits as many instructions as possible. */ 2561060SN/A void commitInsts(); 2571060SN/A 2582292SN/A /** Tries to commit the head ROB instruction passed in. 2592292SN/A * @param head_inst The instruction to be committed. 2602292SN/A */ 2611061SN/A bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 2621060SN/A 2632292SN/A /** Gets instructions from rename and inserts them into the ROB. */ 2641060SN/A void getInsts(); 2651060SN/A 2662965Sksewell@umich.edu /** Insert all instructions from rename into skidBuffer */ 2672965Sksewell@umich.edu void skidInsert(); 2682965Sksewell@umich.edu 2692292SN/A /** Marks completed instructions using information sent from IEW. */ 2701060SN/A void markCompletedInsts(); 2711060SN/A 2722292SN/A /** Gets the thread to commit, based on the SMT policy. */ 2732292SN/A int getCommittingThread(); 2742292SN/A 2752292SN/A /** Returns the thread ID to use based on a round robin policy. */ 2762292SN/A int roundRobin(); 2772292SN/A 2782292SN/A /** Returns the thread ID to use based on an oldest instruction policy. */ 2792292SN/A int oldestReady(); 2802292SN/A 2811684SN/A public: 2822316SN/A /** Returns the PC of the head instruction of the ROB. 2832316SN/A * @todo: Probably remove this function as it returns only thread 0. 2842316SN/A */ 2852316SN/A uint64_t readPC() { return PC[0]; } 2861684SN/A 2872348SN/A /** Returns the PC of a specific thread. */ 2882292SN/A uint64_t readPC(unsigned tid) { return PC[tid]; } 2892292SN/A 2902348SN/A /** Sets the PC of a specific thread. */ 2912292SN/A void setPC(uint64_t val, unsigned tid) { PC[tid] = val; } 2922292SN/A 2932756Sksewell@umich.edu /** Reads the next PC of a specific thread. */ 2942292SN/A uint64_t readNextPC(unsigned tid) { return nextPC[tid]; } 2952292SN/A 2962348SN/A /** Sets the next PC of a specific thread. */ 2972292SN/A void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; } 2981684SN/A 2992756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 3002935Sksewell@umich.edu uint64_t readNextNPC(unsigned tid) { return nextNPC[tid]; } 3012756Sksewell@umich.edu 3022756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 3032935Sksewell@umich.edu void setNextNPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; } 3042756Sksewell@umich.edu 3051684SN/A private: 3061060SN/A /** Time buffer interface. */ 3071060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3081060SN/A 3091060SN/A /** Wire to write information heading to previous stages. */ 3101060SN/A typename TimeBuffer<TimeStruct>::wire toIEW; 3111060SN/A 3121060SN/A /** Wire to read information from IEW (for ROB). */ 3131060SN/A typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 3141060SN/A 3152292SN/A TimeBuffer<FetchStruct> *fetchQueue; 3162292SN/A 3172292SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 3182292SN/A 3191060SN/A /** IEW instruction queue interface. */ 3201060SN/A TimeBuffer<IEWStruct> *iewQueue; 3211060SN/A 3221060SN/A /** Wire to read information from IEW queue. */ 3231060SN/A typename TimeBuffer<IEWStruct>::wire fromIEW; 3241060SN/A 3251060SN/A /** Rename instruction queue interface, for ROB. */ 3261060SN/A TimeBuffer<RenameStruct> *renameQueue; 3271060SN/A 3281060SN/A /** Wire to read information from rename queue. */ 3291060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3301060SN/A 3312292SN/A public: 3321060SN/A /** ROB interface. */ 3331060SN/A ROB *rob; 3341060SN/A 3352292SN/A private: 3362733Sktlim@umich.edu /** Pointer to O3CPU. */ 3372733Sktlim@umich.edu O3CPU *cpu; 3381060SN/A 3392348SN/A /** Vector of all of the threads. */ 3402292SN/A std::vector<Thread *> thread; 3411060SN/A 3422292SN/A /** Records that commit has written to the time buffer this cycle. Used for 3432292SN/A * the CPU to determine if it can deschedule itself if there is no activity. 3442292SN/A */ 3452292SN/A bool wroteToTimeBuffer; 3462292SN/A 3472292SN/A /** Records if the number of ROB entries has changed this cycle. If it has, 3482292SN/A * then the number of free entries must be re-broadcast. 3492292SN/A */ 3502292SN/A bool changedROBNumEntries[Impl::MaxThreads]; 3512292SN/A 3522292SN/A /** A counter of how many threads are currently squashing. */ 3532292SN/A int squashCounter; 3542292SN/A 3552292SN/A /** Records if a thread has to squash this cycle due to a trap. */ 3562292SN/A bool trapSquash[Impl::MaxThreads]; 3572292SN/A 3582292SN/A /** Records if a thread has to squash this cycle due to an XC write. */ 3592680Sktlim@umich.edu bool tcSquash[Impl::MaxThreads]; 3602292SN/A 3612292SN/A /** Priority List used for Commit Policy */ 3622292SN/A std::list<unsigned> priority_list; 3632292SN/A 3641060SN/A /** IEW to Commit delay, in ticks. */ 3651060SN/A unsigned iewToCommitDelay; 3661060SN/A 3672292SN/A /** Commit to IEW delay, in ticks. */ 3682292SN/A unsigned commitToIEWDelay; 3692292SN/A 3701060SN/A /** Rename to ROB delay, in ticks. */ 3711060SN/A unsigned renameToROBDelay; 3721060SN/A 3732292SN/A unsigned fetchToCommitDelay; 3742292SN/A 3751060SN/A /** Rename width, in instructions. Used so ROB knows how many 3761060SN/A * instructions to get from the rename instruction queue. 3771060SN/A */ 3781060SN/A unsigned renameWidth; 3791060SN/A 3801060SN/A /** Commit width, in instructions. */ 3811060SN/A unsigned commitWidth; 3821062SN/A 3832292SN/A /** Number of Reorder Buffers */ 3842292SN/A unsigned numRobs; 3852292SN/A 3862292SN/A /** Number of Active Threads */ 3872292SN/A unsigned numThreads; 3882292SN/A 3892843Sktlim@umich.edu /** Is a drain pending. */ 3902843Sktlim@umich.edu bool drainPending; 3912348SN/A 3922348SN/A /** Is commit switched out. */ 3932307SN/A bool switchedOut; 3942307SN/A 3952348SN/A /** The latency to handle a trap. Used when scheduling trap 3962348SN/A * squash event. 3972348SN/A */ 3982292SN/A Tick trapLatency; 3992292SN/A 4003640Sktlim@umich.edu /** The interrupt fault. */ 4013640Sktlim@umich.edu Fault interrupt; 4023640Sktlim@umich.edu 4032348SN/A /** The commit PC of each thread. Refers to the instruction that 4042348SN/A * is currently being processed/committed. 4052348SN/A */ 4062292SN/A Addr PC[Impl::MaxThreads]; 4072292SN/A 4082348SN/A /** The next PC of each thread. */ 4092292SN/A Addr nextPC[Impl::MaxThreads]; 4102292SN/A 4112756Sksewell@umich.edu /** The next NPC of each thread. */ 4122756Sksewell@umich.edu Addr nextNPC[Impl::MaxThreads]; 4132756Sksewell@umich.edu 4142292SN/A /** The sequence number of the youngest valid instruction in the ROB. */ 4152292SN/A InstSeqNum youngestSeqNum[Impl::MaxThreads]; 4162292SN/A 4174035Sktlim@umich.edu /** Records if there is a trap currently in flight. */ 4184035Sktlim@umich.edu bool trapInFlight[Impl::MaxThreads]; 4194035Sktlim@umich.edu 4204035Sktlim@umich.edu /** Records if there were any stores committed this cycle. */ 4214035Sktlim@umich.edu bool committedStores[Impl::MaxThreads]; 4224035Sktlim@umich.edu 4234035Sktlim@umich.edu /** Records if commit should check if the ROB is truly empty (see 4244035Sktlim@umich.edu commit_impl.hh). */ 4254035Sktlim@umich.edu bool checkEmptyROB[Impl::MaxThreads]; 4264035Sktlim@umich.edu 4272292SN/A /** Pointer to the list of active threads. */ 4282292SN/A std::list<unsigned> *activeThreads; 4292292SN/A 4302292SN/A /** Rename map interface. */ 4312292SN/A RenameMap *renameMap[Impl::MaxThreads]; 4322292SN/A 4332348SN/A /** Updates commit stats based on this instruction. */ 4342301SN/A void updateComInstStats(DynInstPtr &inst); 4352301SN/A 4362292SN/A /** Stat for the total number of committed instructions. */ 4371062SN/A Stats::Scalar<> commitCommittedInsts; 4382292SN/A /** Stat for the total number of squashed instructions discarded by commit. 4392292SN/A */ 4401062SN/A Stats::Scalar<> commitSquashedInsts; 4412292SN/A /** Stat for the total number of times commit is told to squash. 4422292SN/A * @todo: Actually increment this stat. 4432292SN/A */ 4441062SN/A Stats::Scalar<> commitSquashEvents; 4452292SN/A /** Stat for the total number of times commit has had to stall due to a non- 4462292SN/A * speculative instruction reaching the head of the ROB. 4472292SN/A */ 4481062SN/A Stats::Scalar<> commitNonSpecStalls; 4492292SN/A /** Stat for the total number of branch mispredicts that caused a squash. */ 4501062SN/A Stats::Scalar<> branchMispredicts; 4512292SN/A /** Distribution of the number of committed instructions each cycle. */ 4522292SN/A Stats::Distribution<> numCommittedDist; 4531062SN/A 4542316SN/A /** Total number of instructions committed. */ 4552316SN/A Stats::Vector<> statComInst; 4562316SN/A /** Total number of software prefetches committed. */ 4572316SN/A Stats::Vector<> statComSwp; 4582316SN/A /** Stat for the total number of committed memory references. */ 4592316SN/A Stats::Vector<> statComRefs; 4602316SN/A /** Stat for the total number of committed loads. */ 4612316SN/A Stats::Vector<> statComLoads; 4622316SN/A /** Total number of committed memory barriers. */ 4632316SN/A Stats::Vector<> statComMembars; 4642316SN/A /** Total number of committed branches. */ 4652316SN/A Stats::Vector<> statComBranches; 4662301SN/A 4672348SN/A /** Number of cycles where the commit bandwidth limit is reached. */ 4682316SN/A Stats::Scalar<> commitEligibleSamples; 4692348SN/A /** Number of instructions not committed due to bandwidth limits. */ 4702316SN/A Stats::Vector<> commitEligible; 4711060SN/A}; 4721060SN/A 4732292SN/A#endif // __CPU_O3_COMMIT_HH__ 474