commit.hh revision 2301
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu */ 282810Srdreslin@umich.edu 292810Srdreslin@umich.edu#ifndef __CPU_O3_COMMIT_HH__ 302810Srdreslin@umich.edu#define __CPU_O3_COMMIT_HH__ 314458Sstever@eecs.umich.edu 322810Srdreslin@umich.edu#include "arch/faults.hh" 332810Srdreslin@umich.edu#include "cpu/inst_seq.hh" 342810Srdreslin@umich.edu#include "base/statistics.hh" 352810Srdreslin@umich.edu#include "base/timebuf.hh" 362810Srdreslin@umich.edu#include "cpu/exetrace.hh" 372810Srdreslin@umich.edu#include "mem/memory_interface.hh" 382810Srdreslin@umich.edu 392810Srdreslin@umich.edutemplate <class> 402810Srdreslin@umich.educlass O3ThreadState; 412810Srdreslin@umich.edu 422810Srdreslin@umich.edu/** 432810Srdreslin@umich.edu * DefaultCommit handles single threaded and SMT commit. Its width is specified 445338Sstever@gmail.com * by the parameters; each cycle it tries to commit that many instructions. The 455338Sstever@gmail.com * SMT policy decides which thread it tries to commit instructions from. Non- 465338Sstever@gmail.com * speculative instructions must reach the head of the ROB before they are 472810Srdreslin@umich.edu * ready to execute; once they reach the head, commit will broadcast the 484458Sstever@eecs.umich.edu * instruction's sequence number to the previous stages so that they can issue/ 494458Sstever@eecs.umich.edu * execute the instruction. Only one non-speculative instruction is handled per 502813Srdreslin@umich.edu * cycle. Commit is responsible for handling all back-end initiated redirects. 513861Sstever@eecs.umich.edu * It receives the redirect, and then broadcasts it to all stages, indicating 522810Srdreslin@umich.edu * the sequence number they should squash until, and any necessary branch mis- 532810Srdreslin@umich.edu * prediction information as well. It priortizes redirects by instruction's age, 542810Srdreslin@umich.edu * only broadcasting a redirect if it corresponds to an instruction that should 552810Srdreslin@umich.edu * currently be in the ROB. This is done by tracking the sequence number of the 564672Sstever@eecs.umich.edu * youngest instruction in the ROB, which gets updated to any squashing 572810Srdreslin@umich.edu * instruction's sequence number, and only broadcasting a redirect if it 584672Sstever@eecs.umich.edu * corresponds to an older instruction. Commit also supports multiple cycle 592810Srdreslin@umich.edu * squashing, to model a ROB that can only remove a certain number of 602810Srdreslin@umich.edu * instructions per cycle. Eventually traps and interrupts will most likely 612810Srdreslin@umich.edu * be handled here as well. 622810Srdreslin@umich.edu */ 632810Srdreslin@umich.edutemplate<class Impl> 643860Sstever@eecs.umich.educlass DefaultCommit 653860Sstever@eecs.umich.edu{ 662810Srdreslin@umich.edu public: 672810Srdreslin@umich.edu // Typedefs from the Impl. 683738Sstever@eecs.umich.edu typedef typename Impl::FullCPU FullCPU; 692810Srdreslin@umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 702810Srdreslin@umich.edu typedef typename Impl::Params Params; 713738Sstever@eecs.umich.edu typedef typename Impl::CPUPol CPUPol; 723738Sstever@eecs.umich.edu 733738Sstever@eecs.umich.edu typedef typename CPUPol::RenameMap RenameMap; 743738Sstever@eecs.umich.edu typedef typename CPUPol::ROB ROB; 754965Ssaidi@eecs.umich.edu 765314Sstever@gmail.com typedef typename CPUPol::TimeStruct TimeStruct; 774965Ssaidi@eecs.umich.edu typedef typename CPUPol::FetchStruct FetchStruct; 783738Sstever@eecs.umich.edu typedef typename CPUPol::IEWStruct IEWStruct; 793738Sstever@eecs.umich.edu typedef typename CPUPol::RenameStruct RenameStruct; 803738Sstever@eecs.umich.edu 813738Sstever@eecs.umich.edu typedef typename CPUPol::IEW IEW; 824672Sstever@eecs.umich.edu 834672Sstever@eecs.umich.edu typedef O3ThreadState<Impl> Thread; 843738Sstever@eecs.umich.edu 853738Sstever@eecs.umich.edu class TrapEvent : public Event { 864478Sstever@eecs.umich.edu private: 874478Sstever@eecs.umich.edu DefaultCommit<Impl> *commit; 884478Sstever@eecs.umich.edu unsigned tid; 893738Sstever@eecs.umich.edu 903738Sstever@eecs.umich.edu public: 913738Sstever@eecs.umich.edu TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid); 923738Sstever@eecs.umich.edu 933738Sstever@eecs.umich.edu void process(); 943738Sstever@eecs.umich.edu const char *description(); 953738Sstever@eecs.umich.edu }; 963738Sstever@eecs.umich.edu 973738Sstever@eecs.umich.edu /** Overall commit status. Used to determine if the CPU can deschedule 983738Sstever@eecs.umich.edu * itself due to a lack of activity. 993738Sstever@eecs.umich.edu */ 1004965Ssaidi@eecs.umich.edu enum CommitStatus{ 1015314Sstever@gmail.com Active, 1024965Ssaidi@eecs.umich.edu Inactive 1033738Sstever@eecs.umich.edu }; 1043738Sstever@eecs.umich.edu 1053738Sstever@eecs.umich.edu /** Individual thread status. */ 1063738Sstever@eecs.umich.edu enum ThreadStatus { 1074672Sstever@eecs.umich.edu Running, 1084672Sstever@eecs.umich.edu Idle, 1093738Sstever@eecs.umich.edu ROBSquashing, 1103738Sstever@eecs.umich.edu TrapPending, 1114626Sstever@eecs.umich.edu FetchTrapPending 1124626Sstever@eecs.umich.edu }; 1134626Sstever@eecs.umich.edu 1144458Sstever@eecs.umich.edu /** Commit policy for SMT mode. */ 1154478Sstever@eecs.umich.edu enum CommitPolicy { 1164478Sstever@eecs.umich.edu Aggressive, 1174478Sstever@eecs.umich.edu RoundRobin, 1183738Sstever@eecs.umich.edu OldestReady 1193738Sstever@eecs.umich.edu }; 1204458Sstever@eecs.umich.edu 1214458Sstever@eecs.umich.edu private: 1223738Sstever@eecs.umich.edu /** Overall commit status. */ 1233738Sstever@eecs.umich.edu CommitStatus _status; 1243738Sstever@eecs.umich.edu /** Next commit status, to be set at the end of the cycle. */ 1254458Sstever@eecs.umich.edu CommitStatus _nextStatus; 1264626Sstever@eecs.umich.edu /** Per-thread status. */ 1274626Sstever@eecs.umich.edu ThreadStatus commitStatus[Impl::MaxThreads]; 1283738Sstever@eecs.umich.edu /** Commit policy used in SMT mode. */ 1293738Sstever@eecs.umich.edu CommitPolicy commitPolicy; 1302810Srdreslin@umich.edu 1312810Srdreslin@umich.edu public: 1324626Sstever@eecs.umich.edu /** Construct a DefaultCommit with the given parameters. */ 1332810Srdreslin@umich.edu DefaultCommit(Params *params); 1343861Sstever@eecs.umich.edu 1352810Srdreslin@umich.edu /** Returns the name of the DefaultCommit. */ 1364671Sstever@eecs.umich.edu std::string name() const; 1374671Sstever@eecs.umich.edu 1384671Sstever@eecs.umich.edu /** Registers statistics. */ 1392810Srdreslin@umich.edu void regStats(); 1403860Sstever@eecs.umich.edu 1413860Sstever@eecs.umich.edu /** Sets the CPU pointer. */ 1423860Sstever@eecs.umich.edu void setCPU(FullCPU *cpu_ptr); 1433860Sstever@eecs.umich.edu 1443860Sstever@eecs.umich.edu /** Sets the list of threads. */ 1453860Sstever@eecs.umich.edu void setThreads(std::vector<Thread *> &threads); 1463860Sstever@eecs.umich.edu 1473860Sstever@eecs.umich.edu /** Sets the main time buffer pointer, used for backwards communication. */ 1483860Sstever@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1493860Sstever@eecs.umich.edu 1503860Sstever@eecs.umich.edu void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1513860Sstever@eecs.umich.edu 1523860Sstever@eecs.umich.edu /** Sets the pointer to the queue coming from rename. */ 1534626Sstever@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1543860Sstever@eecs.umich.edu 1553860Sstever@eecs.umich.edu /** Sets the pointer to the queue coming from IEW. */ 1563860Sstever@eecs.umich.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1573860Sstever@eecs.umich.edu 1583860Sstever@eecs.umich.edu /** Sets the poitner to the IEW stage. */ 1593860Sstever@eecs.umich.edu void setIEWStage(IEW *iew_stage); 1603860Sstever@eecs.umich.edu 1613860Sstever@eecs.umich.edu /** The pointer to the IEW stage. Used solely to ensure that syscalls do 1623860Sstever@eecs.umich.edu * not execute until all stores have written back. 1633860Sstever@eecs.umich.edu */ 1643860Sstever@eecs.umich.edu IEW *iewStage; 1654628Sstever@eecs.umich.edu 1664219Srdreslin@umich.edu /** Sets pointer to list of active threads. */ 1674219Srdreslin@umich.edu void setActiveThreads(std::list<unsigned> *at_ptr); 1684219Srdreslin@umich.edu 1694219Srdreslin@umich.edu /** Sets pointer to the commited state rename map. */ 1704626Sstever@eecs.umich.edu void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1713860Sstever@eecs.umich.edu 1723860Sstever@eecs.umich.edu /** Sets pointer to the ROB. */ 1733860Sstever@eecs.umich.edu void setROB(ROB *rob_ptr); 1743860Sstever@eecs.umich.edu 1753860Sstever@eecs.umich.edu /** Initializes stage by sending back the number of free entries. */ 1763860Sstever@eecs.umich.edu void initStage(); 1774626Sstever@eecs.umich.edu 1783860Sstever@eecs.umich.edu /** Ticks the commit stage, which tries to commit instructions. */ 1793860Sstever@eecs.umich.edu void tick(); 1803860Sstever@eecs.umich.edu 1813860Sstever@eecs.umich.edu /** Handles any squashes that are sent from IEW, and adds instructions 1824626Sstever@eecs.umich.edu * to the ROB and tries to commit instructions. 1834626Sstever@eecs.umich.edu */ 1843860Sstever@eecs.umich.edu void commit(); 1854665Sstever@eecs.umich.edu 1864628Sstever@eecs.umich.edu /** Returns the number of free ROB entries for a specific thread. */ 1874626Sstever@eecs.umich.edu unsigned numROBFreeEntries(unsigned tid); 1884670Sstever@eecs.umich.edu 1895319Sstever@gmail.com void generateXCEvent(unsigned tid); 1903860Sstever@eecs.umich.edu 1913860Sstever@eecs.umich.edu private: 1923860Sstever@eecs.umich.edu /** Updates the overall status of commit with the nextStatus, and 1933860Sstever@eecs.umich.edu * tell the CPU if commit is active/inactive. */ 1943860Sstever@eecs.umich.edu void updateStatus(); 1953860Sstever@eecs.umich.edu 1964670Sstever@eecs.umich.edu /** Sets the next status based on threads' statuses, which becomes the 1975319Sstever@gmail.com * current status at the end of the cycle. 1983860Sstever@eecs.umich.edu */ 1993860Sstever@eecs.umich.edu void setNextStatus(); 2003860Sstever@eecs.umich.edu 2013860Sstever@eecs.umich.edu /** Checks if the ROB is completed with squashing. This is for the case 2023860Sstever@eecs.umich.edu * where the ROB can take multiple cycles to complete squashing. 2033860Sstever@eecs.umich.edu */ 2043860Sstever@eecs.umich.edu bool robDoneSquashing(); 2053860Sstever@eecs.umich.edu 2062810Srdreslin@umich.edu /** Returns if any of the threads have the number of ROB entries changed 2072810Srdreslin@umich.edu * on this cycle. Used to determine if the number of free ROB entries needs 2085034Smilesck@eecs.umich.edu * to be sent back to previous stages. 2092810Srdreslin@umich.edu */ 2103738Sstever@eecs.umich.edu bool changedROBEntries(); 2114190Ssaidi@eecs.umich.edu 2122813Srdreslin@umich.edu void squashFromTrap(unsigned tid); 2132810Srdreslin@umich.edu 2142810Srdreslin@umich.edu void squashFromXC(unsigned tid); 2152810Srdreslin@umich.edu 2162810Srdreslin@umich.edu void squashInFlightInsts(unsigned tid); 2172982Sstever@eecs.umich.edu 2182810Srdreslin@umich.edu private: 2192810Srdreslin@umich.edu /** Commits as many instructions as possible. */ 2204626Sstever@eecs.umich.edu void commitInsts(); 2212810Srdreslin@umich.edu 2222810Srdreslin@umich.edu /** Tries to commit the head ROB instruction passed in. 2234626Sstever@eecs.umich.edu * @param head_inst The instruction to be committed. 2244626Sstever@eecs.umich.edu */ 2254626Sstever@eecs.umich.edu bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 2262810Srdreslin@umich.edu 2274626Sstever@eecs.umich.edu void generateTrapEvent(unsigned tid); 2282810Srdreslin@umich.edu 2292810Srdreslin@umich.edu /** Gets instructions from rename and inserts them into the ROB. */ 2304626Sstever@eecs.umich.edu void getInsts(); 2314626Sstever@eecs.umich.edu 2324626Sstever@eecs.umich.edu /** Marks completed instructions using information sent from IEW. */ 2332810Srdreslin@umich.edu void markCompletedInsts(); 2345314Sstever@gmail.com 2355314Sstever@gmail.com /** Gets the thread to commit, based on the SMT policy. */ 2363293Srdreslin@umich.edu int getCommittingThread(); 2373293Srdreslin@umich.edu 2382810Srdreslin@umich.edu /** Returns the thread ID to use based on a round robin policy. */ 2392982Sstever@eecs.umich.edu int roundRobin(); 2402810Srdreslin@umich.edu 2414626Sstever@eecs.umich.edu /** Returns the thread ID to use based on an oldest instruction policy. */ 2422810Srdreslin@umich.edu int oldestReady(); 2432810Srdreslin@umich.edu 2442810Srdreslin@umich.edu public: 2452982Sstever@eecs.umich.edu /** Returns the PC of the head instruction of the ROB. */ 2462810Srdreslin@umich.edu uint64_t readPC(); 2474626Sstever@eecs.umich.edu 2482810Srdreslin@umich.edu uint64_t readPC(unsigned tid) { return PC[tid]; } 2494626Sstever@eecs.umich.edu 2504626Sstever@eecs.umich.edu void setPC(uint64_t val, unsigned tid) { PC[tid] = val; } 2514626Sstever@eecs.umich.edu 2524626Sstever@eecs.umich.edu uint64_t readNextPC(unsigned tid) { return nextPC[tid]; } 2534626Sstever@eecs.umich.edu 2544626Sstever@eecs.umich.edu void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; } 2554626Sstever@eecs.umich.edu 2562810Srdreslin@umich.edu /** Sets that the ROB is currently squashing. */ 2572810Srdreslin@umich.edu void setSquashing(unsigned tid); 2582982Sstever@eecs.umich.edu 2592810Srdreslin@umich.edu private: 2602982Sstever@eecs.umich.edu /** Time buffer interface. */ 2612810Srdreslin@umich.edu TimeBuffer<TimeStruct> *timeBuffer; 2624626Sstever@eecs.umich.edu 2634626Sstever@eecs.umich.edu /** Wire to write information heading to previous stages. */ 2644626Sstever@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire toIEW; 2654626Sstever@eecs.umich.edu 2664626Sstever@eecs.umich.edu /** Wire to read information from IEW (for ROB). */ 2674626Sstever@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 2684628Sstever@eecs.umich.edu 2694628Sstever@eecs.umich.edu TimeBuffer<FetchStruct> *fetchQueue; 2704626Sstever@eecs.umich.edu 2714628Sstever@eecs.umich.edu typename TimeBuffer<FetchStruct>::wire fromFetch; 2724626Sstever@eecs.umich.edu 2734626Sstever@eecs.umich.edu /** IEW instruction queue interface. */ 2744626Sstever@eecs.umich.edu TimeBuffer<IEWStruct> *iewQueue; 2754626Sstever@eecs.umich.edu 2764626Sstever@eecs.umich.edu /** Wire to read information from IEW queue. */ 2774626Sstever@eecs.umich.edu typename TimeBuffer<IEWStruct>::wire fromIEW; 2784626Sstever@eecs.umich.edu 2794626Sstever@eecs.umich.edu /** Rename instruction queue interface, for ROB. */ 2804626Sstever@eecs.umich.edu TimeBuffer<RenameStruct> *renameQueue; 2814626Sstever@eecs.umich.edu 2824626Sstever@eecs.umich.edu /** Wire to read information from rename queue. */ 2834626Sstever@eecs.umich.edu typename TimeBuffer<RenameStruct>::wire fromRename; 2844626Sstever@eecs.umich.edu 2854626Sstever@eecs.umich.edu public: 2864626Sstever@eecs.umich.edu /** ROB interface. */ 2874626Sstever@eecs.umich.edu ROB *rob; 2884626Sstever@eecs.umich.edu 2894626Sstever@eecs.umich.edu private: 2904626Sstever@eecs.umich.edu /** Pointer to FullCPU. */ 2912810Srdreslin@umich.edu FullCPU *cpu; 2924626Sstever@eecs.umich.edu 2932810Srdreslin@umich.edu /** Memory interface. Used for d-cache accesses. */ 2942810Srdreslin@umich.edu MemInterface *dcacheInterface; 2954626Sstever@eecs.umich.edu 2964626Sstever@eecs.umich.edu std::vector<Thread *> thread; 2972810Srdreslin@umich.edu 2982810Srdreslin@umich.edu private: 2993861Sstever@eecs.umich.edu Fault fetchFault; 3003861Sstever@eecs.umich.edu InstSeqNum fetchFaultSN; 3013861Sstever@eecs.umich.edu int fetchTrapWait; 3023861Sstever@eecs.umich.edu /** Records that commit has written to the time buffer this cycle. Used for 3033861Sstever@eecs.umich.edu * the CPU to determine if it can deschedule itself if there is no activity. 3044626Sstever@eecs.umich.edu */ 3053861Sstever@eecs.umich.edu bool wroteToTimeBuffer; 3062810Srdreslin@umich.edu 3072810Srdreslin@umich.edu /** Records if the number of ROB entries has changed this cycle. If it has, 3082810Srdreslin@umich.edu * then the number of free entries must be re-broadcast. 309 */ 310 bool changedROBNumEntries[Impl::MaxThreads]; 311 312 /** A counter of how many threads are currently squashing. */ 313 int squashCounter; 314 315 /** Records if a thread has to squash this cycle due to a trap. */ 316 bool trapSquash[Impl::MaxThreads]; 317 318 /** Records if a thread has to squash this cycle due to an XC write. */ 319 bool xcSquash[Impl::MaxThreads]; 320 321 /** Priority List used for Commit Policy */ 322 std::list<unsigned> priority_list; 323 324 /** IEW to Commit delay, in ticks. */ 325 unsigned iewToCommitDelay; 326 327 /** Commit to IEW delay, in ticks. */ 328 unsigned commitToIEWDelay; 329 330 /** Rename to ROB delay, in ticks. */ 331 unsigned renameToROBDelay; 332 333 unsigned fetchToCommitDelay; 334 335 /** Rename width, in instructions. Used so ROB knows how many 336 * instructions to get from the rename instruction queue. 337 */ 338 unsigned renameWidth; 339 340 /** IEW width, in instructions. Used so ROB knows how many 341 * instructions to get from the IEW instruction queue. 342 */ 343 unsigned iewWidth; 344 345 /** Commit width, in instructions. */ 346 unsigned commitWidth; 347 348 /** Number of Reorder Buffers */ 349 unsigned numRobs; 350 351 /** Number of Active Threads */ 352 unsigned numThreads; 353 354 Tick trapLatency; 355 356 Tick fetchTrapLatency; 357 Tick fetchFaultTick; 358 359 Addr PC[Impl::MaxThreads]; 360 361 Addr nextPC[Impl::MaxThreads]; 362 363 /** The sequence number of the youngest valid instruction in the ROB. */ 364 InstSeqNum youngestSeqNum[Impl::MaxThreads]; 365 366 /** Pointer to the list of active threads. */ 367 std::list<unsigned> *activeThreads; 368 369 /** Rename map interface. */ 370 RenameMap *renameMap[Impl::MaxThreads]; 371 372 void updateComInstStats(DynInstPtr &inst); 373 374 /** Stat for the total number of committed instructions. */ 375 Stats::Scalar<> commitCommittedInsts; 376 /** Stat for the total number of squashed instructions discarded by commit. 377 */ 378 Stats::Scalar<> commitSquashedInsts; 379 /** Stat for the total number of times commit is told to squash. 380 * @todo: Actually increment this stat. 381 */ 382 Stats::Scalar<> commitSquashEvents; 383 /** Stat for the total number of times commit has had to stall due to a non- 384 * speculative instruction reaching the head of the ROB. 385 */ 386 Stats::Scalar<> commitNonSpecStalls; 387 /** Stat for the total number of committed branches. */ 388// Stats::Scalar<> commitCommittedBranches; 389 /** Stat for the total number of committed loads. */ 390// Stats::Scalar<> commitCommittedLoads; 391 /** Stat for the total number of committed memory references. */ 392// Stats::Scalar<> commitCommittedMemRefs; 393 /** Stat for the total number of branch mispredicts that caused a squash. */ 394 Stats::Scalar<> branchMispredicts; 395 /** Distribution of the number of committed instructions each cycle. */ 396 Stats::Distribution<> numCommittedDist; 397 398 // total number of instructions committed 399 Stats::Vector<> stat_com_inst; 400 Stats::Vector<> stat_com_swp; 401 Stats::Vector<> stat_com_refs; 402 Stats::Vector<> stat_com_loads; 403 Stats::Vector<> stat_com_membars; 404 Stats::Vector<> stat_com_branches; 405 406 Stats::Scalar<> commit_eligible_samples; 407 Stats::Vector<> commit_eligible; 408}; 409 410#endif // __CPU_O3_COMMIT_HH__ 411