commit.hh revision 1689 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29// Todo: Maybe have a special method for handling interrupts/traps.
30//
31// Traps:  Have IEW send a signal to commit saying that there's a trap to
32// be handled.  Have commit send the PC back to the fetch stage, along
33// with the current commit PC.  Fetch will directly access the IPR and save
34// off all the proper stuff.  Commit can send out a squash, or something
35// close to it.
36// Do the same for hwrei().  However, requires that commit be specifically
37// built to support that kind of stuff.  Probably not horrible to have
38// commit support having the CPU tell it to squash the other stages and
39// restart at a given address.  The IPR register does become an issue.
40// Probably not a big deal if the IPR stuff isn't cycle accurate.  Can just
41// have the original function handle writing to the IPR register.
42
43#ifndef __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
44#define __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
45
46#include "base/statistics.hh"
47#include "base/timebuf.hh"
48#include "mem/memory_interface.hh"
49
50template<class Impl>
51class SimpleCommit
52{
53  public:
54    // Typedefs from the Impl.
55    typedef typename Impl::ISA ISA;
56    typedef typename Impl::FullCPU FullCPU;
57    typedef typename Impl::DynInstPtr DynInstPtr;
58    typedef typename Impl::Params Params;
59    typedef typename Impl::CPUPol CPUPol;
60
61    typedef typename CPUPol::ROB ROB;
62
63    typedef typename CPUPol::TimeStruct TimeStruct;
64    typedef typename CPUPol::IEWStruct IEWStruct;
65    typedef typename CPUPol::RenameStruct RenameStruct;
66
67  public:
68    // I don't believe commit can block, so it will only have two
69    // statuses for now.
70    // Actually if there's a cache access that needs to block (ie
71    // uncachable load or just a mem access in commit) then the stage
72    // may have to wait.
73    enum Status {
74        Running,
75        Idle,
76        ROBSquashing,
77        DcacheMissStall,
78        DcacheMissComplete
79    };
80
81  private:
82    Status _status;
83
84  public:
85    SimpleCommit(Params &params);
86
87    void regStats();
88
89    void setCPU(FullCPU *cpu_ptr);
90
91    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
92
93    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
94
95    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
96
97    void setROB(ROB *rob_ptr);
98
99    void tick();
100
101    void commit();
102
103  private:
104
105    void commitInsts();
106
107    bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
108
109    void getInsts();
110
111    void markCompletedInsts();
112
113  public:
114    uint64_t readCommitPC();
115
116    void setSquashing() { _status = ROBSquashing; }
117
118  private:
119    /** Time buffer interface. */
120    TimeBuffer<TimeStruct> *timeBuffer;
121
122    /** Wire to write information heading to previous stages. */
123    typename TimeBuffer<TimeStruct>::wire toIEW;
124
125    /** Wire to read information from IEW (for ROB). */
126    typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
127
128    /** IEW instruction queue interface. */
129    TimeBuffer<IEWStruct> *iewQueue;
130
131    /** Wire to read information from IEW queue. */
132    typename TimeBuffer<IEWStruct>::wire fromIEW;
133
134    /** Rename instruction queue interface, for ROB. */
135    TimeBuffer<RenameStruct> *renameQueue;
136
137    /** Wire to read information from rename queue. */
138    typename TimeBuffer<RenameStruct>::wire fromRename;
139
140    /** ROB interface. */
141    ROB *rob;
142
143    /** Pointer to FullCPU. */
144    FullCPU *cpu;
145
146    /** Memory interface.  Used for d-cache accesses. */
147    MemInterface *dcacheInterface;
148
149  private:
150    /** IEW to Commit delay, in ticks. */
151    unsigned iewToCommitDelay;
152
153    /** Rename to ROB delay, in ticks. */
154    unsigned renameToROBDelay;
155
156    /** Rename width, in instructions.  Used so ROB knows how many
157     *  instructions to get from the rename instruction queue.
158     */
159    unsigned renameWidth;
160
161    /** IEW width, in instructions.  Used so ROB knows how many
162     *  instructions to get from the IEW instruction queue.
163     */
164    unsigned iewWidth;
165
166    /** Commit width, in instructions. */
167    unsigned commitWidth;
168
169    Stats::Scalar<> commitCommittedInsts;
170    Stats::Scalar<> commitSquashedInsts;
171    Stats::Scalar<> commitSquashEvents;
172    Stats::Scalar<> commitNonSpecStalls;
173    Stats::Scalar<> commitCommittedBranches;
174    Stats::Scalar<> commitCommittedLoads;
175    Stats::Scalar<> commitCommittedMemRefs;
176    Stats::Scalar<> branchMispredicts;
177
178    Stats::Distribution<> n_committed_dist;
179};
180
181#endif // __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
182