commit.hh revision 11877
11689SN/A/* 210331Smitch.hayenga@arm.com * Copyright (c) 2010-2012, 2014 ARM Limited 37855SAli.Saidi@ARM.com * All rights reserved. 47855SAli.Saidi@ARM.com * 57855SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67855SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77855SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87855SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97855SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107855SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117855SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127855SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137855SAli.Saidi@ARM.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_COMMIT_HH__ 452292SN/A#define __CPU_O3_COMMIT_HH__ 461060SN/A 478230Snate@binkert.org#include <queue> 488230Snate@binkert.org 491461SN/A#include "base/statistics.hh" 502292SN/A#include "cpu/exetrace.hh" 512329SN/A#include "cpu/inst_seq.hh" 528229Snate@binkert.org#include "cpu/timebuf.hh" 5310023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh" 541060SN/A 558737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 565529Snate@binkert.org 572292SN/Atemplate <class> 588737Skoansin.tan@gmail.comstruct O3ThreadState; 592292SN/A 602292SN/A/** 612316SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 622316SN/A * specified by the parameters; each cycle it tries to commit that 632316SN/A * many instructions. The SMT policy decides which thread it tries to 642316SN/A * commit instructions from. Non- speculative instructions must reach 652316SN/A * the head of the ROB before they are ready to execute; once they 662316SN/A * reach the head, commit will broadcast the instruction's sequence 672316SN/A * number to the previous stages so that they can issue/ execute the 682316SN/A * instruction. Only one non-speculative instruction is handled per 692316SN/A * cycle. Commit is responsible for handling all back-end initiated 702316SN/A * redirects. It receives the redirect, and then broadcasts it to all 712316SN/A * stages, indicating the sequence number they should squash until, 722316SN/A * and any necessary branch misprediction information as well. It 732316SN/A * priortizes redirects by instruction's age, only broadcasting a 742316SN/A * redirect if it corresponds to an instruction that should currently 752316SN/A * be in the ROB. This is done by tracking the sequence number of the 762316SN/A * youngest instruction in the ROB, which gets updated to any 772316SN/A * squashing instruction's sequence number, and only broadcasting a 782316SN/A * redirect if it corresponds to an older instruction. Commit also 792316SN/A * supports multiple cycle squashing, to model a ROB that can only 802329SN/A * remove a certain number of instructions per cycle. 812292SN/A */ 821060SN/Atemplate<class Impl> 832292SN/Aclass DefaultCommit 841060SN/A{ 851060SN/A public: 861060SN/A // Typedefs from the Impl. 872733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 881061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 891061SN/A typedef typename Impl::CPUPol CPUPol; 901060SN/A 912292SN/A typedef typename CPUPol::RenameMap RenameMap; 921061SN/A typedef typename CPUPol::ROB ROB; 931060SN/A 941061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 952292SN/A typedef typename CPUPol::FetchStruct FetchStruct; 961061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 971061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 981060SN/A 992316SN/A typedef typename CPUPol::Fetch Fetch; 1002292SN/A typedef typename CPUPol::IEW IEW; 1012292SN/A 1022292SN/A typedef O3ThreadState<Impl> Thread; 1032292SN/A 1042348SN/A /** Event class used to schedule a squash due to a trap (fault or 1052348SN/A * interrupt) to happen on a specific cycle. 1062348SN/A */ 1072292SN/A class TrapEvent : public Event { 1082292SN/A private: 1092292SN/A DefaultCommit<Impl> *commit; 1106221Snate@binkert.org ThreadID tid; 1112292SN/A 1122292SN/A public: 1136221Snate@binkert.org TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 1142292SN/A 1152292SN/A void process(); 1165336Shines@cs.fsu.edu const char *description() const; 1172292SN/A }; 1182292SN/A 1192292SN/A /** Overall commit status. Used to determine if the CPU can deschedule 1202292SN/A * itself due to a lack of activity. 1212292SN/A */ 1222292SN/A enum CommitStatus{ 1232292SN/A Active, 1242292SN/A Inactive 1252292SN/A }; 1262292SN/A 1272292SN/A /** Individual thread status. */ 1282292SN/A enum ThreadStatus { 1291060SN/A Running, 1301060SN/A Idle, 1311060SN/A ROBSquashing, 1322292SN/A TrapPending, 1339437SAndreas.Sandberg@ARM.com FetchTrapPending, 1349437SAndreas.Sandberg@ARM.com SquashAfterPending, //< Committing instructions before a squash. 1352292SN/A }; 1362292SN/A 1372292SN/A /** Commit policy for SMT mode. */ 1382292SN/A enum CommitPolicy { 1392292SN/A Aggressive, 1402292SN/A RoundRobin, 1412292SN/A OldestReady 1421060SN/A }; 1431060SN/A 1441060SN/A private: 1452292SN/A /** Overall commit status. */ 1462292SN/A CommitStatus _status; 1472292SN/A /** Next commit status, to be set at the end of the cycle. */ 1482292SN/A CommitStatus _nextStatus; 1492292SN/A /** Per-thread status. */ 1502292SN/A ThreadStatus commitStatus[Impl::MaxThreads]; 1512292SN/A /** Commit policy used in SMT mode. */ 1522292SN/A CommitPolicy commitPolicy; 1531060SN/A 15410023Smatt.horsnell@ARM.com /** Probe Points. */ 15510023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppCommit; 15610023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppCommitStall; 15711246Sradhika.jagtap@ARM.com /** To probe when an instruction is squashed */ 15811246Sradhika.jagtap@ARM.com ProbePointArg<DynInstPtr> *ppSquash; 15910023Smatt.horsnell@ARM.com 1601060SN/A public: 1612292SN/A /** Construct a DefaultCommit with the given parameters. */ 1625529Snate@binkert.org DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 1631060SN/A 1642292SN/A /** Returns the name of the DefaultCommit. */ 1652292SN/A std::string name() const; 1662292SN/A 1672292SN/A /** Registers statistics. */ 1681062SN/A void regStats(); 1691062SN/A 17010023Smatt.horsnell@ARM.com /** Registers probes. */ 17110023Smatt.horsnell@ARM.com void regProbePoints(); 17210023Smatt.horsnell@ARM.com 1732292SN/A /** Sets the list of threads. */ 1742292SN/A void setThreads(std::vector<Thread *> &threads); 1752292SN/A 1762292SN/A /** Sets the main time buffer pointer, used for backwards communication. */ 1771060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1781060SN/A 1792292SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1802292SN/A 1812292SN/A /** Sets the pointer to the queue coming from rename. */ 1821060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1831060SN/A 1842292SN/A /** Sets the pointer to the queue coming from IEW. */ 1851060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1861060SN/A 1872348SN/A /** Sets the pointer to the IEW stage. */ 1882292SN/A void setIEWStage(IEW *iew_stage); 1892292SN/A 1902316SN/A /** The pointer to the IEW stage. Used solely to ensure that 1912316SN/A * various events (traps, interrupts, syscalls) do not occur until 1922316SN/A * all stores have written back. 1932292SN/A */ 1942292SN/A IEW *iewStage; 1952292SN/A 1962292SN/A /** Sets pointer to list of active threads. */ 1976221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1982292SN/A 1992292SN/A /** Sets pointer to the commited state rename map. */ 2002292SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 2012292SN/A 2022292SN/A /** Sets pointer to the ROB. */ 2031060SN/A void setROB(ROB *rob_ptr); 2041060SN/A 2052292SN/A /** Initializes stage by sending back the number of free entries. */ 2069427SAndreas.Sandberg@ARM.com void startupStage(); 2072292SN/A 2082843Sktlim@umich.edu /** Initializes the draining of commit. */ 2099444SAndreas.Sandberg@ARM.com void drain(); 2102843Sktlim@umich.edu 2112843Sktlim@umich.edu /** Resumes execution after draining. */ 2129444SAndreas.Sandberg@ARM.com void drainResume(); 2132307SN/A 2149444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 2159444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2169444SAndreas.Sandberg@ARM.com 2179444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 2189444SAndreas.Sandberg@ARM.com bool isDrained() const; 2192316SN/A 2202348SN/A /** Takes over from another CPU's thread. */ 2212307SN/A void takeOverFrom(); 2222307SN/A 22310331Smitch.hayenga@arm.com /** Deschedules a thread from scheduling */ 22410331Smitch.hayenga@arm.com void deactivateThread(ThreadID tid); 22510331Smitch.hayenga@arm.com 2262292SN/A /** Ticks the commit stage, which tries to commit instructions. */ 2271060SN/A void tick(); 2281060SN/A 2292292SN/A /** Handles any squashes that are sent from IEW, and adds instructions 2302292SN/A * to the ROB and tries to commit instructions. 2312292SN/A */ 2321060SN/A void commit(); 2331060SN/A 2342292SN/A /** Returns the number of free ROB entries for a specific thread. */ 2356221Snate@binkert.org size_t numROBFreeEntries(ThreadID tid); 2362292SN/A 2372348SN/A /** Generates an event to schedule a squash due to a trap. */ 23811877Sbrandon.potter@amd.com void generateTrapEvent(ThreadID tid, Fault inst_fault); 2392348SN/A 2402348SN/A /** Records that commit needs to initiate a squash due to an 2412680Sktlim@umich.edu * external state update through the TC. 2422348SN/A */ 2436221Snate@binkert.org void generateTCEvent(ThreadID tid); 2442292SN/A 2451060SN/A private: 2462292SN/A /** Updates the overall status of commit with the nextStatus, and 2472348SN/A * tell the CPU if commit is active/inactive. 2482348SN/A */ 2492292SN/A void updateStatus(); 2501060SN/A 2512292SN/A /** Returns if any of the threads have the number of ROB entries changed 2522292SN/A * on this cycle. Used to determine if the number of free ROB entries needs 2532292SN/A * to be sent back to previous stages. 2542292SN/A */ 2552292SN/A bool changedROBEntries(); 2562292SN/A 2572348SN/A /** Squashes all in flight instructions. */ 2586221Snate@binkert.org void squashAll(ThreadID tid); 2592316SN/A 2602348SN/A /** Handles squashing due to a trap. */ 2616221Snate@binkert.org void squashFromTrap(ThreadID tid); 2622292SN/A 2632680Sktlim@umich.edu /** Handles squashing due to an TC write. */ 2646221Snate@binkert.org void squashFromTC(ThreadID tid); 2652292SN/A 2669437SAndreas.Sandberg@ARM.com /** Handles a squash from a squashAfter() request. */ 2679437SAndreas.Sandberg@ARM.com void squashFromSquashAfter(ThreadID tid); 2689437SAndreas.Sandberg@ARM.com 2699437SAndreas.Sandberg@ARM.com /** 2709437SAndreas.Sandberg@ARM.com * Handle squashing from instruction with SquashAfter set. 2719437SAndreas.Sandberg@ARM.com * 2727784SAli.Saidi@ARM.com * This differs from the other squashes as it squashes following 2737784SAli.Saidi@ARM.com * instructions instead of the current instruction and doesn't 2749437SAndreas.Sandberg@ARM.com * clean up various status bits about traps/tc writes 2759437SAndreas.Sandberg@ARM.com * pending. Since there might have been instructions committed by 2769437SAndreas.Sandberg@ARM.com * the commit stage before the squashing instruction was reached 2779437SAndreas.Sandberg@ARM.com * and we can't commit and squash in the same cycle, we have to 2789437SAndreas.Sandberg@ARM.com * squash in two steps: 2799437SAndreas.Sandberg@ARM.com * 2809437SAndreas.Sandberg@ARM.com * <ol> 2819437SAndreas.Sandberg@ARM.com * <li>Immediately set the commit status of the thread of 2829437SAndreas.Sandberg@ARM.com * SquashAfterPending. This forces the thread to stop 2839437SAndreas.Sandberg@ARM.com * committing instructions in this cycle. The last 2849437SAndreas.Sandberg@ARM.com * instruction to be committed in this cycle will be the 2859437SAndreas.Sandberg@ARM.com * SquashAfter instruction. 2869437SAndreas.Sandberg@ARM.com * <li>In the next cycle, commit() checks for the 2879437SAndreas.Sandberg@ARM.com * SquashAfterPending state and squashes <i>all</i> 2889437SAndreas.Sandberg@ARM.com * in-flight instructions. Since the SquashAfter instruction 2899437SAndreas.Sandberg@ARM.com * was the last instruction to be committed in the previous 2909437SAndreas.Sandberg@ARM.com * cycle, this causes all subsequent instructions to be 2919437SAndreas.Sandberg@ARM.com * squashed. 2929437SAndreas.Sandberg@ARM.com * </ol> 2939437SAndreas.Sandberg@ARM.com * 2949437SAndreas.Sandberg@ARM.com * @param tid ID of the thread to squash. 2959437SAndreas.Sandberg@ARM.com * @param head_inst Instruction that requested the squash. 2967784SAli.Saidi@ARM.com */ 2979437SAndreas.Sandberg@ARM.com void squashAfter(ThreadID tid, DynInstPtr &head_inst); 2987784SAli.Saidi@ARM.com 2994035Sktlim@umich.edu /** Handles processing an interrupt. */ 3004035Sktlim@umich.edu void handleInterrupt(); 3017847Sminkyu.jeong@arm.com 3027847Sminkyu.jeong@arm.com /** Get fetch redirecting so we can handle an interrupt */ 3037847Sminkyu.jeong@arm.com void propagateInterrupt(); 3044035Sktlim@umich.edu 3052292SN/A /** Commits as many instructions as possible. */ 3061060SN/A void commitInsts(); 3071060SN/A 3082292SN/A /** Tries to commit the head ROB instruction passed in. 3092292SN/A * @param head_inst The instruction to be committed. 3102292SN/A */ 3111061SN/A bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 3121060SN/A 3132292SN/A /** Gets instructions from rename and inserts them into the ROB. */ 3141060SN/A void getInsts(); 3151060SN/A 3162292SN/A /** Marks completed instructions using information sent from IEW. */ 3171060SN/A void markCompletedInsts(); 3181060SN/A 3192292SN/A /** Gets the thread to commit, based on the SMT policy. */ 3206221Snate@binkert.org ThreadID getCommittingThread(); 3212292SN/A 3222292SN/A /** Returns the thread ID to use based on a round robin policy. */ 3236221Snate@binkert.org ThreadID roundRobin(); 3242292SN/A 3252292SN/A /** Returns the thread ID to use based on an oldest instruction policy. */ 3266221Snate@binkert.org ThreadID oldestReady(); 3272292SN/A 3281684SN/A public: 3297720Sgblack@eecs.umich.edu /** Reads the PC of a specific thread. */ 3307720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 3317720Sgblack@eecs.umich.edu 3327720Sgblack@eecs.umich.edu /** Sets the PC of a specific thread. */ 3337720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val, ThreadID tid) 3347720Sgblack@eecs.umich.edu { pc[tid] = val; } 3351684SN/A 3362348SN/A /** Returns the PC of a specific thread. */ 3377720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 3382292SN/A 3397720Sgblack@eecs.umich.edu /** Returns the next PC of a specific thread. */ 3407720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 3414636Sgblack@eecs.umich.edu 3424636Sgblack@eecs.umich.edu /** Reads the micro PC of a specific thread. */ 3437720Sgblack@eecs.umich.edu Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 3442756Sksewell@umich.edu 3451684SN/A private: 3461060SN/A /** Time buffer interface. */ 3471060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3481060SN/A 3491060SN/A /** Wire to write information heading to previous stages. */ 3501060SN/A typename TimeBuffer<TimeStruct>::wire toIEW; 3511060SN/A 3521060SN/A /** Wire to read information from IEW (for ROB). */ 3531060SN/A typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 3541060SN/A 3552292SN/A TimeBuffer<FetchStruct> *fetchQueue; 3562292SN/A 3572292SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 3582292SN/A 3591060SN/A /** IEW instruction queue interface. */ 3601060SN/A TimeBuffer<IEWStruct> *iewQueue; 3611060SN/A 3621060SN/A /** Wire to read information from IEW queue. */ 3631060SN/A typename TimeBuffer<IEWStruct>::wire fromIEW; 3641060SN/A 3651060SN/A /** Rename instruction queue interface, for ROB. */ 3661060SN/A TimeBuffer<RenameStruct> *renameQueue; 3671060SN/A 3681060SN/A /** Wire to read information from rename queue. */ 3691060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3701060SN/A 3712292SN/A public: 3721060SN/A /** ROB interface. */ 3731060SN/A ROB *rob; 3741060SN/A 3752292SN/A private: 3762733Sktlim@umich.edu /** Pointer to O3CPU. */ 3772733Sktlim@umich.edu O3CPU *cpu; 3781060SN/A 3792348SN/A /** Vector of all of the threads. */ 3802292SN/A std::vector<Thread *> thread; 3811060SN/A 3822292SN/A /** Records that commit has written to the time buffer this cycle. Used for 3832292SN/A * the CPU to determine if it can deschedule itself if there is no activity. 3842292SN/A */ 3852292SN/A bool wroteToTimeBuffer; 3862292SN/A 3872292SN/A /** Records if the number of ROB entries has changed this cycle. If it has, 3882292SN/A * then the number of free entries must be re-broadcast. 3892292SN/A */ 3902292SN/A bool changedROBNumEntries[Impl::MaxThreads]; 3912292SN/A 3922292SN/A /** Records if a thread has to squash this cycle due to a trap. */ 3932292SN/A bool trapSquash[Impl::MaxThreads]; 3942292SN/A 3952292SN/A /** Records if a thread has to squash this cycle due to an XC write. */ 3962680Sktlim@umich.edu bool tcSquash[Impl::MaxThreads]; 3972292SN/A 3989437SAndreas.Sandberg@ARM.com /** 3999437SAndreas.Sandberg@ARM.com * Instruction passed to squashAfter(). 4009437SAndreas.Sandberg@ARM.com * 4019437SAndreas.Sandberg@ARM.com * The squash after implementation needs to buffer the instruction 4029437SAndreas.Sandberg@ARM.com * that caused a squash since this needs to be passed to the fetch 4039437SAndreas.Sandberg@ARM.com * stage once squashing starts. 4049437SAndreas.Sandberg@ARM.com */ 4059437SAndreas.Sandberg@ARM.com DynInstPtr squashAfterInst[Impl::MaxThreads]; 4069437SAndreas.Sandberg@ARM.com 4072292SN/A /** Priority List used for Commit Policy */ 4086221Snate@binkert.org std::list<ThreadID> priority_list; 4092292SN/A 4109184Sandreas.hansson@arm.com /** IEW to Commit delay. */ 41110732Snilay@cs.wisc.edu const Cycles iewToCommitDelay; 4121060SN/A 4139184Sandreas.hansson@arm.com /** Commit to IEW delay. */ 41410732Snilay@cs.wisc.edu const Cycles commitToIEWDelay; 4152292SN/A 4169184Sandreas.hansson@arm.com /** Rename to ROB delay. */ 41710732Snilay@cs.wisc.edu const Cycles renameToROBDelay; 4181060SN/A 41910732Snilay@cs.wisc.edu const Cycles fetchToCommitDelay; 4202292SN/A 4211060SN/A /** Rename width, in instructions. Used so ROB knows how many 4221060SN/A * instructions to get from the rename instruction queue. 4231060SN/A */ 42410732Snilay@cs.wisc.edu const unsigned renameWidth; 4251060SN/A 4261060SN/A /** Commit width, in instructions. */ 42710732Snilay@cs.wisc.edu const unsigned commitWidth; 4281062SN/A 4292292SN/A /** Number of Reorder Buffers */ 4302292SN/A unsigned numRobs; 4312292SN/A 4322292SN/A /** Number of Active Threads */ 43310732Snilay@cs.wisc.edu const ThreadID numThreads; 4342292SN/A 43510340Smitch.hayenga@arm.com /** Is a drain pending? Commit is looking for an instruction boundary while 43610340Smitch.hayenga@arm.com * there are no pending interrupts 43710340Smitch.hayenga@arm.com */ 4382843Sktlim@umich.edu bool drainPending; 4392348SN/A 44010340Smitch.hayenga@arm.com /** Is a drain imminent? Commit has found an instruction boundary while no 44110340Smitch.hayenga@arm.com * interrupts were present or in flight. This was the last architecturally 44210340Smitch.hayenga@arm.com * committed instruction. Interrupts disabled and pipeline flushed. 44310340Smitch.hayenga@arm.com * Waiting for structures to finish draining. 44410340Smitch.hayenga@arm.com */ 44510340Smitch.hayenga@arm.com bool drainImminent; 44610340Smitch.hayenga@arm.com 4472348SN/A /** The latency to handle a trap. Used when scheduling trap 4482348SN/A * squash event. 4492348SN/A */ 45010732Snilay@cs.wisc.edu const Cycles trapLatency; 4512292SN/A 4523640Sktlim@umich.edu /** The interrupt fault. */ 4533640Sktlim@umich.edu Fault interrupt; 4543640Sktlim@umich.edu 4557720Sgblack@eecs.umich.edu /** The commit PC state of each thread. Refers to the instruction that 4562348SN/A * is currently being processed/committed. 4572348SN/A */ 4587720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4594636Sgblack@eecs.umich.edu 4602292SN/A /** The sequence number of the youngest valid instruction in the ROB. */ 4612292SN/A InstSeqNum youngestSeqNum[Impl::MaxThreads]; 4622292SN/A 4637855SAli.Saidi@ARM.com /** The sequence number of the last commited instruction. */ 4647855SAli.Saidi@ARM.com InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 4657855SAli.Saidi@ARM.com 4664035Sktlim@umich.edu /** Records if there is a trap currently in flight. */ 4674035Sktlim@umich.edu bool trapInFlight[Impl::MaxThreads]; 4684035Sktlim@umich.edu 4694035Sktlim@umich.edu /** Records if there were any stores committed this cycle. */ 4704035Sktlim@umich.edu bool committedStores[Impl::MaxThreads]; 4714035Sktlim@umich.edu 4724035Sktlim@umich.edu /** Records if commit should check if the ROB is truly empty (see 4734035Sktlim@umich.edu commit_impl.hh). */ 4744035Sktlim@umich.edu bool checkEmptyROB[Impl::MaxThreads]; 4754035Sktlim@umich.edu 4762292SN/A /** Pointer to the list of active threads. */ 4776221Snate@binkert.org std::list<ThreadID> *activeThreads; 4782292SN/A 4792292SN/A /** Rename map interface. */ 4802292SN/A RenameMap *renameMap[Impl::MaxThreads]; 4812292SN/A 4828823Snilay@cs.wisc.edu /** True if last committed microop can be followed by an interrupt */ 4838823Snilay@cs.wisc.edu bool canHandleInterrupts; 4848823Snilay@cs.wisc.edu 4859513SAli.Saidi@ARM.com /** Have we had an interrupt pending and then seen it de-asserted because 4869513SAli.Saidi@ARM.com of a masking change? In this case the variable is set and the next time 4879513SAli.Saidi@ARM.com interrupts are enabled and pending the pipeline will squash to avoid 4889513SAli.Saidi@ARM.com a possible livelock senario. */ 4899513SAli.Saidi@ARM.com bool avoidQuiesceLiveLock; 4909513SAli.Saidi@ARM.com 4912348SN/A /** Updates commit stats based on this instruction. */ 4922301SN/A void updateComInstStats(DynInstPtr &inst); 4932301SN/A 4942292SN/A /** Stat for the total number of squashed instructions discarded by commit. 4952292SN/A */ 4965999Snate@binkert.org Stats::Scalar commitSquashedInsts; 4972292SN/A /** Stat for the total number of times commit has had to stall due to a non- 4982292SN/A * speculative instruction reaching the head of the ROB. 4992292SN/A */ 5005999Snate@binkert.org Stats::Scalar commitNonSpecStalls; 5012292SN/A /** Stat for the total number of branch mispredicts that caused a squash. */ 5025999Snate@binkert.org Stats::Scalar branchMispredicts; 5032292SN/A /** Distribution of the number of committed instructions each cycle. */ 5045999Snate@binkert.org Stats::Distribution numCommittedDist; 5051062SN/A 5062316SN/A /** Total number of instructions committed. */ 5078834Satgutier@umich.edu Stats::Vector instsCommitted; 5088834Satgutier@umich.edu /** Total number of ops (including micro ops) committed. */ 5098834Satgutier@umich.edu Stats::Vector opsCommitted; 5102316SN/A /** Total number of software prefetches committed. */ 5115999Snate@binkert.org Stats::Vector statComSwp; 5122316SN/A /** Stat for the total number of committed memory references. */ 5135999Snate@binkert.org Stats::Vector statComRefs; 5142316SN/A /** Stat for the total number of committed loads. */ 5155999Snate@binkert.org Stats::Vector statComLoads; 5162316SN/A /** Total number of committed memory barriers. */ 5175999Snate@binkert.org Stats::Vector statComMembars; 5182316SN/A /** Total number of committed branches. */ 5195999Snate@binkert.org Stats::Vector statComBranches; 5207897Shestness@cs.utexas.edu /** Total number of floating point instructions */ 5217897Shestness@cs.utexas.edu Stats::Vector statComFloating; 5227897Shestness@cs.utexas.edu /** Total number of integer instructions */ 5237897Shestness@cs.utexas.edu Stats::Vector statComInteger; 5247897Shestness@cs.utexas.edu /** Total number of function calls */ 5257897Shestness@cs.utexas.edu Stats::Vector statComFunctionCalls; 52610193SCurtis.Dunham@arm.com /** Committed instructions by instruction type (OpClass) */ 52710193SCurtis.Dunham@arm.com Stats::Vector2d statCommittedInstType; 5282301SN/A 5292348SN/A /** Number of cycles where the commit bandwidth limit is reached. */ 5305999Snate@binkert.org Stats::Scalar commitEligibleSamples; 5311060SN/A}; 5321060SN/A 5332292SN/A#endif // __CPU_O3_COMMIT_HH__ 534