commit.hh revision 1060 
1// Todo: Squash properly.  Have commit be able to send a squash signal
2// to previous stages; will be needed when trap() is implemented.
3// Maybe have a special method for handling interrupts/traps.
4//
5// Traps:  Have IEW send a signal to commit saying that there's a trap to
6// be handled.  Have commit send the PC back to the fetch stage, along
7// with the current commit PC.  Fetch will directly access the IPR and save
8// off all the proper stuff.  Commit can send out a squash, or something
9// close to it.
10// Do the same for hwrei().  However, requires that commit be specifically
11// built to support that kind of stuff.  Probably not horrible to have
12// commit support having the CPU tell it to squash the other stages and
13// restart at a given address.  The IPR register does become an issue.
14// Probably not a big deal if the IPR stuff isn't cycle accurate.  Can just
15// have the original function handle writing to the IPR register.
16
17#ifndef __SIMPLE_COMMIT_HH__
18#define __SIMPLE_COMMIT_HH__
19
20//Includes: ROB, time buffer, structs, memory interface
21#include "arch/alpha/isa_traits.hh"
22#include "base/timebuf.hh"
23#include "cpu/beta_cpu/comm.hh"
24#include "cpu/beta_cpu/rename_map.hh"
25#include "cpu/beta_cpu/rob.hh"
26#include "mem/memory_interface.hh"
27
28template<class Impl>
29class SimpleCommit
30{
31  public:
32    // Typedefs from the Impl.
33    typedef typename Impl::ISA ISA;
34    typedef typename Impl::FullCPU FullCPU;
35    typedef typename Impl::DynInst DynInst;
36    typedef typename Impl::Params Params;
37
38    typedef typename Impl::CPUPol::ROB ROB;
39
40    typedef typename Impl::TimeStruct TimeStruct;
41    typedef typename Impl::IEWStruct IEWStruct;
42    typedef typename Impl::RenameStruct RenameStruct;
43
44  public:
45    // I don't believe commit can block, so it will only have two
46    // statuses for now.
47    // Actually if there's a cache access that needs to block (ie
48    // uncachable load or just a mem access in commit) then the stage
49    // may have to wait.
50    enum Status {
51        Running,
52        Idle,
53        ROBSquashing,
54        DcacheMissStall,
55        DcacheMissComplete
56    };
57
58  private:
59    Status _status;
60
61  public:
62    SimpleCommit(Params &params);
63
64    void setCPU(FullCPU *cpu_ptr);
65
66    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
67
68    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
69
70    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
71
72    void setROB(ROB *rob_ptr);
73
74    void tick();
75
76    void commit();
77
78    uint64_t readCommitPC();
79
80    void setSquashing() { _status = ROBSquashing; }
81
82  private:
83
84    void commitInsts();
85
86    bool commitHead(DynInst *head_inst, unsigned inst_num);
87
88    void getInsts();
89
90    void markCompletedInsts();
91
92    /** Time buffer interface. */
93    TimeBuffer<TimeStruct> *timeBuffer;
94
95    /** Wire to write information heading to previous stages. */
96    typename TimeBuffer<TimeStruct>::wire toIEW;
97
98    /** Wire to read information from IEW (for ROB). */
99    typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
100
101    /** IEW instruction queue interface. */
102    TimeBuffer<IEWStruct> *iewQueue;
103
104    /** Wire to read information from IEW queue. */
105    typename TimeBuffer<IEWStruct>::wire fromIEW;
106
107    /** Rename instruction queue interface, for ROB. */
108    TimeBuffer<RenameStruct> *renameQueue;
109
110    /** Wire to read information from rename queue. */
111    typename TimeBuffer<RenameStruct>::wire fromRename;
112
113    /** ROB interface. */
114    ROB *rob;
115
116    /** Pointer to FullCPU. */
117    FullCPU *cpu;
118
119    /** Pointer to the rename map.  DO NOT USE if possible. */
120    typename Impl::CPUPol::RenameMap *renameMap;
121
122    //Store buffer interface?  Will need to move committed stores to the
123    //store buffer
124
125    /** Memory interface.  Used for d-cache accesses. */
126    MemInterface *dcacheInterface;
127
128  private:
129    /** IEW to Commit delay, in ticks. */
130    unsigned iewToCommitDelay;
131
132    /** Rename to ROB delay, in ticks. */
133    unsigned renameToROBDelay;
134
135    /** Rename width, in instructions.  Used so ROB knows how many
136     *  instructions to get from the rename instruction queue.
137     */
138    unsigned renameWidth;
139
140    /** IEW width, in instructions.  Used so ROB knows how many
141     *  instructions to get from the IEW instruction queue.
142     */
143    unsigned iewWidth;
144
145    /** Commit width, in instructions. */
146    unsigned commitWidth;
147};
148
149#endif // __SIMPLE_COMMIT_HH__
150