commit.hh revision 10023
11689SN/A/* 29437SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 37855SAli.Saidi@ARM.com * All rights reserved. 47855SAli.Saidi@ARM.com * 57855SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67855SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77855SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87855SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97855SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107855SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117855SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127855SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137855SAli.Saidi@ARM.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_COMMIT_HH__ 452292SN/A#define __CPU_O3_COMMIT_HH__ 461060SN/A 478230Snate@binkert.org#include <queue> 488230Snate@binkert.org 491461SN/A#include "base/statistics.hh" 502292SN/A#include "cpu/exetrace.hh" 512329SN/A#include "cpu/inst_seq.hh" 528229Snate@binkert.org#include "cpu/timebuf.hh" 5310023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh" 541060SN/A 558737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 565529Snate@binkert.org 572292SN/Atemplate <class> 588737Skoansin.tan@gmail.comstruct O3ThreadState; 592292SN/A 602292SN/A/** 612316SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 622316SN/A * specified by the parameters; each cycle it tries to commit that 632316SN/A * many instructions. The SMT policy decides which thread it tries to 642316SN/A * commit instructions from. Non- speculative instructions must reach 652316SN/A * the head of the ROB before they are ready to execute; once they 662316SN/A * reach the head, commit will broadcast the instruction's sequence 672316SN/A * number to the previous stages so that they can issue/ execute the 682316SN/A * instruction. Only one non-speculative instruction is handled per 692316SN/A * cycle. Commit is responsible for handling all back-end initiated 702316SN/A * redirects. It receives the redirect, and then broadcasts it to all 712316SN/A * stages, indicating the sequence number they should squash until, 722316SN/A * and any necessary branch misprediction information as well. It 732316SN/A * priortizes redirects by instruction's age, only broadcasting a 742316SN/A * redirect if it corresponds to an instruction that should currently 752316SN/A * be in the ROB. This is done by tracking the sequence number of the 762316SN/A * youngest instruction in the ROB, which gets updated to any 772316SN/A * squashing instruction's sequence number, and only broadcasting a 782316SN/A * redirect if it corresponds to an older instruction. Commit also 792316SN/A * supports multiple cycle squashing, to model a ROB that can only 802329SN/A * remove a certain number of instructions per cycle. 812292SN/A */ 821060SN/Atemplate<class Impl> 832292SN/Aclass DefaultCommit 841060SN/A{ 851060SN/A public: 861060SN/A // Typedefs from the Impl. 872733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 881061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 891061SN/A typedef typename Impl::CPUPol CPUPol; 901060SN/A 912292SN/A typedef typename CPUPol::RenameMap RenameMap; 921061SN/A typedef typename CPUPol::ROB ROB; 931060SN/A 941061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 952292SN/A typedef typename CPUPol::FetchStruct FetchStruct; 961061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 971061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 981060SN/A 992316SN/A typedef typename CPUPol::Fetch Fetch; 1002292SN/A typedef typename CPUPol::IEW IEW; 1012292SN/A 1022292SN/A typedef O3ThreadState<Impl> Thread; 1032292SN/A 1042348SN/A /** Event class used to schedule a squash due to a trap (fault or 1052348SN/A * interrupt) to happen on a specific cycle. 1062348SN/A */ 1072292SN/A class TrapEvent : public Event { 1082292SN/A private: 1092292SN/A DefaultCommit<Impl> *commit; 1106221Snate@binkert.org ThreadID tid; 1112292SN/A 1122292SN/A public: 1136221Snate@binkert.org TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); 1142292SN/A 1152292SN/A void process(); 1165336Shines@cs.fsu.edu const char *description() const; 1172292SN/A }; 1182292SN/A 1192292SN/A /** Overall commit status. Used to determine if the CPU can deschedule 1202292SN/A * itself due to a lack of activity. 1212292SN/A */ 1222292SN/A enum CommitStatus{ 1232292SN/A Active, 1242292SN/A Inactive 1252292SN/A }; 1262292SN/A 1272292SN/A /** Individual thread status. */ 1282292SN/A enum ThreadStatus { 1291060SN/A Running, 1301060SN/A Idle, 1311060SN/A ROBSquashing, 1322292SN/A TrapPending, 1339437SAndreas.Sandberg@ARM.com FetchTrapPending, 1349437SAndreas.Sandberg@ARM.com SquashAfterPending, //< Committing instructions before a squash. 1352292SN/A }; 1362292SN/A 1372292SN/A /** Commit policy for SMT mode. */ 1382292SN/A enum CommitPolicy { 1392292SN/A Aggressive, 1402292SN/A RoundRobin, 1412292SN/A OldestReady 1421060SN/A }; 1431060SN/A 1441060SN/A private: 1452292SN/A /** Overall commit status. */ 1462292SN/A CommitStatus _status; 1472292SN/A /** Next commit status, to be set at the end of the cycle. */ 1482292SN/A CommitStatus _nextStatus; 1492292SN/A /** Per-thread status. */ 1502292SN/A ThreadStatus commitStatus[Impl::MaxThreads]; 1512292SN/A /** Commit policy used in SMT mode. */ 1522292SN/A CommitPolicy commitPolicy; 1531060SN/A 15410023Smatt.horsnell@ARM.com /** Probe Points. */ 15510023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppCommit; 15610023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppCommitStall; 15710023Smatt.horsnell@ARM.com 1581060SN/A public: 1592292SN/A /** Construct a DefaultCommit with the given parameters. */ 1605529Snate@binkert.org DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 1611060SN/A 1622292SN/A /** Returns the name of the DefaultCommit. */ 1632292SN/A std::string name() const; 1642292SN/A 1652292SN/A /** Registers statistics. */ 1661062SN/A void regStats(); 1671062SN/A 16810023Smatt.horsnell@ARM.com /** Registers probes. */ 16910023Smatt.horsnell@ARM.com void regProbePoints(); 17010023Smatt.horsnell@ARM.com 1712292SN/A /** Sets the list of threads. */ 1722292SN/A void setThreads(std::vector<Thread *> &threads); 1732292SN/A 1742292SN/A /** Sets the main time buffer pointer, used for backwards communication. */ 1751060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1761060SN/A 1772292SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1782292SN/A 1792292SN/A /** Sets the pointer to the queue coming from rename. */ 1801060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1811060SN/A 1822292SN/A /** Sets the pointer to the queue coming from IEW. */ 1831060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1841060SN/A 1852348SN/A /** Sets the pointer to the IEW stage. */ 1862292SN/A void setIEWStage(IEW *iew_stage); 1872292SN/A 1882965Sksewell@umich.edu /** Skid buffer between rename and commit. */ 1892965Sksewell@umich.edu std::queue<DynInstPtr> skidBuffer; 1902965Sksewell@umich.edu 1912316SN/A /** The pointer to the IEW stage. Used solely to ensure that 1922316SN/A * various events (traps, interrupts, syscalls) do not occur until 1932316SN/A * all stores have written back. 1942292SN/A */ 1952292SN/A IEW *iewStage; 1962292SN/A 1972292SN/A /** Sets pointer to list of active threads. */ 1986221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1992292SN/A 2002292SN/A /** Sets pointer to the commited state rename map. */ 2012292SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 2022292SN/A 2032292SN/A /** Sets pointer to the ROB. */ 2041060SN/A void setROB(ROB *rob_ptr); 2051060SN/A 2062292SN/A /** Initializes stage by sending back the number of free entries. */ 2079427SAndreas.Sandberg@ARM.com void startupStage(); 2082292SN/A 2092843Sktlim@umich.edu /** Initializes the draining of commit. */ 2109444SAndreas.Sandberg@ARM.com void drain(); 2112843Sktlim@umich.edu 2122843Sktlim@umich.edu /** Resumes execution after draining. */ 2139444SAndreas.Sandberg@ARM.com void drainResume(); 2142307SN/A 2159444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 2169444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2179444SAndreas.Sandberg@ARM.com 2189444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 2199444SAndreas.Sandberg@ARM.com bool isDrained() const; 2202316SN/A 2212348SN/A /** Takes over from another CPU's thread. */ 2222307SN/A void takeOverFrom(); 2232307SN/A 2242292SN/A /** Ticks the commit stage, which tries to commit instructions. */ 2251060SN/A void tick(); 2261060SN/A 2272292SN/A /** Handles any squashes that are sent from IEW, and adds instructions 2282292SN/A * to the ROB and tries to commit instructions. 2292292SN/A */ 2301060SN/A void commit(); 2311060SN/A 2322292SN/A /** Returns the number of free ROB entries for a specific thread. */ 2336221Snate@binkert.org size_t numROBFreeEntries(ThreadID tid); 2342292SN/A 2352348SN/A /** Generates an event to schedule a squash due to a trap. */ 2366221Snate@binkert.org void generateTrapEvent(ThreadID tid); 2372348SN/A 2382348SN/A /** Records that commit needs to initiate a squash due to an 2392680Sktlim@umich.edu * external state update through the TC. 2402348SN/A */ 2416221Snate@binkert.org void generateTCEvent(ThreadID tid); 2422292SN/A 2431060SN/A private: 2442292SN/A /** Updates the overall status of commit with the nextStatus, and 2452348SN/A * tell the CPU if commit is active/inactive. 2462348SN/A */ 2472292SN/A void updateStatus(); 2481060SN/A 2492292SN/A /** Sets the next status based on threads' statuses, which becomes the 2502292SN/A * current status at the end of the cycle. 2512292SN/A */ 2522292SN/A void setNextStatus(); 2532292SN/A 2542292SN/A /** Checks if the ROB is completed with squashing. This is for the case 2552292SN/A * where the ROB can take multiple cycles to complete squashing. 2562292SN/A */ 2572292SN/A bool robDoneSquashing(); 2582292SN/A 2592292SN/A /** Returns if any of the threads have the number of ROB entries changed 2602292SN/A * on this cycle. Used to determine if the number of free ROB entries needs 2612292SN/A * to be sent back to previous stages. 2622292SN/A */ 2632292SN/A bool changedROBEntries(); 2642292SN/A 2652348SN/A /** Squashes all in flight instructions. */ 2666221Snate@binkert.org void squashAll(ThreadID tid); 2672316SN/A 2682348SN/A /** Handles squashing due to a trap. */ 2696221Snate@binkert.org void squashFromTrap(ThreadID tid); 2702292SN/A 2712680Sktlim@umich.edu /** Handles squashing due to an TC write. */ 2726221Snate@binkert.org void squashFromTC(ThreadID tid); 2732292SN/A 2749437SAndreas.Sandberg@ARM.com /** Handles a squash from a squashAfter() request. */ 2759437SAndreas.Sandberg@ARM.com void squashFromSquashAfter(ThreadID tid); 2769437SAndreas.Sandberg@ARM.com 2779437SAndreas.Sandberg@ARM.com /** 2789437SAndreas.Sandberg@ARM.com * Handle squashing from instruction with SquashAfter set. 2799437SAndreas.Sandberg@ARM.com * 2807784SAli.Saidi@ARM.com * This differs from the other squashes as it squashes following 2817784SAli.Saidi@ARM.com * instructions instead of the current instruction and doesn't 2829437SAndreas.Sandberg@ARM.com * clean up various status bits about traps/tc writes 2839437SAndreas.Sandberg@ARM.com * pending. Since there might have been instructions committed by 2849437SAndreas.Sandberg@ARM.com * the commit stage before the squashing instruction was reached 2859437SAndreas.Sandberg@ARM.com * and we can't commit and squash in the same cycle, we have to 2869437SAndreas.Sandberg@ARM.com * squash in two steps: 2879437SAndreas.Sandberg@ARM.com * 2889437SAndreas.Sandberg@ARM.com * <ol> 2899437SAndreas.Sandberg@ARM.com * <li>Immediately set the commit status of the thread of 2909437SAndreas.Sandberg@ARM.com * SquashAfterPending. This forces the thread to stop 2919437SAndreas.Sandberg@ARM.com * committing instructions in this cycle. The last 2929437SAndreas.Sandberg@ARM.com * instruction to be committed in this cycle will be the 2939437SAndreas.Sandberg@ARM.com * SquashAfter instruction. 2949437SAndreas.Sandberg@ARM.com * <li>In the next cycle, commit() checks for the 2959437SAndreas.Sandberg@ARM.com * SquashAfterPending state and squashes <i>all</i> 2969437SAndreas.Sandberg@ARM.com * in-flight instructions. Since the SquashAfter instruction 2979437SAndreas.Sandberg@ARM.com * was the last instruction to be committed in the previous 2989437SAndreas.Sandberg@ARM.com * cycle, this causes all subsequent instructions to be 2999437SAndreas.Sandberg@ARM.com * squashed. 3009437SAndreas.Sandberg@ARM.com * </ol> 3019437SAndreas.Sandberg@ARM.com * 3029437SAndreas.Sandberg@ARM.com * @param tid ID of the thread to squash. 3039437SAndreas.Sandberg@ARM.com * @param head_inst Instruction that requested the squash. 3047784SAli.Saidi@ARM.com */ 3059437SAndreas.Sandberg@ARM.com void squashAfter(ThreadID tid, DynInstPtr &head_inst); 3067784SAli.Saidi@ARM.com 3074035Sktlim@umich.edu /** Handles processing an interrupt. */ 3084035Sktlim@umich.edu void handleInterrupt(); 3097847Sminkyu.jeong@arm.com 3107847Sminkyu.jeong@arm.com /** Get fetch redirecting so we can handle an interrupt */ 3117847Sminkyu.jeong@arm.com void propagateInterrupt(); 3124035Sktlim@umich.edu 3132292SN/A /** Commits as many instructions as possible. */ 3141060SN/A void commitInsts(); 3151060SN/A 3162292SN/A /** Tries to commit the head ROB instruction passed in. 3172292SN/A * @param head_inst The instruction to be committed. 3182292SN/A */ 3191061SN/A bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 3201060SN/A 3212292SN/A /** Gets instructions from rename and inserts them into the ROB. */ 3221060SN/A void getInsts(); 3231060SN/A 3242965Sksewell@umich.edu /** Insert all instructions from rename into skidBuffer */ 3252965Sksewell@umich.edu void skidInsert(); 3262965Sksewell@umich.edu 3272292SN/A /** Marks completed instructions using information sent from IEW. */ 3281060SN/A void markCompletedInsts(); 3291060SN/A 3302292SN/A /** Gets the thread to commit, based on the SMT policy. */ 3316221Snate@binkert.org ThreadID getCommittingThread(); 3322292SN/A 3332292SN/A /** Returns the thread ID to use based on a round robin policy. */ 3346221Snate@binkert.org ThreadID roundRobin(); 3352292SN/A 3362292SN/A /** Returns the thread ID to use based on an oldest instruction policy. */ 3376221Snate@binkert.org ThreadID oldestReady(); 3382292SN/A 3391684SN/A public: 3407720Sgblack@eecs.umich.edu /** Reads the PC of a specific thread. */ 3417720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 3427720Sgblack@eecs.umich.edu 3437720Sgblack@eecs.umich.edu /** Sets the PC of a specific thread. */ 3447720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val, ThreadID tid) 3457720Sgblack@eecs.umich.edu { pc[tid] = val; } 3461684SN/A 3472348SN/A /** Returns the PC of a specific thread. */ 3487720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 3492292SN/A 3507720Sgblack@eecs.umich.edu /** Returns the next PC of a specific thread. */ 3517720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 3524636Sgblack@eecs.umich.edu 3534636Sgblack@eecs.umich.edu /** Reads the micro PC of a specific thread. */ 3547720Sgblack@eecs.umich.edu Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 3552756Sksewell@umich.edu 3561684SN/A private: 3571060SN/A /** Time buffer interface. */ 3581060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3591060SN/A 3601060SN/A /** Wire to write information heading to previous stages. */ 3611060SN/A typename TimeBuffer<TimeStruct>::wire toIEW; 3621060SN/A 3631060SN/A /** Wire to read information from IEW (for ROB). */ 3641060SN/A typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 3651060SN/A 3662292SN/A TimeBuffer<FetchStruct> *fetchQueue; 3672292SN/A 3682292SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 3692292SN/A 3701060SN/A /** IEW instruction queue interface. */ 3711060SN/A TimeBuffer<IEWStruct> *iewQueue; 3721060SN/A 3731060SN/A /** Wire to read information from IEW queue. */ 3741060SN/A typename TimeBuffer<IEWStruct>::wire fromIEW; 3751060SN/A 3761060SN/A /** Rename instruction queue interface, for ROB. */ 3771060SN/A TimeBuffer<RenameStruct> *renameQueue; 3781060SN/A 3791060SN/A /** Wire to read information from rename queue. */ 3801060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3811060SN/A 3822292SN/A public: 3831060SN/A /** ROB interface. */ 3841060SN/A ROB *rob; 3851060SN/A 3862292SN/A private: 3872733Sktlim@umich.edu /** Pointer to O3CPU. */ 3882733Sktlim@umich.edu O3CPU *cpu; 3891060SN/A 3902348SN/A /** Vector of all of the threads. */ 3912292SN/A std::vector<Thread *> thread; 3921060SN/A 3932292SN/A /** Records that commit has written to the time buffer this cycle. Used for 3942292SN/A * the CPU to determine if it can deschedule itself if there is no activity. 3952292SN/A */ 3962292SN/A bool wroteToTimeBuffer; 3972292SN/A 3982292SN/A /** Records if the number of ROB entries has changed this cycle. If it has, 3992292SN/A * then the number of free entries must be re-broadcast. 4002292SN/A */ 4012292SN/A bool changedROBNumEntries[Impl::MaxThreads]; 4022292SN/A 4032292SN/A /** A counter of how many threads are currently squashing. */ 4046221Snate@binkert.org ThreadID squashCounter; 4052292SN/A 4062292SN/A /** Records if a thread has to squash this cycle due to a trap. */ 4072292SN/A bool trapSquash[Impl::MaxThreads]; 4082292SN/A 4092292SN/A /** Records if a thread has to squash this cycle due to an XC write. */ 4102680Sktlim@umich.edu bool tcSquash[Impl::MaxThreads]; 4112292SN/A 4129437SAndreas.Sandberg@ARM.com /** 4139437SAndreas.Sandberg@ARM.com * Instruction passed to squashAfter(). 4149437SAndreas.Sandberg@ARM.com * 4159437SAndreas.Sandberg@ARM.com * The squash after implementation needs to buffer the instruction 4169437SAndreas.Sandberg@ARM.com * that caused a squash since this needs to be passed to the fetch 4179437SAndreas.Sandberg@ARM.com * stage once squashing starts. 4189437SAndreas.Sandberg@ARM.com */ 4199437SAndreas.Sandberg@ARM.com DynInstPtr squashAfterInst[Impl::MaxThreads]; 4209437SAndreas.Sandberg@ARM.com 4212292SN/A /** Priority List used for Commit Policy */ 4226221Snate@binkert.org std::list<ThreadID> priority_list; 4232292SN/A 4249184Sandreas.hansson@arm.com /** IEW to Commit delay. */ 4259184Sandreas.hansson@arm.com Cycles iewToCommitDelay; 4261060SN/A 4279184Sandreas.hansson@arm.com /** Commit to IEW delay. */ 4289184Sandreas.hansson@arm.com Cycles commitToIEWDelay; 4292292SN/A 4309184Sandreas.hansson@arm.com /** Rename to ROB delay. */ 4319184Sandreas.hansson@arm.com Cycles renameToROBDelay; 4321060SN/A 4339184Sandreas.hansson@arm.com Cycles fetchToCommitDelay; 4342292SN/A 4351060SN/A /** Rename width, in instructions. Used so ROB knows how many 4361060SN/A * instructions to get from the rename instruction queue. 4371060SN/A */ 4381060SN/A unsigned renameWidth; 4391060SN/A 4401060SN/A /** Commit width, in instructions. */ 4411060SN/A unsigned commitWidth; 4421062SN/A 4432292SN/A /** Number of Reorder Buffers */ 4442292SN/A unsigned numRobs; 4452292SN/A 4462292SN/A /** Number of Active Threads */ 4476221Snate@binkert.org ThreadID numThreads; 4482292SN/A 4492843Sktlim@umich.edu /** Is a drain pending. */ 4502843Sktlim@umich.edu bool drainPending; 4512348SN/A 4522348SN/A /** The latency to handle a trap. Used when scheduling trap 4532348SN/A * squash event. 4542348SN/A */ 4559180Sandreas.hansson@arm.com Cycles trapLatency; 4562292SN/A 4573640Sktlim@umich.edu /** The interrupt fault. */ 4583640Sktlim@umich.edu Fault interrupt; 4593640Sktlim@umich.edu 4607720Sgblack@eecs.umich.edu /** The commit PC state of each thread. Refers to the instruction that 4612348SN/A * is currently being processed/committed. 4622348SN/A */ 4637720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4644636Sgblack@eecs.umich.edu 4652292SN/A /** The sequence number of the youngest valid instruction in the ROB. */ 4662292SN/A InstSeqNum youngestSeqNum[Impl::MaxThreads]; 4672292SN/A 4687855SAli.Saidi@ARM.com /** The sequence number of the last commited instruction. */ 4697855SAli.Saidi@ARM.com InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 4707855SAli.Saidi@ARM.com 4714035Sktlim@umich.edu /** Records if there is a trap currently in flight. */ 4724035Sktlim@umich.edu bool trapInFlight[Impl::MaxThreads]; 4734035Sktlim@umich.edu 4744035Sktlim@umich.edu /** Records if there were any stores committed this cycle. */ 4754035Sktlim@umich.edu bool committedStores[Impl::MaxThreads]; 4764035Sktlim@umich.edu 4774035Sktlim@umich.edu /** Records if commit should check if the ROB is truly empty (see 4784035Sktlim@umich.edu commit_impl.hh). */ 4794035Sktlim@umich.edu bool checkEmptyROB[Impl::MaxThreads]; 4804035Sktlim@umich.edu 4812292SN/A /** Pointer to the list of active threads. */ 4826221Snate@binkert.org std::list<ThreadID> *activeThreads; 4832292SN/A 4842292SN/A /** Rename map interface. */ 4852292SN/A RenameMap *renameMap[Impl::MaxThreads]; 4862292SN/A 4878823Snilay@cs.wisc.edu /** True if last committed microop can be followed by an interrupt */ 4888823Snilay@cs.wisc.edu bool canHandleInterrupts; 4898823Snilay@cs.wisc.edu 4909513SAli.Saidi@ARM.com /** Have we had an interrupt pending and then seen it de-asserted because 4919513SAli.Saidi@ARM.com of a masking change? In this case the variable is set and the next time 4929513SAli.Saidi@ARM.com interrupts are enabled and pending the pipeline will squash to avoid 4939513SAli.Saidi@ARM.com a possible livelock senario. */ 4949513SAli.Saidi@ARM.com bool avoidQuiesceLiveLock; 4959513SAli.Saidi@ARM.com 4962348SN/A /** Updates commit stats based on this instruction. */ 4972301SN/A void updateComInstStats(DynInstPtr &inst); 4982301SN/A 4992292SN/A /** Stat for the total number of squashed instructions discarded by commit. 5002292SN/A */ 5015999Snate@binkert.org Stats::Scalar commitSquashedInsts; 5022292SN/A /** Stat for the total number of times commit is told to squash. 5032292SN/A * @todo: Actually increment this stat. 5042292SN/A */ 5055999Snate@binkert.org Stats::Scalar commitSquashEvents; 5062292SN/A /** Stat for the total number of times commit has had to stall due to a non- 5072292SN/A * speculative instruction reaching the head of the ROB. 5082292SN/A */ 5095999Snate@binkert.org Stats::Scalar commitNonSpecStalls; 5102292SN/A /** Stat for the total number of branch mispredicts that caused a squash. */ 5115999Snate@binkert.org Stats::Scalar branchMispredicts; 5122292SN/A /** Distribution of the number of committed instructions each cycle. */ 5135999Snate@binkert.org Stats::Distribution numCommittedDist; 5141062SN/A 5152316SN/A /** Total number of instructions committed. */ 5168834Satgutier@umich.edu Stats::Vector instsCommitted; 5178834Satgutier@umich.edu /** Total number of ops (including micro ops) committed. */ 5188834Satgutier@umich.edu Stats::Vector opsCommitted; 5192316SN/A /** Total number of software prefetches committed. */ 5205999Snate@binkert.org Stats::Vector statComSwp; 5212316SN/A /** Stat for the total number of committed memory references. */ 5225999Snate@binkert.org Stats::Vector statComRefs; 5232316SN/A /** Stat for the total number of committed loads. */ 5245999Snate@binkert.org Stats::Vector statComLoads; 5252316SN/A /** Total number of committed memory barriers. */ 5265999Snate@binkert.org Stats::Vector statComMembars; 5272316SN/A /** Total number of committed branches. */ 5285999Snate@binkert.org Stats::Vector statComBranches; 5297897Shestness@cs.utexas.edu /** Total number of floating point instructions */ 5307897Shestness@cs.utexas.edu Stats::Vector statComFloating; 5317897Shestness@cs.utexas.edu /** Total number of integer instructions */ 5327897Shestness@cs.utexas.edu Stats::Vector statComInteger; 5337897Shestness@cs.utexas.edu /** Total number of function calls */ 5347897Shestness@cs.utexas.edu Stats::Vector statComFunctionCalls; 5352301SN/A 5362348SN/A /** Number of cycles where the commit bandwidth limit is reached. */ 5375999Snate@binkert.org Stats::Scalar commitEligibleSamples; 5382348SN/A /** Number of instructions not committed due to bandwidth limits. */ 5395999Snate@binkert.org Stats::Vector commitEligible; 5401060SN/A}; 5411060SN/A 5422292SN/A#endif // __CPU_O3_COMMIT_HH__ 543